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lxdream.org :: lxdream :: r597:87cbdf62aa35
lxdream 0.9.1
released Jun 29
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changeset597:87cbdf62aa35
parent596:dfc0c93d882e
child598:8798c3f0bf78
authornkeynes
dateTue Jan 22 09:45:21 2008 +0000 (11 years ago)
Initial VMA support for the SH4 disassembly
src/sh4/mmu.c
src/sh4/sh4.c
src/sh4/sh4core.h
src/sh4/sh4dasm.c
src/sh4/sh4dasm.in
1.1 --- a/src/sh4/mmu.c Mon Jan 21 11:59:46 2008 +0000
1.2 +++ b/src/sh4/mmu.c Tue Jan 22 09:45:21 2008 +0000
1.3 @@ -849,6 +849,41 @@
1.4 }
1.5 }
1.6
1.7 +/**
1.8 + * Translate address for disassembly purposes (ie performs an instruction
1.9 + * lookup) - does not raise exceptions or modify any state, and ignores
1.10 + * protection bits. Returns the translated address, or MMU_VMA_ERROR
1.11 + * on translation failure.
1.12 + */
1.13 +sh4addr_t mmu_vma_to_phys_disasm( sh4vma_t vma )
1.14 +{
1.15 + if( vma & 0x80000000 ) {
1.16 + if( vma < 0xC0000000 ) {
1.17 + /* P1, P2 and P4 regions are pass-through (no translation) */
1.18 + return VMA_TO_EXT_ADDR(vma);
1.19 + } else if( vma >= 0xE0000000 && vma < 0xFFFFFF00 ) {
1.20 + /* Not translatable */
1.21 + return MMU_VMA_ERROR;
1.22 + }
1.23 + }
1.24 +
1.25 + uint32_t mmucr = MMIO_READ(MMU,MMUCR);
1.26 + if( (mmucr & MMUCR_AT) == 0 ) {
1.27 + return VMA_TO_EXT_ADDR(vma);
1.28 + }
1.29 +
1.30 + int entryNo = mmu_itlb_lookup_vpn( vma );
1.31 + if( entryNo == -2 ) {
1.32 + entryNo = mmu_itlb_lookup_vpn_asid( vma );
1.33 + }
1.34 + if( entryNo < 0 ) {
1.35 + return MMU_VMA_ERROR;
1.36 + } else {
1.37 + return (mmu_itlb[entryNo].ppn & mmu_itlb[entryNo].mask) |
1.38 + (vma & (~mmu_itlb[entryNo].mask));
1.39 + }
1.40 +}
1.41 +
1.42 gboolean sh4_flush_store_queue( sh4addr_t addr )
1.43 {
1.44 uint32_t mmucr = MMIO_READ(MMU,MMUCR);
2.1 --- a/src/sh4/sh4.c Mon Jan 21 11:59:46 2008 +0000
2.2 +++ b/src/sh4/sh4.c Tue Jan 22 09:45:21 2008 +0000
2.3 @@ -358,3 +358,8 @@
2.4 xf[10]*fv[2] + xf[14]*fv[3];
2.5 }
2.6
2.7 +gboolean sh4_has_page( sh4vma_t vma )
2.8 +{
2.9 + sh4addr_t addr = mmu_vma_to_phys_disasm(vma);
2.10 + return addr != MMU_VMA_ERROR && mem_has_page(addr);
2.11 +}
3.1 --- a/src/sh4/sh4core.h Mon Jan 21 11:59:46 2008 +0000
3.2 +++ b/src/sh4/sh4core.h Tue Jan 22 09:45:21 2008 +0000
3.3 @@ -110,6 +110,7 @@
3.4 uint32_t sh4_read_sr(void);
3.5 void sh4_write_sr(uint32_t val);
3.6 void signsat48(void);
3.7 +gboolean sh4_has_page( sh4vma_t vma );
3.8
3.9 /* SH4 Memory */
3.10 #define MMU_VMA_ERROR 0x8000000
3.11 @@ -132,6 +133,7 @@
3.12 */
3.13 sh4addr_t mmu_vma_to_phys_read( sh4vma_t addr );
3.14 sh4addr_t mmu_vma_to_phys_write( sh4vma_t addr );
3.15 +sh4addr_t mmu_vma_to_phys_disasm( sh4vma_t addr );
3.16
3.17 int64_t sh4_read_quad( sh4addr_t addr );
3.18 int32_t sh4_read_long( sh4addr_t addr );
4.1 --- a/src/sh4/sh4dasm.c Mon Jan 21 11:59:46 2008 +0000
4.2 +++ b/src/sh4/sh4dasm.c Tue Jan 22 09:45:21 2008 +0000
4.3 @@ -43,14 +43,15 @@
4.4
4.5
4.6 const struct cpu_desc_struct sh4_cpu_desc =
4.7 - { "SH4", sh4_disasm_instruction, sh4_execute_instruction, mem_has_page,
4.8 + { "SH4", sh4_disasm_instruction, sh4_execute_instruction, sh4_has_page,
4.9 sh4_set_breakpoint, sh4_clear_breakpoint, sh4_get_breakpoint, 2,
4.10 (char *)&sh4r, sizeof(sh4r), sh4_reg_map,
4.11 &sh4r.pc };
4.12
4.13 -uint32_t sh4_disasm_instruction( uint32_t pc, char *buf, int len, char *opcode )
4.14 +uint32_t sh4_disasm_instruction( sh4vma_t pc, char *buf, int len, char *opcode )
4.15 {
4.16 - uint16_t ir = sh4_read_word(pc);
4.17 + sh4addr_t addr = mmu_vma_to_phys_disasm(pc);
4.18 + uint16_t ir = sh4_read_word(addr);
4.19
4.20 #define UNDEF(ir) snprintf( buf, len, "???? " );
4.21 #define RN(ir) ((ir&0x0F00)>>8)
4.22 @@ -1199,7 +1200,7 @@
4.23 case 0x9:
4.24 { /* MOV.W @(disp, PC), Rn */
4.25 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1;
4.26 - snprintf( buf, len, "MOV.W @($%xh), R%d ; <- #%08x", disp + pc + 4, Rn, sh4_read_word(disp+pc+4) );
4.27 + snprintf( buf, len, "MOV.W @($%xh), R%d ; <- #%08x", disp + pc + 4, Rn, sh4_read_word(disp+addr+4) );
4.28 }
4.29 break;
4.30 case 0xA:
4.31 @@ -1317,7 +1318,7 @@
4.32 case 0xD:
4.33 { /* MOV.L @(disp, PC), Rn */
4.34 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2;
4.35 - snprintf( buf, len, "MOV.L @($%xh), R%d ; <- #%08x", disp + (pc & 0xFFFFFFFC) + 4, Rn, sh4_read_long(disp+(pc&0xFFFFFFFC)+4) );
4.36 + snprintf( buf, len, "MOV.L @($%xh), R%d ; <- #%08x", disp + (pc & 0xFFFFFFFC) + 4, Rn, sh4_read_long(disp+(addr&0xFFFFFFFC)+4) );
4.37 }
4.38 break;
4.39 case 0xE:
5.1 --- a/src/sh4/sh4dasm.in Mon Jan 21 11:59:46 2008 +0000
5.2 +++ b/src/sh4/sh4dasm.in Tue Jan 22 09:45:21 2008 +0000
5.3 @@ -43,14 +43,15 @@
5.4
5.5
5.6 const struct cpu_desc_struct sh4_cpu_desc =
5.7 - { "SH4", sh4_disasm_instruction, sh4_execute_instruction, mem_has_page,
5.8 + { "SH4", sh4_disasm_instruction, sh4_execute_instruction, sh4_has_page,
5.9 sh4_set_breakpoint, sh4_clear_breakpoint, sh4_get_breakpoint, 2,
5.10 (char *)&sh4r, sizeof(sh4r), sh4_reg_map,
5.11 &sh4r.pc };
5.12
5.13 -uint32_t sh4_disasm_instruction( uint32_t pc, char *buf, int len, char *opcode )
5.14 +uint32_t sh4_disasm_instruction( sh4vma_t pc, char *buf, int len, char *opcode )
5.15 {
5.16 - uint16_t ir = sh4_read_word(pc);
5.17 + sh4addr_t addr = mmu_vma_to_phys_disasm(pc);
5.18 + uint16_t ir = sh4_read_word(addr);
5.19
5.20 #define UNDEF(ir) snprintf( buf, len, "???? " );
5.21 #define RN(ir) ((ir&0x0F00)>>8)
5.22 @@ -188,7 +189,7 @@
5.23 MOV.L @Rm+, Rn {: snprintf( buf, len, "MOV.L @R%d+, R%d", Rm, Rn ); :}
5.24 MOV.L @(R0, Rm), Rn {: snprintf( buf, len, "MOV.L @(R0, R%d), R%d", Rm, Rn ); :}
5.25 MOV.L @(disp, GBR), R0 {: snprintf( buf, len, "MOV.L @(%d, GBR), R0",disp ); :}
5.26 -MOV.L @(disp, PC), Rn {: snprintf( buf, len, "MOV.L @($%xh), R%d ; <- #%08x", disp + (pc & 0xFFFFFFFC) + 4, Rn, sh4_read_long(disp+(pc&0xFFFFFFFC)+4) ); :}
5.27 +MOV.L @(disp, PC), Rn {: snprintf( buf, len, "MOV.L @($%xh), R%d ; <- #%08x", disp + (pc & 0xFFFFFFFC) + 4, Rn, sh4_read_long(disp+(addr&0xFFFFFFFC)+4) ); :}
5.28 MOV.L @(disp, Rm), Rn {: snprintf( buf, len, "MOV.L @(%d, R%d), R%d", disp, Rm, Rn ); :}
5.29 MOV.W Rm, @Rn {: snprintf( buf, len, "MOV.W R%d, @R%d", Rm, Rn ); :}
5.30 MOV.W Rm, @-Rn {: snprintf( buf, len, "MOV.W R%d, @-R%d", Rm, Rn ); :}
5.31 @@ -199,7 +200,7 @@
5.32 MOV.W @Rm+, Rn {: snprintf( buf, len, "MOV.W @R%d+, R%d", Rm, Rn ); :}
5.33 MOV.W @(R0, Rm), Rn {: snprintf( buf, len, "MOV.W @(R0, R%d), R%d", Rm, Rn ); :}
5.34 MOV.W @(disp, GBR), R0 {: snprintf( buf, len, "MOV.W @(%d, GBR), R0", disp ); :}
5.35 -MOV.W @(disp, PC), Rn {: snprintf( buf, len, "MOV.W @($%xh), R%d ; <- #%08x", disp + pc + 4, Rn, sh4_read_word(disp+pc+4) ); :}
5.36 +MOV.W @(disp, PC), Rn {: snprintf( buf, len, "MOV.W @($%xh), R%d ; <- #%08x", disp + pc + 4, Rn, sh4_read_word(disp+addr+4) ); :}
5.37 MOV.W @(disp, Rm), R0 {: snprintf( buf, len, "MOV.W @(%d, R%d), R0", disp, Rm ); :}
5.38 MOVA @(disp, PC), R0 {: snprintf( buf, len, "MOVA @($%xh), R0", disp + (pc&0xFFFFFFFC) + 4 ); :}
5.39 MOVCA.L R0, @Rn {: snprintf( buf, len, "MOVCA.L R0, @R%d", Rn ); :}
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