1.1 --- a/src/sh4/sh4core.c	Fri Mar 17 12:13:12 2006 +0000
     1.2 +++ b/src/sh4/sh4core.c	Fri Mar 17 12:45:11 2006 +0000
     1.3 @@ -1,5 +1,5 @@
     1.4  /**
     1.5 - * $Id: sh4core.c,v 1.22 2006-03-14 11:44:04 nkeynes Exp $
     1.6 + * $Id: sh4core.c,v 1.23 2006-03-17 12:45:11 nkeynes Exp $
     1.7   * 
     1.8   * SH4 emulation core, and parent module for all the SH4 peripheral
     1.9   * modules.
    1.10 @@ -1118,9 +1118,7 @@
    1.11                  case 3: /* TRAPA   imm8 */
    1.12                      CHECKSLOTILLEGAL()
    1.13                      sh4r.in_delay_slot = 1;
    1.14 -                    MMIO_WRITE( MMU, TRA, UIMM8(ir) );
    1.15 -                    sh4r.pc = sh4r.new_pc;  /* RAISE ends the instruction */
    1.16 -                    sh4r.new_pc += 2;
    1.17 +                    MMIO_WRITE( MMU, TRA, UIMM8(ir)<<2 );
    1.18                      RAISE( EXC_TRAP, EXV_TRAP );
    1.19                      break;
    1.20                  case 4: /* MOV.B   [GBR + disp8], R0 */