1.1 --- a/src/sh4/cache.c	Wed Dec 24 06:05:42 2008 +0000
     1.2 +++ b/src/sh4/cache.c	Wed Dec 24 06:06:23 2008 +0000
     1.3 @@ -163,11 +163,118 @@
     1.4          ocram_page1_read_byte, ocram_page1_write_byte,
     1.5          ocram_page1_read_burst, ocram_page1_write_burst };
     1.6  
     1.7 +/************************** Cache direct access ******************************/
     1.8 +
     1.9 +static int32_t ccn_icache_addr_read( sh4addr_t addr )
    1.10 +{
    1.11 +    int entry = (addr & 0x00001FE0);
    1.12 +    return ccn_icache[entry>>5].tag;
    1.13 +}
    1.14 +
    1.15 +static void ccn_icache_addr_write( sh4addr_t addr, uint32_t val )
    1.16 +{
    1.17 +    int entry = (addr & 0x00003FE0);
    1.18 +    struct cache_line *line = &ccn_ocache[entry>>5];
    1.19 +    if( addr & 0x08 ) { // Associative
    1.20 +        /* FIXME: implement this - requires ITLB lookups, with exception in case of multi-hit */
    1.21 +    } else {
    1.22 +        line->tag = val & 0x1FFFFC01;
    1.23 +        line->key = (val & 0x1FFFFC00)|(entry & 0x000003E0);
    1.24 +    }
    1.25 +}
    1.26 +
    1.27 +struct mem_region_fn p4_region_icache_addr = {
    1.28 +        ccn_icache_addr_read, ccn_icache_addr_write,
    1.29 +        unmapped_read_long, unmapped_write_long,
    1.30 +        unmapped_read_long, unmapped_write_long,
    1.31 +        unmapped_read_burst, unmapped_write_burst };
    1.32 +
    1.33 +
    1.34 +static int32_t ccn_icache_data_read( sh4addr_t addr )
    1.35 +{
    1.36 +    int entry = (addr & 0x00001FFC);
    1.37 +    return *(uint32_t *)&ccn_icache_data[entry];
    1.38 +}
    1.39 +
    1.40 +static void ccn_icache_data_write( sh4addr_t addr, uint32_t val )
    1.41 +{
    1.42 +    int entry = (addr & 0x00001FFC);
    1.43 +    *(uint32_t *)&ccn_icache_data[entry] = val;    
    1.44 +}
    1.45 +
    1.46 +struct mem_region_fn p4_region_icache_data = {
    1.47 +        ccn_icache_data_read, ccn_icache_data_write,
    1.48 +        unmapped_read_long, unmapped_write_long,
    1.49 +        unmapped_read_long, unmapped_write_long,
    1.50 +        unmapped_read_burst, unmapped_write_burst };
    1.51 +
    1.52 +
    1.53 +static int32_t ccn_ocache_addr_read( sh4addr_t addr )
    1.54 +{
    1.55 +    int entry = (addr & 0x00003FE0);
    1.56 +    return ccn_ocache[entry>>5].tag;
    1.57 +}
    1.58 +
    1.59 +static void ccn_ocache_addr_write( sh4addr_t addr, uint32_t val )
    1.60 +{
    1.61 +    int entry = (addr & 0x00003FE0);
    1.62 +    struct cache_line *line = &ccn_ocache[entry>>5];
    1.63 +    if( addr & 0x08 ) { // Associative
    1.64 +    } else {
    1.65 +        if( (line->tag & (CACHE_VALID|CACHE_DIRTY)) == (CACHE_VALID|CACHE_DIRTY) ) {
    1.66 +            char *cache_data = &ccn_ocache_data[entry&0x00003FE0];
    1.67 +            // Cache line is dirty - writeback. 
    1.68 +            ext_address_space[line->tag>>12]->write_burst(line->key, cache_data);
    1.69 +        }
    1.70 +        line->tag = val & 0x1FFFFC03;
    1.71 +        line->key = (val & 0x1FFFFC00)|(entry & 0x000003E0);
    1.72 +    }
    1.73 +}
    1.74 +
    1.75 +struct mem_region_fn p4_region_ocache_addr = {
    1.76 +        ccn_ocache_addr_read, ccn_ocache_addr_write,
    1.77 +        unmapped_read_long, unmapped_write_long,
    1.78 +        unmapped_read_long, unmapped_write_long,
    1.79 +        unmapped_read_burst, unmapped_write_burst };
    1.80 +
    1.81 +
    1.82 +static int32_t ccn_ocache_data_read( sh4addr_t addr )
    1.83 +{
    1.84 +    int entry = (addr & 0x00003FFC);
    1.85 +    return *(uint32_t *)&ccn_ocache_data[entry];
    1.86 +}
    1.87 +
    1.88 +static void ccn_ocache_data_write( sh4addr_t addr, uint32_t val )
    1.89 +{
    1.90 +    int entry = (addr & 0x00003FFC);
    1.91 +    *(uint32_t *)&ccn_ocache_data[entry] = val;
    1.92 +}
    1.93 +
    1.94 +struct mem_region_fn p4_region_ocache_data = {
    1.95 +        ccn_ocache_data_read, ccn_ocache_data_write,
    1.96 +        unmapped_read_long, unmapped_write_long,
    1.97 +        unmapped_read_long, unmapped_write_long,
    1.98 +        unmapped_read_burst, unmapped_write_burst };
    1.99 +
   1.100 +
   1.101  /****************** Cache control *********************/
   1.102  
   1.103  void CCN_set_cache_control( int reg )
   1.104  {
   1.105      uint32_t i;
   1.106 +    
   1.107 +    if( reg & CCR_ICI ) { /* icache invalidate */
   1.108 +        for( i=0; i<ICACHE_ENTRY_COUNT; i++ ) {
   1.109 +            ccn_icache[i].tag &= ~CACHE_VALID;
   1.110 +        }
   1.111 +    }
   1.112 +    
   1.113 +    if( reg & CCR_OCI ) { /* ocache invalidate */
   1.114 +        for( i=0; i<OCACHE_ENTRY_COUNT; i++ ) {
   1.115 +            ccn_ocache[i].tag &= ~(CACHE_VALID|CACHE_DIRTY);
   1.116 +        }
   1.117 +    }
   1.118 +    
   1.119      switch( reg & (CCR_OIX|CCR_ORA|CCR_OCE) ) {
   1.120      case MEM_OC_INDEX0: /* OIX=0 */
   1.121          for( i=OCRAM_START; i<OCRAM_END; i+=4 ) {

     2.1 --- a/src/sh4/mmu.c	Wed Dec 24 06:05:42 2008 +0000
     2.2 +++ b/src/sh4/mmu.c	Wed Dec 24 06:06:23 2008 +0000
     2.3 @@ -526,41 +526,6 @@
     2.4      }
     2.5  }
     2.6  
     2.7 -/* Cache access - not implemented */
     2.8 -
     2.9 -int32_t FASTCALL mmu_icache_addr_read( sh4addr_t addr )
    2.10 -{
    2.11 -    return 0; // not implemented
    2.12 -}
    2.13 -int32_t FASTCALL mmu_icache_data_read( sh4addr_t addr )
    2.14 -{
    2.15 -    return 0; // not implemented
    2.16 -}
    2.17 -int32_t FASTCALL mmu_ocache_addr_read( sh4addr_t addr )
    2.18 -{
    2.19 -    return 0; // not implemented
    2.20 -}
    2.21 -int32_t FASTCALL mmu_ocache_data_read( sh4addr_t addr )
    2.22 -{
    2.23 -    return 0; // not implemented
    2.24 -}
    2.25 -
    2.26 -void FASTCALL mmu_icache_addr_write( sh4addr_t addr, uint32_t val )
    2.27 -{
    2.28 -}
    2.29 -
    2.30 -void FASTCALL mmu_icache_data_write( sh4addr_t addr, uint32_t val )
    2.31 -{
    2.32 -}
    2.33 -
    2.34 -void FASTCALL mmu_ocache_addr_write( sh4addr_t addr, uint32_t val )
    2.35 -{
    2.36 -}
    2.37 -
    2.38 -void FASTCALL mmu_ocache_data_write( sh4addr_t addr, uint32_t val )
    2.39 -{
    2.40 -}
    2.41 -
    2.42  /******************************************************************************/
    2.43  /*                        MMU TLB address translation                         */
    2.44  /******************************************************************************/
    2.45 @@ -1017,7 +982,6 @@
    2.46      sh4ptr_t src = (sh4ptr_t)&sh4r.store_queue[queue];
    2.47      sh4addr_t target = (addr&0x03FFFFE0) | hi;
    2.48      ext_address_space[target>>12]->write_burst( target, src );
    2.49 -//    mem_copy_to_sh4( target, src, 32 );
    2.50  } 
    2.51  
    2.52  gboolean FASTCALL sh4_flush_store_queue_mmu( sh4addr_t addr )
    2.53 @@ -1060,7 +1024,6 @@
    2.54      }
    2.55  
    2.56      ext_address_space[target>>12]->write_burst( target, src );
    2.57 -    // mem_copy_to_sh4( target, src, 32 );
    2.58      return TRUE;
    2.59  }
    2.60  

     3.1 --- a/src/sh4/sh4mem.c	Wed Dec 24 06:05:42 2008 +0000
     3.2 +++ b/src/sh4/sh4mem.c	Wed Dec 24 06:06:23 2008 +0000
     3.3 @@ -38,15 +38,15 @@
     3.4  extern struct mem_region_fn mem_region_bootrom;
     3.5  
     3.6  /* On-chip regions other than defined MMIO regions */
     3.7 -extern struct mem_region_fn mem_region_storequeue;
     3.8 -extern struct mem_region_fn mem_region_icache_addr;
     3.9 -extern struct mem_region_fn mem_region_icache_data;
    3.10 -extern struct mem_region_fn mem_region_ocache_addr;
    3.11 -extern struct mem_region_fn mem_region_ocache_data;
    3.12 -extern struct mem_region_fn mem_region_itlb_addr;
    3.13 -extern struct mem_region_fn mem_region_itlb_data;
    3.14 -extern struct mem_region_fn mem_region_utlb_addr;
    3.15 -extern struct mem_region_fn mem_region_utlb_data;
    3.16 +extern struct mem_region_fn p4_region_storequeue;
    3.17 +extern struct mem_region_fn p4_region_icache_addr;
    3.18 +extern struct mem_region_fn p4_region_icache_data;
    3.19 +extern struct mem_region_fn p4_region_ocache_addr;
    3.20 +extern struct mem_region_fn p4_region_ocache_data;
    3.21 +extern struct mem_region_fn p4_region_itlb_addr;
    3.22 +extern struct mem_region_fn p4_region_itlb_data;
    3.23 +extern struct mem_region_fn p4_region_utlb_addr;
    3.24 +extern struct mem_region_fn p4_region_utlb_data;
    3.25  
    3.26  /********************* The main ram address space **********************/
    3.27  static int32_t FASTCALL ext_sdram_read_long( sh4addr_t addr )
    3.28 @@ -178,28 +178,6 @@
    3.29          p4_storequeue_read_long, p4_storequeue_write_long,
    3.30          unmapped_read_burst, unmapped_write_burst }; // No burst access.
    3.31  
    3.32 -/* Cache access */
    3.33 -struct mem_region_fn p4_region_icache_addr = {
    3.34 -        mmu_icache_addr_read, mmu_icache_addr_write,
    3.35 -        mmu_icache_addr_read, mmu_icache_addr_write,
    3.36 -        mmu_icache_addr_read, mmu_icache_addr_write,
    3.37 -        unmapped_read_burst, unmapped_write_burst };
    3.38 -struct mem_region_fn p4_region_icache_data = {
    3.39 -        mmu_icache_data_read, mmu_icache_data_write,
    3.40 -        mmu_icache_data_read, mmu_icache_data_write,
    3.41 -        mmu_icache_data_read, mmu_icache_data_write,
    3.42 -        unmapped_read_burst, unmapped_write_burst };
    3.43 -struct mem_region_fn p4_region_ocache_addr = {
    3.44 -        mmu_ocache_addr_read, mmu_ocache_addr_write,
    3.45 -        mmu_ocache_addr_read, mmu_ocache_addr_write,
    3.46 -        mmu_ocache_addr_read, mmu_ocache_addr_write,
    3.47 -        unmapped_read_burst, unmapped_write_burst };
    3.48 -struct mem_region_fn p4_region_ocache_data = {
    3.49 -        mmu_ocache_data_read, mmu_ocache_data_write,
    3.50 -        mmu_ocache_data_read, mmu_ocache_data_write,
    3.51 -        mmu_ocache_data_read, mmu_ocache_data_write,
    3.52 -        unmapped_read_burst, unmapped_write_burst };
    3.53 -
    3.54  /* TLB access */
    3.55  struct mem_region_fn p4_region_itlb_addr = {
    3.56          mmu_itlb_addr_read, mmu_itlb_addr_write,