1.1 --- a/src/sh4/sh4core.c	Mon Mar 13 12:39:07 2006 +0000
     1.2 +++ b/src/sh4/sh4core.c	Tue Mar 14 11:44:04 2006 +0000
     1.3 @@ -1,5 +1,5 @@
     1.4  /**
     1.5 - * $Id: sh4core.c,v 1.21 2006-03-13 12:38:39 nkeynes Exp $
     1.6 + * $Id: sh4core.c,v 1.22 2006-03-14 11:44:04 nkeynes Exp $
     1.7   * 
     1.8   * SH4 emulation core, and parent module for all the SH4 peripheral
     1.9   * modules.
    1.10 @@ -192,13 +192,13 @@
    1.11      sh4r.new_pc = pc+2;
    1.12  }
    1.13  
    1.14 -#define UNDEF(ir) do{ ERROR( "Raising exception on undefined instruction at %08x, opcode = %04x", sh4r.pc, ir ); RAISE( EXC_ILLEGAL, EXV_ILLEGAL ); }while(0)
    1.15 +#define UNDEF(ir) do{ ERROR( "Raising exception on undefined instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop();  return FALSE; }while(0)
    1.16  #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
    1.17  
    1.18  #define RAISE( x, v ) do{ \
    1.19      if( sh4r.vbr == 0 ) { \
    1.20          ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
    1.21 -        sh4_stop(); \
    1.22 +        dreamcast_stop(); return FALSE;	\
    1.23      } else { \
    1.24          sh4r.spc = sh4r.pc + 2; \
    1.25          sh4r.ssr = sh4_read_sr(); \
    1.26 @@ -334,7 +334,7 @@
    1.27      if( pc > 0xFFFFFF00 ) {
    1.28  	/* SYSCALL Magic */
    1.29  	syscall_invoke( pc );
    1.30 -	sh4r.in_delay_slot = 1;
    1.31 +	sh4r.in_delay_slot = 0;
    1.32  	pc = sh4r.pc = sh4r.pr;
    1.33  	sh4r.new_pc = sh4r.pc + 2;
    1.34      }