revision 302:96b5cc24309c
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raw | bz2 | zip | gz changeset | 302:96b5cc24309c |
parent | 301:1ace395139c3 |
child | 303:41786e056449 |
author | nkeynes |
date | Wed Jan 17 21:27:20 2007 +0000 (17 years ago) |
Rename SPUDMA to G2DMA (following KOS's lead)
Remove sh4r.icount (obsolete)
Rewrite G2 fifo status in terms of slice cycles
Remove sh4r.icount (obsolete)
Rewrite G2 fifo status in terms of slice cycles
src/aica/armdasm.c | view | annotate | diff | log | ||
src/asic.c | view | annotate | diff | log | ||
src/asic.h | view | annotate | diff | log | ||
src/sh4/sh4core.c | view | annotate | diff | log | ||
src/sh4/sh4core.h | view | annotate | diff | log | ||
src/sh4/sh4dasm.c | view | annotate | diff | log |
1.1 --- a/src/aica/armdasm.c Wed Jan 17 09:37:22 2007 +00001.2 +++ b/src/aica/armdasm.c Wed Jan 17 21:27:20 2007 +00001.3 @@ -1,5 +1,5 @@1.4 /**1.5 - * $Id: armdasm.c,v 1.11 2006-01-03 12:20:36 nkeynes Exp $1.6 + * $Id: armdasm.c,v 1.12 2007-01-17 21:27:20 nkeynes Exp $1.7 *1.8 * armdasm.c 21 Aug 2004 - ARM7tdmi (ARMv4) disassembler1.9 *1.10 @@ -64,12 +64,12 @@1.11 { "ARM7", arm_disasm_instruction, arm_execute_instruction, arm_has_page,1.12 arm_set_breakpoint, arm_clear_breakpoint, arm_get_breakpoint, 4,1.13 (char *)&armr, sizeof(armr), arm_reg_map,1.14 - &armr.r[15], &armr.icount };1.15 + &armr.r[15] };1.16 const struct cpu_desc_struct armt_cpu_desc =1.17 { "ARM7T", armt_disasm_instruction, arm_execute_instruction, arm_has_page,1.18 arm_set_breakpoint, arm_clear_breakpoint, arm_get_breakpoint, 2,1.19 (char*)&armr, sizeof(armr), arm_reg_map,1.20 - &armr.r[15], &armr.icount };1.21 + &armr.r[15] };
2.1 --- a/src/asic.c Wed Jan 17 09:37:22 2007 +00002.2 +++ b/src/asic.c Wed Jan 17 21:27:20 2007 +00002.3 @@ -1,5 +1,5 @@2.4 /**2.5 - * $Id: asic.c,v 1.23 2007-01-14 02:54:40 nkeynes Exp $2.6 + * $Id: asic.c,v 1.24 2007-01-17 21:27:20 nkeynes Exp $2.7 *2.8 * Support for the miscellaneous ASIC functions (Primarily event multiplexing,2.9 * and DMA).2.10 @@ -44,28 +44,63 @@2.11 static void asic_check_cleared_events( void );2.12 static void asic_init( void );2.13 static void asic_reset( void );2.14 +static uint32_t asic_run_slice( uint32_t nanosecs );2.15 static void asic_save_state( FILE *f );2.16 static int asic_load_state( FILE *f );2.17 +static uint32_t g2_update_fifo_status( uint32_t slice_cycle );2.19 -struct dreamcast_module asic_module = { "ASIC", asic_init, asic_reset, NULL, NULL,2.20 +struct dreamcast_module asic_module = { "ASIC", asic_init, asic_reset, NULL, asic_run_slice,2.21 NULL, asic_save_state, asic_load_state };2.23 -#define G2_BIT5_TICKS 82.24 -#define G2_BIT4_TICKS 162.25 -#define G2_BIT0_ON_TICKS 242.26 -#define G2_BIT0_OFF_TICKS 242.27 +#define G2_BIT5_TICKS 602.28 +#define G2_BIT4_TICKS 1602.29 +#define G2_BIT0_ON_TICKS 1202.30 +#define G2_BIT0_OFF_TICKS 4202.32 struct asic_g2_state {2.33 - unsigned int last_update_time;2.34 - unsigned int bit5_off_timer;2.35 - unsigned int bit4_on_timer;2.36 - unsigned int bit4_off_timer;2.37 - unsigned int bit0_on_timer;2.38 - unsigned int bit0_off_timer;2.39 + int bit5_off_timer;2.40 + int bit4_on_timer;2.41 + int bit4_off_timer;2.42 + int bit0_on_timer;2.43 + int bit0_off_timer;2.44 };2.46 static struct asic_g2_state g2_state;2.48 +static uint32_t asic_run_slice( uint32_t nanosecs )2.49 +{2.50 + g2_update_fifo_status(nanosecs);2.51 + if( g2_state.bit5_off_timer <= (int32_t)nanosecs ) {2.52 + g2_state.bit5_off_timer = -1;2.53 + } else {2.54 + g2_state.bit5_off_timer -= nanosecs;2.55 + }2.56 +2.57 + if( g2_state.bit4_off_timer <= (int32_t)nanosecs ) {2.58 + g2_state.bit4_off_timer = -1;2.59 + } else {2.60 + g2_state.bit4_off_timer -= nanosecs;2.61 + }2.62 + if( g2_state.bit4_on_timer <= (int32_t)nanosecs ) {2.63 + g2_state.bit4_on_timer = -1;2.64 + } else {2.65 + g2_state.bit4_on_timer -= nanosecs;2.66 + }2.67 +2.68 + if( g2_state.bit0_off_timer <= (int32_t)nanosecs ) {2.69 + g2_state.bit0_off_timer = -1;2.70 + } else {2.71 + g2_state.bit0_off_timer -= nanosecs;2.72 + }2.73 + if( g2_state.bit0_on_timer <= (int32_t)nanosecs ) {2.74 + g2_state.bit0_on_timer = -1;2.75 + } else {2.76 + g2_state.bit0_on_timer -= nanosecs;2.77 + }2.78 +2.79 + return nanosecs;2.80 +}2.81 +2.82 static void asic_init( void )2.83 {2.84 register_io_region( &mmio_region_ASIC );2.85 @@ -75,7 +110,7 @@2.87 static void asic_reset( void )2.88 {2.89 - memset( &g2_state, 0, sizeof(g2_state) );2.90 + memset( &g2_state, 0xFF, sizeof(g2_state) );2.91 }2.93 static void asic_save_state( FILE *f )2.94 @@ -92,53 +127,84 @@2.95 }2.98 -/* FIXME: Handle rollover */2.99 +/**2.100 + * Setup the timers for the 3 FIFO status bits following a write through the G22.101 + * bus from the SH4 side. The timing is roughly as follows: (times are2.102 + * approximate based on software readings - I wouldn't take this as gospel but2.103 + * it seems to be enough to fool most programs).2.104 + * 0ns: Bit 5 (Input fifo?) goes high immediately on the write2.105 + * 40ns: Bit 5 goes low and bit 4 goes high2.106 + * 120ns: Bit 4 goes low, bit 0 goes high2.107 + * 240ns: Bit 0 goes low.2.108 + *2.109 + * Additional writes while the FIFO is in operation extend the time that the2.110 + * bits remain high as one might expect, without altering the time at which2.111 + * they initially go high.2.112 + */2.113 void asic_g2_write_word()2.114 {2.115 - g2_state.last_update_time = sh4r.icount;2.116 - g2_state.bit5_off_timer = sh4r.icount + G2_BIT5_TICKS;2.117 - if( g2_state.bit4_off_timer < sh4r.icount )2.118 - g2_state.bit4_on_timer = sh4r.icount + G2_BIT5_TICKS;2.119 - g2_state.bit4_off_timer = max(sh4r.icount,g2_state.bit4_off_timer) + G2_BIT4_TICKS;2.120 - if( g2_state.bit0_off_timer < sh4r.icount ) {2.121 - g2_state.bit0_on_timer = sh4r.icount + G2_BIT0_ON_TICKS;2.122 + if( g2_state.bit5_off_timer < (int32_t)sh4r.slice_cycle ) {2.123 + g2_state.bit5_off_timer = sh4r.slice_cycle + G2_BIT5_TICKS;2.124 + } else {2.125 + g2_state.bit5_off_timer += G2_BIT5_TICKS;2.126 + }2.127 +2.128 + if( g2_state.bit4_on_timer < (int32_t)sh4r.slice_cycle ) {2.129 + g2_state.bit4_on_timer = sh4r.slice_cycle + G2_BIT5_TICKS;2.130 + }2.131 +2.132 + if( g2_state.bit4_off_timer < (int32_t)sh4r.slice_cycle ) {2.133 + g2_state.bit4_off_timer = g2_state.bit4_on_timer + G2_BIT4_TICKS;2.134 + } else {2.135 + g2_state.bit4_off_timer += G2_BIT4_TICKS;2.136 + }2.137 +2.138 + if( g2_state.bit0_on_timer < (int32_t)sh4r.slice_cycle ) {2.139 + g2_state.bit0_on_timer = sh4r.slice_cycle + G2_BIT0_ON_TICKS;2.140 + }2.141 +2.142 + if( g2_state.bit0_off_timer < (int32_t)sh4r.slice_cycle ) {2.143 g2_state.bit0_off_timer = g2_state.bit0_on_timer + G2_BIT0_OFF_TICKS;2.144 } else {2.145 g2_state.bit0_off_timer += G2_BIT0_OFF_TICKS;2.146 }2.147 +2.148 MMIO_WRITE( ASIC, G2STATUS, MMIO_READ(ASIC, G2STATUS) | 0x20 );2.149 }2.151 -static uint32_t g2_read_status()2.152 +static uint32_t g2_update_fifo_status( uint32_t nanos )2.153 {2.154 - if( sh4r.icount < g2_state.last_update_time ) {2.155 - /* Rollover */2.156 - if( g2_state.last_update_time < g2_state.bit5_off_timer )2.157 - g2_state.bit5_off_timer = 0;2.158 - if( g2_state.last_update_time < g2_state.bit4_off_timer )2.159 - g2_state.bit4_off_timer = 0;2.160 - if( g2_state.last_update_time < g2_state.bit4_on_timer )2.161 - g2_state.bit4_on_timer = 0;2.162 - if( g2_state.last_update_time < g2_state.bit0_off_timer )2.163 - g2_state.bit0_off_timer = 0;2.164 - if( g2_state.last_update_time < g2_state.bit0_on_timer )2.165 - g2_state.bit0_on_timer = 0;2.166 + uint32_t val = MMIO_READ( ASIC, G2STATUS );2.167 + if( ((uint32_t)g2_state.bit5_off_timer) <= nanos ) {2.168 + val = val & (~0x20);2.169 + g2_state.bit5_off_timer = -1;2.170 }2.171 - uint32_t val = MMIO_READ( ASIC, G2STATUS );2.172 - if( g2_state.bit5_off_timer <= sh4r.icount )2.173 - val = val & (~0x20);2.174 - if( g2_state.bit4_off_timer <= sh4r.icount ||2.175 - (sh4r.icount + G2_BIT5_TICKS) < g2_state.bit4_off_timer )2.176 + if( ((uint32_t)g2_state.bit4_on_timer) <= nanos ) {2.177 + val = val | 0x10;2.178 + g2_state.bit4_on_timer = -1;2.179 + }2.180 + if( ((uint32_t)g2_state.bit4_off_timer) <= nanos ) {2.181 val = val & (~0x10);2.182 - else if( g2_state.bit4_on_timer <= sh4r.icount )2.183 - val = val | 0x10;2.184 - if( g2_state.bit0_off_timer <= sh4r.icount )2.185 + g2_state.bit4_off_timer = -1;2.186 + }2.187 +2.188 + if( ((uint32_t)g2_state.bit0_on_timer) <= nanos ) {2.189 + val = val | 0x01;2.190 + g2_state.bit0_on_timer = -1;2.191 + }2.192 + if( ((uint32_t)g2_state.bit0_off_timer) <= nanos ) {2.193 val = val & (~0x01);2.194 - else if( g2_state.bit0_on_timer <= sh4r.icount )2.195 - val = val | 0x01;2.196 - return val | 0x0E;2.197 + g2_state.bit0_off_timer = -1;2.198 + }2.199 +2.200 + MMIO_WRITE( ASIC, G2STATUS, val );2.201 + return val;2.202 }2.204 +static int g2_read_status() {2.205 + return g2_update_fifo_status( sh4r.slice_cycle );2.206 +}2.207 +2.209 void asic_event( int event )2.210 {2.211 @@ -183,13 +249,13 @@2.212 {2.213 uint32_t offset = channel << 5;2.215 - if( MMIO_READ( EXTDMA, SPUDMA0CTL1 + offset ) == 1 ) {2.216 - if( MMIO_READ( EXTDMA, SPUDMA0CTL2 + offset ) == 1 ) {2.217 - uint32_t extaddr = MMIO_READ( EXTDMA, SPUDMA0EXT + offset );2.218 - uint32_t sh4addr = MMIO_READ( EXTDMA, SPUDMA0SH4 + offset );2.219 - uint32_t length = MMIO_READ( EXTDMA, SPUDMA0SIZ + offset ) & 0x1FFFFFFF;2.220 - uint32_t dir = MMIO_READ( EXTDMA, SPUDMA0DIR + offset );2.221 - uint32_t mode = MMIO_READ( EXTDMA, SPUDMA0MOD + offset );2.222 + if( MMIO_READ( EXTDMA, G2DMA0CTL1 + offset ) == 1 ) {2.223 + if( MMIO_READ( EXTDMA, G2DMA0CTL2 + offset ) == 1 ) {2.224 + uint32_t extaddr = MMIO_READ( EXTDMA, G2DMA0EXT + offset );2.225 + uint32_t sh4addr = MMIO_READ( EXTDMA, G2DMA0SH4 + offset );2.226 + uint32_t length = MMIO_READ( EXTDMA, G2DMA0SIZ + offset ) & 0x1FFFFFFF;2.227 + uint32_t dir = MMIO_READ( EXTDMA, G2DMA0DIR + offset );2.228 + uint32_t mode = MMIO_READ( EXTDMA, G2DMA0MOD + offset );2.229 char buf[length];2.230 if( dir == 0 ) { /* SH4 to device */2.231 mem_copy_from_sh4( buf, sh4addr, length );2.232 @@ -198,10 +264,10 @@2.233 mem_copy_from_sh4( buf, extaddr, length );2.234 mem_copy_to_sh4( sh4addr, buf, length );2.235 }2.236 - MMIO_WRITE( EXTDMA, SPUDMA0CTL2 + offset, 0 );2.237 - asic_event( EVENT_SPU_DMA0 + channel );2.238 + MMIO_WRITE( EXTDMA, G2DMA0CTL2 + offset, 0 );2.239 + asic_event( EVENT_G2_DMA0 + channel );2.240 } else {2.241 - MMIO_WRITE( EXTDMA, SPUDMA0CTL2 + offset, 0 );2.242 + MMIO_WRITE( EXTDMA, G2DMA0CTL2 + offset, 0 );2.243 }2.244 }2.245 }2.246 @@ -368,34 +434,34 @@2.247 idereg.interface_enabled = FALSE;2.248 }2.249 break;2.250 - case SPUDMA0CTL1:2.251 - case SPUDMA0CTL2:2.252 + case G2DMA0CTL1:2.253 + case G2DMA0CTL2:2.254 MMIO_WRITE( EXTDMA, reg, val );2.255 g2_dma_transfer( 0 );2.256 break;2.257 - case SPUDMA0UN1:2.258 + case G2DMA0STOP:2.259 break;2.260 - case SPUDMA1CTL1:2.261 - case SPUDMA1CTL2:2.262 + case G2DMA1CTL1:2.263 + case G2DMA1CTL2:2.264 MMIO_WRITE( EXTDMA, reg, val );2.265 g2_dma_transfer( 1 );2.266 break;2.268 - case SPUDMA1UN1:2.269 + case G2DMA1STOP:2.270 break;2.271 - case SPUDMA2CTL1:2.272 - case SPUDMA2CTL2:2.273 + case G2DMA2CTL1:2.274 + case G2DMA2CTL2:2.275 MMIO_WRITE( EXTDMA, reg, val );2.276 g2_dma_transfer( 2 );2.277 break;2.278 - case SPUDMA2UN1:2.279 + case G2DMA2STOP:2.280 break;2.281 - case SPUDMA3CTL1:2.282 - case SPUDMA3CTL2:2.283 + case G2DMA3CTL1:2.284 + case G2DMA3CTL2:2.285 MMIO_WRITE( EXTDMA, reg, val );2.286 g2_dma_transfer( 3 );2.287 break;2.288 - case SPUDMA3UN1:2.289 + case G2DMA3STOP:2.290 break;2.291 case PVRDMA2CTL1:2.292 case PVRDMA2CTL2:
3.1 --- a/src/asic.h Wed Jan 17 09:37:22 2007 +00003.2 +++ b/src/asic.h Wed Jan 17 21:27:20 2007 +00003.3 @@ -1,5 +1,5 @@3.4 /**3.5 - * $Id: asic.h,v 1.16 2007-01-14 11:43:00 nkeynes Exp $3.6 + * $Id: asic.h,v 1.17 2007-01-17 21:27:20 nkeynes Exp $3.7 *3.8 * Support for the miscellaneous ASIC functions (Primarily event multiplexing,3.9 * and DMA). Includes MMIO definitions for the 5f6000 and 5f7000 regions,3.10 @@ -40,7 +40,7 @@3.11 LONG_PORT( 0x84C, ASICUNK8, PORT_MRW, 0, "ASIC <unknown8>" )3.12 LONG_PORT( 0x884, PVRDMARGN, PORT_MRW, 0, "PVR DMA Dest region" )3.13 LONG_PORT( 0x888, ASICUNKA, PORT_MRW, 0, "ASIC <unknownA>" )3.14 - LONG_PORT( 0x88C, G2STATUS, PORT_MR|PORT_NOTRACE, 0, "G2 Bus status" )3.15 + LONG_PORT( 0x88C, G2STATUS, PORT_MR|PORT_NOTRACE, 0x0E, "G2 Fifo status" )3.16 LONG_PORT( 0x890, SYSRESET, PORT_W, 0, "System reset port" )3.17 LONG_PORT( 0x89C, ASICUNKB, PORT_MRW, 0xB, "Unknown, always 0xB?" )3.18 LONG_PORT( 0x8A0, ASICUNKC, PORT_MRW, 0, "ASIC <unknownC>" )3.19 @@ -117,50 +117,50 @@3.20 LONG_PORT( 0x4B8, IDEDMACFG, PORT_MRW, 0, "IDE DMA Config" ) /* 88437F00 */3.21 LONG_PORT( 0x4E4, IDEACTIVATE, PORT_MRW, 0, "IDE activate" )3.22 LONG_PORT( 0x4F8, IDEDMATXSIZ, PORT_MRW, 0, "IDE DMA transfered size" )3.23 - LONG_PORT( 0x800, SPUDMA0EXT, PORT_MRW, 0, "SPU DMA0 External address" )3.24 - LONG_PORT( 0x804, SPUDMA0SH4, PORT_MRW, 0, "SPU DMA0 SH4-based address" )3.25 - LONG_PORT( 0x808, SPUDMA0SIZ, PORT_MRW, 0, "SPU DMA0 Size" )3.26 - LONG_PORT( 0x80C, SPUDMA0DIR, PORT_MRW, 0, "SPU DMA0 Direction" )3.27 - LONG_PORT( 0x810, SPUDMA0MOD, PORT_MRW, 0, "SPU DMA0 Mode" )3.28 - LONG_PORT( 0x814, SPUDMA0CTL1, PORT_MRW, 0, "SPU DMA0 Control 1" )3.29 - LONG_PORT( 0x818, SPUDMA0CTL2, PORT_MRW, 0, "SPU DMA0 Control 2" )3.30 - LONG_PORT( 0x81C, SPUDMA0UN1, PORT_MRW, 0, "SPU DMA0 <unknown1>" )3.31 - LONG_PORT( 0x820, SPUDMA1EXT, PORT_MRW, 0, "SPU DMA1 External address" )3.32 - LONG_PORT( 0x824, SPUDMA1SH4, PORT_MRW, 0, "SPU DMA1 SH4-based address" )3.33 - LONG_PORT( 0x828, SPUDMA1SIZ, PORT_MRW, 0, "SPU DMA1 Size" )3.34 - LONG_PORT( 0x82C, SPUDMA1DIR, PORT_MRW, 0, "SPU DMA1 Direction" )3.35 - LONG_PORT( 0x830, SPUDMA1MOD, PORT_MRW, 0, "SPU DMA1 Mode" )3.36 - LONG_PORT( 0x834, SPUDMA1CTL1, PORT_MRW, 0, "SPU DMA1 Control 1" )3.37 - LONG_PORT( 0x838, SPUDMA1CTL2, PORT_MRW, 0, "SPU DMA1 Control 2" )3.38 - LONG_PORT( 0x83C, SPUDMA1UN1, PORT_MRW, 0, "SPU DMA1 <unknown1>" )3.39 - LONG_PORT( 0x840, SPUDMA2EXT, PORT_MRW, 0, "SPU DMA2 External address" )3.40 - LONG_PORT( 0x844, SPUDMA2SH4, PORT_MRW, 0, "SPU DMA2 SH4-based address" )3.41 - LONG_PORT( 0x848, SPUDMA2SIZ, PORT_MRW, 0, "SPU DMA2 Size" )3.42 - LONG_PORT( 0x84C, SPUDMA2DIR, PORT_MRW, 0, "SPU DMA2 Direction" )3.43 - LONG_PORT( 0x850, SPUDMA2MOD, PORT_MRW, 0, "SPU DMA2 Mode" )3.44 - LONG_PORT( 0x854, SPUDMA2CTL1, PORT_MRW, 0, "SPU DMA2 Control 1" )3.45 - LONG_PORT( 0x858, SPUDMA2CTL2, PORT_MRW, 0, "SPU DMA2 Control 2" )3.46 - LONG_PORT( 0x85C, SPUDMA2UN1, PORT_MRW, 0, "SPU DMA2 <unknown1>" )3.47 - LONG_PORT( 0x860, SPUDMA3EXT, PORT_MRW, 0, "SPU DMA3 External address" )3.48 - LONG_PORT( 0x864, SPUDMA3SH4, PORT_MRW, 0, "SPU DMA3 SH4-based address" )3.49 - LONG_PORT( 0x868, SPUDMA3SIZ, PORT_MRW, 0, "SPU DMA3 Size" )3.50 - LONG_PORT( 0x86C, SPUDMA3DIR, PORT_MRW, 0, "SPU DMA3 Direction" )3.51 - LONG_PORT( 0x870, SPUDMA3MOD, PORT_MRW, 0, "SPU DMA3 Mode" )3.52 - LONG_PORT( 0x874, SPUDMA3CTL1, PORT_MRW, 0, "SPU DMA3 Control 1" )3.53 - LONG_PORT( 0x878, SPUDMA3CTL2, PORT_MRW, 0, "SPU DMA3 Control 2" )3.54 - LONG_PORT( 0x87C, SPUDMA3UN1, PORT_MRW, 0, "SPU DMA3 <unknown1>" )3.55 - LONG_PORT( 0x890, SPUDMAWAIT, PORT_MRW, 0, "SPU DMA wait states (?)" )3.56 - LONG_PORT( 0x894, SPUDMAUN1, PORT_MRW, 0, "SPU DMA <unknown1>" )3.57 - LONG_PORT( 0x898, SPUDMAUN2, PORT_MRW, 0, "SPU DMA <unknown2>" )3.58 - LONG_PORT( 0x89C, SPUDMAUN3, PORT_MRW, 0, "SPU DMA <unknown3>" )3.59 - LONG_PORT( 0x8A0, SPUDMAUN4, PORT_MRW, 0, "SPU DMA <unknown4>" )3.60 - LONG_PORT( 0x8A4, SPUDMAUN5, PORT_MRW, 0, "SPU DMA <unknown5>" )3.61 - LONG_PORT( 0x8A8, SPUDMAUN6, PORT_MRW, 0, "SPU DMA <unknown6>" )3.62 - LONG_PORT( 0x8AC, SPUDMAUN7, PORT_MRW, 0, "SPU DMA <unknown7>" )3.63 - LONG_PORT( 0x8B0, SPUDMAUN8, PORT_MRW, 0, "SPU DMA <unknown8>" )3.64 - LONG_PORT( 0x8B4, SPUDMAUN9, PORT_MRW, 0, "SPU DMA <unknown9>" )3.65 - LONG_PORT( 0x8B8, SPUDMAUN10, PORT_MRW, 0, "SPU DMA <unknown10>" )3.66 - LONG_PORT( 0x8BC, SPUDMACFG, PORT_MRW, 0, "SPU DMA Config" ) /* 46597F00 */3.67 + LONG_PORT( 0x800, G2DMA0EXT, PORT_MRW, 0, "G2 DMA0 External address" )3.68 + LONG_PORT( 0x804, G2DMA0SH4, PORT_MRW, 0, "G2 DMA0 SH4-based address" )3.69 + LONG_PORT( 0x808, G2DMA0SIZ, PORT_MRW, 0, "G2 DMA0 Size" )3.70 + LONG_PORT( 0x80C, G2DMA0DIR, PORT_MRW, 0, "G2 DMA0 Direction" )3.71 + LONG_PORT( 0x810, G2DMA0MOD, PORT_MRW, 0, "G2 DMA0 Mode" )3.72 + LONG_PORT( 0x814, G2DMA0CTL1, PORT_MRW, 0, "G2 DMA0 Control 1" )3.73 + LONG_PORT( 0x818, G2DMA0CTL2, PORT_MRW, 0, "G2 DMA0 Control 2" )3.74 + LONG_PORT( 0x81C, G2DMA0STOP, PORT_MRW, 0x20, "G2 DMA0 Stop" )3.75 + LONG_PORT( 0x820, G2DMA1EXT, PORT_MRW, 0, "G2 DMA1 External address" )3.76 + LONG_PORT( 0x824, G2DMA1SH4, PORT_MRW, 0, "G2 DMA1 SH4-based address" )3.77 + LONG_PORT( 0x828, G2DMA1SIZ, PORT_MRW, 0, "G2 DMA1 Size" )3.78 + LONG_PORT( 0x82C, G2DMA1DIR, PORT_MRW, 0, "G2 DMA1 Direction" )3.79 + LONG_PORT( 0x830, G2DMA1MOD, PORT_MRW, 0, "G2 DMA1 Mode" )3.80 + LONG_PORT( 0x834, G2DMA1CTL1, PORT_MRW, 0, "G2 DMA1 Control 1" )3.81 + LONG_PORT( 0x838, G2DMA1CTL2, PORT_MRW, 0, "G2 DMA1 Control 2" )3.82 + LONG_PORT( 0x83C, G2DMA1STOP, PORT_MRW, 0, "G2 DMA1 Stop" )3.83 + LONG_PORT( 0x840, G2DMA2EXT, PORT_MRW, 0, "G2 DMA2 External address" )3.84 + LONG_PORT( 0x844, G2DMA2SH4, PORT_MRW, 0, "G2 DMA2 SH4-based address" )3.85 + LONG_PORT( 0x848, G2DMA2SIZ, PORT_MRW, 0, "G2 DMA2 Size" )3.86 + LONG_PORT( 0x84C, G2DMA2DIR, PORT_MRW, 0, "G2 DMA2 Direction" )3.87 + LONG_PORT( 0x850, G2DMA2MOD, PORT_MRW, 0, "G2 DMA2 Mode" )3.88 + LONG_PORT( 0x854, G2DMA2CTL1, PORT_MRW, 0, "G2 DMA2 Control 1" )3.89 + LONG_PORT( 0x858, G2DMA2CTL2, PORT_MRW, 0, "G2 DMA2 Control 2" )3.90 + LONG_PORT( 0x85C, G2DMA2STOP, PORT_MRW, 0, "G2 DMA2 Stop" )3.91 + LONG_PORT( 0x860, G2DMA3EXT, PORT_MRW, 0, "G2 DMA3 External address" )3.92 + LONG_PORT( 0x864, G2DMA3SH4, PORT_MRW, 0, "G2 DMA3 SH4-based address" )3.93 + LONG_PORT( 0x868, G2DMA3SIZ, PORT_MRW, 0, "G2 DMA3 Size" )3.94 + LONG_PORT( 0x86C, G2DMA3DIR, PORT_MRW, 0, "G2 DMA3 Direction" )3.95 + LONG_PORT( 0x870, G2DMA3MOD, PORT_MRW, 0, "G2 DMA3 Mode" )3.96 + LONG_PORT( 0x874, G2DMA3CTL1, PORT_MRW, 0, "G2 DMA3 Control 1" )3.97 + LONG_PORT( 0x878, G2DMA3CTL2, PORT_MRW, 0, "G2 DMA3 Control 2" )3.98 + LONG_PORT( 0x87C, G2DMA3STOP, PORT_MRW, 0, "G2 DMA3 Stop" )3.99 + LONG_PORT( 0x890, G2DMAWAIT, PORT_MRW, 0, "G2 DMA wait states (?)" )3.100 + LONG_PORT( 0x894, G2DMAUN1, PORT_MRW, 0, "G2 DMA <unknown1>" )3.101 + LONG_PORT( 0x898, G2DMAUN2, PORT_MRW, 0, "G2 DMA <unknown2>" )3.102 + LONG_PORT( 0x89C, G2DMAUN3, PORT_MRW, 0, "G2 DMA <unknown3>" )3.103 + LONG_PORT( 0x8A0, G2DMAUN4, PORT_MRW, 0, "G2 DMA <unknown4>" )3.104 + LONG_PORT( 0x8A4, G2DMAUN5, PORT_MRW, 0, "G2 DMA <unknown5>" )3.105 + LONG_PORT( 0x8A8, G2DMAUN6, PORT_MRW, 0, "G2 DMA <unknown6>" )3.106 + LONG_PORT( 0x8AC, G2DMAUN7, PORT_MRW, 0, "G2 DMA <unknown7>" )3.107 + LONG_PORT( 0x8B0, G2DMAUN8, PORT_MRW, 0, "G2 DMA <unknown8>" )3.108 + LONG_PORT( 0x8B4, G2DMAUN9, PORT_MRW, 0, "G2 DMA <unknown9>" )3.109 + LONG_PORT( 0x8B8, G2DMAUN10, PORT_MRW, 0, "G2 DMA <unknown10>" )3.110 + LONG_PORT( 0x8BC, G2DMACFG, PORT_MRW, 0, "G2 DMA Config" ) /* 46597F00 */3.111 LONG_PORT( 0xC00, PVRDMA2EXT, PORT_MRW, 0, "PVR DMA External address" )3.112 LONG_PORT( 0xC04, PVRDMA2SH4, PORT_MRW, 0, "PVR DMA SH4 address" )3.113 LONG_PORT( 0xC08, PVRDMA2SIZ, PORT_MRW, 0, "PVR DMA Size" )3.114 @@ -184,10 +184,10 @@3.115 #define EVENT_MAPLE_DMA 123.116 #define EVENT_MAPLE_ERR 13 /* ??? */3.117 #define EVENT_IDE_DMA 143.118 -#define EVENT_SPU_DMA0 153.119 -#define EVENT_SPU_DMA1 163.120 -#define EVENT_SPU_DMA2 173.121 -#define EVENT_SPU_DMA3 183.122 +#define EVENT_G2_DMA0 153.123 +#define EVENT_G2_DMA1 163.124 +#define EVENT_G2_DMA2 173.125 +#define EVENT_G2_DMA3 183.126 #define EVENT_PVR_DMA 193.127 #define EVENT_PVR_PUNCHOUT_DONE 21
4.1 --- a/src/sh4/sh4core.c Wed Jan 17 09:37:22 2007 +00004.2 +++ b/src/sh4/sh4core.c Wed Jan 17 21:27:20 2007 +00004.3 @@ -1,5 +1,5 @@4.4 /**4.5 - * $Id: sh4core.c,v 1.38 2007-01-11 12:14:11 nkeynes Exp $4.6 + * $Id: sh4core.c,v 1.39 2007-01-17 21:27:20 nkeynes Exp $4.7 *4.8 * SH4 emulation core, and parent module for all the SH4 peripheral4.9 * modules.4.10 @@ -205,7 +205,6 @@4.11 TMU_run_slice( nanosecs );4.12 SCIF_run_slice( nanosecs );4.13 }4.14 - sh4r.icount += sh4r.slice_cycle / sh4_cpu_period;4.15 return nanosecs;4.16 }4.18 @@ -491,7 +490,6 @@4.19 ir = sh4_icache[(pc&0xFFF)>>1];4.20 }4.21 }4.22 - sh4r.icount++;4.24 switch( (ir&0xF000)>>12 ) {4.25 case 0: /* 0000nnnnmmmmxxxx */
5.1 --- a/src/sh4/sh4core.h Wed Jan 17 09:37:22 2007 +00005.2 +++ b/src/sh4/sh4core.h Wed Jan 17 21:27:20 2007 +00005.3 @@ -1,5 +1,5 @@5.4 /**5.5 - * $Id: sh4core.h,v 1.16 2007-01-06 04:06:36 nkeynes Exp $5.6 + * $Id: sh4core.h,v 1.17 2007-01-17 21:27:20 nkeynes Exp $5.7 *5.8 * This file defines the internal functions exported/used by the SH4 core,5.9 * except for disassembly functions defined in sh4dasm.h5.10 @@ -69,13 +69,12 @@5.11 int32_t store_queue[16]; /* technically 2 banks of 32 bytes */5.13 uint32_t new_pc; /* Not a real register, but used to handle delay slots */5.14 - uint32_t icount; /* Also not a real register, instruction counter */5.15 uint32_t event_pending; /* slice cycle time of the next pending event, or FFFFFFFF5.16 when no events are pending */5.17 uint32_t event_types; /* bit 0 = IRQ pending, bit 1 = general event pending */5.18 int in_delay_slot; /* flag to indicate the current instruction is in5.19 * a delay slot (certain rules apply) */5.20 - uint32_t slice_cycle; /* Current cycle within the timeslice */5.21 + uint32_t slice_cycle; /* Current nanosecond within the timeslice */5.22 int sh4_state; /* Current power-on state (one of the SH4_STATE_* values ) */5.23 };
6.1 --- a/src/sh4/sh4dasm.c Wed Jan 17 09:37:22 2007 +00006.2 +++ b/src/sh4/sh4dasm.c Wed Jan 17 21:27:20 2007 +00006.3 @@ -1,5 +1,5 @@6.4 /**6.5 - * $Id: sh4dasm.c,v 1.9 2006-01-01 08:08:40 nkeynes Exp $6.6 + * $Id: sh4dasm.c,v 1.10 2007-01-17 21:27:20 nkeynes Exp $6.7 *6.8 * SH4 CPU definition and disassembly functions6.9 *6.10 @@ -46,7 +46,7 @@6.11 { "SH4", sh4_disasm_instruction, sh4_execute_instruction, mem_has_page,6.12 sh4_set_breakpoint, sh4_clear_breakpoint, sh4_get_breakpoint, 2,6.13 (char *)&sh4r, sizeof(sh4r), sh4_reg_map,6.14 - &sh4r.pc, &sh4r.icount };6.15 + &sh4r.pc };6.17 uint32_t sh4_disasm_instruction( uint32_t pc, char *buf, int len, char *opcode )6.18 {
.