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lxdream.org :: lxdream :: r7:976a16e92aab
lxdream 0.9.1
released Jun 29
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changeset7:976a16e92aab
parent6:6e3663e58565
child8:6730608cdaf0
authornkeynes
dateSun Dec 12 07:44:09 2004 +0000 (14 years ago)
More progress on arm
src/aica/armcore.c
src/aica/armcore.h
src/aica/armdasm.c
src/aica/armmem.c
1.1 --- a/src/aica/armcore.c Sat Oct 02 05:49:39 2004 +0000
1.2 +++ b/src/aica/armcore.c Sun Dec 12 07:44:09 2004 +0000
1.3 @@ -1,5 +1,5 @@
1.4
1.5 -#include "armcore.h"
1.6 +#include "aica/armcore.h"
1.7
1.8 struct arm_registers armr;
1.9
1.10 @@ -19,7 +19,7 @@
1.11 #define IS_SUBOVERFLOW( result, op1, op2 ) (((op1^op2) & (result^op1)) >> 31)
1.12 #define IS_ADDOVERFLOW( result, op1, op2 ) (((op1&op2) & (result^op1)) >> 31)
1.13
1.14 -#define PC armr.r[15];
1.15 +#define PC armr.r[15]
1.16
1.17 /* Instruction fields */
1.18 #define COND(ir) (ir>>28)
1.19 @@ -44,10 +44,13 @@
1.20
1.21 #define IMM8(ir) (ir&0xFF)
1.22 #define IMM12(ir) (ir&0xFFF)
1.23 -#define SHIFTIMM(ir) ((ir>>7)0x1F)
1.24 -#define IMMROT(ir) ((ir>>7)&1E)
1.25 +#define SHIFTIMM(ir) ((ir>>7)&0x1F)
1.26 +#define IMMROT(ir) ((ir>>7)&0x1E)
1.27 #define SHIFT(ir) ((ir>>4)&0x07)
1.28 #define DISP24(ir) ((ir&0x00FFFFFF))
1.29 +#define UNDEF(ir) do{ ERROR( "Raising exception on undefined instruction at %08x, opcode = %04x", PC, ir ); return; } while(0)
1.30 +#define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", PC, ir ); return; }while(0)
1.31 +
1.32
1.33 static uint32_t arm_get_shift_operand( uint32_t ir )
1.34 {
1.35 @@ -84,7 +87,7 @@
1.36 case 6:
1.37 tmp = SHIFTIMM(ir);
1.38 if( tmp == 0 ) /* RRX aka rotate with carry */
1.39 - operand = (operand >> 1) | (arm4.c<<31);
1.40 + operand = (operand >> 1) | (armr.c<<31);
1.41 else
1.42 operand = ROTATE_RIGHT_LONG(operand,tmp);
1.43 break;
1.44 @@ -185,7 +188,7 @@
1.45 tmp = SHIFTIMM(ir);
1.46 if( tmp == 0 ) { /* RRX aka rotate with carry */
1.47 armr.shift_c = operand&0x01;
1.48 - operand = (operand >> 1) | (arm4.c<<31);
1.49 + operand = (operand >> 1) | (armr.c<<31);
1.50 } else {
1.51 armr.shift_c = operand>>(tmp-1);
1.52 operand = ROTATE_RIGHT_LONG(operand,tmp);
1.53 @@ -229,6 +232,8 @@
1.54 static uint32_t arm_get_address_index( uint32_t ir )
1.55 {
1.56 uint32_t operand = RM(ir);
1.57 + uint32_t tmp;
1.58 +
1.59 switch(SHIFT(ir)) {
1.60 case 0: /* (Rm << imm) */
1.61 operand = operand << SHIFTIMM(ir);
1.62 @@ -244,7 +249,7 @@
1.63 case 6:
1.64 tmp = SHIFTIMM(ir);
1.65 if( tmp == 0 ) /* RRX aka rotate with carry */
1.66 - operand = (operand >> 1) | (arm4.c<<31);
1.67 + operand = (operand >> 1) | (armr.c<<31);
1.68 else
1.69 operand = ROTATE_RIGHT_LONG(operand,tmp);
1.70 break;
1.71 @@ -262,50 +267,50 @@
1.72 case 0: /* Rn -= imm offset (post-indexed) [5.2.8 A5-28] */
1.73 case 1:
1.74 addr = RN(ir);
1.75 - RN(ir) = addr - IMM12(ir);
1.76 + LRN(ir) = addr - IMM12(ir);
1.77 break;
1.78 case 4: /* Rn += imm offsett (post-indexed) [5.2.8 A5-28] */
1.79 case 5:
1.80 addr = RN(ir);
1.81 - RN(ir) = addr + IMM12(ir);
1.82 + LRN(ir) = addr + IMM12(ir);
1.83 break;
1.84 case 8: /* Rn - imm offset [5.2.2 A5-20] */
1.85 addr = RN(ir) - IMM12(ir);
1.86 break;
1.87 case 9: /* Rn -= imm offset (pre-indexed) [5.2.5 A5-24] */
1.88 addr = RN(ir) - IMM12(ir);
1.89 - RN(ir) = addr;
1.90 + LRN(ir) = addr;
1.91 break;
1.92 case 12: /* Rn + imm offset [5.2.2 A5-20] */
1.93 addr = RN(ir) + IMM12(ir);
1.94 break;
1.95 case 13: /* Rn += imm offset [5.2.5 A5-24 ] */
1.96 addr = RN(ir) + IMM12(ir);
1.97 - RN(ir) = addr;
1.98 + LRN(ir) = addr;
1.99 break;
1.100 case 16: /* Rn -= Rm (post-indexed) [5.2.10 A5-32 ] */
1.101 case 17:
1.102 addr = RN(ir);
1.103 - RN(ir) = addr - arm_get_address_index(ir);
1.104 + LRN(ir) = addr - arm_get_address_index(ir);
1.105 break;
1.106 case 20: /* Rn += Rm (post-indexed) [5.2.10 A5-32 ] */
1.107 case 21:
1.108 addr = RN(ir);
1.109 - RN(ir) = addr - arm_get_address_index(ir);
1.110 + LRN(ir) = addr - arm_get_address_index(ir);
1.111 break;
1.112 case 24: /* Rn - Rm [5.2.4 A5-23] */
1.113 addr = RN(ir) - arm_get_address_index(ir);
1.114 break;
1.115 case 25: /* RN -= Rm (pre-indexed) [5.2.7 A5-26] */
1.116 addr = RN(ir) - arm_get_address_index(ir);
1.117 - RN(ir) = addr;
1.118 + LRN(ir) = addr;
1.119 break;
1.120 case 28: /* Rn + Rm [5.2.4 A5-23] */
1.121 addr = RN(ir) + arm_get_address_index(ir);
1.122 break;
1.123 case 29: /* RN += Rm (pre-indexed) [5.2.7 A5-26] */
1.124 addr = RN(ir) + arm_get_address_index(ir);
1.125 - RN(ir) = addr;
1.126 + LRN(ir) = addr;
1.127 break;
1.128 default:
1.129 UNIMP(ir); /* Unreachable */
1.130 @@ -316,8 +321,8 @@
1.131 void arm_execute_instruction( void )
1.132 {
1.133 uint32_t pc = PC;
1.134 - uint32_t ir = MEM_READ_LONG(PC);
1.135 - uint32_t operand, operand2, tmp, armr.shift_c;
1.136 + uint32_t ir = MEM_READ_LONG(pc);
1.137 + uint32_t operand, operand2, tmp, cond;
1.138
1.139 pc += 4;
1.140 PC = pc;
1.141 @@ -393,7 +398,7 @@
1.142 case 0x03600000: /* MSR SPSR, imm */
1.143 break;
1.144 default:
1.145 - UNIMP();
1.146 + UNIMP(ir);
1.147 }
1.148 } else if( (ir & 0x0E000090) == 0x00000090 ) {
1.149 /* Neither are these */
1.150 @@ -460,11 +465,11 @@
1.151
1.152 switch(OPCODE(ir)) {
1.153 case 0: /* AND Rd, Rn, operand */
1.154 - RD(ir) = RN(ir) & arm_get_shift_operand(ir);
1.155 + LRD(ir) = RN(ir) & arm_get_shift_operand(ir);
1.156 break;
1.157 case 1: /* ANDS Rd, Rn, operand */
1.158 operand = arm_get_shift_operand_s(ir) & RN(ir);
1.159 - RD(ir) = operand;
1.160 + LRD(ir) = operand;
1.161 if( RDn(ir) == 15 ) {
1.162 arm_restore_cpsr();
1.163 } else {
1.164 @@ -474,11 +479,11 @@
1.165 }
1.166 break;
1.167 case 2: /* EOR Rd, Rn, operand */
1.168 - RD(ir) = RN(ir) ^ arm_get_shift_operand(ir);
1.169 + LRD(ir) = RN(ir) ^ arm_get_shift_operand(ir);
1.170 break;
1.171 case 3: /* EORS Rd, Rn, operand */
1.172 operand = arm_get_shift_operand_s(ir) ^ RN(ir);
1.173 - RD(ir) = operand;
1.174 + LRD(ir) = operand;
1.175 if( RDn(ir) == 15 ) {
1.176 arm_restore_cpsr();
1.177 } else {
1.178 @@ -488,13 +493,13 @@
1.179 }
1.180 break;
1.181 case 4: /* SUB Rd, Rn, operand */
1.182 - RD(ir) = RN(ir) - arm_get_shift_operand(ir);
1.183 + LRD(ir) = RN(ir) - arm_get_shift_operand(ir);
1.184 break;
1.185 case 5: /* SUBS Rd, Rn, operand */
1.186 operand = RN(ir);
1.187 - operand2 = arm_get_shift_operand(ir)
1.188 + operand2 = arm_get_shift_operand(ir);
1.189 tmp = operand - operand2;
1.190 - RD(ir) = tmp;
1.191 + LRD(ir) = tmp;
1.192 if( RDn(ir) == 15 ) {
1.193 arm_restore_cpsr();
1.194 } else {
1.195 @@ -505,13 +510,13 @@
1.196 }
1.197 break;
1.198 case 6: /* RSB Rd, operand, Rn */
1.199 - RD(ir) = arm_get_shift_operand(ir) - RN(ir);
1.200 + LRD(ir) = arm_get_shift_operand(ir) - RN(ir);
1.201 break;
1.202 case 7: /* RSBS Rd, operand, Rn */
1.203 operand = arm_get_shift_operand(ir);
1.204 operand2 = RN(ir);
1.205 tmp = operand - operand2;
1.206 - RD(ir) = tmp;
1.207 + LRD(ir) = tmp;
1.208 if( RDn(ir) == 15 ) {
1.209 arm_restore_cpsr();
1.210 } else {
1.211 @@ -522,13 +527,13 @@
1.212 }
1.213 break;
1.214 case 8: /* ADD Rd, Rn, operand */
1.215 - RD(ir) = RN(ir) + arm_get_shift_operand(ir);
1.216 + LRD(ir) = RN(ir) + arm_get_shift_operand(ir);
1.217 break;
1.218 case 9: /* ADDS Rd, Rn, operand */
1.219 operand = arm_get_shift_operand(ir);
1.220 operand2 = RN(ir);
1.221 - tmp = operand + operand2
1.222 - RD(ir) = tmp;
1.223 + tmp = operand + operand2;
1.224 + LRD(ir) = tmp;
1.225 if( RDn(ir) == 15 ) {
1.226 arm_restore_cpsr();
1.227 } else {
1.228 @@ -559,7 +564,7 @@
1.229 break;
1.230 case 21: /* CMP Rn, operand */
1.231 operand = RN(ir);
1.232 - operand2 = arm_get_shift_operand(ir)
1.233 + operand2 = arm_get_shift_operand(ir);
1.234 tmp = operand - operand2;
1.235 armr.n = tmp>>31;
1.236 armr.z = (tmp == 0);
1.237 @@ -568,7 +573,7 @@
1.238 break;
1.239 case 23: /* CMN Rn, operand */
1.240 operand = RN(ir);
1.241 - operand2 = arm_get_shift_operand(ir)
1.242 + operand2 = arm_get_shift_operand(ir);
1.243 tmp = operand + operand2;
1.244 armr.n = tmp>>31;
1.245 armr.z = (tmp == 0);
1.246 @@ -576,11 +581,11 @@
1.247 armr.v = IS_ADDOVERFLOW(tmp,operand,operand2);
1.248 break;
1.249 case 24: /* ORR Rd, Rn, operand */
1.250 - RD(ir) = RN(ir) | arm_get_shift_operand(ir);
1.251 + LRD(ir) = RN(ir) | arm_get_shift_operand(ir);
1.252 break;
1.253 case 25: /* ORRS Rd, Rn, operand */
1.254 operand = arm_get_shift_operand_s(ir) | RN(ir);
1.255 - RD(ir) = operand;
1.256 + LRD(ir) = operand;
1.257 if( RDn(ir) == 15 ) {
1.258 arm_restore_cpsr();
1.259 } else {
1.260 @@ -590,11 +595,11 @@
1.261 }
1.262 break;
1.263 case 26: /* MOV Rd, operand */
1.264 - RD(ir) = arm_get_shift_operand(ir);
1.265 + LRD(ir) = arm_get_shift_operand(ir);
1.266 break;
1.267 case 27: /* MOVS Rd, operand */
1.268 operand = arm_get_shift_operand_s(ir);
1.269 - RD(ir) = operand;
1.270 + LRD(ir) = operand;
1.271 if( RDn(ir) == 15 ) {
1.272 arm_restore_cpsr();
1.273 } else {
1.274 @@ -604,11 +609,11 @@
1.275 }
1.276 break;
1.277 case 28: /* BIC Rd, Rn, operand */
1.278 - RD(ir) = RN(ir) & (~arm_get_shift_operand(ir));
1.279 + LRD(ir) = RN(ir) & (~arm_get_shift_operand(ir));
1.280 break;
1.281 case 29: /* BICS Rd, Rn, operand */
1.282 operand = RN(ir) & (~arm_get_shift_operand_s(ir));
1.283 - RD(ir) = operand;
1.284 + LRD(ir) = operand;
1.285 if( RDn(ir) == 15 ) {
1.286 arm_restore_cpsr();
1.287 } else {
1.288 @@ -618,11 +623,11 @@
1.289 }
1.290 break;
1.291 case 30: /* MVN Rd, operand */
1.292 - RD(ir) = ~arm_get_shift_operand(ir);
1.293 + LRD(ir) = ~arm_get_shift_operand(ir);
1.294 break;
1.295 case 31: /* MVNS Rd, operand */
1.296 operand = ~arm_get_shift_operand_s(ir);
1.297 - RD(ir) = operand;
1.298 + LRD(ir) = operand;
1.299 if( RDn(ir) == 15 ) {
1.300 arm_restore_cpsr();
1.301 } else {
1.302 @@ -644,4 +649,3 @@
1.303 break;
1.304 }
1.305 }
1.306 -
2.1 --- a/src/aica/armcore.h Sat Oct 02 05:49:39 2004 +0000
2.2 +++ b/src/aica/armcore.h Sun Dec 12 07:44:09 2004 +0000
2.3 @@ -5,7 +5,7 @@
2.4 #include "dream.h"
2.5 #include <stdint.h>
2.6
2.7 -
2.8 +#define ROTATE_RIGHT_LONG(operand,shift) ((((uint32_t)operand) >> shift) | ((operand<<(32-shift))) )
2.9
2.10 struct arm_registers {
2.11 uint32_t r[16]; /* Current register bank */
3.1 --- a/src/aica/armdasm.c Sat Oct 02 05:49:39 2004 +0000
3.2 +++ b/src/aica/armdasm.c Sun Dec 12 07:44:09 2004 +0000
3.3 @@ -5,7 +5,8 @@
3.4 * under the terms of the GNU General Public License version 2 or later.
3.5 */
3.6
3.7 -#include "armcore.h"
3.8 +#include "aica/armcore.h"
3.9 +#include <stdlib.h>
3.10
3.11 #define COND(ir) (ir>>28)
3.12 #define OPCODE(ir) ((ir>>20)&0x1F)
3.13 @@ -15,7 +16,7 @@
3.14 #define PFLAG(ir) (ir&0x01000000)
3.15 #define UFLAG(ir) (ir&0x00800000)
3.16 #define BFLAG(ir) (ir&0x00400000)
3.17 -#define WFLAG(ir) (IR&0x00200000)
3.18 +#define WFLAG(ir) (ir&0x00200000)
3.19 #define LFLAG(ir) SFLAG(ir)
3.20 #define RN(ir) ((ir>>16)&0x0F)
3.21 #define RD(ir) ((ir>>12)&0x0F)
3.22 @@ -24,8 +25,8 @@
3.23
3.24 #define IMM8(ir) (ir&0xFF)
3.25 #define IMM12(ir) (ir&0xFFF)
3.26 -#define SHIFTIMM(ir) ((ir>>7)0x1F)
3.27 -#define IMMROT(ir) ((ir>>7)&1E)
3.28 +#define SHIFTIMM(ir) ((ir>>7)&0x1F)
3.29 +#define IMMROT(ir) ((ir>>7)&0x1E)
3.30 #define SHIFT(ir) ((ir>>4)&0x07)
3.31 #define DISP24(ir) ((ir&0x00FFFFFF))
3.32 #define FSXC(ir) msrFieldMask[RN(ir)]
3.33 @@ -37,13 +38,101 @@
3.34 /* fsxc */
3.35 char *msrFieldMask[] = { "", "c", "x", "xc", "s", "sc", "sx", "sxc",
3.36 "f", "fc", "fx", "fxc", "fs", "fsc", "fsx", "fsxc" };
3.37 +char *ldmModes[] = { "DA", "IA", "DB", "IB" };
3.38
3.39 #define UNIMP(ir) snprintf( buf, len, "??? " )
3.40
3.41 -int arm_disasm_instruction( int pc, char *buf, int len )
3.42 +int arm_disasm_shift_operand( uint32_t ir, char *buf, int len )
3.43 {
3.44 + uint32_t operand, tmp;
3.45 + if( IFLAG(ir) == 0 ) {
3.46 + switch(SHIFT(ir)) {
3.47 + case 0: /* (Rm << imm) */
3.48 + return snprintf(buf, len, "R%d << %d", RM(ir), SHIFTIMM(ir) );
3.49 + case 1: /* (Rm << Rs) */
3.50 + return snprintf(buf, len, "R%d << R%d", RM(ir), RS(ir) );
3.51 + case 2: /* (Rm >> imm) */
3.52 + return snprintf(buf, len, "R%d >> %d", RM(ir), SHIFTIMM(ir) );
3.53 + case 3: /* (Rm >> Rs) */
3.54 + return snprintf(buf, len, "R%d >> R%d", RM(ir), RS(ir) );
3.55 + case 4: /* (Rm >>> imm) */
3.56 + return snprintf(buf, len, "R%d >>> %d", RM(ir), SHIFTIMM(ir) );
3.57 + case 5: /* (Rm >>> Rs) */
3.58 + return snprintf(buf, len, "R%d >>> R%d", RM(ir), RS(ir) );
3.59 + case 6:
3.60 + tmp = SHIFTIMM(ir);
3.61 + if( tmp == 0 ) /* RRX aka rotate with carry */
3.62 + return snprintf(buf, len, "R%d roc 1", RM(ir) );
3.63 + else
3.64 + return snprintf(buf, len, "R%d rot %d", RM(ir), SHIFTIMM(ir) );
3.65 + case 7:
3.66 + return snprintf(buf, len, "R%d rot R%d", RM(ir), RS(ir) );
3.67 + }
3.68 + } else {
3.69 + operand = IMM8(ir);
3.70 + tmp = IMMROT(ir);
3.71 + operand = ROTATE_RIGHT_LONG(operand, tmp);
3.72 + return snprintf(buf, len, "%08X", operand );
3.73 + }
3.74 +}
3.75 +
3.76 +static int arm_disasm_address_index( uint32_t ir, char *buf, int len )
3.77 +{
3.78 + uint32_t tmp;
3.79 +
3.80 + switch(SHIFT(ir)) {
3.81 + case 0: /* (Rm << imm) */
3.82 + return snprintf( buf, len, "R%d << %d", RM(ir), SHIFTIMM(ir) );
3.83 + case 2: /* (Rm >> imm) */
3.84 + return snprintf( buf, len, "R%d >> %d", RM(ir), SHIFTIMM(ir) );
3.85 + case 4: /* (Rm >>> imm) */
3.86 + return snprintf( buf, len, "R%d >>> %d", RM(ir), SHIFTIMM(ir) );
3.87 + case 6:
3.88 + tmp = SHIFTIMM(ir);
3.89 + if( tmp == 0 ) /* RRX aka rotate with carry */
3.90 + return snprintf( buf, len, "R%d roc 1", RM(ir) );
3.91 + else
3.92 + return snprintf( buf, len, "R%d rot %d", RM(ir), tmp );
3.93 + default:
3.94 + return UNIMP(ir);
3.95 + }
3.96 +}
3.97 +
3.98 +static int arm_disasm_address_operand( uint32_t ir, char *buf, int len )
3.99 +{
3.100 + char shift[32];
3.101 +
3.102 + char sign = UFLAG(ir) ? '-' : '+';
3.103 + /* I P U . W */
3.104 + switch( (ir>>21)&0x19 ) {
3.105 + case 0: /* Rn -= imm offset (post-indexed) [5.2.8 A5-28] */
3.106 + case 1:
3.107 + return snprintf( buf, len, "[R%d], R%d %c= %04X", RN(ir), RN(ir), sign, IMM12(ir) );
3.108 + case 8: /* Rn - imm offset [5.2.2 A5-20] */
3.109 + return snprintf( buf, len, "[R%d %c %04X]", RN(ir), sign, IMM12(ir) );
3.110 + case 9: /* Rn -= imm offset (pre-indexed) [5.2.5 A5-24] */
3.111 + return snprintf( buf, len, "[R%d %c= %04X]", RN(ir), sign, IMM12(ir) );
3.112 + case 16: /* Rn -= Rm (post-indexed) [5.2.10 A5-32 ] */
3.113 + case 17:
3.114 + arm_disasm_address_index( ir, shift, sizeof(shift) );
3.115 + return snprintf( buf, len, "[R%d], R%d %c= %s", RN(ir), RN(ir), sign, shift );
3.116 + case 24: /* Rn - Rm [5.2.4 A5-23] */
3.117 + arm_disasm_address_index( ir, shift, sizeof(shift) );
3.118 + return snprintf( buf, len, "[R%d %c %s]", RN(ir), sign, shift );
3.119 + case 25: /* RN -= Rm (pre-indexed) [5.2.7 A5-26] */
3.120 + arm_disasm_address_index( ir, shift, sizeof(shift) );
3.121 + return snprintf( buf, len, "[R%d %c= %s]", RN(ir), sign, shift );
3.122 + default:
3.123 + return UNIMP(ir); /* Unreachable */
3.124 + }
3.125 +}
3.126 +
3.127 +int arm_disasm_instruction( uint32_t pc, char *buf, int len )
3.128 +{
3.129 + char operand[32];
3.130 uint32_t ir = arm_mem_read_long(pc);
3.131 -
3.132 + int i,j;
3.133 +
3.134 if( COND(ir) == 0x0F ) {
3.135 UNIMP(ir);
3.136 return pc+4;
3.137 @@ -153,176 +242,116 @@
3.138
3.139 switch(OPCODE(ir)) {
3.140 case 0: /* AND Rd, Rn, operand */
3.141 - RD(ir) = RN(ir) & arm_get_shift_operand(ir);
3.142 + arm_disasm_shift_operand(ir, operand, sizeof(operand));
3.143 + snprintf(buf, len, "AND%s R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
3.144 break;
3.145 case 1: /* ANDS Rd, Rn, operand */
3.146 - operand = arm_get_shift_operand_s(ir) & RN(ir);
3.147 - RD(ir) = operand;
3.148 - if( RDn(ir) == 15 ) {
3.149 - arm_restore_cpsr();
3.150 - } else {
3.151 - armr.n = operand>>31;
3.152 - armr.z = (operand == 0);
3.153 - armr.c = armr.shift_c;
3.154 - }
3.155 + arm_disasm_shift_operand(ir, operand, sizeof(operand));
3.156 + snprintf(buf, len, "ANDS%s R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
3.157 break;
3.158 case 2: /* EOR Rd, Rn, operand */
3.159 - RD(ir) = RN(ir) ^ arm_get_shift_operand(ir);
3.160 + arm_disasm_shift_operand(ir, operand, sizeof(operand));
3.161 + snprintf(buf, len, "EOR%s R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
3.162 break;
3.163 case 3: /* EORS Rd, Rn, operand */
3.164 - operand = arm_get_shift_operand_s(ir) ^ RN(ir);
3.165 - RD(ir) = operand;
3.166 - if( RDn(ir) == 15 ) {
3.167 - arm_restore_cpsr();
3.168 - } else {
3.169 - armr.n = operand>>31;
3.170 - armr.z = (operand == 0);
3.171 - armr.c = armr.shift_c;
3.172 - }
3.173 + arm_disasm_shift_operand(ir, operand, sizeof(operand));
3.174 + snprintf(buf, len, "EORS%s R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
3.175 break;
3.176 case 4: /* SUB Rd, Rn, operand */
3.177 - RD(ir) = RN(ir) - arm_get_shift_operand(ir);
3.178 + arm_disasm_shift_operand(ir, operand, sizeof(operand));
3.179 + snprintf(buf, len, "SUB%s R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
3.180 break;
3.181 case 5: /* SUBS Rd, Rn, operand */
3.182 - operand = RN(ir);
3.183 - operand2 = arm_get_shift_operand(ir)
3.184 - tmp = operand - operand2;
3.185 - RD(ir) = tmp;
3.186 - if( RDn(ir) == 15 ) {
3.187 - arm_restore_cpsr();
3.188 - } else {
3.189 - armr.n = tmp>>31;
3.190 - armr.z = (tmp == 0);
3.191 - armr.c = IS_NOTBORROW(tmp,operand,operand2);
3.192 - armr.v = IS_SUBOVERFLOW(tmp,operand,operand2);
3.193 - }
3.194 + arm_disasm_shift_operand(ir, operand, sizeof(operand));
3.195 + snprintf(buf, len, "SUBS%s R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
3.196 break;
3.197 - case 6: /* RSB Rd, operand, Rn */
3.198 - RD(ir) = arm_get_shift_operand(ir) - RN(ir);
3.199 + case 6: /* RSB Rd, Rn, operand */
3.200 + arm_disasm_shift_operand(ir, operand, sizeof(operand));
3.201 + snprintf(buf, len, "RSB%s R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
3.202 break;
3.203 - case 7: /* RSBS Rd, operand, Rn */
3.204 - operand = arm_get_shift_operand(ir);
3.205 - operand2 = RN(ir);
3.206 - tmp = operand - operand2;
3.207 - RD(ir) = tmp;
3.208 - if( RDn(ir) == 15 ) {
3.209 - arm_restore_cpsr();
3.210 - } else {
3.211 - armr.n = tmp>>31;
3.212 - armr.z = (tmp == 0);
3.213 - armr.c = IS_NOTBORROW(tmp,operand,operand2);
3.214 - armr.v = IS_SUBOVERFLOW(tmp,operand,operand2);
3.215 - }
3.216 + case 7: /* RSBS Rd, Rn, operand */
3.217 + arm_disasm_shift_operand(ir, operand, sizeof(operand));
3.218 + snprintf(buf, len, "RSBS%s R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
3.219 break;
3.220 case 8: /* ADD Rd, Rn, operand */
3.221 - RD(ir) = RN(ir) + arm_get_shift_operand(ir);
3.222 + arm_disasm_shift_operand(ir, operand, sizeof(operand));
3.223 + snprintf(buf, len, "ADD%s R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
3.224 break;
3.225 case 9: /* ADDS Rd, Rn, operand */
3.226 - operand = arm_get_shift_operand(ir);
3.227 - operand2 = RN(ir);
3.228 - tmp = operand + operand2
3.229 - RD(ir) = tmp;
3.230 - if( RDn(ir) == 15 ) {
3.231 - arm_restore_cpsr();
3.232 - } else {
3.233 - armr.n = tmp>>31;
3.234 - armr.z = (tmp == 0);
3.235 - armr.c = IS_CARRY(tmp,operand,operand2);
3.236 - armr.v = IS_ADDOVERFLOW(tmp,operand,operand2);
3.237 - }
3.238 - break;
3.239 - case 10: /* ADC */
3.240 - case 11: /* ADCS */
3.241 - case 12: /* SBC */
3.242 - case 13: /* SBCS */
3.243 - case 14: /* RSC */
3.244 - case 15: /* RSCS */
3.245 + arm_disasm_shift_operand(ir, operand, sizeof(operand));
3.246 + snprintf(buf, len, "ADDS%s R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
3.247 break;
3.248 - case 17: /* TST Rn, operand */
3.249 - operand = arm_get_shift_operand_s(ir) & RN(ir);
3.250 - armr.n = operand>>31;
3.251 - armr.z = (operand == 0);
3.252 - armr.c = armr.shift_c;
3.253 + case 10: /* ADC Rd, Rn, operand */
3.254 + arm_disasm_shift_operand(ir, operand, sizeof(operand));
3.255 + snprintf(buf, len, "ADC%s R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
3.256 break;
3.257 - case 19: /* TEQ Rn, operand */
3.258 - operand = arm_get_shift_operand_s(ir) ^ RN(ir);
3.259 - armr.n = operand>>31;
3.260 - armr.z = (operand == 0);
3.261 - armr.c = armr.shift_c;
3.262 - break;
3.263 - case 21: /* CMP Rn, operand */
3.264 - operand = RN(ir);
3.265 - operand2 = arm_get_shift_operand(ir)
3.266 - tmp = operand - operand2;
3.267 - armr.n = tmp>>31;
3.268 - armr.z = (tmp == 0);
3.269 - armr.c = IS_NOTBORROW(tmp,operand,operand2);
3.270 - armr.v = IS_SUBOVERFLOW(tmp,operand,operand2);
3.271 + case 11: /* ADCS Rd, Rn, operand */
3.272 + arm_disasm_shift_operand(ir, operand, sizeof(operand));
3.273 + snprintf(buf, len, "ADCS%s R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
3.274 break;
3.275 - case 23: /* CMN Rn, operand */
3.276 - operand = RN(ir);
3.277 - operand2 = arm_get_shift_operand(ir)
3.278 - tmp = operand + operand2;
3.279 - armr.n = tmp>>31;
3.280 - armr.z = (tmp == 0);
3.281 - armr.c = IS_CARRY(tmp,operand,operand2);
3.282 - armr.v = IS_ADDOVERFLOW(tmp,operand,operand2);
3.283 + case 12: /* SBC Rd, Rn, operand */
3.284 + arm_disasm_shift_operand(ir, operand, sizeof(operand));
3.285 + snprintf(buf, len, "SBC%s R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
3.286 + break;
3.287 + case 13: /* SBCS Rd, Rn, operand */
3.288 + arm_disasm_shift_operand(ir, operand, sizeof(operand));
3.289 + snprintf(buf, len, "SBCS%s R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
3.290 + break;
3.291 + case 14: /* RSC Rd, Rn, operand */
3.292 + arm_disasm_shift_operand(ir, operand, sizeof(operand));
3.293 + snprintf(buf, len, "RSC%s R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
3.294 + break;
3.295 + case 15: /* RSCS Rd, Rn, operand */
3.296 + arm_disasm_shift_operand(ir, operand, sizeof(operand));
3.297 + snprintf(buf, len, "RSCS%s R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
3.298 + break;
3.299 + case 16: /* TST Rd, Rn, operand */
3.300 + arm_disasm_shift_operand(ir, operand, sizeof(operand));
3.301 + snprintf(buf, len, "TST%s R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
3.302 + break;
3.303 + case 18: /* TEQ Rd, Rn, operand */
3.304 + arm_disasm_shift_operand(ir, operand, sizeof(operand));
3.305 + snprintf(buf, len, "TEQ%s R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
3.306 + break;
3.307 + case 20: /* CMP Rd, Rn, operand */
3.308 + arm_disasm_shift_operand(ir, operand, sizeof(operand));
3.309 + snprintf(buf, len, "CMP%s R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
3.310 + break;
3.311 + case 22: /* CMN Rd, Rn, operand */
3.312 + arm_disasm_shift_operand(ir, operand, sizeof(operand));
3.313 + snprintf(buf, len, "CMN%s R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
3.314 break;
3.315 case 24: /* ORR Rd, Rn, operand */
3.316 - RD(ir) = RN(ir) | arm_get_shift_operand(ir);
3.317 + arm_disasm_shift_operand(ir, operand, sizeof(operand));
3.318 + snprintf(buf, len, "ORR%s R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
3.319 break;
3.320 case 25: /* ORRS Rd, Rn, operand */
3.321 - operand = arm_get_shift_operand_s(ir) | RN(ir);
3.322 - RD(ir) = operand;
3.323 - if( RDn(ir) == 15 ) {
3.324 - arm_restore_cpsr();
3.325 - } else {
3.326 - armr.n = operand>>31;
3.327 - armr.z = (operand == 0);
3.328 - armr.c = armr.shift_c;
3.329 - }
3.330 + arm_disasm_shift_operand(ir, operand, sizeof(operand));
3.331 + snprintf(buf, len, "ORRS%s R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
3.332 break;
3.333 - case 26: /* MOV Rd, operand */
3.334 - RD(ir) = arm_get_shift_operand(ir);
3.335 + case 26: /* MOV Rd, Rn, operand */
3.336 + arm_disasm_shift_operand(ir, operand, sizeof(operand));
3.337 + snprintf(buf, len, "MOV%s R%d, %s", cond, RD(ir), operand);
3.338 break;
3.339 - case 27: /* MOVS Rd, operand */
3.340 - operand = arm_get_shift_operand_s(ir);
3.341 - RD(ir) = operand;
3.342 - if( RDn(ir) == 15 ) {
3.343 - arm_restore_cpsr();
3.344 - } else {
3.345 - armr.n = operand>>31;
3.346 - armr.z = (operand == 0);
3.347 - armr.c = armr.shift_c;
3.348 - }
3.349 + case 27: /* MOVS Rd, Rn, operand */
3.350 + arm_disasm_shift_operand(ir, operand, sizeof(operand));
3.351 + snprintf(buf, len, "MOVS%s R%d, %s", cond, RD(ir), operand);
3.352 break;
3.353 case 28: /* BIC Rd, Rn, operand */
3.354 - RD(ir) = RN(ir) & (~arm_get_shift_operand(ir));
3.355 + arm_disasm_shift_operand(ir, operand, sizeof(operand));
3.356 + snprintf(buf, len, "BIC%s R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
3.357 break;
3.358 case 29: /* BICS Rd, Rn, operand */
3.359 - operand = RN(ir) & (~arm_get_shift_operand_s(ir));
3.360 - RD(ir) = operand;
3.361 - if( RDn(ir) == 15 ) {
3.362 - arm_restore_cpsr();
3.363 - } else {
3.364 - armr.n = operand>>31;
3.365 - armr.z = (operand == 0);
3.366 - armr.c = armr.shift_c;
3.367 - }
3.368 + arm_disasm_shift_operand(ir, operand, sizeof(operand));
3.369 + snprintf(buf, len, "BICS%s R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
3.370 break;
3.371 - case 30: /* MVN Rd, operand */
3.372 - RD(ir) = ~arm_get_shift_operand(ir);
3.373 + case 30: /* MVN Rd, Rn, operand */
3.374 + arm_disasm_shift_operand(ir, operand, sizeof(operand));
3.375 + snprintf(buf, len, "MVN%s R%d, %s", cond, RD(ir), operand);
3.376 break;
3.377 - case 31: /* MVNS Rd, operand */
3.378 - operand = ~arm_get_shift_operand_s(ir);
3.379 - RD(ir) = operand;
3.380 - if( RDn(ir) == 15 ) {
3.381 - arm_restore_cpsr();
3.382 - } else {
3.383 - armr.n = operand>>31;
3.384 - armr.z = (operand == 0);
3.385 - armr.c = armr.shift_c;
3.386 - }
3.387 + case 31: /* MVNS Rd, Rn, operand */
3.388 + arm_disasm_shift_operand(ir, operand, sizeof(operand));
3.389 + snprintf(buf, len, "MVNS%s R%d, %s", cond, RD(ir), operand);
3.390 break;
3.391 default:
3.392 UNIMP(ir);
3.393 @@ -330,10 +359,61 @@
3.394 }
3.395 break;
3.396 case 1: /* Load/store */
3.397 + arm_disasm_address_operand( ir, operand, sizeof(operand) );
3.398 + switch( (ir>>20)&0x17 ) {
3.399 + case 0:
3.400 + case 16:
3.401 + case 18:
3.402 + snprintf(buf, len, "STR%s R%d, %s", cond, RD(ir), operand );
3.403 + break;
3.404 + case 1:
3.405 + case 17:
3.406 + case 19:
3.407 + snprintf(buf, len, "LDR%s R%d, %s", cond, RD(ir), operand );
3.408 + break;
3.409 + case 2:
3.410 + snprintf(buf, len, "STRT%s R%d, %s", cond, RD(ir), operand );
3.411 + break;
3.412 + case 3:
3.413 + snprintf(buf, len, "LDRT%s R%d, %s", cond, RD(ir), operand );
3.414 + break;
3.415 + case 4:
3.416 + case 20:
3.417 + case 22:
3.418 + snprintf(buf, len, "STRB%s R%d, %s", cond, RD(ir), operand );
3.419 + break;
3.420 + case 5:
3.421 + case 21:
3.422 + case 23:
3.423 + snprintf(buf, len, "LDRB%s R%d, %s", cond, RD(ir), operand );
3.424 + break;
3.425 + case 6:
3.426 + snprintf(buf, len, "STRBT%s R%d, %s", cond, RD(ir), operand );
3.427 + break;
3.428 + case 7:
3.429 + snprintf(buf, len, "LDRBT%s R%d, %s", cond, RD(ir), operand );
3.430 + break;
3.431 + }
3.432 break;
3.433 case 2: /* Load/store multiple, branch*/
3.434 + j = snprintf( buf, len, LFLAG(ir) ? "LDM%s%s R%d%c,":"STM%s%s R%d%c,",
3.435 + ldmModes[(ir>>23)&0x03], cond, RN(ir), WFLAG(ir)?'!':' ' );
3.436 + buf += j;
3.437 + len -= j;
3.438 + for( i = 0; i<16 && len > 2; i++ ) {
3.439 + if( (ir >> i)&1 ) {
3.440 + j = snprintf( buf, len, "R%d", i );
3.441 + buf+=j;
3.442 + len-=j;
3.443 + }
3.444 + }
3.445 + if( SFLAG(ir) && len > 0 ) {
3.446 + buf[0] = '^';
3.447 + buf[1] = '\0';
3.448 + }
3.449 break;
3.450 case 3: /* Copro */
3.451 + UNIMP(ir);
3.452 break;
3.453 }
3.454
4.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
4.2 +++ b/src/aica/armmem.c Sun Dec 12 07:44:09 2004 +0000
4.3 @@ -0,0 +1,16 @@
4.4 +#include "mem.h"
4.5 +
4.6 +void arm_mem_init() {
4.7 +
4.8 +}
4.9 +
4.10 +uint32_t arm_mem_read_long( uint32_t addr ) {
4.11 +}
4.12 +
4.13 +uint32_t arm_mem_read_byte( uint32_t addr ) {
4.14 +}
4.15 +
4.16 +uint32_t arm_mem_read_long_user( uint32_t addr ) {
4.17 +}
4.18 +
4.19 +uint32_t arm_mem_read_byte_user( uint32_t addr ) {
.