1.1 --- a/src/sh4/sh4core.c	Mon Dec 26 06:38:51 2005 +0000
     1.2 +++ b/src/sh4/sh4core.c	Mon Dec 26 10:47:10 2005 +0000
     1.3 @@ -1,5 +1,5 @@
     1.4  /**
     1.5 - * $Id: sh4core.c,v 1.14 2005-12-26 06:38:13 nkeynes Exp $
     1.6 + * $Id: sh4core.c,v 1.15 2005-12-26 10:47:10 nkeynes Exp $
     1.7   * 
     1.8   * SH4 emulation core, and parent module for all the SH4 peripheral
     1.9   * modules.
    1.10 @@ -343,8 +343,8 @@
    1.11                                  uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
    1.12                                  uint32_t target = tmp&0x03FFFFE0 | hi;
    1.13                                  mem_copy_to_sh4( target, src, 32 );
    1.14 -                                WARN( "Executed SQ%c => %08X",
    1.15 -                                      (queue == 0 ? '0' : '1'), target );
    1.16 +				//                                WARN( "Executed SQ%c => %08X",
    1.17 +				//                                      (queue == 0 ? '0' : '1'), target );
    1.18                              }
    1.19                              break;
    1.20                          case 9: /* OCBI    [Rn] */

     2.1 --- a/src/sh4/sh4mem.c	Mon Dec 26 06:38:51 2005 +0000
     2.2 +++ b/src/sh4/sh4mem.c	Mon Dec 26 10:47:10 2005 +0000
     2.3 @@ -1,5 +1,5 @@
     2.4  /**
     2.5 - * $Id: sh4mem.c,v 1.2 2005-12-26 03:54:55 nkeynes Exp $
     2.6 + * $Id: sh4mem.c,v 1.3 2005-12-26 10:47:10 nkeynes Exp $
     2.7   * sh4mem.c is responsible for the SH4's access to memory (including memory
     2.8   * mapped I/O), using the page maps created in mem.c
     2.9   *
    2.10 @@ -73,7 +73,9 @@
    2.11          if( (addr & 0xFC000000) == 0xE0000000 ) {
    2.12              /* Store queue */
    2.13              SH4_WRITE_STORE_QUEUE( addr, val );
    2.14 -        } else {
    2.15 +        } else if( (addr & 0xFF000000) != 0xF4000000 ) {
    2.16 +	    /* OC address cache isn't implemented, but don't complain about it.
    2.17 +	     * Complain about anything else though */
    2.18              ERROR( "Attempted write to unknown P4 region: %08X", addr );
    2.19          }
    2.20      } else {