revision 19:9da7a8e38f9d
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raw | bz2 | zip | gz changeset | 19:9da7a8e38f9d |
parent | 18:9a1b5d75703f |
child | 20:3ffb66aa25c7 |
author | nkeynes |
date | Thu Dec 22 07:38:12 2005 +0000 (18 years ago) |
Implement 95% of the SCIF serial interface
Implement basic load_bin_file function to try to load demos directly
Update TMU to run all 3 timers, start on general timing
Implement basic load_bin_file function to try to load demos directly
Update TMU to run all 3 timers, start on general timing
src/Makefile.am | view | annotate | diff | log | ||
src/Makefile.in | view | annotate | diff | log | ||
src/clock.h | view | annotate | diff | log | ||
src/dreamcast.h | view | annotate | diff | log | ||
src/gui/callbacks.c | view | annotate | diff | log | ||
src/loader.c | view | annotate | diff | log | ||
src/mem.c | view | annotate | diff | log | ||
src/mem.h | view | annotate | diff | log | ||
src/pvr2/pvr2.c | view | annotate | diff | log | ||
src/pvr2/pvr2.h | view | annotate | diff | log | ||
src/serial.h | view | annotate | diff | log | ||
src/sh4/intc.c | view | annotate | diff | log | ||
src/sh4/sh4core.c | view | annotate | diff | log | ||
src/sh4/sh4mmio.c | view | annotate | diff | log | ||
src/sh4/sh4mmio.h | view | annotate | diff | log |
1.1 --- a/src/Makefile.am Thu Dec 15 13:33:14 2005 +00001.2 +++ b/src/Makefile.am Thu Dec 22 07:38:12 2005 +00001.3 @@ -20,7 +20,7 @@1.4 maple.c maple.h maple/controller.c maple/controller.h \1.5 sh4/intc.c sh4/intc.h sh4/sh4mem.c \1.6 sh4/sh4core.c sh4/sh4core.h sh4/sh4dasm.c sh4/sh4dasm.h \1.7 - sh4/sh4mmio.c sh4/sh4mmio.h sh4/watch.c \1.8 + sh4/sh4mmio.c sh4/sh4mmio.h sh4/scif.c sh4/watch.c \1.9 aica/armcore.c aica/armcore.h aica/armdasm.c aica/armmem.c \1.10 aica/aica.c aica/aica.h \1.11 fileio.c ipbin.c util.c
2.1 --- a/src/Makefile.in Thu Dec 15 13:33:14 2005 +00002.2 +++ b/src/Makefile.in Thu Dec 22 07:38:12 2005 +00002.3 @@ -147,7 +147,7 @@2.4 maple.c maple.h maple/controller.c maple/controller.h \2.5 sh4/intc.c sh4/intc.h sh4/sh4mem.c \2.6 sh4/sh4core.c sh4/sh4core.h sh4/sh4dasm.c sh4/sh4dasm.h \2.7 - sh4/sh4mmio.c sh4/sh4mmio.h sh4/watch.c \2.8 + sh4/sh4mmio.c sh4/sh4mmio.h sh4/scif.c sh4/watch.c \2.9 aica/armcore.c aica/armcore.h aica/armdasm.c aica/armmem.c \2.10 aica/aica.c aica/aica.h \2.11 fileio.c ipbin.c util.c2.12 @@ -170,9 +170,10 @@2.13 asic.$(OBJEXT) pvr2.$(OBJEXT) ide.$(OBJEXT) video.$(OBJEXT) \2.14 dreamcast.$(OBJEXT) maple.$(OBJEXT) controller.$(OBJEXT) \2.15 intc.$(OBJEXT) sh4mem.$(OBJEXT) sh4core.$(OBJEXT) \2.16 - sh4dasm.$(OBJEXT) sh4mmio.$(OBJEXT) watch.$(OBJEXT) \2.17 - armcore.$(OBJEXT) armdasm.$(OBJEXT) armmem.$(OBJEXT) \2.18 - aica.$(OBJEXT) fileio.$(OBJEXT) ipbin.$(OBJEXT) util.$(OBJEXT)2.19 + sh4dasm.$(OBJEXT) sh4mmio.$(OBJEXT) scif.$(OBJEXT) \2.20 + watch.$(OBJEXT) armcore.$(OBJEXT) armdasm.$(OBJEXT) \2.21 + armmem.$(OBJEXT) aica.$(OBJEXT) fileio.$(OBJEXT) \2.22 + ipbin.$(OBJEXT) util.$(OBJEXT)2.23 dream_OBJECTS = $(am_dream_OBJECTS)2.24 dream_DEPENDENCIES =2.25 dream_LDFLAGS =2.26 @@ -190,11 +191,11 @@2.27 @AMDEP_TRUE@ ./$(DEPDIR)/interface.Po ./$(DEPDIR)/ipbin.Po \2.28 @AMDEP_TRUE@ ./$(DEPDIR)/main.Po ./$(DEPDIR)/maple.Po \2.29 @AMDEP_TRUE@ ./$(DEPDIR)/mem.Po ./$(DEPDIR)/mmr_win.Po \2.30 -@AMDEP_TRUE@ ./$(DEPDIR)/pvr2.Po ./$(DEPDIR)/sh4core.Po \2.31 -@AMDEP_TRUE@ ./$(DEPDIR)/sh4dasm.Po ./$(DEPDIR)/sh4mem.Po \2.32 -@AMDEP_TRUE@ ./$(DEPDIR)/sh4mmio.Po ./$(DEPDIR)/support.Po \2.33 -@AMDEP_TRUE@ ./$(DEPDIR)/util.Po ./$(DEPDIR)/video.Po \2.34 -@AMDEP_TRUE@ ./$(DEPDIR)/watch.Po2.35 +@AMDEP_TRUE@ ./$(DEPDIR)/pvr2.Po ./$(DEPDIR)/scif.Po \2.36 +@AMDEP_TRUE@ ./$(DEPDIR)/sh4core.Po ./$(DEPDIR)/sh4dasm.Po \2.37 +@AMDEP_TRUE@ ./$(DEPDIR)/sh4mem.Po ./$(DEPDIR)/sh4mmio.Po \2.38 +@AMDEP_TRUE@ ./$(DEPDIR)/support.Po ./$(DEPDIR)/util.Po \2.39 +@AMDEP_TRUE@ ./$(DEPDIR)/video.Po ./$(DEPDIR)/watch.Po2.40 COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \2.41 $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)2.42 CCLD = $(CC)2.43 @@ -267,6 +268,7 @@2.44 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mem.Po@am__quote@2.45 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mmr_win.Po@am__quote@2.46 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pvr2.Po@am__quote@2.47 +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/scif.Po@am__quote@2.48 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sh4core.Po@am__quote@2.49 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sh4dasm.Po@am__quote@2.50 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sh4mem.Po@am__quote@2.51 @@ -430,6 +432,28 @@2.52 @AMDEP_TRUE@@am__fastdepCC_FALSE@ $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@2.53 @am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o sh4mmio.obj `if test -f 'sh4/sh4mmio.c'; then $(CYGPATH_W) 'sh4/sh4mmio.c'; else $(CYGPATH_W) '$(srcdir)/sh4/sh4mmio.c'; fi`2.55 +scif.o: sh4/scif.c2.56 +@am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT scif.o -MD -MP -MF "$(DEPDIR)/scif.Tpo" \2.57 +@am__fastdepCC_TRUE@ -c -o scif.o `test -f 'sh4/scif.c' || echo '$(srcdir)/'`sh4/scif.c; \2.58 +@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/scif.Tpo" "$(DEPDIR)/scif.Po"; \2.59 +@am__fastdepCC_TRUE@ else rm -f "$(DEPDIR)/scif.Tpo"; exit 1; \2.60 +@am__fastdepCC_TRUE@ fi2.61 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='sh4/scif.c' object='scif.o' libtool=no @AMDEPBACKSLASH@2.62 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ depfile='$(DEPDIR)/scif.Po' tmpdepfile='$(DEPDIR)/scif.TPo' @AMDEPBACKSLASH@2.63 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@2.64 +@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o scif.o `test -f 'sh4/scif.c' || echo '$(srcdir)/'`sh4/scif.c2.65 +2.66 +scif.obj: sh4/scif.c2.67 +@am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT scif.obj -MD -MP -MF "$(DEPDIR)/scif.Tpo" \2.68 +@am__fastdepCC_TRUE@ -c -o scif.obj `if test -f 'sh4/scif.c'; then $(CYGPATH_W) 'sh4/scif.c'; else $(CYGPATH_W) '$(srcdir)/sh4/scif.c'; fi`; \2.69 +@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/scif.Tpo" "$(DEPDIR)/scif.Po"; \2.70 +@am__fastdepCC_TRUE@ else rm -f "$(DEPDIR)/scif.Tpo"; exit 1; \2.71 +@am__fastdepCC_TRUE@ fi2.72 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='sh4/scif.c' object='scif.obj' libtool=no @AMDEPBACKSLASH@2.73 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ depfile='$(DEPDIR)/scif.Po' tmpdepfile='$(DEPDIR)/scif.TPo' @AMDEPBACKSLASH@2.74 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@2.75 +@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o scif.obj `if test -f 'sh4/scif.c'; then $(CYGPATH_W) 'sh4/scif.c'; else $(CYGPATH_W) '$(srcdir)/sh4/scif.c'; fi`2.76 +2.77 watch.o: sh4/watch.c2.78 @am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT watch.o -MD -MP -MF "$(DEPDIR)/watch.Tpo" \2.79 @am__fastdepCC_TRUE@ -c -o watch.o `test -f 'sh4/watch.c' || echo '$(srcdir)/'`sh4/watch.c; \
3.1 --- /dev/null Thu Jan 01 00:00:00 1970 +00003.2 +++ b/src/clock.h Thu Dec 22 07:38:12 2005 +00003.3 @@ -0,0 +1,41 @@3.4 +/**3.5 + * $Id: clock.h,v 1.1 2005-12-22 07:38:06 nkeynes Exp $3.6 + * External interface to the dreamcast serial port, implemented by3.7 + * sh4/scif.c3.8 + *3.9 + * Copyright (c) 2005 Nathan Keynes.3.10 + *3.11 + * This program is free software; you can redistribute it and/or modify3.12 + * it under the terms of the GNU General Public License as published by3.13 + * the Free Software Foundation; either version 2 of the License, or3.14 + * (at your option) any later version.3.15 + *3.16 + * This program is distributed in the hope that it will be useful,3.17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of3.18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the3.19 + * GNU General Public License for more details.3.20 + */3.21 +#ifndef dream_clock_H3.22 +#define dream_clock_H 13.23 +3.24 +#include <stdint.h>3.25 +3.26 +#ifdef __cplusplus3.27 +extern "C" {3.28 +#endif3.29 +3.30 +#define MHZ * 10000003.31 +3.32 +#define SH4_BASE_RATE 200 MHZ3.33 +#define ARM_BASE_RATE 33 MHZ3.34 +3.35 + extern uint32_t sh4_freq;3.36 + extern uint32_t sh4_peripheral_freq;3.37 + extern uint32_t sh4_bus_freq;3.38 + extern uint32_t arm_freq;3.39 +3.40 +#ifdef __cplusplus3.41 +}3.42 +#endif3.43 +3.44 +#endif
4.1 --- a/src/dreamcast.h Thu Dec 15 13:33:14 2005 +00004.2 +++ b/src/dreamcast.h Thu Dec 22 07:38:12 2005 +00004.3 @@ -21,7 +21,7 @@4.4 int dreamcast_load_state( const gchar *filename );4.6 int open_file( gchar *filename );4.7 -4.8 +int load_bin_file( gchar *filename );4.10 #ifdef __cplusplus4.11 }
5.1 --- a/src/gui/callbacks.c Thu Dec 15 13:33:14 2005 +00005.2 +++ b/src/gui/callbacks.c Thu Dec 22 07:38:12 2005 +00005.3 @@ -74,7 +74,7 @@5.4 on_load_btn_clicked (GtkButton *button,5.5 gpointer user_data)5.6 {5.7 - open_file_dialog( "Open...", open_file, NULL, NULL );5.8 + open_file_dialog( "Open...", load_bin_file, NULL, NULL );5.9 }5.12 @@ -116,6 +116,7 @@5.13 sh4_runto(target, 1000000);5.14 update_icount(data);5.15 run_timers(1000000);5.16 + SCIF_clock_tick();5.17 while( gtk_events_pending() )5.18 gtk_main_iteration();5.19 pvr2_next_frame();
6.1 --- a/src/loader.c Thu Dec 15 13:33:14 2005 +00006.2 +++ b/src/loader.c Thu Dec 22 07:38:12 2005 +00006.3 @@ -11,6 +11,7 @@6.4 #include "gui.h"6.5 #include "ipbin.h"6.6 #include "sh4core.h"6.7 +#include "pvr2.h"6.8 #include "mem.h"6.10 char ip_bin_magic[32] = "SEGA SEGAKATANA SEGA ENTERPRISES";6.11 @@ -84,3 +85,12 @@6.12 close(fd);6.13 return 0;6.14 }6.15 +6.16 +int load_bin_file( const gchar *filename ) {6.17 + mem_load_block( filename, 0x8c010000, -1 );6.18 + sh4_set_pc( 0x8c010000 );6.19 + set_disassembly_region( main_debug, 0x8c010000 );6.20 + set_disassembly_pc( main_debug, sh4r.pc, TRUE );6.21 + pvr2_set_base_address( 0x00025940 );6.22 + update_gui();6.23 +}
7.1 --- a/src/mem.c Thu Dec 15 13:33:14 2005 +00007.2 +++ b/src/mem.c Thu Dec 22 07:38:12 2005 +00007.3 @@ -1,5 +1,5 @@7.4 /**7.5 - * $Id: mem.c,v 1.5 2005-12-15 13:33:14 nkeynes Exp $7.6 + * $Id: mem.c,v 1.6 2005-12-22 07:38:06 nkeynes Exp $7.7 * mem.c is responsible for creating and maintaining the overall system memory7.8 * map, as visible from the SH4 processor.7.9 *7.10 @@ -17,6 +17,7 @@7.11 */7.13 #include <sys/mman.h>7.14 +#include <sys/stat.h>7.15 #include <assert.h>7.16 #include <stdint.h>7.17 #include <stdlib.h>7.18 @@ -159,6 +160,43 @@7.19 return 0;7.20 }7.22 +void mem_save_block( const gchar *file, uint32_t start, uint32_t length )7.23 +{7.24 +7.25 +}7.26 +7.27 +int mem_load_block( const gchar *file, uint32_t start, uint32_t length )7.28 +{7.29 + char *region;7.30 + int len = 4096, total = 0;7.31 + uint32_t addr = start;7.32 + struct stat st;7.33 + FILE *f = fopen(file,"r");7.34 +7.35 + if( f == NULL )7.36 + return errno;7.37 + fstat( fileno(f), &st );7.38 + if( length == 0 || length == -1 )7.39 + length = st.st_size;7.40 +7.41 + while( total < length ) {7.42 + region = mem_get_region(addr);7.43 + len = 4096 - (addr & 0x0FFF);7.44 + if( len > (length-total) )7.45 + len = (length-total);7.46 + if( fread( region, len, 1, f ) != 1 ) {7.47 + ERROR( "Unexpected error: %d %d", len, errno );7.48 + break;7.49 + }7.50 +7.51 + addr += len;7.52 + total += len;7.53 + }7.54 + fclose( f );7.55 + INFO( "Loaded %d of %d bytes to %08X", total, length, start );7.56 + return 0;7.57 +}7.58 +7.59 struct mem_region *mem_map_region( void *mem, uint32_t base, uint32_t size,7.60 char *name, int flags )7.61 {
8.1 --- a/src/mem.h Thu Dec 15 13:33:14 2005 +00008.2 +++ b/src/mem.h Thu Dec 22 07:38:12 2005 +00008.3 @@ -28,6 +28,7 @@8.5 void *mem_create_ram_region( uint32_t base, uint32_t size, char *name );8.6 void *mem_load_rom( char *name, uint32_t base, uint32_t size, uint32_t crc );8.7 +void *mem_alloc_pages( int n );8.8 char *mem_get_region( uint32_t addr );8.9 char *mem_get_region_by_name( char *name );8.10 int mem_has_page( uint32_t addr );
9.1 --- a/src/pvr2/pvr2.c Thu Dec 15 13:33:14 2005 +00009.2 +++ b/src/pvr2/pvr2.c Thu Dec 22 07:38:12 2005 +00009.3 @@ -100,3 +100,8 @@9.4 return MMIO_READ( PVR2, reg );9.5 }9.6 }9.7 +9.8 +void pvr2_set_base_address( uint32_t base )9.9 +{9.10 + mmio_region_PVR2_write( DISPADDR1, base );9.11 +}
10.1 --- a/src/pvr2/pvr2.h Thu Dec 15 13:33:14 2005 +000010.2 +++ b/src/pvr2/pvr2.h Thu Dec 22 07:38:12 2005 +000010.3 @@ -79,3 +79,4 @@10.4 #define BS_PALN 0x000000C0 /* ? */10.6 void pvr2_next_frame( void );10.7 +void pvr2_set_base_address( uint32_t );
11.1 --- /dev/null Thu Jan 01 00:00:00 1970 +000011.2 +++ b/src/serial.h Thu Dec 22 07:38:12 2005 +000011.3 @@ -0,0 +1,51 @@11.4 +/**11.5 + * $Id: serial.h,v 1.1 2005-12-22 07:38:06 nkeynes Exp $11.6 + * External interface to the dreamcast serial port, implemented by11.7 + * sh4/scif.c11.8 + *11.9 + * Copyright (c) 2005 Nathan Keynes.11.10 + *11.11 + * This program is free software; you can redistribute it and/or modify11.12 + * it under the terms of the GNU General Public License as published by11.13 + * the Free Software Foundation; either version 2 of the License, or11.14 + * (at your option) any later version.11.15 + *11.16 + * This program is distributed in the hope that it will be useful,11.17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of11.18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the11.19 + * GNU General Public License for more details.11.20 + */11.21 +#ifndef dream_serial_H11.22 +#define dream_serial_H 111.23 +11.24 +#include <stdint.h>11.25 +11.26 +#ifdef __cplusplus11.27 +extern "C" {11.28 +#endif11.29 +11.30 +#define SERIAL_8BIT 0x0011.31 +#define SERIAL_7BIT 0x4011.32 +#define SERIAL_PARITY_OFF 0x0011.33 +#define SERIAL_PARITY_EVEN 0x2011.34 +#define SERIAL_PARITY_ODD 0x3011.35 +#define SERIAL_1STOPBIT 0x0011.36 +#define SERIAL_2STOPBITS 0x0811.37 +11.38 +typedef struct serial_device {11.39 + void (*set_line_speed)(uint32_t bps);11.40 + void (*set_line_params)(int flags);11.41 + void (*receive_data)(uint8_t value);11.42 +} *serial_device_t;11.43 +11.44 +void serial_attach_device( serial_device_t dev );11.45 +void serial_detach_device( );11.46 +11.47 +void serial_transmit_data( char *data, int length );11.48 +void serial_transmit_break( void );11.49 +11.50 +#ifdef __cplusplus11.51 +}11.52 +#endif11.53 +11.54 +#endif
12.1 --- a/src/sh4/intc.c Thu Dec 15 13:33:14 2005 +000012.2 +++ b/src/sh4/intc.c Thu Dec 22 07:38:12 2005 +000012.3 @@ -113,6 +113,11 @@12.4 intc_num_pending++;12.5 }12.7 +void intc_clear_interrupt( int which )12.8 +{12.9 +12.10 +}12.11 +12.12 uint32_t intc_accept_interrupt( void )12.13 {12.14 assert(intc_num_pending > 0);
13.1 --- a/src/sh4/sh4core.c Thu Dec 15 13:33:14 2005 +000013.2 +++ b/src/sh4/sh4core.c Thu Dec 22 07:38:12 2005 +000013.3 @@ -24,13 +24,13 @@13.5 void sh4_reset(void)13.6 {13.7 + /* zero everything out, for the sake of having a consistent state. */13.8 + memset( &sh4r, 0, sizeof(sh4r) );13.9 sh4r.pc = 0xA0000000;13.10 sh4r.new_pc= 0xA0000002;13.11 sh4r.vbr = 0x00000000;13.12 sh4r.fpscr = 0x00040001;13.13 sh4r.sr = 0x700000F0;13.14 - sh4r.icount= 0;13.15 - /* Everything else is undefined anyway, so don't bother setting it */13.16 intc_reset();13.17 }
14.1 --- a/src/sh4/sh4mmio.c Thu Dec 15 13:33:14 2005 +000014.2 +++ b/src/sh4/sh4mmio.c Thu Dec 22 07:38:12 2005 +000014.3 @@ -1,5 +1,6 @@14.4 #include "dream.h"14.5 #include "mem.h"14.6 +#include "clock.h"14.7 #include "sh4core.h"14.8 #include "sh4mmio.h"14.9 #define MMIO_IMPL14.10 @@ -30,7 +31,7 @@14.12 void mmu_init()14.13 {14.14 - cache = mem_alloc_pages(2);14.15 + cache = mem_alloc_pages(2);14.16 }14.18 void mmu_set_cache_mode( int mode )14.19 @@ -135,6 +136,11 @@14.21 /********************************* CPG *************************************/14.23 +uint32_t sh4_freq = SH4_BASE_RATE;14.24 +uint32_t sh4_bus_freq = SH4_BASE_RATE;14.25 +uint32_t sh4_peripheral_freq = SH4_BASE_RATE / 2;14.26 +14.27 +14.28 MMIO_REGION_STUBFNS( CPG )14.30 /********************************* DMAC *************************************/14.31 @@ -182,7 +188,7 @@14.32 {14.33 int tcr = MMIO_READ( TMU, TSTR );14.34 cycles *= 16;14.35 - if( tcr & 1 ) {14.36 + if( tcr & 0x01 ) {14.37 int count = cycles / timer_divider[0];14.38 int *val = MMIO_REG( TMU, TCNT0 );14.39 if( *val < count ) {14.40 @@ -194,13 +200,33 @@14.41 *val -= count;14.42 }14.43 }14.44 + if( tcr & 0x02 ) {14.45 + int count = cycles / timer_divider[1];14.46 + int *val = MMIO_REG( TMU, TCNT1 );14.47 + if( *val < count ) {14.48 + MMIO_READ( TMU, TCR1 ) |= 0x100;14.49 + /* interrupt goes here */14.50 + count -= *val;14.51 + *val = MMIO_READ( TMU, TCOR1 ) - count;14.52 + } else {14.53 + *val -= count;14.54 + }14.55 + }14.56 + if( tcr & 0x04 ) {14.57 + int count = cycles / timer_divider[2];14.58 + int *val = MMIO_REG( TMU, TCNT2 );14.59 + if( *val < count ) {14.60 + MMIO_READ( TMU, TCR2 ) |= 0x100;14.61 + /* interrupt goes here */14.62 + count -= *val;14.63 + *val = MMIO_READ( TMU, TCOR2 ) - count;14.64 + } else {14.65 + *val -= count;14.66 + }14.67 + }14.68 }14.70 /********************************** SCI *************************************/14.72 MMIO_REGION_STUBFNS( SCI )14.74 -/********************************* SCIF *************************************/14.75 -14.76 -MMIO_REGION_STUBFNS( SCIF )14.77 -
15.1 --- a/src/sh4/sh4mmio.h Thu Dec 15 13:33:14 2005 +000015.2 +++ b/src/sh4/sh4mmio.h Thu Dec 22 07:38:12 2005 +000015.3 @@ -135,6 +135,15 @@15.5 MMIO_REGION_BEGIN( 0xFFE80000, SCIF, "Serial Controller (FIFO) Registers" )15.6 WORD_PORT( 0x000, SCSMR2, PORT_MRW, 0x0000, "Serial mode register (FIFO)" )15.7 + BYTE_PORT( 0x004, SCBRR2, PORT_MRW, 0xFF, "Bit rate register (FIFO)" )15.8 + WORD_PORT( 0x008, SCSCR2, PORT_MRW, 0x0000, "Serial control register" )15.9 + BYTE_PORT( 0x00C, SCFTDR2, PORT_W, UNDEFINED, "Transmit FIFO data register" )15.10 + WORD_PORT( 0x010, SCFSR2, PORT_MRW, 0x0060, "Serial status register (FIFO)")15.11 + BYTE_PORT( 0x014, SCFRDR2, PORT_R, UNDEFINED, "Receive FIFO data register" )15.12 + WORD_PORT( 0x018, SCFCR2, PORT_MRW, 0x0000, "FIFO control register" )15.13 + WORD_PORT( 0x01C, SCFDR2, PORT_MR, 0x0000, "FIFO data count register" )15.14 + WORD_PORT( 0x020, SCSPTR2, PORT_MRW, 0x0000, "Serial port register (FIFO)" )15.15 + WORD_PORT( 0x024, SCLSR2, PORT_MRW, 0x0000, "Line status register (FIFO)" )15.16 MMIO_REGION_END15.18 MMIO_REGION_LIST_BEGIN( sh4mmio )
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