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lxdream.org :: lxdream :: r626:a010e30a30e9
lxdream 0.9.1
released Jun 29
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changeset626:a010e30a30e9
parent624:b13c97bf4071
child627:c218b062a843
authornkeynes
dateFri Feb 08 00:06:56 2008 +0000 (12 years ago)
Fix LDS/STS to FPUL/FPSCR to check the FPU disabled bit. Fixes
the linux 2.4.0-test8 kernel boot
(this wasn't exactly very well documented in the original manual)
src/sh4/sh4core.c
src/sh4/sh4core.in
src/sh4/sh4x86.c
src/sh4/sh4x86.in
1.1 --- a/src/sh4/sh4core.c Thu Jan 31 09:50:41 2008 +0000
1.2 +++ b/src/sh4/sh4core.c Fri Feb 08 00:06:56 2008 +0000
1.3 @@ -482,12 +482,14 @@
1.4 case 0x5:
1.5 { /* STS FPUL, Rn */
1.6 uint32_t Rn = ((ir>>8)&0xF);
1.7 + CHECKFPUEN();
1.8 sh4r.r[Rn] = sh4r.fpul;
1.9 }
1.10 break;
1.11 case 0x6:
1.12 { /* STS FPSCR, Rn */
1.13 uint32_t Rn = ((ir>>8)&0xF);
1.14 + CHECKFPUEN();
1.15 sh4r.r[Rn] = sh4r.fpscr;
1.16 }
1.17 break;
1.18 @@ -913,6 +915,7 @@
1.19 case 0x5:
1.20 { /* STS.L FPUL, @-Rn */
1.21 uint32_t Rn = ((ir>>8)&0xF);
1.22 + CHECKFPUEN();
1.23 CHECKWALIGN32( sh4r.r[Rn] );
1.24 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.fpul );
1.25 sh4r.r[Rn] -= 4;
1.26 @@ -921,6 +924,7 @@
1.27 case 0x6:
1.28 { /* STS.L FPSCR, @-Rn */
1.29 uint32_t Rn = ((ir>>8)&0xF);
1.30 + CHECKFPUEN();
1.31 CHECKWALIGN32( sh4r.r[Rn] );
1.32 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.fpscr );
1.33 sh4r.r[Rn] -= 4;
1.34 @@ -1100,6 +1104,7 @@
1.35 case 0x5:
1.36 { /* LDS.L @Rm+, FPUL */
1.37 uint32_t Rm = ((ir>>8)&0xF);
1.38 + CHECKFPUEN();
1.39 CHECKRALIGN32( sh4r.r[Rm] );
1.40 MEM_READ_LONG(sh4r.r[Rm], sh4r.fpul);
1.41 sh4r.r[Rm] +=4;
1.42 @@ -1108,6 +1113,7 @@
1.43 case 0x6:
1.44 { /* LDS.L @Rm+, FPSCR */
1.45 uint32_t Rm = ((ir>>8)&0xF);
1.46 + CHECKFPUEN();
1.47 CHECKRALIGN32( sh4r.r[Rm] );
1.48 MEM_READ_LONG(sh4r.r[Rm], sh4r.fpscr);
1.49 sh4r.r[Rm] +=4;
1.50 @@ -1276,12 +1282,14 @@
1.51 case 0x5:
1.52 { /* LDS Rm, FPUL */
1.53 uint32_t Rm = ((ir>>8)&0xF);
1.54 + CHECKFPUEN();
1.55 sh4r.fpul = sh4r.r[Rm];
1.56 }
1.57 break;
1.58 case 0x6:
1.59 { /* LDS Rm, FPSCR */
1.60 uint32_t Rm = ((ir>>8)&0xF);
1.61 + CHECKFPUEN();
1.62 sh4r.fpscr = sh4r.r[Rm];
1.63 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
1.64 }
2.1 --- a/src/sh4/sh4core.in Thu Jan 31 09:50:41 2008 +0000
2.2 +++ b/src/sh4/sh4core.in Fri Feb 08 00:06:56 2008 +0000
2.3 @@ -851,31 +851,45 @@
2.4 CHECKPRIV();
2.5 sh4r.spc = sh4r.r[Rm];
2.6 :}
2.7 -STS FPUL, Rn {: sh4r.r[Rn] = sh4r.fpul; :}
2.8 +STS FPUL, Rn {:
2.9 + CHECKFPUEN();
2.10 + sh4r.r[Rn] = sh4r.fpul;
2.11 +:}
2.12 STS.L FPUL, @-Rn {:
2.13 + CHECKFPUEN();
2.14 CHECKWALIGN32( sh4r.r[Rn] );
2.15 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.fpul );
2.16 sh4r.r[Rn] -= 4;
2.17 :}
2.18 LDS.L @Rm+, FPUL {:
2.19 + CHECKFPUEN();
2.20 CHECKRALIGN32( sh4r.r[Rm] );
2.21 MEM_READ_LONG(sh4r.r[Rm], sh4r.fpul);
2.22 sh4r.r[Rm] +=4;
2.23 :}
2.24 -LDS Rm, FPUL {: sh4r.fpul = sh4r.r[Rm]; :}
2.25 -STS FPSCR, Rn {: sh4r.r[Rn] = sh4r.fpscr; :}
2.26 +LDS Rm, FPUL {:
2.27 + CHECKFPUEN();
2.28 + sh4r.fpul = sh4r.r[Rm];
2.29 +:}
2.30 +STS FPSCR, Rn {:
2.31 + CHECKFPUEN();
2.32 + sh4r.r[Rn] = sh4r.fpscr;
2.33 +:}
2.34 STS.L FPSCR, @-Rn {:
2.35 + CHECKFPUEN();
2.36 CHECKWALIGN32( sh4r.r[Rn] );
2.37 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.fpscr );
2.38 sh4r.r[Rn] -= 4;
2.39 :}
2.40 LDS.L @Rm+, FPSCR {:
2.41 + CHECKFPUEN();
2.42 CHECKRALIGN32( sh4r.r[Rm] );
2.43 MEM_READ_LONG(sh4r.r[Rm], sh4r.fpscr);
2.44 sh4r.r[Rm] +=4;
2.45 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
2.46 :}
2.47 LDS Rm, FPSCR {:
2.48 + CHECKFPUEN();
2.49 sh4r.fpscr = sh4r.r[Rm];
2.50 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
2.51 :}
3.1 --- a/src/sh4/sh4x86.c Thu Jan 31 09:50:41 2008 +0000
3.2 +++ b/src/sh4/sh4x86.c Fri Feb 08 00:06:56 2008 +0000
3.3 @@ -761,6 +761,7 @@
3.4 case 0x5:
3.5 { /* STS FPUL, Rn */
3.6 uint32_t Rn = ((ir>>8)&0xF);
3.7 + check_fpuen();
3.8 load_spreg( R_EAX, R_FPUL );
3.9 store_reg( R_EAX, Rn );
3.10 }
3.11 @@ -768,6 +769,7 @@
3.12 case 0x6:
3.13 { /* STS FPSCR, Rn */
3.14 uint32_t Rn = ((ir>>8)&0xF);
3.15 + check_fpuen();
3.16 load_spreg( R_EAX, R_FPSCR );
3.17 store_reg( R_EAX, Rn );
3.18 }
3.19 @@ -1441,6 +1443,7 @@
3.20 case 0x5:
3.21 { /* STS.L FPUL, @-Rn */
3.22 uint32_t Rn = ((ir>>8)&0xF);
3.23 + check_fpuen();
3.24 load_reg( R_EAX, Rn );
3.25 check_walign32( R_EAX );
3.26 ADD_imm8s_r32( -4, R_EAX );
3.27 @@ -1454,6 +1457,7 @@
3.28 case 0x6:
3.29 { /* STS.L FPSCR, @-Rn */
3.30 uint32_t Rn = ((ir>>8)&0xF);
3.31 + check_fpuen();
3.32 load_reg( R_EAX, Rn );
3.33 check_walign32( R_EAX );
3.34 ADD_imm8s_r32( -4, R_EAX );
3.35 @@ -1702,6 +1706,7 @@
3.36 case 0x5:
3.37 { /* LDS.L @Rm+, FPUL */
3.38 uint32_t Rm = ((ir>>8)&0xF);
3.39 + check_fpuen();
3.40 load_reg( R_EAX, Rm );
3.41 check_ralign32( R_EAX );
3.42 MMU_TRANSLATE_READ( R_EAX );
3.43 @@ -1714,6 +1719,7 @@
3.44 case 0x6:
3.45 { /* LDS.L @Rm+, FPSCR */
3.46 uint32_t Rm = ((ir>>8)&0xF);
3.47 + check_fpuen();
3.48 load_reg( R_EAX, Rm );
3.49 check_ralign32( R_EAX );
3.50 MMU_TRANSLATE_READ( R_EAX );
3.51 @@ -1939,6 +1945,7 @@
3.52 case 0x5:
3.53 { /* LDS Rm, FPUL */
3.54 uint32_t Rm = ((ir>>8)&0xF);
3.55 + check_fpuen();
3.56 load_reg( R_EAX, Rm );
3.57 store_spreg( R_EAX, R_FPUL );
3.58 }
3.59 @@ -1946,6 +1953,7 @@
3.60 case 0x6:
3.61 { /* LDS Rm, FPSCR */
3.62 uint32_t Rm = ((ir>>8)&0xF);
3.63 + check_fpuen();
3.64 load_reg( R_EAX, Rm );
3.65 store_spreg( R_EAX, R_FPSCR );
3.66 update_fr_bank( R_EAX );
4.1 --- a/src/sh4/sh4x86.in Thu Jan 31 09:50:41 2008 +0000
4.2 +++ b/src/sh4/sh4x86.in Fri Feb 08 00:06:56 2008 +0000
4.3 @@ -2487,13 +2487,15 @@
4.4 store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
4.5 sh4_x86.tstate = TSTATE_NONE;
4.6 :}
4.7 -LDS Rm, FPSCR {:
4.8 +LDS Rm, FPSCR {:
4.9 + check_fpuen();
4.10 load_reg( R_EAX, Rm );
4.11 store_spreg( R_EAX, R_FPSCR );
4.12 update_fr_bank( R_EAX );
4.13 sh4_x86.tstate = TSTATE_NONE;
4.14 :}
4.15 LDS.L @Rm+, FPSCR {:
4.16 + check_fpuen();
4.17 load_reg( R_EAX, Rm );
4.18 check_ralign32( R_EAX );
4.19 MMU_TRANSLATE_READ( R_EAX );
4.20 @@ -2504,10 +2506,12 @@
4.21 sh4_x86.tstate = TSTATE_NONE;
4.22 :}
4.23 LDS Rm, FPUL {:
4.24 + check_fpuen();
4.25 load_reg( R_EAX, Rm );
4.26 store_spreg( R_EAX, R_FPUL );
4.27 :}
4.28 LDS.L @Rm+, FPUL {:
4.29 + check_fpuen();
4.30 load_reg( R_EAX, Rm );
4.31 check_ralign32( R_EAX );
4.32 MMU_TRANSLATE_READ( R_EAX );
4.33 @@ -2716,10 +2720,12 @@
4.34 sh4_x86.tstate = TSTATE_NONE;
4.35 :}
4.36 STS FPSCR, Rn {:
4.37 + check_fpuen();
4.38 load_spreg( R_EAX, R_FPSCR );
4.39 store_reg( R_EAX, Rn );
4.40 :}
4.41 STS.L FPSCR, @-Rn {:
4.42 + check_fpuen();
4.43 load_reg( R_EAX, Rn );
4.44 check_walign32( R_EAX );
4.45 ADD_imm8s_r32( -4, R_EAX );
4.46 @@ -2730,10 +2736,12 @@
4.47 sh4_x86.tstate = TSTATE_NONE;
4.48 :}
4.49 STS FPUL, Rn {:
4.50 + check_fpuen();
4.51 load_spreg( R_EAX, R_FPUL );
4.52 store_reg( R_EAX, Rn );
4.53 :}
4.54 STS.L FPUL, @-Rn {:
4.55 + check_fpuen();
4.56 load_reg( R_EAX, Rn );
4.57 check_walign32( R_EAX );
4.58 ADD_imm8s_r32( -4, R_EAX );
.