1.1 --- a/src/aica/aica.c	Mon Jul 14 07:42:45 2008 +0000
     1.2 +++ b/src/aica/aica.c	Mon Jul 14 07:44:42 2008 +0000
     1.3 @@ -41,8 +41,8 @@
     1.4  uint32_t aica_run_slice( uint32_t );
     1.5  
     1.6  struct dreamcast_module aica_module = { "AICA", aica_init, aica_reset, 
     1.7 -					aica_start, aica_run_slice, aica_stop,
     1.8 -					aica_save_state, aica_load_state };
     1.9 +        aica_start, aica_run_slice, aica_stop,
    1.10 +        aica_save_state, aica_load_state };
    1.11  
    1.12  struct aica_state_struct {
    1.13      uint32_t time_of_day;
    1.14 @@ -82,7 +82,7 @@
    1.15      aica_state.nanosecs_done = 0;
    1.16      aica_state.event_pending = 0;
    1.17      aica_state.clear_count = 0;
    1.18 -//    aica_event(2); /* Pre-deliver a timer interrupt */
    1.19 +    //    aica_event(2); /* Pre-deliver a timer interrupt */
    1.20  }
    1.21  
    1.22  void aica_start( void )
    1.23 @@ -95,17 +95,17 @@
    1.24      /* Run arm instructions */
    1.25      int reset = MMIO_READ( AICA2, AICA_RESET );
    1.26      if( (reset & 1) == 0 ) { /* Running */
    1.27 -	int num_samples = (int)((uint64_t)AICA_SAMPLE_RATE * (aica_state.nanosecs_done + nanosecs) / 1000000000) - aica_state.samples_done;
    1.28 -	num_samples = arm_run_slice( num_samples );
    1.29 -	audio_mix_samples( num_samples );
    1.30 +        int num_samples = (int)((uint64_t)AICA_SAMPLE_RATE * (aica_state.nanosecs_done + nanosecs) / 1000000000) - aica_state.samples_done;
    1.31 +        num_samples = arm_run_slice( num_samples );
    1.32 +        audio_mix_samples( num_samples );
    1.33  
    1.34 -	aica_state.samples_done += num_samples;
    1.35 -	aica_state.nanosecs_done += nanosecs;
    1.36 +        aica_state.samples_done += num_samples;
    1.37 +        aica_state.nanosecs_done += nanosecs;
    1.38      }
    1.39      if( aica_state.nanosecs_done > 1000000000 ) {
    1.40 -	aica_state.samples_done -= AICA_SAMPLE_RATE;
    1.41 -	aica_state.nanosecs_done -= 1000000000;
    1.42 -	aica_state.time_of_day++;
    1.43 +        aica_state.samples_done -= AICA_SAMPLE_RATE;
    1.44 +        aica_state.nanosecs_done -= 1000000000;
    1.45 +        aica_state.time_of_day++;
    1.46      }
    1.47      return nanosecs;
    1.48  }
    1.49 @@ -136,35 +136,35 @@
    1.50  void aica_event( int event )
    1.51  {
    1.52      if( aica_state.event_pending == 0 )
    1.53 -	armr.int_pending |= CPSR_F;
    1.54 +        armr.int_pending |= CPSR_F;
    1.55      aica_state.event_pending |= (1<<event);
    1.56 -    
    1.57 +
    1.58      int pending = MMIO_READ( AICA2, AICA_IRQ );
    1.59      if( pending == 0 || event < pending )
    1.60 -	MMIO_WRITE( AICA2, AICA_IRQ, event );
    1.61 +        MMIO_WRITE( AICA2, AICA_IRQ, event );
    1.62  }
    1.63  
    1.64  void aica_clear_event( )
    1.65  {
    1.66      aica_state.clear_count++;
    1.67      if( aica_state.clear_count == 4 ) {
    1.68 -	int i;
    1.69 -	aica_state.clear_count = 0;
    1.70 +        int i;
    1.71 +        aica_state.clear_count = 0;
    1.72  
    1.73 -	for( i=0; i<8; i++ ) {
    1.74 -	    if( aica_state.event_pending & (1<<i) ) {
    1.75 -		aica_state.event_pending &= ~(1<<i);
    1.76 -		break;
    1.77 -	    }
    1.78 -	}
    1.79 -	for( ;i<8; i++ ) {
    1.80 -	    if( aica_state.event_pending & (1<<i) ) {
    1.81 -		MMIO_WRITE( AICA2, AICA_IRQ, i );
    1.82 -		break;
    1.83 -	    }
    1.84 -	}
    1.85 -	if( aica_state.event_pending == 0 )
    1.86 -	    armr.int_pending &= ~CPSR_F;
    1.87 +        for( i=0; i<8; i++ ) {
    1.88 +            if( aica_state.event_pending & (1<<i) ) {
    1.89 +                aica_state.event_pending &= ~(1<<i);
    1.90 +                break;
    1.91 +            }
    1.92 +        }
    1.93 +        for( ;i<8; i++ ) {
    1.94 +            if( aica_state.event_pending & (1<<i) ) {
    1.95 +                MMIO_WRITE( AICA2, AICA_IRQ, i );
    1.96 +                break;
    1.97 +            }
    1.98 +        }
    1.99 +        if( aica_state.event_pending == 0 )
   1.100 +            armr.int_pending &= ~CPSR_F;
   1.101      }
   1.102  }
   1.103  
   1.104 @@ -218,24 +218,24 @@
   1.105  
   1.106      switch( reg ) {
   1.107      case AICA_RESET:
   1.108 -	tmp = MMIO_READ( AICA2, AICA_RESET );
   1.109 -	if( (tmp & 1) == 1 && (val & 1) == 0 ) {
   1.110 -	    /* ARM enabled - execute a core reset */
   1.111 -	    DEBUG( "ARM enabled" );
   1.112 -	    arm_reset();
   1.113 -	    aica_state.samples_done = 0;
   1.114 -	    aica_state.nanosecs_done = 0;
   1.115 -	} else if( (tmp&1) == 0 && (val&1) == 1 ) {
   1.116 -	    DEBUG( "ARM disabled" );
   1.117 -	}
   1.118 -	MMIO_WRITE( AICA2, AICA_RESET, val );
   1.119 -	break;
   1.120 +        tmp = MMIO_READ( AICA2, AICA_RESET );
   1.121 +        if( (tmp & 1) == 1 && (val & 1) == 0 ) {
   1.122 +            /* ARM enabled - execute a core reset */
   1.123 +            DEBUG( "ARM enabled" );
   1.124 +            arm_reset();
   1.125 +            aica_state.samples_done = 0;
   1.126 +            aica_state.nanosecs_done = 0;
   1.127 +        } else if( (tmp&1) == 0 && (val&1) == 1 ) {
   1.128 +            DEBUG( "ARM disabled" );
   1.129 +        }
   1.130 +        MMIO_WRITE( AICA2, AICA_RESET, val );
   1.131 +        break;
   1.132      case AICA_IRQCLEAR:
   1.133 -	aica_clear_event();
   1.134 -	break;
   1.135 +        aica_clear_event();
   1.136 +        break;
   1.137      default:
   1.138 -	MMIO_WRITE( AICA2, reg, val );
   1.139 -	break;
   1.140 +        MMIO_WRITE( AICA2, reg, val );
   1.141 +        break;
   1.142      }
   1.143  }
   1.144  
   1.145 @@ -246,21 +246,21 @@
   1.146      int32_t val;
   1.147      switch( reg ) {
   1.148      case AICA_CHANSTATE:
   1.149 -	channo = (MMIO_READ( AICA2, AICA_CHANSEL ) >> 8) & 0x3F;
   1.150 -	channel = audio_get_channel(channo);
   1.151 -	if( channel->loop == LOOP_LOOPED ) {
   1.152 -	    val = 0x8000;
   1.153 -	    channel->loop = LOOP_ON;
   1.154 -	} else {
   1.155 -	    val = 0;
   1.156 -	}
   1.157 -	return val;
   1.158 +        channo = (MMIO_READ( AICA2, AICA_CHANSEL ) >> 8) & 0x3F;
   1.159 +        channel = audio_get_channel(channo);
   1.160 +        if( channel->loop == LOOP_LOOPED ) {
   1.161 +            val = 0x8000;
   1.162 +            channel->loop = LOOP_ON;
   1.163 +        } else {
   1.164 +            val = 0;
   1.165 +        }
   1.166 +        return val;
   1.167      case AICA_CHANPOSN:
   1.168 -	channo = (MMIO_READ( AICA2, AICA_CHANSEL ) >> 8) & 0x3F;
   1.169 -	channel = audio_get_channel(channo);
   1.170 -	return channel->posn;
   1.171 +        channo = (MMIO_READ( AICA2, AICA_CHANSEL ) >> 8) & 0x3F;
   1.172 +        channel = audio_get_channel(channo);
   1.173 +        return channel->posn;
   1.174      default:
   1.175 -	return MMIO_READ( AICA2, reg );
   1.176 +        return MMIO_READ( AICA2, reg );
   1.177      }
   1.178  }
   1.179  
   1.180 @@ -270,10 +270,10 @@
   1.181      switch( reg ) {
   1.182      case AICA_RTCHI:
   1.183          rv = (aica_state.time_of_day >> 16) & 0xFFFF;
   1.184 -	break;
   1.185 +        break;
   1.186      case AICA_RTCLO:
   1.187 -	rv = aica_state.time_of_day & 0xFFFF;
   1.188 -	break;
   1.189 +        rv = aica_state.time_of_day & 0xFFFF;
   1.190 +        break;
   1.191      }
   1.192      // DEBUG( "Read AICA RTC %d => %08X", reg, rv );
   1.193      return rv;
   1.194 @@ -284,22 +284,22 @@
   1.195  {
   1.196      switch( reg ) {
   1.197      case AICA_RTCEN:
   1.198 -	MMIO_WRITE( AICARTC, reg, val&0x01 );
   1.199 -	break;
   1.200 +        MMIO_WRITE( AICARTC, reg, val&0x01 );
   1.201 +        break;
   1.202      case AICA_RTCLO:
   1.203 -	if( MMIO_READ( AICARTC, AICA_RTCEN ) & 0x01 ) {
   1.204 -	    aica_state.time_of_day = (aica_state.time_of_day & 0xFFFF0000) | (val & 0xFFFF);
   1.205 -	}
   1.206 -	break;
   1.207 +        if( MMIO_READ( AICARTC, AICA_RTCEN ) & 0x01 ) {
   1.208 +            aica_state.time_of_day = (aica_state.time_of_day & 0xFFFF0000) | (val & 0xFFFF);
   1.209 +        }
   1.210 +        break;
   1.211      case AICA_RTCHI:
   1.212 -	if( MMIO_READ( AICARTC, AICA_RTCEN ) & 0x01 ) {
   1.213 -	    aica_state.time_of_day = (aica_state.time_of_day & 0xFFFF) | (val<<16);
   1.214 -	    MMIO_WRITE( AICARTC, AICA_RTCEN, 0 );
   1.215 -	}
   1.216 -	break;
   1.217 +        if( MMIO_READ( AICARTC, AICA_RTCEN ) & 0x01 ) {
   1.218 +            aica_state.time_of_day = (aica_state.time_of_day & 0xFFFF) | (val<<16);
   1.219 +            MMIO_WRITE( AICARTC, AICA_RTCEN, 0 );
   1.220 +        }
   1.221 +        break;
   1.222      }
   1.223  }
   1.224 -	
   1.225 +
   1.226  /**
   1.227   * Translate the channel frequency to a sample rate. The frequency is a
   1.228   * 14-bit floating point number, where bits 0..9 is the mantissa,
   1.229 @@ -314,14 +314,14 @@
   1.230      uint32_t mantissa = freq & 0x03FF;
   1.231      uint32_t rate;
   1.232      if( freq & 0x4000 ) {
   1.233 -	/* neg exponent - rate < 44100 */
   1.234 -	exponent = 8 - exponent;
   1.235 -	rate = (44100 >> exponent) +
   1.236 -	    ((44100 * mantissa) >> (10+exponent));
   1.237 +        /* neg exponent - rate < 44100 */
   1.238 +        exponent = 8 - exponent;
   1.239 +        rate = (44100 >> exponent) +
   1.240 +        ((44100 * mantissa) >> (10+exponent));
   1.241      } else {
   1.242 -	/* pos exponent - rate > 44100 */
   1.243 -	rate = (44100 << exponent) +
   1.244 -	    ((44100 * mantissa) >> (10-exponent));
   1.245 +        /* pos exponent - rate > 44100 */
   1.246 +        rate = (44100 << exponent) +
   1.247 +        ((44100 * mantissa) >> (10-exponent));
   1.248      }
   1.249      return rate;
   1.250  }
   1.251 @@ -330,12 +330,12 @@
   1.252  {
   1.253      int i;
   1.254      for( i=0; i<32; i++ ) {
   1.255 -	uint32_t val = MMIO_READ( AICA0, i<<7 );
   1.256 -	audio_start_stop_channel(i, val&0x4000);
   1.257 +        uint32_t val = MMIO_READ( AICA0, i<<7 );
   1.258 +        audio_start_stop_channel(i, val&0x4000);
   1.259      }
   1.260      for( ; i<64; i++ ) {
   1.261 -	uint32_t val = MMIO_READ( AICA1, (i-32)<<7 );
   1.262 -	audio_start_stop_channel(i, val&0x4000);
   1.263 +        uint32_t val = MMIO_READ( AICA1, (i-32)<<7 );
   1.264 +        audio_start_stop_channel(i, val&0x4000);
   1.265      }
   1.266  }
   1.267  
   1.268 @@ -343,22 +343,22 @@
   1.269   * Derived directly from Dan Potter's log table
   1.270   */
   1.271  uint8_t aica_volume_table[256] = {
   1.272 -      0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   1,
   1.273 -      1,   1,   1,   1,   1,   1,   2,   2,   2,   2,   2,   3,   3,   3,   3,   4,
   1.274 -      4,   4,   4,   5,   5,   5,   5,   6,   6,   6,   7,   7,   7,   8,   8,   9,
   1.275 -      9,   9,  10,  10,  11,  11,  11,  12,  12,  13,  13,  14,  14,  15,  15,  16,
   1.276 -     16,  17,  17,  18,  18,  19,  19,  20,  20,  21,  22,  22,  23,  23,  24,  25,
   1.277 -     25,  26,  27,  27,  28,  29,  29,  30,  31,  31,  32,  33,  34,  34,  35,  36,
   1.278 -     37,  37,  38,  39,  40,  40,  41,  42,  43,  44,  45,  45,  46,  47,  48,  49,
   1.279 -     50,  51,  52,  52,  53,  54,  55,  56,  57,  58,  59,  60,  61,  62,  63,  64,
   1.280 -     65,  66,  67,  68,  69,  70,  71,  72,  73,  74,  76,  77,  78,  79,  80,  81,
   1.281 -     82,  83,  85,  86,  87,  88,  89,  90,  92,  93,  94,  95,  97,  98,  99, 100,
   1.282 -    102, 103, 104, 105, 107, 108, 109, 111, 112, 113, 115, 116, 117, 119, 120, 121,
   1.283 -    123, 124, 126, 127, 128, 130, 131, 133, 134, 136, 137, 139, 140, 142, 143, 145,
   1.284 -    146, 148, 149, 151, 152, 154, 155, 157, 159, 160, 162, 163, 165, 167, 168, 170,
   1.285 -    171, 173, 175, 176, 178, 180, 181, 183, 185, 187, 188, 190, 192, 194, 195, 197,
   1.286 -    199, 201, 202, 204, 206, 208, 210, 211, 213, 215, 217, 219, 221, 223, 224, 226,
   1.287 -    228, 230, 232, 234, 236, 238, 240, 242, 244, 246, 248, 250, 252, 253, 254, 255 };
   1.288 +        0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   1,
   1.289 +        1,   1,   1,   1,   1,   1,   2,   2,   2,   2,   2,   3,   3,   3,   3,   4,
   1.290 +        4,   4,   4,   5,   5,   5,   5,   6,   6,   6,   7,   7,   7,   8,   8,   9,
   1.291 +        9,   9,  10,  10,  11,  11,  11,  12,  12,  13,  13,  14,  14,  15,  15,  16,
   1.292 +        16,  17,  17,  18,  18,  19,  19,  20,  20,  21,  22,  22,  23,  23,  24,  25,
   1.293 +        25,  26,  27,  27,  28,  29,  29,  30,  31,  31,  32,  33,  34,  34,  35,  36,
   1.294 +        37,  37,  38,  39,  40,  40,  41,  42,  43,  44,  45,  45,  46,  47,  48,  49,
   1.295 +        50,  51,  52,  52,  53,  54,  55,  56,  57,  58,  59,  60,  61,  62,  63,  64,
   1.296 +        65,  66,  67,  68,  69,  70,  71,  72,  73,  74,  76,  77,  78,  79,  80,  81,
   1.297 +        82,  83,  85,  86,  87,  88,  89,  90,  92,  93,  94,  95,  97,  98,  99, 100,
   1.298 +        102, 103, 104, 105, 107, 108, 109, 111, 112, 113, 115, 116, 117, 119, 120, 121,
   1.299 +        123, 124, 126, 127, 128, 130, 131, 133, 134, 136, 137, 139, 140, 142, 143, 145,
   1.300 +        146, 148, 149, 151, 152, 154, 155, 157, 159, 160, 162, 163, 165, 167, 168, 170,
   1.301 +        171, 173, 175, 176, 178, 180, 181, 183, 185, 187, 188, 190, 192, 194, 195, 197,
   1.302 +        199, 201, 202, 204, 206, 208, 210, 211, 213, 215, 217, 219, 221, 223, 224, 226,
   1.303 +        228, 230, 232, 234, 236, 238, 240, 242, 244, 246, 248, 250, 252, 253, 254, 255 };
   1.304  
   1.305  
   1.306  void aica_write_channel( int channelNo, uint32_t reg, uint32_t val ) 
   1.307 @@ -367,58 +367,58 @@
   1.308      audio_channel_t channel = audio_get_channel(channelNo);
   1.309      switch( reg ) {
   1.310      case 0x00: /* Config + high address bits*/
   1.311 -	channel->start = (channel->start & 0xFFFF) | ((val&0x1F) << 16);
   1.312 -	if( val & 0x200 ) 
   1.313 -	    channel->loop = LOOP_ON;
   1.314 -	else 
   1.315 -	    channel->loop = LOOP_OFF;
   1.316 -	switch( (val >> 7) & 0x03 ) {
   1.317 -	case 0:
   1.318 -	    channel->sample_format = AUDIO_FMT_16BIT;
   1.319 -	    break;
   1.320 -	case 1:
   1.321 -	    channel->sample_format = AUDIO_FMT_8BIT;
   1.322 -	    break;
   1.323 -	case 2:
   1.324 -	case 3:
   1.325 -	    channel->sample_format = AUDIO_FMT_ADPCM;
   1.326 -	    break;
   1.327 -	}
   1.328 -	if( val & 0x8000 ) {
   1.329 -	    aica_start_stop_channels();
   1.330 -	}
   1.331 -	break;
   1.332 -    case 0x04: /* Low 16 address bits */
   1.333 -	channel->start = (channel->start & 0x001F0000) | val;
   1.334 -	break;
   1.335 -    case 0x08: /* Loop start */
   1.336 -	channel->loop_start = val;
   1.337 -	break;
   1.338 -    case 0x0C: /* End */
   1.339 -	channel->end = val;
   1.340 -	break;
   1.341 -    case 0x10: /* Envelope register 1 */
   1.342 -	break;
   1.343 -    case 0x14: /* Envelope register 2 */
   1.344 -	break;
   1.345 -    case 0x18: /* Frequency */
   1.346 -	channel->sample_rate = aica_frequency_to_sample_rate ( val );
   1.347 -	break;
   1.348 -    case 0x1C: /* ??? */
   1.349 -    case 0x20: /* ??? */
   1.350 -    case 0x24: /* Volume? /pan */
   1.351 -	val = val & 0x1F;
   1.352 -	if( val <= 0x0F ) 
   1.353 -	    val = 0x0F - val; /* Convert to smooth pan over 0..31 */
   1.354 -	channel->pan = val;
   1.355 -	break;
   1.356 -    case 0x28: /* Volume */
   1.357 -	// This isn't remotely correct, but it will have to suffice until I have
   1.358 -	// time to figure out what's actually going on here... 
   1.359 -	channel->vol = aica_volume_table[max((val & 0xFF),((val>>8)&0xFF))];
   1.360 -	break;
   1.361 -    default: /* ??? */
   1.362 -	break;
   1.363 +        channel->start = (channel->start & 0xFFFF) | ((val&0x1F) << 16);
   1.364 +        if( val & 0x200 ) 
   1.365 +            channel->loop = LOOP_ON;
   1.366 +        else 
   1.367 +            channel->loop = LOOP_OFF;
   1.368 +        switch( (val >> 7) & 0x03 ) {
   1.369 +        case 0:
   1.370 +            channel->sample_format = AUDIO_FMT_16BIT;
   1.371 +            break;
   1.372 +        case 1:
   1.373 +            channel->sample_format = AUDIO_FMT_8BIT;
   1.374 +            break;
   1.375 +        case 2:
   1.376 +        case 3:
   1.377 +            channel->sample_format = AUDIO_FMT_ADPCM;
   1.378 +            break;
   1.379 +        }
   1.380 +        if( val & 0x8000 ) {
   1.381 +            aica_start_stop_channels();
   1.382 +        }
   1.383 +        break;
   1.384 +        case 0x04: /* Low 16 address bits */
   1.385 +            channel->start = (channel->start & 0x001F0000) | val;
   1.386 +            break;
   1.387 +        case 0x08: /* Loop start */
   1.388 +            channel->loop_start = val;
   1.389 +            break;
   1.390 +        case 0x0C: /* End */
   1.391 +            channel->end = val;
   1.392 +            break;
   1.393 +        case 0x10: /* Envelope register 1 */
   1.394 +            break;
   1.395 +        case 0x14: /* Envelope register 2 */
   1.396 +            break;
   1.397 +        case 0x18: /* Frequency */
   1.398 +            channel->sample_rate = aica_frequency_to_sample_rate ( val );
   1.399 +            break;
   1.400 +        case 0x1C: /* ??? */
   1.401 +        case 0x20: /* ??? */
   1.402 +        case 0x24: /* Volume? /pan */
   1.403 +            val = val & 0x1F;
   1.404 +            if( val <= 0x0F ) 
   1.405 +                val = 0x0F - val; /* Convert to smooth pan over 0..31 */
   1.406 +            channel->pan = val;
   1.407 +            break;
   1.408 +        case 0x28: /* Volume */
   1.409 +            // This isn't remotely correct, but it will have to suffice until I have
   1.410 +            // time to figure out what's actually going on here... 
   1.411 +            channel->vol = aica_volume_table[max((val & 0xFF),((val>>8)&0xFF))];
   1.412 +            break;
   1.413 +        default: /* ??? */
   1.414 +            break;
   1.415      }
   1.416  
   1.417  }

     2.1 --- a/src/aica/armcore.c	Mon Jul 14 07:42:45 2008 +0000
     2.2 +++ b/src/aica/armcore.c	Mon Jul 14 07:44:42 2008 +0000
     2.3 @@ -30,12 +30,12 @@
     2.4  void arm_set_mode( int mode );
     2.5  
     2.6  uint32_t arm_exceptions[][2] = {{ MODE_SVC, 0x00000000 },
     2.7 -				{ MODE_UND, 0x00000004 },
     2.8 -				{ MODE_SVC, 0x00000008 },
     2.9 -				{ MODE_ABT, 0x0000000C },
    2.10 -				{ MODE_ABT, 0x00000010 },
    2.11 -				{ MODE_IRQ, 0x00000018 },
    2.12 -				{ MODE_FIQ, 0x0000001C } };
    2.13 +        { MODE_UND, 0x00000004 },
    2.14 +        { MODE_SVC, 0x00000008 },
    2.15 +        { MODE_ABT, 0x0000000C },
    2.16 +        { MODE_ABT, 0x00000010 },
    2.17 +        { MODE_IRQ, 0x00000018 },
    2.18 +        { MODE_FIQ, 0x0000001C } };
    2.19  
    2.20  #define EXC_RESET 0
    2.21  #define EXC_UNDEFINED 1
    2.22 @@ -65,15 +65,15 @@
    2.23      int i;
    2.24  
    2.25      for( i=0; i<arm_breakpoint_count; i++ ) {
    2.26 -	if( arm_breakpoints[i].address == pc && 
    2.27 -	    arm_breakpoints[i].type == type ) {
    2.28 -	    while( ++i < arm_breakpoint_count ) {
    2.29 -		arm_breakpoints[i-1].address = arm_breakpoints[i].address;
    2.30 -		arm_breakpoints[i-1].type = arm_breakpoints[i].type;
    2.31 -	    }
    2.32 -	    arm_breakpoint_count--;
    2.33 -	    return TRUE;
    2.34 -	}
    2.35 +        if( arm_breakpoints[i].address == pc && 
    2.36 +                arm_breakpoints[i].type == type ) {
    2.37 +            while( ++i < arm_breakpoint_count ) {
    2.38 +                arm_breakpoints[i-1].address = arm_breakpoints[i].address;
    2.39 +                arm_breakpoints[i-1].type = arm_breakpoints[i].type;
    2.40 +            }
    2.41 +            arm_breakpoint_count--;
    2.42 +            return TRUE;
    2.43 +        }
    2.44      }
    2.45      return FALSE;
    2.46  }
    2.47 @@ -82,8 +82,8 @@
    2.48  {
    2.49      int i;
    2.50      for( i=0; i<arm_breakpoint_count; i++ ) {
    2.51 -	if( arm_breakpoints[i].address == pc )
    2.52 -	    return arm_breakpoints[i].type;
    2.53 +        if( arm_breakpoints[i].address == pc )
    2.54 +            return arm_breakpoints[i].type;
    2.55      }
    2.56      return 0;
    2.57  }
    2.58 @@ -93,35 +93,35 @@
    2.59      int i,j,k;
    2.60  
    2.61      if( !armr.running )
    2.62 -	return num_samples;
    2.63 +        return num_samples;
    2.64  
    2.65      for( i=0; i<num_samples; i++ ) {
    2.66 -	for( j=0; j < CYCLES_PER_SAMPLE; j++ ) {
    2.67 -	    armr.icount++;
    2.68 -	    if( !arm_execute_instruction() )
    2.69 -		return i;
    2.70 +        for( j=0; j < CYCLES_PER_SAMPLE; j++ ) {
    2.71 +            armr.icount++;
    2.72 +            if( !arm_execute_instruction() )
    2.73 +                return i;
    2.74  #ifdef ENABLE_DEBUG_MODE
    2.75 -	    for( k=0; k<arm_breakpoint_count; k++ ) {
    2.76 -		if( arm_breakpoints[k].address == armr.r[15] ) {
    2.77 -		    dreamcast_stop();
    2.78 -		    if( arm_breakpoints[k].type == BREAK_ONESHOT )
    2.79 -			arm_clear_breakpoint( armr.r[15], BREAK_ONESHOT );
    2.80 -		    return i;
    2.81 -		}
    2.82 -	    }
    2.83 +            for( k=0; k<arm_breakpoint_count; k++ ) {
    2.84 +                if( arm_breakpoints[k].address == armr.r[15] ) {
    2.85 +                    dreamcast_stop();
    2.86 +                    if( arm_breakpoints[k].type == BREAK_ONESHOT )
    2.87 +                        arm_clear_breakpoint( armr.r[15], BREAK_ONESHOT );
    2.88 +                    return i;
    2.89 +                }
    2.90 +            }
    2.91  #endif	
    2.92 -	}
    2.93 -	
    2.94 -	k = MMIO_READ( AICA2, AICA_TCR );
    2.95 -	uint8_t val = MMIO_READ( AICA2, AICA_TIMER );
    2.96 -	val++;
    2.97 -	if( val == 0 ) {
    2.98 -	    aica_event( AICA_EVENT_TIMER );
    2.99 -	    // MMIO_WRITE( AICA2, AICA_TCR, k & ~0x40 );
   2.100 -	}
   2.101 -	MMIO_WRITE( AICA2, AICA_TIMER, val );
   2.102 -	if( !dreamcast_is_running() )
   2.103 -	    break;
   2.104 +        }
   2.105 +
   2.106 +        k = MMIO_READ( AICA2, AICA_TCR );
   2.107 +        uint8_t val = MMIO_READ( AICA2, AICA_TIMER );
   2.108 +        val++;
   2.109 +        if( val == 0 ) {
   2.110 +            aica_event( AICA_EVENT_TIMER );
   2.111 +            // MMIO_WRITE( AICA2, AICA_TCR, k & ~0x40 );
   2.112 +        }
   2.113 +        MMIO_WRITE( AICA2, AICA_TIMER, val );
   2.114 +        if( !dreamcast_is_running() )
   2.115 +            break;
   2.116      }
   2.117  
   2.118      return i;
   2.119 @@ -173,12 +173,12 @@
   2.120  static uint32_t *arm_user_reg( int reg )
   2.121  {
   2.122      if( IS_EXCEPTION_MODE() ) {
   2.123 -	if( reg == 13 || reg == 14 )
   2.124 -	    return &armr.user_r[reg-8];
   2.125 -	if( IS_FIQ_MODE() ) {
   2.126 -	    if( reg >= 8 || reg <= 12 )
   2.127 -		return &armr.user_r[reg-8];
   2.128 -	}
   2.129 +        if( reg == 13 || reg == 14 )
   2.130 +            return &armr.user_r[reg-8];
   2.131 +        if( IS_FIQ_MODE() ) {
   2.132 +            if( reg >= 8 || reg <= 12 )
   2.133 +                return &armr.user_r[reg-8];
   2.134 +        }
   2.135      }
   2.136      return &armr.r[reg];
   2.137  }
   2.138 @@ -195,23 +195,23 @@
   2.139  void arm_set_cpsr( uint32_t value, uint32_t fields )
   2.140  {
   2.141      if( IS_PRIVILEGED_MODE() ) {
   2.142 -	if( fields & SET_CPSR_CONTROL ) {
   2.143 -	    int mode = value & CPSR_MODE;
   2.144 -	    arm_set_mode( mode );
   2.145 -	    armr.t = ( value & CPSR_T ); /* Technically illegal to change */
   2.146 -	    armr.cpsr = (armr.cpsr & 0xFFFFFF00) | (value & 0x000000FF);
   2.147 -	}
   2.148 +        if( fields & SET_CPSR_CONTROL ) {
   2.149 +            int mode = value & CPSR_MODE;
   2.150 +            arm_set_mode( mode );
   2.151 +            armr.t = ( value & CPSR_T ); /* Technically illegal to change */
   2.152 +            armr.cpsr = (armr.cpsr & 0xFFFFFF00) | (value & 0x000000FF);
   2.153 +        }
   2.154  
   2.155 -	/* Middle 16 bits not currently defined */
   2.156 +        /* Middle 16 bits not currently defined */
   2.157      }
   2.158      if( fields & SET_CPSR_FLAGS ) {
   2.159 -	/* Break flags directly out of given value - don't bother writing
   2.160 -	 * back to CPSR 
   2.161 -	 */
   2.162 -	armr.n = ( value & CPSR_N );
   2.163 -	armr.z = ( value & CPSR_Z );
   2.164 -	armr.c = ( value & CPSR_C );
   2.165 -	armr.v = ( value & CPSR_V );
   2.166 +        /* Break flags directly out of given value - don't bother writing
   2.167 +         * back to CPSR 
   2.168 +         */
   2.169 +        armr.n = ( value & CPSR_N );
   2.170 +        armr.z = ( value & CPSR_Z );
   2.171 +        armr.c = ( value & CPSR_C );
   2.172 +        armr.v = ( value & CPSR_V );
   2.173      }
   2.174  }
   2.175  
   2.176 @@ -219,15 +219,15 @@
   2.177  {
   2.178      /* Only defined if we actually have an SPSR register */
   2.179      if( IS_EXCEPTION_MODE() ) {
   2.180 -	if( fields & SET_CPSR_CONTROL ) {
   2.181 -	    armr.spsr = (armr.spsr & 0xFFFFFF00) | (value & 0x000000FF);
   2.182 -	}
   2.183 +        if( fields & SET_CPSR_CONTROL ) {
   2.184 +            armr.spsr = (armr.spsr & 0xFFFFFF00) | (value & 0x000000FF);
   2.185 +        }
   2.186  
   2.187 -	/* Middle 16 bits not currently defined */
   2.188 +        /* Middle 16 bits not currently defined */
   2.189  
   2.190 -	if( fields & SET_CPSR_FLAGS ) {
   2.191 -	    armr.spsr = (armr.spsr & 0x00FFFFFF) | (value & 0xFF000000);
   2.192 -	}
   2.193 +        if( fields & SET_CPSR_FLAGS ) {
   2.194 +            armr.spsr = (armr.spsr & 0x00FFFFFF) | (value & 0xFF000000);
   2.195 +        }
   2.196      }
   2.197  }
   2.198  
   2.199 @@ -244,7 +244,7 @@
   2.200      armr.r[14] = armr.r[15] + 4;
   2.201      armr.cpsr = (spsr & 0xFFFFFF00) | mode | CPSR_I; 
   2.202      if( mode == MODE_FIQ )
   2.203 -	armr.cpsr |= CPSR_F;
   2.204 +        armr.cpsr |= CPSR_F;
   2.205      armr.r[15] = arm_exceptions[exception][1];
   2.206  }
   2.207  
   2.208 @@ -272,92 +272,92 @@
   2.209  {
   2.210      int currentMode = armr.cpsr & CPSR_MODE;
   2.211      if( currentMode == targetMode )
   2.212 -	return;
   2.213 +        return;
   2.214  
   2.215      switch( currentMode ) {
   2.216      case MODE_USER:
   2.217      case MODE_SYS:
   2.218 -	armr.user_r[5] = armr.r[13];
   2.219 -	armr.user_r[6] = armr.r[14];
   2.220 -	break;
   2.221 +        armr.user_r[5] = armr.r[13];
   2.222 +        armr.user_r[6] = armr.r[14];
   2.223 +        break;
   2.224      case MODE_SVC:
   2.225 -	armr.svc_r[0] = armr.r[13];
   2.226 -	armr.svc_r[1] = armr.r[14];
   2.227 -	armr.svc_r[2] = armr.spsr;
   2.228 -	break;
   2.229 +        armr.svc_r[0] = armr.r[13];
   2.230 +        armr.svc_r[1] = armr.r[14];
   2.231 +        armr.svc_r[2] = armr.spsr;
   2.232 +        break;
   2.233      case MODE_ABT:
   2.234 -	armr.abt_r[0] = armr.r[13];
   2.235 -	armr.abt_r[1] = armr.r[14];
   2.236 -	armr.abt_r[2] = armr.spsr;
   2.237 -	break;
   2.238 +        armr.abt_r[0] = armr.r[13];
   2.239 +        armr.abt_r[1] = armr.r[14];
   2.240 +        armr.abt_r[2] = armr.spsr;
   2.241 +        break;
   2.242      case MODE_UND:
   2.243 -	armr.und_r[0] = armr.r[13];
   2.244 -	armr.und_r[1] = armr.r[14];
   2.245 -	armr.und_r[2] = armr.spsr;
   2.246 -	break;
   2.247 +        armr.und_r[0] = armr.r[13];
   2.248 +        armr.und_r[1] = armr.r[14];
   2.249 +        armr.und_r[2] = armr.spsr;
   2.250 +        break;
   2.251      case MODE_IRQ:
   2.252 -	armr.irq_r[0] = armr.r[13];
   2.253 -	armr.irq_r[1] = armr.r[14];
   2.254 -	armr.irq_r[2] = armr.spsr;
   2.255 -	break;
   2.256 +        armr.irq_r[0] = armr.r[13];
   2.257 +        armr.irq_r[1] = armr.r[14];
   2.258 +        armr.irq_r[2] = armr.spsr;
   2.259 +        break;
   2.260      case MODE_FIQ:
   2.261 -	armr.fiq_r[0] = armr.r[8];
   2.262 -	armr.fiq_r[1] = armr.r[9];
   2.263 -	armr.fiq_r[2] = armr.r[10];
   2.264 -	armr.fiq_r[3] = armr.r[11];
   2.265 -	armr.fiq_r[4] = armr.r[12];
   2.266 -	armr.fiq_r[5] = armr.r[13];
   2.267 -	armr.fiq_r[6] = armr.r[14];
   2.268 -	armr.fiq_r[7] = armr.spsr;
   2.269 -	armr.r[8] = armr.user_r[0];
   2.270 -	armr.r[9] = armr.user_r[1];
   2.271 -	armr.r[10] = armr.user_r[2];
   2.272 -	armr.r[11] = armr.user_r[3];
   2.273 -	armr.r[12] = armr.user_r[4];
   2.274 -	break;
   2.275 +        armr.fiq_r[0] = armr.r[8];
   2.276 +        armr.fiq_r[1] = armr.r[9];
   2.277 +        armr.fiq_r[2] = armr.r[10];
   2.278 +        armr.fiq_r[3] = armr.r[11];
   2.279 +        armr.fiq_r[4] = armr.r[12];
   2.280 +        armr.fiq_r[5] = armr.r[13];
   2.281 +        armr.fiq_r[6] = armr.r[14];
   2.282 +        armr.fiq_r[7] = armr.spsr;
   2.283 +        armr.r[8] = armr.user_r[0];
   2.284 +        armr.r[9] = armr.user_r[1];
   2.285 +        armr.r[10] = armr.user_r[2];
   2.286 +        armr.r[11] = armr.user_r[3];
   2.287 +        armr.r[12] = armr.user_r[4];
   2.288 +        break;
   2.289      }
   2.290 -    
   2.291 +
   2.292      switch( targetMode ) {
   2.293      case MODE_USER:
   2.294      case MODE_SYS:
   2.295 -	armr.r[13] = armr.user_r[5];
   2.296 -	armr.r[14] = armr.user_r[6];
   2.297 -	break;
   2.298 +        armr.r[13] = armr.user_r[5];
   2.299 +        armr.r[14] = armr.user_r[6];
   2.300 +        break;
   2.301      case MODE_SVC:
   2.302 -	armr.r[13] = armr.svc_r[0];
   2.303 -	armr.r[14] = armr.svc_r[1];
   2.304 -	armr.spsr = armr.svc_r[2];
   2.305 -	break;
   2.306 +        armr.r[13] = armr.svc_r[0];
   2.307 +        armr.r[14] = armr.svc_r[1];
   2.308 +        armr.spsr = armr.svc_r[2];
   2.309 +        break;
   2.310      case MODE_ABT:
   2.311 -	armr.r[13] = armr.abt_r[0];
   2.312 -	armr.r[14] = armr.abt_r[1];
   2.313 -	armr.spsr = armr.abt_r[2];
   2.314 -	break;
   2.315 +        armr.r[13] = armr.abt_r[0];
   2.316 +        armr.r[14] = armr.abt_r[1];
   2.317 +        armr.spsr = armr.abt_r[2];
   2.318 +        break;
   2.319      case MODE_UND:
   2.320 -	armr.r[13] = armr.und_r[0];
   2.321 -	armr.r[14] = armr.und_r[1];
   2.322 -	armr.spsr = armr.und_r[2];
   2.323 -	break;
   2.324 +        armr.r[13] = armr.und_r[0];
   2.325 +        armr.r[14] = armr.und_r[1];
   2.326 +        armr.spsr = armr.und_r[2];
   2.327 +        break;
   2.328      case MODE_IRQ:
   2.329 -	armr.r[13] = armr.irq_r[0];
   2.330 -	armr.r[14] = armr.irq_r[1];
   2.331 -	armr.spsr = armr.irq_r[2];
   2.332 -	break;
   2.333 +        armr.r[13] = armr.irq_r[0];
   2.334 +        armr.r[14] = armr.irq_r[1];
   2.335 +        armr.spsr = armr.irq_r[2];
   2.336 +        break;
   2.337      case MODE_FIQ:
   2.338 -	armr.user_r[0] = armr.r[8];
   2.339 -	armr.user_r[1] = armr.r[9];
   2.340 -	armr.user_r[2] = armr.r[10];
   2.341 -	armr.user_r[3] = armr.r[11];
   2.342 -	armr.user_r[4] = armr.r[12];
   2.343 -	armr.r[8] = armr.fiq_r[0];
   2.344 -	armr.r[9] = armr.fiq_r[1];
   2.345 -	armr.r[10] = armr.fiq_r[2];
   2.346 -	armr.r[11] = armr.fiq_r[3];
   2.347 -	armr.r[12] = armr.fiq_r[4];
   2.348 -	armr.r[13] = armr.fiq_r[5];
   2.349 -	armr.r[14] = armr.fiq_r[6];
   2.350 -	armr.spsr = armr.fiq_r[7];
   2.351 -	break;
   2.352 +        armr.user_r[0] = armr.r[8];
   2.353 +        armr.user_r[1] = armr.r[9];
   2.354 +        armr.user_r[2] = armr.r[10];
   2.355 +        armr.user_r[3] = armr.r[11];
   2.356 +        armr.user_r[4] = armr.r[12];
   2.357 +        armr.r[8] = armr.fiq_r[0];
   2.358 +        armr.r[9] = armr.fiq_r[1];
   2.359 +        armr.r[10] = armr.fiq_r[2];
   2.360 +        armr.r[11] = armr.fiq_r[3];
   2.361 +        armr.r[12] = armr.fiq_r[4];
   2.362 +        armr.r[13] = armr.fiq_r[5];
   2.363 +        armr.r[14] = armr.fiq_r[6];
   2.364 +        armr.spsr = armr.fiq_r[7];
   2.365 +        break;
   2.366      }
   2.367  }
   2.368  
   2.369 @@ -418,54 +418,54 @@
   2.370   */
   2.371  static uint32_t arm_get_shift_operand( uint32_t ir )
   2.372  {
   2.373 -	uint32_t operand, tmp;
   2.374 -	if( IFLAG(ir) == 0 ) {
   2.375 -		operand = RM(ir);
   2.376 -		switch(SHIFT(ir)) {
   2.377 -		case 0: /* (Rm << imm) */
   2.378 -			operand = operand << SHIFTIMM(ir);
   2.379 -			break;
   2.380 -		case 1: /* (Rm << Rs) */
   2.381 -			tmp = RS(ir)&0xFF;
   2.382 -			if( tmp > 31 ) operand = 0;
   2.383 -			else operand = operand << tmp;
   2.384 -			break;
   2.385 -		case 2: /* (Rm >> imm) */
   2.386 -			operand = operand >> SHIFTIMM(ir);
   2.387 -			break;
   2.388 -		case 3: /* (Rm >> Rs) */
   2.389 -			tmp = RS(ir) & 0xFF;
   2.390 -			if( tmp > 31 ) operand = 0;
   2.391 -			else operand = operand >> ir;
   2.392 -			break;
   2.393 -		case 4: /* (Rm >>> imm) */
   2.394 -			tmp = SHIFTIMM(ir);
   2.395 -			if( tmp == 0 ) operand = ((int32_t)operand) >> 31;
   2.396 -			else operand = ((int32_t)operand) >> tmp;
   2.397 -			break;
   2.398 -		case 5: /* (Rm >>> Rs) */
   2.399 -			tmp = RS(ir) & 0xFF;
   2.400 -			if( tmp > 31 ) operand = ((int32_t)operand) >> 31;
   2.401 -			else operand = ((int32_t)operand) >> tmp;
   2.402 -			break;
   2.403 -		case 6:
   2.404 -			tmp = SHIFTIMM(ir);
   2.405 -			if( tmp == 0 ) /* RRX aka rotate with carry */
   2.406 -				operand = (operand >> 1) | (armr.c<<31);
   2.407 -			else
   2.408 -				operand = ROTATE_RIGHT_LONG(operand,tmp);
   2.409 -			break;
   2.410 -		case 7:
   2.411 -			tmp = RS(ir)&0x1F;
   2.412 -			operand = ROTATE_RIGHT_LONG(operand,tmp);
   2.413 -			break;
   2.414 -		}
   2.415 -	} else {
   2.416 -		operand = IMM8(ir);
   2.417 -		tmp = IMMROT(ir);
   2.418 -		operand = ROTATE_RIGHT_LONG(operand, tmp);
   2.419 -	}
   2.420 -	return operand;
   2.421 +    uint32_t operand, tmp;
   2.422 +    if( IFLAG(ir) == 0 ) {
   2.423 +        operand = RM(ir);
   2.424 +        switch(SHIFT(ir)) {
   2.425 +        case 0: /* (Rm << imm) */
   2.426 +            operand = operand << SHIFTIMM(ir);
   2.427 +            break;
   2.428 +        case 1: /* (Rm << Rs) */
   2.429 +            tmp = RS(ir)&0xFF;
   2.430 +            if( tmp > 31 ) operand = 0;
   2.431 +            else operand = operand << tmp;
   2.432 +            break;
   2.433 +        case 2: /* (Rm >> imm) */
   2.434 +            operand = operand >> SHIFTIMM(ir);
   2.435 +            break;
   2.436 +        case 3: /* (Rm >> Rs) */
   2.437 +            tmp = RS(ir) & 0xFF;
   2.438 +            if( tmp > 31 ) operand = 0;
   2.439 +            else operand = operand >> ir;
   2.440 +            break;
   2.441 +        case 4: /* (Rm >>> imm) */
   2.442 +            tmp = SHIFTIMM(ir);
   2.443 +            if( tmp == 0 ) operand = ((int32_t)operand) >> 31;
   2.444 +            else operand = ((int32_t)operand) >> tmp;
   2.445 +            break;
   2.446 +        case 5: /* (Rm >>> Rs) */
   2.447 +            tmp = RS(ir) & 0xFF;
   2.448 +            if( tmp > 31 ) operand = ((int32_t)operand) >> 31;
   2.449 +            else operand = ((int32_t)operand) >> tmp;
   2.450 +            break;
   2.451 +        case 6:
   2.452 +            tmp = SHIFTIMM(ir);
   2.453 +            if( tmp == 0 ) /* RRX aka rotate with carry */
   2.454 +                operand = (operand >> 1) | (armr.c<<31);
   2.455 +            else
   2.456 +                operand = ROTATE_RIGHT_LONG(operand,tmp);
   2.457 +            break;
   2.458 +        case 7:
   2.459 +            tmp = RS(ir)&0x1F;
   2.460 +            operand = ROTATE_RIGHT_LONG(operand,tmp);
   2.461 +            break;
   2.462 +        }
   2.463 +    } else {
   2.464 +        operand = IMM8(ir);
   2.465 +        tmp = IMMROT(ir);
   2.466 +        operand = ROTATE_RIGHT_LONG(operand, tmp);
   2.467 +    }
   2.468 +    return operand;
   2.469  }
   2.470  
   2.471  /**
   2.472 @@ -475,115 +475,115 @@
   2.473   */
   2.474  static uint32_t arm_get_shift_operand_s( uint32_t ir )
   2.475  {
   2.476 -	uint32_t operand, tmp;
   2.477 -	if( IFLAG(ir) == 0 ) {
   2.478 -		operand = RM(ir);
   2.479 -		switch(SHIFT(ir)) {
   2.480 -		case 0: /* (Rm << imm) */
   2.481 -			tmp = SHIFTIMM(ir);
   2.482 -			if( tmp == 0 ) { /* Rm */
   2.483 -				armr.shift_c = armr.c;
   2.484 -			} else { /* Rm << imm */
   2.485 -				armr.shift_c = (operand >> (32-tmp)) & 0x01;
   2.486 -				operand = operand << tmp;
   2.487 -			}
   2.488 -			break;
   2.489 -		case 1: /* (Rm << Rs) */
   2.490 -			tmp = RS(ir)&0xFF;
   2.491 -			if( tmp == 0 ) {
   2.492 -				armr.shift_c = armr.c;
   2.493 -			} else {
   2.494 -				if( tmp <= 32 )
   2.495 -					armr.shift_c = (operand >> (32-tmp)) & 0x01;
   2.496 -				else armr.shift_c = 0;
   2.497 -				if( tmp < 32 )
   2.498 -					operand = operand << tmp;
   2.499 -				else operand = 0;
   2.500 -			}
   2.501 -			break;
   2.502 -		case 2: /* (Rm >> imm) */
   2.503 -			tmp = SHIFTIMM(ir);
   2.504 -			if( tmp == 0 ) {
   2.505 -				armr.shift_c = operand >> 31;
   2.506 -				operand = 0;
   2.507 -			} else {
   2.508 -				armr.shift_c = (operand >> (tmp-1)) & 0x01;
   2.509 -				operand = RM(ir) >> tmp;
   2.510 -			}
   2.511 -			break;
   2.512 -		case 3: /* (Rm >> Rs) */
   2.513 -			tmp = RS(ir) & 0xFF;
   2.514 -			if( tmp == 0 ) {
   2.515 -				armr.shift_c = armr.c;
   2.516 -			} else {
   2.517 -				if( tmp <= 32 )
   2.518 -					armr.shift_c = (operand >> (tmp-1))&0x01;
   2.519 -				else armr.shift_c = 0;
   2.520 -				if( tmp < 32 )
   2.521 -					operand = operand >> tmp;
   2.522 -				else operand = 0;
   2.523 -			}
   2.524 -			break;
   2.525 -		case 4: /* (Rm >>> imm) */
   2.526 -			tmp = SHIFTIMM(ir);
   2.527 -			if( tmp == 0 ) {
   2.528 -				armr.shift_c = operand >> 31;
   2.529 -				operand = -armr.shift_c;
   2.530 -			} else {
   2.531 -				armr.shift_c = (operand >> (tmp-1)) & 0x01;
   2.532 -				operand = ((int32_t)operand) >> tmp;
   2.533 -			}
   2.534 -			break;
   2.535 -		case 5: /* (Rm >>> Rs) */
   2.536 -			tmp = RS(ir) & 0xFF;
   2.537 -			if( tmp == 0 ) {
   2.538 -				armr.shift_c = armr.c;
   2.539 -			} else {
   2.540 -				if( tmp < 32 ) {
   2.541 -					armr.shift_c = (operand >> (tmp-1))&0x01;
   2.542 -					operand = ((int32_t)operand) >> tmp;
   2.543 -				} else {
   2.544 -					armr.shift_c = operand >> 31;
   2.545 -					operand = ((int32_t)operand) >> 31;
   2.546 -				}
   2.547 -			}
   2.548 -			break;
   2.549 -		case 6:
   2.550 -			tmp = SHIFTIMM(ir);
   2.551 -			if( tmp == 0 ) { /* RRX aka rotate with carry */
   2.552 -				armr.shift_c = operand&0x01;
   2.553 -				operand = (operand >> 1) | (armr.c<<31);
   2.554 -			} else {
   2.555 -				armr.shift_c = operand>>(tmp-1);
   2.556 -				operand = ROTATE_RIGHT_LONG(operand,tmp);
   2.557 -			}
   2.558 -			break;
   2.559 -		case 7:
   2.560 -			tmp = RS(ir)&0xFF;
   2.561 -			if( tmp == 0 ) {
   2.562 -				armr.shift_c = armr.c;
   2.563 -			} else {
   2.564 -				tmp &= 0x1F;
   2.565 -				if( tmp == 0 ) {
   2.566 -					armr.shift_c = operand>>31;
   2.567 -				} else {
   2.568 -					armr.shift_c = (operand>>(tmp-1))&0x1;
   2.569 -					operand = ROTATE_RIGHT_LONG(operand,tmp);
   2.570 -				}
   2.571 -			}
   2.572 -			break;
   2.573 -		}
   2.574 -	} else {
   2.575 -		operand = IMM8(ir);
   2.576 -		tmp = IMMROT(ir);
   2.577 -		if( tmp == 0 ) {
   2.578 -			armr.shift_c = armr.c;
   2.579 -		} else {
   2.580 -			operand = ROTATE_RIGHT_LONG(operand, tmp);
   2.581 -			armr.shift_c = operand>>31;
   2.582 -		}
   2.583 -	}
   2.584 -	return operand;
   2.585 +    uint32_t operand, tmp;
   2.586 +    if( IFLAG(ir) == 0 ) {
   2.587 +        operand = RM(ir);
   2.588 +        switch(SHIFT(ir)) {
   2.589 +        case 0: /* (Rm << imm) */
   2.590 +            tmp = SHIFTIMM(ir);
   2.591 +            if( tmp == 0 ) { /* Rm */
   2.592 +                armr.shift_c = armr.c;
   2.593 +            } else { /* Rm << imm */
   2.594 +                armr.shift_c = (operand >> (32-tmp)) & 0x01;
   2.595 +                operand = operand << tmp;
   2.596 +            }
   2.597 +            break;
   2.598 +        case 1: /* (Rm << Rs) */
   2.599 +            tmp = RS(ir)&0xFF;
   2.600 +            if( tmp == 0 ) {
   2.601 +                armr.shift_c = armr.c;
   2.602 +            } else {
   2.603 +                if( tmp <= 32 )
   2.604 +                    armr.shift_c = (operand >> (32-tmp)) & 0x01;
   2.605 +                else armr.shift_c = 0;
   2.606 +                if( tmp < 32 )
   2.607 +                    operand = operand << tmp;
   2.608 +                else operand = 0;
   2.609 +            }
   2.610 +            break;
   2.611 +        case 2: /* (Rm >> imm) */
   2.612 +            tmp = SHIFTIMM(ir);
   2.613 +            if( tmp == 0 ) {
   2.614 +                armr.shift_c = operand >> 31;
   2.615 +                operand = 0;
   2.616 +            } else {
   2.617 +                armr.shift_c = (operand >> (tmp-1)) & 0x01;
   2.618 +                operand = RM(ir) >> tmp;
   2.619 +            }
   2.620 +            break;
   2.621 +        case 3: /* (Rm >> Rs) */
   2.622 +            tmp = RS(ir) & 0xFF;
   2.623 +            if( tmp == 0 ) {
   2.624 +                armr.shift_c = armr.c;
   2.625 +            } else {
   2.626 +                if( tmp <= 32 )
   2.627 +                    armr.shift_c = (operand >> (tmp-1))&0x01;
   2.628 +                else armr.shift_c = 0;
   2.629 +                if( tmp < 32 )
   2.630 +                    operand = operand >> tmp;
   2.631 +                else operand = 0;
   2.632 +            }
   2.633 +            break;
   2.634 +        case 4: /* (Rm >>> imm) */
   2.635 +            tmp = SHIFTIMM(ir);
   2.636 +            if( tmp == 0 ) {
   2.637 +                armr.shift_c = operand >> 31;
   2.638 +                operand = -armr.shift_c;
   2.639 +            } else {
   2.640 +                armr.shift_c = (operand >> (tmp-1)) & 0x01;
   2.641 +                operand = ((int32_t)operand) >> tmp;
   2.642 +            }
   2.643 +            break;
   2.644 +        case 5: /* (Rm >>> Rs) */
   2.645 +            tmp = RS(ir) & 0xFF;
   2.646 +            if( tmp == 0 ) {
   2.647 +                armr.shift_c = armr.c;
   2.648 +            } else {
   2.649 +                if( tmp < 32 ) {
   2.650 +                    armr.shift_c = (operand >> (tmp-1))&0x01;
   2.651 +                    operand = ((int32_t)operand) >> tmp;
   2.652 +                } else {
   2.653 +                    armr.shift_c = operand >> 31;
   2.654 +                    operand = ((int32_t)operand) >> 31;
   2.655 +                }
   2.656 +            }
   2.657 +            break;
   2.658 +        case 6:
   2.659 +            tmp = SHIFTIMM(ir);
   2.660 +            if( tmp == 0 ) { /* RRX aka rotate with carry */
   2.661 +                armr.shift_c = operand&0x01;
   2.662 +                operand = (operand >> 1) | (armr.c<<31);
   2.663 +            } else {
   2.664 +                armr.shift_c = operand>>(tmp-1);
   2.665 +                operand = ROTATE_RIGHT_LONG(operand,tmp);
   2.666 +            }
   2.667 +            break;
   2.668 +        case 7:
   2.669 +            tmp = RS(ir)&0xFF;
   2.670 +            if( tmp == 0 ) {
   2.671 +                armr.shift_c = armr.c;
   2.672 +            } else {
   2.673 +                tmp &= 0x1F;
   2.674 +                if( tmp == 0 ) {
   2.675 +                    armr.shift_c = operand>>31;
   2.676 +                } else {
   2.677 +                    armr.shift_c = (operand>>(tmp-1))&0x1;
   2.678 +                    operand = ROTATE_RIGHT_LONG(operand,tmp);
   2.679 +                }
   2.680 +            }
   2.681 +            break;
   2.682 +        }
   2.683 +    } else {
   2.684 +        operand = IMM8(ir);
   2.685 +        tmp = IMMROT(ir);
   2.686 +        if( tmp == 0 ) {
   2.687 +            armr.shift_c = armr.c;
   2.688 +        } else {
   2.689 +            operand = ROTATE_RIGHT_LONG(operand, tmp);
   2.690 +            armr.shift_c = operand>>31;
   2.691 +        }
   2.692 +    }
   2.693 +    return operand;
   2.694  }
   2.695  
   2.696  /**
   2.697 @@ -595,31 +595,31 @@
   2.698   */
   2.699  static uint32_t arm_get_address_index( uint32_t ir )
   2.700  {
   2.701 -	uint32_t operand = RM(ir);
   2.702 -	uint32_t tmp;
   2.703 -	
   2.704 -	switch(SHIFT(ir)) {
   2.705 -	case 0: /* (Rm << imm) */
   2.706 -		operand = operand << SHIFTIMM(ir);
   2.707 -		break;
   2.708 -	case 2: /* (Rm >> imm) */
   2.709 -		operand = operand >> SHIFTIMM(ir);
   2.710 -		break;
   2.711 -	case 4: /* (Rm >>> imm) */
   2.712 -		tmp = SHIFTIMM(ir);
   2.713 -		if( tmp == 0 ) operand = ((int32_t)operand) >> 31;
   2.714 -		else operand = ((int32_t)operand) >> tmp;
   2.715 -		break;
   2.716 -	case 6:
   2.717 -		tmp = SHIFTIMM(ir);
   2.718 -		if( tmp == 0 ) /* RRX aka rotate with carry */
   2.719 -			operand = (operand >> 1) | (armr.c<<31);
   2.720 -		else
   2.721 -			operand = ROTATE_RIGHT_LONG(operand,tmp);
   2.722 -		break;
   2.723 -	default: UNIMP(ir);
   2.724 -	}
   2.725 -	return operand;	
   2.726 +    uint32_t operand = RM(ir);
   2.727 +    uint32_t tmp;
   2.728 +
   2.729 +    switch(SHIFT(ir)) {
   2.730 +    case 0: /* (Rm << imm) */
   2.731 +        operand = operand << SHIFTIMM(ir);
   2.732 +        break;
   2.733 +    case 2: /* (Rm >> imm) */
   2.734 +        operand = operand >> SHIFTIMM(ir);
   2.735 +        break;
   2.736 +    case 4: /* (Rm >>> imm) */
   2.737 +        tmp = SHIFTIMM(ir);
   2.738 +        if( tmp == 0 ) operand = ((int32_t)operand) >> 31;
   2.739 +        else operand = ((int32_t)operand) >> tmp;
   2.740 +        break;
   2.741 +    case 6:
   2.742 +        tmp = SHIFTIMM(ir);
   2.743 +        if( tmp == 0 ) /* RRX aka rotate with carry */
   2.744 +            operand = (operand >> 1) | (armr.c<<31);
   2.745 +        else
   2.746 +            operand = ROTATE_RIGHT_LONG(operand,tmp);
   2.747 +        break;
   2.748 +    default: UNIMP(ir);
   2.749 +    }
   2.750 +    return operand;	
   2.751  }
   2.752  
   2.753  /**
   2.754 @@ -631,60 +631,60 @@
   2.755   */
   2.756  static uint32_t arm_get_address_operand( uint32_t ir )
   2.757  {
   2.758 -	uint32_t addr=0;
   2.759 -	
   2.760 -	/* I P U . W */
   2.761 -	switch( (ir>>21)&0x1D ) {
   2.762 -	case 0: /* Rn -= imm offset (post-indexed) [5.2.8 A5-28] */
   2.763 -	case 1:
   2.764 -		addr = RN(ir);
   2.765 -		LRN(ir) = addr - IMM12(ir);
   2.766 -		break;
   2.767 -	case 4: /* Rn += imm offsett (post-indexed) [5.2.8 A5-28] */
   2.768 -	case 5:
   2.769 -		addr = RN(ir);
   2.770 -		LRN(ir) = addr + IMM12(ir);
   2.771 -		break;
   2.772 -	case 8: /* Rn - imm offset  [5.2.2 A5-20] */
   2.773 -		addr = RN(ir) - IMM12(ir);
   2.774 -		break;
   2.775 -	case 9: /* Rn -= imm offset (pre-indexed)  [5.2.5 A5-24] */
   2.776 -		addr = RN(ir) - IMM12(ir);
   2.777 -		LRN(ir) = addr;
   2.778 -		break;
   2.779 -	case 12: /* Rn + imm offset  [5.2.2 A5-20] */
   2.780 -		addr = RN(ir) + IMM12(ir);
   2.781 -		break;
   2.782 -	case 13: /* Rn += imm offset  [5.2.5 A5-24 ] */
   2.783 -		addr = RN(ir) + IMM12(ir);
   2.784 -		LRN(ir) = addr;
   2.785 -		break;
   2.786 -	case 16: /* Rn -= Rm (post-indexed)  [5.2.10 A5-32 ] */
   2.787 -	case 17:
   2.788 -		addr = RN(ir);
   2.789 -		LRN(ir) = addr - arm_get_address_index(ir);
   2.790 -		break;
   2.791 -	case 20: /* Rn += Rm (post-indexed)  [5.2.10 A5-32 ] */
   2.792 -	case 21:
   2.793 -		addr = RN(ir);
   2.794 -		LRN(ir) = addr - arm_get_address_index(ir);
   2.795 -		break;
   2.796 -	case 24: /* Rn - Rm  [5.2.4 A5-23] */
   2.797 -		addr = RN(ir) - arm_get_address_index(ir);
   2.798 -		break;
   2.799 -	case 25: /* RN -= Rm (pre-indexed)  [5.2.7 A5-26] */
   2.800 -		addr = RN(ir) - arm_get_address_index(ir);
   2.801 -		LRN(ir) = addr;
   2.802 -		break;
   2.803 -	case 28: /* Rn + Rm  [5.2.4 A5-23] */
   2.804 -		addr = RN(ir) + arm_get_address_index(ir);
   2.805 -		break;
   2.806 -	case 29: /* RN += Rm (pre-indexed) [5.2.7 A5-26] */
   2.807 -		addr = RN(ir) + arm_get_address_index(ir);
   2.808 -		LRN(ir) = addr;
   2.809 -		break;
   2.810 -	}
   2.811 -	return addr;
   2.812 +    uint32_t addr=0;
   2.813 +
   2.814 +    /* I P U . W */
   2.815 +    switch( (ir>>21)&0x1D ) {
   2.816 +    case 0: /* Rn -= imm offset (post-indexed) [5.2.8 A5-28] */
   2.817 +    case 1:
   2.818 +        addr = RN(ir);
   2.819 +        LRN(ir) = addr - IMM12(ir);
   2.820 +        break;
   2.821 +    case 4: /* Rn += imm offsett (post-indexed) [5.2.8 A5-28] */
   2.822 +    case 5:
   2.823 +        addr = RN(ir);
   2.824 +        LRN(ir) = addr + IMM12(ir);
   2.825 +        break;
   2.826 +    case 8: /* Rn - imm offset  [5.2.2 A5-20] */
   2.827 +        addr = RN(ir) - IMM12(ir);
   2.828 +        break;
   2.829 +    case 9: /* Rn -= imm offset (pre-indexed)  [5.2.5 A5-24] */
   2.830 +        addr = RN(ir) - IMM12(ir);
   2.831 +        LRN(ir) = addr;
   2.832 +        break;
   2.833 +    case 12: /* Rn + imm offset  [5.2.2 A5-20] */
   2.834 +        addr = RN(ir) + IMM12(ir);
   2.835 +        break;
   2.836 +    case 13: /* Rn += imm offset  [5.2.5 A5-24 ] */
   2.837 +        addr = RN(ir) + IMM12(ir);
   2.838 +        LRN(ir) = addr;
   2.839 +        break;
   2.840 +    case 16: /* Rn -= Rm (post-indexed)  [5.2.10 A5-32 ] */
   2.841 +    case 17:
   2.842 +        addr = RN(ir);
   2.843 +        LRN(ir) = addr - arm_get_address_index(ir);
   2.844 +        break;
   2.845 +    case 20: /* Rn += Rm (post-indexed)  [5.2.10 A5-32 ] */
   2.846 +    case 21:
   2.847 +        addr = RN(ir);
   2.848 +        LRN(ir) = addr - arm_get_address_index(ir);
   2.849 +        break;
   2.850 +    case 24: /* Rn - Rm  [5.2.4 A5-23] */
   2.851 +        addr = RN(ir) - arm_get_address_index(ir);
   2.852 +        break;
   2.853 +    case 25: /* RN -= Rm (pre-indexed)  [5.2.7 A5-26] */
   2.854 +        addr = RN(ir) - arm_get_address_index(ir);
   2.855 +        LRN(ir) = addr;
   2.856 +        break;
   2.857 +    case 28: /* Rn + Rm  [5.2.4 A5-23] */
   2.858 +        addr = RN(ir) + arm_get_address_index(ir);
   2.859 +        break;
   2.860 +    case 29: /* RN += Rm (pre-indexed) [5.2.7 A5-26] */
   2.861 +        addr = RN(ir) + arm_get_address_index(ir);
   2.862 +        LRN(ir) = addr;
   2.863 +        break;
   2.864 +    }
   2.865 +    return addr;
   2.866  }
   2.867  
   2.868  gboolean arm_execute_instruction( void ) 
   2.869 @@ -696,11 +696,11 @@
   2.870  
   2.871      tmp = armr.int_pending & (~armr.cpsr);
   2.872      if( tmp ) {
   2.873 -	if( tmp & CPSR_F ) {
   2.874 -	    arm_raise_exception( EXC_FAST_IRQ );
   2.875 -	} else {
   2.876 -	    arm_raise_exception( EXC_IRQ );
   2.877 -	}
   2.878 +        if( tmp & CPSR_F ) {
   2.879 +            arm_raise_exception( EXC_FAST_IRQ );
   2.880 +        } else {
   2.881 +            arm_raise_exception( EXC_IRQ );
   2.882 +        }
   2.883      }
   2.884  
   2.885      ir = MEM_READ_LONG(PC);
   2.886 @@ -713,673 +713,673 @@
   2.887       */
   2.888      switch( COND(ir) ) {
   2.889      case 0: /* EQ */ 
   2.890 -	cond = armr.z;
   2.891 -	break;
   2.892 +        cond = armr.z;
   2.893 +        break;
   2.894      case 1: /* NE */
   2.895 -	cond = !armr.z;
   2.896 -	break;
   2.897 +        cond = !armr.z;
   2.898 +        break;
   2.899      case 2: /* CS/HS */
   2.900 -	cond = armr.c;
   2.901 -	break;
   2.902 +        cond = armr.c;
   2.903 +        break;
   2.904      case 3: /* CC/LO */
   2.905 -	cond = !armr.c;
   2.906 -	break;
   2.907 +        cond = !armr.c;
   2.908 +        break;
   2.909      case 4: /* MI */
   2.910 -	cond = armr.n;
   2.911 -	break;
   2.912 +        cond = armr.n;
   2.913 +        break;
   2.914      case 5: /* PL */
   2.915 -	cond = !armr.n;
   2.916 -	break;
   2.917 +        cond = !armr.n;
   2.918 +        break;
   2.919      case 6: /* VS */
   2.920 -	cond = armr.v;
   2.921 -	break;
   2.922 +        cond = armr.v;
   2.923 +        break;
   2.924      case 7: /* VC */
   2.925 -	cond = !armr.v;
   2.926 -	break;
   2.927 +        cond = !armr.v;
   2.928 +        break;
   2.929      case 8: /* HI */
   2.930 -	cond = armr.c && !armr.z;
   2.931 -	break;
   2.932 +        cond = armr.c && !armr.z;
   2.933 +        break;
   2.934      case 9: /* LS */
   2.935 -	cond = (!armr.c) || armr.z;
   2.936 -	break;
   2.937 +        cond = (!armr.c) || armr.z;
   2.938 +        break;
   2.939      case 10: /* GE */
   2.940 -	cond = (armr.n == armr.v);
   2.941 -	break;
   2.942 +        cond = (armr.n == armr.v);
   2.943 +        break;
   2.944      case 11: /* LT */
   2.945 -	cond = (armr.n != armr.v);
   2.946 -	break;
   2.947 +        cond = (armr.n != armr.v);
   2.948 +        break;
   2.949      case 12: /* GT */
   2.950 -	cond = (!armr.z) && (armr.n == armr.v);
   2.951 -	break;
   2.952 +        cond = (!armr.z) && (armr.n == armr.v);
   2.953 +        break;
   2.954      case 13: /* LE */
   2.955 -	cond = armr.z || (armr.n != armr.v);
   2.956 -	break;
   2.957 +        cond = armr.z || (armr.n != armr.v);
   2.958 +        break;
   2.959      case 14: /* AL */
   2.960 -	cond = 1;
   2.961 -	break;
   2.962 +        cond = 1;
   2.963 +        break;
   2.964      case 15: /* (NV) */
   2.965      default:
   2.966 -	cond = 0;
   2.967 -	UNDEF(ir);
   2.968 +        cond = 0;
   2.969 +        UNDEF(ir);
   2.970      }
   2.971      if( cond ) {
   2.972  
   2.973 -    /**
   2.974 -     * Condition passed, now for the actual instructions...
   2.975 -     */
   2.976 -    switch( GRP(ir) ) {
   2.977 -    case 0:
   2.978 -	if( (ir & 0x0D900000) == 0x01000000 ) {
   2.979 -	    /* Instructions that aren't actual data processing even though
   2.980 -	     * they sit in the DP instruction block.
   2.981 -	     */
   2.982 -	    switch( ir & 0x0FF000F0 ) {
   2.983 -	    case 0x01200010: /* BX Rd */
   2.984 -		armr.t = ir & 0x01;
   2.985 -		armr.r[15] = RM(ir) & 0xFFFFFFFE;
   2.986 -		break;
   2.987 -	    case 0x01000000: /* MRS Rd, CPSR */
   2.988 -		LRD(ir) = arm_get_cpsr();
   2.989 -		break;
   2.990 -	    case 0x01400000: /* MRS Rd, SPSR */
   2.991 -		LRD(ir) = armr.spsr;
   2.992 -		break;
   2.993 -	    case 0x01200000: /* MSR CPSR, Rd */
   2.994 -		arm_set_cpsr( RM(ir), ir );
   2.995 -		break;
   2.996 -	    case 0x01600000: /* MSR SPSR, Rd */
   2.997 -		arm_set_spsr( RM(ir), ir );
   2.998 -		break;
   2.999 -	    case 0x03200000: /* MSR CPSR, imm */
  2.1000 -		arm_set_cpsr( ROTIMM12(ir), ir );
  2.1001 -		break;
  2.1002 -	    case 0x03600000: /* MSR SPSR, imm */
  2.1003 -		arm_set_spsr( ROTIMM12(ir), ir );
  2.1004 -		break;
  2.1005 -	    default:
  2.1006 -		UNIMP(ir);
  2.1007 -	    }
  2.1008 -	} else if( (ir & 0x0E000090) == 0x00000090 ) {
  2.1009 -	    /* Neither are these */
  2.1010 -	    switch( (ir>>5)&0x03 ) {
  2.1011 -	    case 0:
  2.1012 -		/* Arithmetic extension area */
  2.1013 -		switch(OPCODE(ir)) {
  2.1014 -		case 0: /* MUL */
  2.1015 -		    LRN(ir) = RM(ir) * RS(ir);
  2.1016 -		    break;
  2.1017 -		case 1: /* MULS */
  2.1018 -		    tmp = RM(ir) * RS(ir);
  2.1019 -		    LRN(ir) = tmp;
  2.1020 -		    armr.n = tmp>>31;
  2.1021 -		    armr.z = (tmp == 0);
  2.1022 -		    break;
  2.1023 -		case 2: /* MLA */
  2.1024 -		    LRN(ir) = RM(ir) * RS(ir) + RD(ir);
  2.1025 -		    break;
  2.1026 -		case 3: /* MLAS */
  2.1027 -		    tmp = RM(ir) * RS(ir) + RD(ir);
  2.1028 -		    LRN(ir) = tmp;
  2.1029 -		    armr.n = tmp>>31;
  2.1030 -		    armr.z = (tmp == 0);
  2.1031 -		    break;
  2.1032 -		case 8: /* UMULL */
  2.1033 -		case 9: /* UMULLS */
  2.1034 -		case 10: /* UMLAL */
  2.1035 -		case 11: /* UMLALS */
  2.1036 -		case 12: /* SMULL */
  2.1037 -		case 13: /* SMULLS */
  2.1038 -		case 14: /* SMLAL */
  2.1039 -		case 15: /* SMLALS */
  2.1040 -		    UNIMP(ir);
  2.1041 -		    break;
  2.1042 -		case 16: /* SWP */
  2.1043 -		    tmp = arm_read_long( RN(ir) );
  2.1044 -		    switch( RN(ir) & 0x03 ) {
  2.1045 -		    case 1:
  2.1046 -			tmp = ROTATE_RIGHT_LONG(tmp, 8);
  2.1047 -			break;
  2.1048 -		    case 2:
  2.1049 -			tmp = ROTATE_RIGHT_LONG(tmp, 16);
  2.1050 -			break;
  2.1051 -		    case 3:
  2.1052 -			tmp = ROTATE_RIGHT_LONG(tmp, 24);
  2.1053 -			break;
  2.1054 -		    }
  2.1055 -		    arm_write_long( RN(ir), RM(ir) );
  2.1056 -		    LRD(ir) = tmp;
  2.1057 -		    break;
  2.1058 -		case 20: /* SWPB */
  2.1059 -		    tmp = arm_read_byte( RN(ir) );
  2.1060 -		    arm_write_byte( RN(ir), RM(ir) );
  2.1061 -		    LRD(ir) = tmp;
  2.1062 -		    break;
  2.1063 -		default:
  2.1064 -		    UNIMP(ir);
  2.1065 -		}
  2.1066 -		break;
  2.1067 -	    case 1:
  2.1068 -		if( LFLAG(ir) ) {
  2.1069 -		    /* LDRH */
  2.1070 -		} else {
  2.1071 -		    /* STRH */
  2.1072 -		}
  2.1073 -		UNIMP(ir);
  2.1074 -		break;
  2.1075 -	    case 2:
  2.1076 -		if( LFLAG(ir) ) {
  2.1077 -		    /* LDRSB */
  2.1078 -		} else {
  2.1079 -		}
  2.1080 -		UNIMP(ir);
  2.1081 -		break;
  2.1082 -	    case 3:
  2.1083 -		if( LFLAG(ir) ) {
  2.1084 -		    /* LDRSH */
  2.1085 -		} else {
  2.1086 -		}
  2.1087 -		UNIMP(ir);
  2.1088 -		break;
  2.1089 -	    }
  2.1090 -	} else {
  2.1091 -	    /* Data processing */
  2.1092 +        /**
  2.1093 +         * Condition passed, now for the actual instructions...
  2.1094 +         */
  2.1095 +        switch( GRP(ir) ) {
  2.1096 +        case 0:
  2.1097 +            if( (ir & 0x0D900000) == 0x01000000 ) {
  2.1098 +                /* Instructions that aren't actual data processing even though
  2.1099 +                 * they sit in the DP instruction block.
  2.1100 +                 */
  2.1101 +                switch( ir & 0x0FF000F0 ) {
  2.1102 +                case 0x01200010: /* BX Rd */
  2.1103 +                    armr.t = ir & 0x01;
  2.1104 +                    armr.r[15] = RM(ir) & 0xFFFFFFFE;
  2.1105 +                    break;
  2.1106 +                case 0x01000000: /* MRS Rd, CPSR */
  2.1107 +                    LRD(ir) = arm_get_cpsr();
  2.1108 +                    break;
  2.1109 +                case 0x01400000: /* MRS Rd, SPSR */
  2.1110 +                    LRD(ir) = armr.spsr;
  2.1111 +                    break;
  2.1112 +                case 0x01200000: /* MSR CPSR, Rd */
  2.1113 +                    arm_set_cpsr( RM(ir), ir );
  2.1114 +                    break;
  2.1115 +                case 0x01600000: /* MSR SPSR, Rd */
  2.1116 +                    arm_set_spsr( RM(ir), ir );
  2.1117 +                    break;
  2.1118 +                case 0x03200000: /* MSR CPSR, imm */
  2.1119 +                    arm_set_cpsr( ROTIMM12(ir), ir );
  2.1120 +                    break;
  2.1121 +                case 0x03600000: /* MSR SPSR, imm */
  2.1122 +                    arm_set_spsr( ROTIMM12(ir), ir );
  2.1123 +                    break;
  2.1124 +                default:
  2.1125 +                    UNIMP(ir);
  2.1126 +                }
  2.1127 +            } else if( (ir & 0x0E000090) == 0x00000090 ) {
  2.1128 +                /* Neither are these */
  2.1129 +                switch( (ir>>5)&0x03 ) {
  2.1130 +                case 0:
  2.1131 +                    /* Arithmetic extension area */
  2.1132 +                    switch(OPCODE(ir)) {
  2.1133 +                    case 0: /* MUL */
  2.1134 +                        LRN(ir) = RM(ir) * RS(ir);
  2.1135 +                        break;
  2.1136 +                    case 1: /* MULS */
  2.1137 +                        tmp = RM(ir) * RS(ir);
  2.1138 +                        LRN(ir) = tmp;
  2.1139 +                        armr.n = tmp>>31;
  2.1140 +                        armr.z = (tmp == 0);
  2.1141 +                        break;
  2.1142 +                    case 2: /* MLA */
  2.1143 +                        LRN(ir) = RM(ir) * RS(ir) + RD(ir);
  2.1144 +                        break;
  2.1145 +                    case 3: /* MLAS */
  2.1146 +                        tmp = RM(ir) * RS(ir) + RD(ir);
  2.1147 +                        LRN(ir) = tmp;
  2.1148 +                        armr.n = tmp>>31;
  2.1149 +                        armr.z = (tmp == 0);
  2.1150 +                        break;
  2.1151 +                    case 8: /* UMULL */
  2.1152 +                    case 9: /* UMULLS */
  2.1153 +                    case 10: /* UMLAL */
  2.1154 +                    case 11: /* UMLALS */
  2.1155 +                    case 12: /* SMULL */
  2.1156 +                    case 13: /* SMULLS */
  2.1157 +                    case 14: /* SMLAL */
  2.1158 +                    case 15: /* SMLALS */
  2.1159 +                        UNIMP(ir);
  2.1160 +                        break;
  2.1161 +                    case 16: /* SWP */
  2.1162 +                        tmp = arm_read_long( RN(ir) );
  2.1163 +                        switch( RN(ir) & 0x03 ) {
  2.1164 +                        case 1:
  2.1165 +                            tmp = ROTATE_RIGHT_LONG(tmp, 8);
  2.1166 +                            break;
  2.1167 +                        case 2:
  2.1168 +                            tmp = ROTATE_RIGHT_LONG(tmp, 16);
  2.1169 +                            break;
  2.1170 +                        case 3:
  2.1171 +                            tmp = ROTATE_RIGHT_LONG(tmp, 24);
  2.1172 +                            break;
  2.1173 +                        }
  2.1174 +                        arm_write_long( RN(ir), RM(ir) );
  2.1175 +                        LRD(ir) = tmp;
  2.1176 +                        break;
  2.1177 +                        case 20: /* SWPB */
  2.1178 +                            tmp = arm_read_byte( RN(ir) );
  2.1179 +                            arm_write_byte( RN(ir), RM(ir) );
  2.1180 +                            LRD(ir) = tmp;
  2.1181 +                            break;
  2.1182 +                        default:
  2.1183 +                            UNIMP(ir);
  2.1184 +                    }
  2.1185 +                    break;
  2.1186 +                    case 1:
  2.1187 +                        if( LFLAG(ir) ) {
  2.1188 +                            /* LDRH */
  2.1189 +                        } else {
  2.1190 +                            /* STRH */
  2.1191 +                        }
  2.1192 +                        UNIMP(ir);
  2.1193 +                        break;
  2.1194 +                    case 2:
  2.1195 +                        if( LFLAG(ir) ) {
  2.1196 +                            /* LDRSB */
  2.1197 +                        } else {
  2.1198 +                        }
  2.1199 +                        UNIMP(ir);
  2.1200 +                        break;
  2.1201 +                    case 3:
  2.1202 +                        if( LFLAG(ir) ) {
  2.1203 +                            /* LDRSH */
  2.1204 +                        } else {
  2.1205 +                        }
  2.1206 +                        UNIMP(ir);
  2.1207 +                        break;
  2.1208 +                }
  2.1209 +            } else {
  2.1210 +                /* Data processing */
  2.1211  
  2.1212 -	    switch(OPCODE(ir)) {
  2.1213 -	    case 0: /* AND Rd, Rn, operand */
  2.1214 -		LRD(ir) = RN(ir) & arm_get_shift_operand(ir);
  2.1215 -		break;
  2.1216 -	    case 1: /* ANDS Rd, Rn, operand */
  2.1217 -		operand = arm_get_shift_operand_s(ir) & RN(ir);
  2.1218 -		LRD(ir) = operand;
  2.1219 -		if( RDn(ir) == 15 ) {
  2.1220 -		    arm_restore_cpsr();
  2.1221 -		} else {
  2.1222 -		    armr.n = operand>>31;
  2.1223 -		    armr.z = (operand == 0);
  2.1224 -		    armr.c = armr.shift_c;
  2.1225 -		}
  2.1226 -		break;
  2.1227 -	    case 2: /* EOR Rd, Rn, operand */
  2.1228 -		LRD(ir) = RN(ir) ^ arm_get_shift_operand(ir);
  2.1229 -		break;
  2.1230 -	    case 3: /* EORS Rd, Rn, operand */
  2.1231 -		operand = arm_get_shift_operand_s(ir) ^ RN(ir);
  2.1232 -		LRD(ir) = operand;
  2.1233 -		if( RDn(ir) == 15 ) {
  2.1234 -		    arm_restore_cpsr();
  2.1235 -		} else {
  2.1236 -		    armr.n = operand>>31;
  2.1237 -		    armr.z = (operand == 0);
  2.1238 -		    armr.c = armr.shift_c;
  2.1239 -		}
  2.1240 -		break;
  2.1241 -	    case 4: /* SUB Rd, Rn, operand */
  2.1242 -		LRD(ir) = RN(ir) - arm_get_shift_operand(ir);
  2.1243 -		break;
  2.1244 -	    case 5: /* SUBS Rd, Rn, operand */
  2.1245 -		operand = RN(ir);
  2.1246 -		operand2 = arm_get_shift_operand(ir);
  2.1247 -		tmp = operand - operand2;
  2.1248 -		LRD(ir) = tmp;
  2.1249 -		if( RDn(ir) == 15 ) {
  2.1250 -		    arm_restore_cpsr();
  2.1251 -		} else {
  2.1252 -		    armr.n = tmp>>31;
  2.1253 -		    armr.z = (tmp == 0);
  2.1254 -		    armr.c = IS_NOTBORROW(tmp,operand,operand2);
  2.1255 -		    armr.v = IS_SUBOVERFLOW(tmp,operand,operand2);
  2.1256 -		}
  2.1257 -		break;
  2.1258 -	    case 6: /* RSB Rd, operand, Rn */
  2.1259 -		LRD(ir) = arm_get_shift_operand(ir) - RN(ir);
  2.1260 -		break;
  2.1261 -	    case 7: /* RSBS Rd, operand, Rn */
  2.1262 -		operand = arm_get_shift_operand(ir);
  2.1263 -		operand2 = RN(ir);
  2.1264 -		tmp = operand - operand2;
  2.1265 -		LRD(ir) = tmp;
  2.1266 -		if( RDn(ir) == 15 ) {
  2.1267 -		    arm_restore_cpsr();
  2.1268 -		} else {
  2.1269 -		    armr.n = tmp>>31;
  2.1270 -		    armr.z = (tmp == 0);
  2.1271 -		    armr.c = IS_NOTBORROW(tmp,operand,operand2);
  2.1272 -		    armr.v = IS_SUBOVERFLOW(tmp,operand,operand2);
  2.1273 -		}
  2.1274 -		break;
  2.1275 -	    case 8: /* ADD Rd, Rn, operand */
  2.1276 -		LRD(ir) = RN(ir) + arm_get_shift_operand(ir);
  2.1277 -		break;
  2.1278 -	    case 9: /* ADDS Rd, Rn, operand */
  2.1279 -		operand = arm_get_shift_operand(ir);
  2.1280 -		operand2 = RN(ir);
  2.1281 -		tmp = operand + operand2;
  2.1282 -		LRD(ir) = tmp;
  2.1283 -		if( RDn(ir) == 15 ) {
  2.1284 -		    arm_restore_cpsr();
  2.1285 -		} else {
  2.1286 -		    armr.n = tmp>>31;
  2.1287 -		    armr.z = (tmp == 0);
  2.1288 -		    armr.c = IS_CARRY(tmp,operand,operand2);
  2.1289 -		    armr.v = IS_ADDOVERFLOW(tmp,operand,operand2);
  2.1290 -		}
  2.1291 -		break;			
  2.1292 -	    case 10: /* ADC */
  2.1293 -		LRD(ir) = RN(ir) + arm_get_shift_operand(ir) + 
  2.1294 -		    (armr.c ? 1 : 0);
  2.1295 -		break;
  2.1296 -	    case 11: /* ADCS */
  2.1297 -		operand = arm_get_shift_operand(ir);
  2.1298 -		operand2 = RN(ir);
  2.1299 -		tmp = operand + operand2;
  2.1300 -		tmp2 = tmp + armr.c ? 1 : 0;
  2.1301 -		LRD(ir) = tmp2;
  2.1302 -		if( RDn(ir) == 15 ) {
  2.1303 -		    arm_restore_cpsr();
  2.1304 -		} else {
  2.1305 -		    armr.n = tmp >> 31;
  2.1306 -		    armr.z = (tmp == 0 );
  2.1307 -		    armr.c = IS_CARRY(tmp,operand,operand2) ||
  2.1308 -			(tmp2 < tmp);
  2.1309 -		    armr.v = IS_ADDOVERFLOW(tmp,operand, operand2) ||
  2.1310 -			((tmp&0x80000000) != (tmp2&0x80000000));
  2.1311 -		}
  2.1312 -		break;
  2.1313 -	    case 12: /* SBC */
  2.1314 -		LRD(ir) = RN(ir) - arm_get_shift_operand(ir) - 
  2.1315 -		    (armr.c ? 0 : 1);
  2.1316 -		break;
  2.1317 -	    case 13: /* SBCS */
  2.1318 -		operand = RN(ir);
  2.1319 -		operand2 = arm_get_shift_operand(ir);
  2.1320 -		tmp = operand - operand2;
  2.1321 -		tmp2 = tmp - (armr.c ? 0 : 1);
  2.1322 -		if( RDn(ir) == 15 ) {
  2.1323 -		    arm_restore_cpsr();
  2.1324 -		} else {
  2.1325 -		    armr.n = tmp >> 31;
  2.1326 -		    armr.z = (tmp == 0 );
  2.1327 -		    armr.c = IS_NOTBORROW(tmp,operand,operand2) &&
  2.1328 -			(tmp2<tmp);
  2.1329 -		    armr.v = IS_SUBOVERFLOW(tmp,operand,operand2) ||
  2.1330 -			((tmp&0x80000000) != (tmp2&0x80000000));
  2.1331 -		}
  2.1332 -		break;
  2.1333 -	    case 14: /* RSC */
  2.1334 -		LRD(ir) = arm_get_shift_operand(ir) - RN(ir) -
  2.1335 -		    (armr.c ? 0 : 1);
  2.1336 -		break;
  2.1337 -	    case 15: /* RSCS */
  2.1338 -		operand = arm_get_shift_operand(ir);
  2.1339 -		operand2 = RN(ir);
  2.1340 -		tmp = operand - operand2;
  2.1341 -		tmp2 = tmp - (armr.c ? 0 : 1);
  2.1342 -		if( RDn(ir) == 15 ) {
  2.1343 -		    arm_restore_cpsr();
  2.1344 -		} else {
  2.1345 -		    armr.n = tmp >> 31;
  2.1346 -		    armr.z = (tmp == 0 );
  2.1347 -		    armr.c = IS_NOTBORROW(tmp,operand,operand2) &&
  2.1348 -			(tmp2<tmp);
  2.1349 -		    armr.v = IS_SUBOVERFLOW(tmp,operand,operand2) ||
  2.1350 -			((tmp&0x80000000) != (tmp2&0x80000000));
  2.1351 -		}
  2.1352 -		break;
  2.1353 -	    case 17: /* TST Rn, operand */
  2.1354 -		operand = arm_get_shift_operand_s(ir) & RN(ir);
  2.1355 -		armr.n = operand>>31;
  2.1356 -		armr.z = (operand == 0);
  2.1357 -		armr.c = armr.shift_c;
  2.1358 -		break;
  2.1359 -	    case 19: /* TEQ Rn, operand */
  2.1360 -		operand = arm_get_shift_operand_s(ir) ^ RN(ir);
  2.1361 -		armr.n = operand>>31;
  2.1362 -		armr.z = (operand == 0);
  2.1363 -		armr.c = armr.shift_c;
  2.1364 -		break;				
  2.1365 -	    case 21: /* CMP Rn, operand */
  2.1366 -		operand = RN(ir);
  2.1367 -		operand2 = arm_get_shift_operand(ir);
  2.1368 -		tmp = operand - operand2;
  2.1369 -		armr.n = tmp>>31;
  2.1370 -		armr.z = (tmp == 0);
  2.1371 -		armr.c = IS_NOTBORROW(tmp,operand,operand2);
  2.1372 -		armr.v = IS_SUBOVERFLOW(tmp,operand,operand2);
  2.1373 -		break;
  2.1374 -	    case 23: /* CMN Rn, operand */
  2.1375 -		operand = RN(ir);
  2.1376 -		operand2 = arm_get_shift_operand(ir);
  2.1377 -		tmp = operand + operand2;
  2.1378 -		armr.n = tmp>>31;
  2.1379 -		armr.z = (tmp == 0);
  2.1380 -		armr.c = IS_CARRY(tmp,operand,operand2);
  2.1381 -		armr.v = IS_ADDOVERFLOW(tmp,operand,operand2);
  2.1382 -		break;
  2.1383 -	    case 24: /* ORR Rd, Rn, operand */
  2.1384 -		LRD(ir) = RN(ir) | arm_get_shift_operand(ir);
  2.1385 -		break;
  2.1386 -	    case 25: /* ORRS Rd, Rn, operand */
  2.1387 -		operand = arm_get_shift_operand_s(ir) | RN(ir);
  2.1388 -		LRD(ir) = operand;
  2.1389 -		if( RDn(ir) == 15 ) {
  2.1390 -		    arm_restore_cpsr();
  2.1391 -		} else {
  2.1392 -		    armr.n = operand>>31;
  2.1393 -		    armr.z = (operand == 0);
  2.1394 -		    armr.c = armr.shift_c;
  2.1395 -		}
  2.1396 -		break;
  2.1397 -	    case 26: /* MOV Rd, operand */
  2.1398 -		LRD(ir) = arm_get_shift_operand(ir);
  2.1399 -		break;
  2.1400 -	    case 27: /* MOVS Rd, operand */
  2.1401 -		operand = arm_get_shift_operand_s(ir);
  2.1402 -		LRD(ir) = operand;
  2.1403 -		if( RDn(ir) == 15 ) {
  2.1404 -		    arm_restore_cpsr();
  2.1405 -		} else {
  2.1406 -		    armr.n = operand>>31;
  2.1407 -		    armr.z = (operand == 0);
  2.1408 -		    armr.c = armr.shift_c;
  2.1409 -		}
  2.1410 -		break;
  2.1411 -	    case 28: /* BIC Rd, Rn, operand */
  2.1412 -		LRD(ir) = RN(ir) & (~arm_get_shift_operand(ir));
  2.1413 -		break;
  2.1414 -	    case 29: /* BICS Rd, Rn, operand */
  2.1415 -		operand = RN(ir) & (~arm_get_shift_operand_s(ir));
  2.1416 -		LRD(ir) = operand;
  2.1417 -		if( RDn(ir) == 15 ) {
  2.1418 -		    arm_restore_cpsr();
  2.1419 -		} else {
  2.1420 -		    armr.n = operand>>31;
  2.1421 -		    armr.z = (operand == 0);
  2.1422 -		    armr.c = armr.shift_c;
  2.1423 -		}
  2.1424 -		break;
  2.1425 -	    case 30: /* MVN Rd, operand */
  2.1426 -		LRD(ir) = ~arm_get_shift_operand(ir);
  2.1427 -		break;
  2.1428 -	    case 31: /* MVNS Rd, operand */
  2.1429 -		operand = ~arm_get_shift_operand_s(ir);
  2.1430 -		LRD(ir) = operand;
  2.1431 -		if( RDn(ir) == 15 ) {
  2.1432 -		    arm_restore_cpsr();
  2.1433 -		} else {
  2.1434 -		    armr.n = operand>>31;
  2.1435 -		    armr.z = (operand == 0);
  2.1436 -		    armr.c = armr.shift_c;
  2.1437 -		}
  2.1438 -		break;
  2.1439 -	    default:
  2.1440 -		UNIMP(ir);
  2.1441 -	    }
  2.1442 -	}
  2.1443 -	break;
  2.1444 -    case 1: /* Load/store */
  2.1445 -	operand = arm_get_address_operand(ir);
  2.1446 -	switch( (ir>>20)&0x17 ) {
  2.1447 -	case 0: case 16: case 18: /* STR Rd, address */
  2.1448 -	    arm_write_long( operand, RD(ir) );
  2.1449 -	    break;
  2.1450 -	case 1: case 17: case 19: /* LDR Rd, address */
  2.1451 -	    LRD(ir) = arm_read_long(operand);
  2.1452 -	    break;
  2.1453 -	case 2: /* STRT Rd, address */
  2.1454 -	    arm_write_long_user( operand, RD(ir) );
  2.1455 -	    break;
  2.1456 -	case 3: /* LDRT Rd, address */
  2.1457 -	    LRD(ir) = arm_read_long_user( operand );
  2.1458 -	    break;
  2.1459 -	case 4: case 20: case 22: /* STRB Rd, address */
  2.1460 -	    arm_write_byte( operand, RD(ir) );
  2.1461 -	    break;
  2.1462 -	case 5: case 21: case 23: /* LDRB Rd, address */
  2.1463 -	    LRD(ir) = arm_read_byte( operand );
  2.1464 -	    break;
  2.1465 -	case 6: /* STRBT Rd, address */
  2.1466 -	    arm_write_byte_user( operand, RD(ir) );
  2.1467 -	    break;
  2.1468 -	case 7: /* LDRBT Rd, address */
  2.1469 -	    LRD(ir) = arm_read_byte_user( operand );
  2.1470 -	    break;
  2.1471 -	}
  2.1472 -	break;
  2.1473 -    case 2: /* Load/store multiple, branch*/
  2.1474 -	if( (ir & 0x02000000) == 0x02000000 ) { /* B[L] imm24 */
  2.1475 -	    operand = (SIGNEXT24(ir&0x00FFFFFF) << 2);
  2.1476 -	    if( (ir & 0x01000000) == 0x01000000 ) { 
  2.1477 -		armr.r[14] = pc; /* BL */
  2.1478 -	    }
  2.1479 -	    armr.r[15] = pc + 4 + operand;
  2.1480 -	} else { /* Load/store multiple */
  2.1481 -	    gboolean needRestore = FALSE;
  2.1482 -	    operand = RN(ir);
  2.1483 -	    
  2.1484 -	    switch( (ir & 0x01D00000) >> 20 ) {
  2.1485 -	    case 0: /* STMDA */
  2.1486 -		if( ir & 0x8000 ) {
  2.1487 -		    arm_write_long( operand, armr.r[15]+4 );
  2.1488 -		    operand -= 4;
  2.1489 -		}
  2.1490 -		for( i=14; i>= 0; i-- ) {
  2.1491 -		    if( (ir & (1<<i)) ) {
  2.1492 -			arm_write_long( operand, armr.r[i] );
  2.1493 -			operand -= 4;
  2.1494 -		    }
  2.1495 -		}
  2.1496 -		break;
  2.1497 -	    case 1: /* LDMDA */
  2.1498 -		for( i=15; i>= 0; i-- ) {
  2.1499 -		    if( (ir & (1<<i)) ) {
  2.1500 -			armr.r[i] = arm_read_long( operand );
  2.1501 -			operand -= 4;
  2.1502 -		    }
  2.1503 -		}
  2.1504 -		break;
  2.1505 -	    case 4: /* STMDA (S) */
  2.1506 -		if( ir & 0x8000 ) {
  2.1507 -		    arm_write_long( operand, armr.r[15]+4 );
  2.1508 -		    operand -= 4;
  2.1509 -		}
  2.1510 -		for( i=14; i>= 0; i-- ) {
  2.1511 -		    if( (ir & (1<<i)) ) {
  2.1512 -			arm_write_long( operand, USER_R(i) );
  2.1513 -			operand -= 4;
  2.1514 -		    }
  2.1515 -		}
  2.1516 -		break;
  2.1517 -	    case 5: /* LDMDA (S) */
  2.1518 -		if( (ir&0x00008000) ) { /* Load PC */
  2.1519 -		    for( i=15; i>= 0; i-- ) {
  2.1520 -			if( (ir & (1<<i)) ) {
  2.1521 -			    armr.r[i] = arm_read_long( operand );
  2.1522 -			    operand -= 4;
  2.1523 -			}
  2.1524 -		    }
  2.1525 -		    needRestore = TRUE;
  2.1526 -		} else {
  2.1527 -		    for( i=15; i>= 0; i-- ) {
  2.1528 -			if( (ir & (1<<i)) ) {
  2.1529 -			    USER_R(i) = arm_read_long( operand );
  2.1530 -			    operand -= 4;
  2.1531 -			}
  2.1532 -		    }
  2.1533 -		}
  2.1534 -		break;
  2.1535 -	    case 8: /* STMIA */
  2.1536 -		for( i=0; i< 15; i++ ) {
  2.1537 -		    if( (ir & (1<<i)) ) {
  2.1538 -			arm_write_long( operand, armr.r[i] );
  2.1539 -			operand += 4;
  2.1540 -		    }
  2.1541 -		}
  2.1542 -		if( ir & 0x8000 ) {
  2.1543 -		    arm_write_long( operand, armr.r[15]+4 );
  2.1544 -		    operand += 4;
  2.1545 -		}
  2.1546 -		break;
  2.1547 -	    case 9: /* LDMIA */
  2.1548 -		for( i=0; i< 16; i++ ) {
  2.1549 -		    if( (ir & (1<<i)) ) {
  2.1550 -			armr.r[i] = arm_read_long( operand );
  2.1551 -			operand += 4;
  2.1552 -		    }
  2.1553 -		}
  2.1554 -		break;
  2.1555 -	    case 12: /* STMIA (S) */
  2.1556 -		for( i=0; i< 15; i++ ) {
  2.1557 -		    if( (ir & (1<<i)) ) {
  2.1558 -			arm_write_long( operand, USER_R(i) );
  2.1559 -			operand += 4;
  2.1560 -		    }
  2.1561 -		}
  2.1562 -		if( ir & 0x8000 ) {
  2.1563 -		    arm_write_long( operand, armr.r[15]+4 );
  2.1564 -		    operand += 4;
  2.1565 -		}
  2.1566 -		break;
  2.1567 -	    case 13: /* LDMIA (S) */
  2.1568 -		if( (ir&0x00008000) ) { /* Load PC */
  2.1569 -		    for( i=0; i < 16; i++ ) {
  2.1570 -			if( (ir & (1<<i)) ) {
  2.1571 -			    armr.r[i] = arm_read_long( operand );
  2.1572 -			    operand += 4;
  2.1573 -			}
  2.1574 -		    }
  2.1575 -		    needRestore = TRUE;
  2.1576 -		} else {
  2.1577 -		    for( i=0; i < 16; i++ ) {
  2.1578 -			if( (ir & (1<<i)) ) {
  2.1579 -			    USER_R(i) = arm_read_long( operand );
  2.1580 -			    operand += 4;
  2.1581 -			}
  2.1582 -		    }
  2.1583 -		}
  2.1584 -		break;
  2.1585 -	    case 16: /* STMDB */
  2.1586 -		if( ir & 0x8000 ) {
  2.1587 -		    operand -= 4;
  2.1588 -		    arm_write_long( operand, armr.r[15]+4 );
  2.1589 -		}
  2.1590 -		for( i=14; i>= 0; i-- ) {
  2.1591 -		    if( (ir & (1<<i)) ) {
  2.1592 -			operand -= 4;
  2.1593 -			arm_write_long( operand, armr.r[i] );
  2.1594 -		    }
  2.1595 -		}
  2.1596 -		break;
  2.1597 -	    case 17: /* LDMDB */
  2.1598 -		for( i=15; i>= 0; i-- ) {
  2.1599 -		    if( (ir & (1<<i)) ) {
  2.1600 -			operand -= 4;
  2.1601 -			armr.r[i] = arm_read_long( operand );
  2.1602 -		    }
  2.1603 -		}
  2.1604 -		break;
  2.1605 -	    case 20: /* STMDB (S) */
  2.1606 -		if( ir & 0x8000 ) {
  2.1607 -		    operand -= 4;
  2.1608 -		    arm_write_long( operand, armr.r[15]+4 );
  2.1609 -		}
  2.1610 -		for( i=14; i>= 0; i-- ) {
  2.1611 -		    if( (ir & (1<<i)) ) {
  2.1612 -			operand -= 4;
  2.1613 -			arm_write_long( operand, USER_R(i) );
  2.1614 -		    }
  2.1615 -		}
  2.1616 -		break;
  2.1617 -	    case 21: /* LDMDB (S) */
  2.1618 -		if( (ir&0x00008000) ) { /* Load PC */
  2.1619 -		    for( i=15; i>= 0; i-- ) {
  2.1620 -			if( (ir & (1<<i)) ) {
  2.1621 -			    operand -= 4;
  2.1622 -			    armr.r[i] = arm_read_long( operand );
  2.1623 -			}
  2.1624 -		    }
  2.1625 -		    needRestore = TRUE;
  2.1626 -		} else {
  2.1627 -		    for( i=15; i>= 0; i-- ) {
  2.1628 -			if( (ir & (1<<i)) ) {
  2.1629 -			    operand -= 4;
  2.1630 -			    USER_R(i) = arm_read_long( operand );
  2.1631 -			}
  2.1632 -		    }
  2.1633 -		}
  2.1634 -		break;
  2.1635 -	    case 24: /* STMIB */
  2.1636 -		for( i=0; i< 15; i++ ) {
  2.1637 -		    if( (ir & (1<<i)) ) {
  2.1638 -			operand += 4;
  2.1639 -			arm_write_long( operand, armr.r[i] );
  2.1640 -		    }
  2.1641 -		}
  2.1642 -		if( ir & 0x8000 ) {
  2.1643 -		    operand += 4;
  2.1644 -		    arm_write_long( operand, armr.r[15]+4 );
  2.1645 -		}
  2.1646 -		break;
  2.1647 -	    case 25: /* LDMIB */
  2.1648 -		for( i=0; i< 16; i++ ) {
  2.1649 -		    if( (ir & (1<<i)) ) {
  2.1650 -			operand += 4;
  2.1651 -			armr.r[i] = arm_read_long( operand );
  2.1652 -		    }
  2.1653 -		}
  2.1654 -		break;
  2.1655 -	    case 28: /* STMIB (S) */
  2.1656 -		for( i=0; i< 15; i++ ) {
  2.1657 -		    if( (ir & (1<<i)) ) {
  2.1658 -			operand += 4;
  2.1659 -			arm_write_long( operand, USER_R(i) );
  2.1660 -		    }
  2.1661 -		}
  2.1662 -		if( ir & 0x8000 ) {
  2.1663 -		    operand += 4;
  2.1664 -		    arm_write_long( operand, armr.r[15]+4 );
  2.1665 -		}
  2.1666 -		break;
  2.1667 -	    case 29: /* LDMIB (S) */
  2.1668 -		if( (ir&0x00008000) ) { /* Load PC */
  2.1669 -		    for( i=0; i < 16; i++ ) {
  2.1670 -			if( (ir & (1<<i)) ) {
  2.1671 -			    operand += 4;
  2.1672 -			    armr.r[i] = arm_read_long( operand );
  2.1673 -			}
  2.1674 -		    }
  2.1675 -		    needRestore = TRUE;
  2.1676 -		} else {
  2.1677 -		    for( i=0; i < 16; i++ ) {
  2.1678 -			if( (ir & (1<<i)) ) {
  2.1679 -			    operand += 4;
  2.1680 -			    USER_R(i) = arm_read_long( operand );
  2.1681 -			}
  2.1682 -		    }
  2.1683 -		}
  2.1684 -		break;
  2.1685 -	    }
  2.1686 -	    
  2.1687 -	    if( WFLAG(ir) ) 
  2.1688 -		LRN(ir) = operand;
  2.1689 -	    if( needRestore ) 
  2.1690 -		arm_restore_cpsr();
  2.1691 -	}
  2.1692 -	break;
  2.1693 -    case 3: /* Copro */
  2.1694 -	if( (ir & 0x0F000000) == 0x0F000000 ) { /* SWI */
  2.1695 -	    arm_raise_exception( EXC_SOFTWARE );
  2.1696 -	} else {
  2.1697 -	    UNIMP(ir);
  2.1698 -	}
  2.1699 -	break;
  2.1700 -    }
  2.1701 +                switch(OPCODE(ir)) {
  2.1702 +                case 0: /* AND Rd, Rn, operand */
  2.1703 +                    LRD(ir) = RN(ir) & arm_get_shift_operand(ir);
  2.1704 +                    break;
  2.1705 +                case 1: /* ANDS Rd, Rn, operand */
  2.1706 +                    operand = arm_get_shift_operand_s(ir) & RN(ir);
  2.1707 +                    LRD(ir) = operand;
  2.1708 +                    if( RDn(ir) == 15 ) {
  2.1709 +                        arm_restore_cpsr();
  2.1710 +                    } else {
  2.1711 +                        armr.n = operand>>31;
  2.1712 +                        armr.z = (operand == 0);
  2.1713 +                        armr.c = armr.shift_c;
  2.1714 +                    }
  2.1715 +                    break;
  2.1716 +                case 2: /* EOR Rd, Rn, operand */
  2.1717 +                    LRD(ir) = RN(ir) ^ arm_get_shift_operand(ir);
  2.1718 +                    break;
  2.1719 +                case 3: /* EORS Rd, Rn, operand */
  2.1720 +                    operand = arm_get_shift_operand_s(ir) ^ RN(ir);
  2.1721 +                    LRD(ir) = operand;
  2.1722 +                    if( RDn(ir) == 15 ) {
  2.1723 +                        arm_restore_cpsr();
  2.1724 +                    } else {
  2.1725 +                        armr.n = operand>>31;
  2.1726 +                        armr.z = (operand == 0);
  2.1727 +                        armr.c = armr.shift_c;
  2.1728 +                    }
  2.1729 +                    break;
  2.1730 +                case 4: /* SUB Rd, Rn, operand */
  2.1731 +                    LRD(ir) = RN(ir) - arm_get_shift_operand(ir);
  2.1732 +                    break;
  2.1733 +                case 5: /* SUBS Rd, Rn, operand */
  2.1734 +                    operand = RN(ir);
  2.1735 +                    operand2 = arm_get_shift_operand(ir);
  2.1736 +                    tmp = operand - operand2;
  2.1737 +                    LRD(ir) = tmp;
  2.1738 +                    if( RDn(ir) == 15 ) {
  2.1739 +                        arm_restore_cpsr();
  2.1740 +                    } else {
  2.1741 +                        armr.n = tmp>>31;
  2.1742 +                        armr.z = (tmp == 0);
  2.1743 +                        armr.c = IS_NOTBORROW(tmp,operand,operand2);
  2.1744 +                        armr.v = IS_SUBOVERFLOW(tmp,operand,operand2);
  2.1745 +                    }
  2.1746 +                    break;
  2.1747 +                case 6: /* RSB Rd, operand, Rn */
  2.1748 +                    LRD(ir) = arm_get_shift_operand(ir) - RN(ir);
  2.1749 +                    break;
  2.1750 +                case 7: /* RSBS Rd, operand, Rn */
  2.1751 +                    operand = arm_get_shift_operand(ir);
  2.1752 +                    operand2 = RN(ir);
  2.1753 +                    tmp = operand - operand2;
  2.1754 +                    LRD(ir) = tmp;
  2.1755 +                    if( RDn(ir) == 15 ) {
  2.1756 +                        arm_restore_cpsr();
  2.1757 +                    } else {
  2.1758 +                        armr.n = tmp>>31;
  2.1759 +                        armr.z = (tmp == 0);
  2.1760 +                        armr.c = IS_NOTBORROW(tmp,operand,operand2);
  2.1761 +                        armr.v = IS_SUBOVERFLOW(tmp,operand,operand2);
  2.1762 +                    }
  2.1763 +                    break;
  2.1764 +                case 8: /* ADD Rd, Rn, operand */
  2.1765 +                    LRD(ir) = RN(ir) + arm_get_shift_operand(ir);
  2.1766 +                    break;
  2.1767 +                case 9: /* ADDS Rd, Rn, operand */
  2.1768 +                    operand = arm_get_shift_operand(ir);
  2.1769 +                    operand2 = RN(ir);
  2.1770 +                    tmp = operand + operand2;
  2.1771 +                    LRD(ir) = tmp;
  2.1772 +                    if( RDn(ir) == 15 ) {
  2.1773 +                        arm_restore_cpsr();
  2.1774 +                    } else {
  2.1775 +                        armr.n = tmp>>31;
  2.1776 +                        armr.z = (tmp == 0);
  2.1777 +                        armr.c = IS_CARRY(tmp,operand,operand2);
  2.1778 +                        armr.v = IS_ADDOVERFLOW(tmp,operand,operand2);
  2.1779 +                    }
  2.1780 +                    break;			
  2.1781 +                case 10: /* ADC */
  2.1782 +                    LRD(ir) = RN(ir) + arm_get_shift_operand(ir) + 
  2.1783 +                    (armr.c ? 1 : 0);
  2.1784 +                    break;
  2.1785 +                case 11: /* ADCS */
  2.1786 +                    operand = arm_get_shift_operand(ir);
  2.1787 +                    operand2 = RN(ir);
  2.1788 +                    tmp = operand + operand2;
  2.1789 +                    tmp2 = tmp + armr.c ? 1 : 0;
  2.1790 +                    LRD(ir) = tmp2;
  2.1791 +                    if( RDn(ir) == 15 ) {
  2.1792 +                        arm_restore_cpsr();
  2.1793 +                    } else {
  2.1794 +                        armr.n = tmp >> 31;
  2.1795 +                        armr.z = (tmp == 0 );
  2.1796 +                        armr.c = IS_CARRY(tmp,operand,operand2) ||
  2.1797 +                        (tmp2 < tmp);
  2.1798 +                        armr.v = IS_ADDOVERFLOW(tmp,operand, operand2) ||
  2.1799 +                        ((tmp&0x80000000) != (tmp2&0x80000000));
  2.1800 +                    }
  2.1801 +                    break;
  2.1802 +                case 12: /* SBC */
  2.1803 +                    LRD(ir) = RN(ir) - arm_get_shift_operand(ir) - 
  2.1804 +                    (armr.c ? 0 : 1);
  2.1805 +                    break;
  2.1806 +                case 13: /* SBCS */
  2.1807 +                    operand = RN(ir);
  2.1808 +                    operand2 = arm_get_shift_operand(ir);
  2.1809 +                    tmp = operand - operand2;
  2.1810 +                    tmp2 = tmp - (armr.c ? 0 : 1);
  2.1811 +                    if( RDn(ir) == 15 ) {
  2.1812 +                        arm_restore_cpsr();
  2.1813 +                    } else {
  2.1814 +                        armr.n = tmp >> 31;
  2.1815 +                        armr.z = (tmp == 0 );
  2.1816 +                        armr.c = IS_NOTBORROW(tmp,operand,operand2) &&
  2.1817 +                        (tmp2<tmp);
  2.1818 +                        armr.v = IS_SUBOVERFLOW(tmp,operand,operand2) ||
  2.1819 +                        ((tmp&0x80000000) != (tmp2&0x80000000));
  2.1820 +                    }
  2.1821 +                    break;
  2.1822 +                case 14: /* RSC */
  2.1823 +                    LRD(ir) = arm_get_shift_operand(ir) - RN(ir) -
  2.1824 +                    (armr.c ? 0 : 1);
  2.1825 +                    break;
  2.1826 +                case 15: /* RSCS */
  2.1827 +                    operand = arm_get_shift_operand(ir);
  2.1828 +                    operand2 = RN(ir);
  2.1829 +                    tmp = operand - operand2;
  2.1830 +                    tmp2 = tmp - (armr.c ? 0 : 1);
  2.1831 +                    if( RDn(ir) == 15 ) {
  2.1832 +                        arm_restore_cpsr();
  2.1833 +                    } else {
  2.1834 +                        armr.n = tmp >> 31;
  2.1835 +                        armr.z = (tmp == 0 );
  2.1836 +                        armr.c = IS_NOTBORROW(tmp,operand,operand2) &&
  2.1837 +                        (tmp2<tmp);
  2.1838 +                        armr.v = IS_SUBOVERFLOW(tmp,operand,operand2) ||
  2.1839 +                        ((tmp&0x80000000) != (tmp2&0x80000000));
  2.1840 +                    }
  2.1841 +                    break;
  2.1842 +                case 17: /* TST Rn, operand */
  2.1843 +                    operand = arm_get_shift_operand_s(ir) & RN(ir);
  2.1844 +                    armr.n = operand>>31;
  2.1845 +                    armr.z = (operand == 0);
  2.1846 +                    armr.c = armr.shift_c;
  2.1847 +                    break;
  2.1848 +                case 19: /* TEQ Rn, operand */
  2.1849 +                    operand = arm_get_shift_operand_s(ir) ^ RN(ir);
  2.1850 +                    armr.n = operand>>31;
  2.1851 +                    armr.z = (operand == 0);
  2.1852 +                    armr.c = armr.shift_c;
  2.1853 +                    break;				
  2.1854 +                case 21: /* CMP Rn, operand */
  2.1855 +                    operand = RN(ir);
  2.1856 +                    operand2 = arm_get_shift_operand(ir);
  2.1857 +                    tmp = operand - operand2;
  2.1858 +                    armr.n = tmp>>31;
  2.1859 +                    armr.z = (tmp == 0);
  2.1860 +                    armr.c = IS_NOTBORROW(tmp,operand,operand2);
  2.1861 +                    armr.v = IS_SUBOVERFLOW(tmp,operand,operand2);
  2.1862 +                    break;
  2.1863 +                case 23: /* CMN Rn, operand */
  2.1864 +                    operand = RN(ir);
  2.1865 +                    operand2 = arm_get_shift_operand(ir);
  2.1866 +                    tmp = operand + operand2;
  2.1867 +                    armr.n = tmp>>31;
  2.1868 +                    armr.z = (tmp == 0);
  2.1869 +                    armr.c = IS_CARRY(tmp,operand,operand2);
  2.1870 +                    armr.v = IS_ADDOVERFLOW(tmp,operand,operand2);
  2.1871 +                    break;
  2.1872 +                case 24: /* ORR Rd, Rn, operand */
  2.1873 +                    LRD(ir) = RN(ir) | arm_get_shift_operand(ir);
  2.1874 +                    break;
  2.1875 +                case 25: /* ORRS Rd, Rn, operand */
  2.1876 +                    operand = arm_get_shift_operand_s(ir) | RN(ir);
  2.1877 +                    LRD(ir) = operand;
  2.1878 +                    if( RDn(ir) == 15 ) {
  2.1879 +                        arm_restore_cpsr();
  2.1880 +                    } else {
  2.1881 +                        armr.n = operand>>31;
  2.1882 +                        armr.z = (operand == 0);
  2.1883 +                        armr.c = armr.shift_c;
  2.1884 +                    }
  2.1885 +                    break;
  2.1886 +                case 26: /* MOV Rd, operand */
  2.1887 +                    LRD(ir) = arm_get_shift_operand(ir);
  2.1888 +                    break;
  2.1889 +                case 27: /* MOVS Rd, operand */
  2.1890 +                    operand = arm_get_shift_operand_s(ir);
  2.1891 +                    LRD(ir) = operand;
  2.1892 +                    if( RDn(ir) == 15 ) {
  2.1893 +                        arm_restore_cpsr();
  2.1894 +                    } else {
  2.1895 +                        armr.n = operand>>31;
  2.1896 +                        armr.z = (operand == 0);
  2.1897 +                        armr.c = armr.shift_c;
  2.1898 +                    }
  2.1899 +                    break;
  2.1900 +                case 28: /* BIC Rd, Rn, operand */
  2.1901 +                    LRD(ir) = RN(ir) & (~arm_get_shift_operand(ir));
  2.1902 +                    break;
  2.1903 +                case 29: /* BICS Rd, Rn, operand */
  2.1904 +                    operand = RN(ir) & (~arm_get_shift_operand_s(ir));
  2.1905 +                    LRD(ir) = operand;
  2.1906 +                    if( RDn(ir) == 15 ) {
  2.1907 +                        arm_restore_cpsr();
  2.1908 +                    } else {
  2.1909 +                        armr.n = operand>>31;
  2.1910 +                        armr.z = (operand == 0);
  2.1911 +                        armr.c = armr.shift_c;
  2.1912 +                    }
  2.1913 +                    break;
  2.1914 +                case 30: /* MVN Rd, operand */
  2.1915 +                    LRD(ir) = ~arm_get_shift_operand(ir);
  2.1916 +                    break;
  2.1917 +                case 31: /* MVNS Rd, operand */
  2.1918 +                    operand = ~arm_get_shift_operand_s(ir);
  2.1919 +                    LRD(ir) = operand;
  2.1920 +                    if( RDn(ir) == 15 ) {
  2.1921 +                        arm_restore_cpsr();
  2.1922 +                    } else {
  2.1923 +                        armr.n = operand>>31;
  2.1924 +                        armr.z = (operand == 0);
  2.1925 +                        armr.c = armr.shift_c;
  2.1926 +                    }
  2.1927 +                    break;
  2.1928 +                default:
  2.1929 +                    UNIMP(ir);
  2.1930 +                }
  2.1931 +            }
  2.1932 +            break;
  2.1933 +        case 1: /* Load/store */
  2.1934 +            operand = arm_get_address_operand(ir);
  2.1935 +            switch( (ir>>20)&0x17 ) {
  2.1936 +            case 0: case 16: case 18: /* STR Rd, address */
  2.1937 +                arm_write_long( operand, RD(ir) );
  2.1938 +                break;
  2.1939 +            case 1: case 17: case 19: /* LDR Rd, address */
  2.1940 +                LRD(ir) = arm_read_long(operand);
  2.1941 +                break;
  2.1942 +            case 2: /* STRT Rd, address */
  2.1943 +                arm_write_long_user( operand, RD(ir) );
  2.1944 +                break;
  2.1945 +            case 3: /* LDRT Rd, address */
  2.1946 +                LRD(ir) = arm_read_long_user( operand );
  2.1947 +                break;
  2.1948 +            case 4: case 20: case 22: /* STRB Rd, address */
  2.1949 +                arm_write_byte( operand, RD(ir) );
  2.1950 +                break;
  2.1951 +            case 5: case 21: case 23: /* LDRB Rd, address */
  2.1952 +                LRD(ir) = arm_read_byte( operand );
  2.1953 +                break;
  2.1954 +            case 6: /* STRBT Rd, address */
  2.1955 +                arm_write_byte_user( operand, RD(ir) );
  2.1956 +                break;
  2.1957 +            case 7: /* LDRBT Rd, address */
  2.1958 +                LRD(ir) = arm_read_byte_user( operand );
  2.1959 +                break;
  2.1960 +            }
  2.1961 +            break;
  2.1962 +            case 2: /* Load/store multiple, branch*/
  2.1963 +                if( (ir & 0x02000000) == 0x02000000 ) { /* B[L] imm24 */
  2.1964 +                    operand = (SIGNEXT24(ir&0x00FFFFFF) << 2);
  2.1965 +                    if( (ir & 0x01000000) == 0x01000000 ) { 
  2.1966 +                        armr.r[14] = pc; /* BL */
  2.1967 +                    }
  2.1968 +                    armr.r[15] = pc + 4 + operand;
  2.1969 +                } else { /* Load/store multiple */
  2.1970 +                    gboolean needRestore = FALSE;
  2.1971 +                    operand = RN(ir);
  2.1972 +
  2.1973 +                    switch( (ir & 0x01D00000) >> 20 ) {
  2.1974 +                    case 0: /* STMDA */
  2.1975 +                        if( ir & 0x8000 ) {
  2.1976 +                            arm_write_long( operand, armr.r[15]+4 );
  2.1977 +                            operand -= 4;
  2.1978 +                        }
  2.1979 +                        for( i=14; i>= 0; i-- ) {
  2.1980 +                            if( (ir & (1<<i)) ) {
  2.1981 +                                arm_write_long( operand, armr.r[i] );
  2.1982 +                                operand -= 4;
  2.1983 +                            }
  2.1984 +                        }
  2.1985 +                        break;
  2.1986 +                    case 1: /* LDMDA */
  2.1987 +                        for( i=15; i>= 0; i-- ) {
  2.1988 +                            if( (ir & (1<<i)) ) {
  2.1989 +                                armr.r[i] = arm_read_long( operand );
  2.1990 +                                operand -= 4;
  2.1991 +                            }
  2.1992 +                        }
  2.1993 +                        break;
  2.1994 +                    case 4: /* STMDA (S) */
  2.1995 +                        if( ir & 0x8000 ) {
  2.1996 +                            arm_write_long( operand, armr.r[15]+4 );
  2.1997 +                            operand -= 4;
  2.1998 +                        }
  2.1999 +                        for( i=14; i>= 0; i-- ) {
  2.2000 +                            if( (ir & (1<<i)) ) {
  2.2001 +                                arm_write_long( operand, USER_R(i) );
  2.2002 +                                operand -= 4;
  2.2003 +                            }
  2.2004 +                        }
  2.2005 +                        break;
  2.2006 +                    case 5: /* LDMDA (S) */
  2.2007 +                        if( (ir&0x00008000) ) { /* Load PC */
  2.2008 +                            for( i=15; i>= 0; i-- ) {
  2.2009 +                                if( (ir & (1<<i)) ) {
  2.2010 +                                    armr.r[i] = arm_read_long( operand );
  2.2011 +                                    operand -= 4;
  2.2012 +                                }
  2.2013 +                            }
  2.2014 +                            needRestore = TRUE;
  2.2015 +                        } else {
  2.2016 +                            for( i=15; i>= 0; i-- ) {
  2.2017 +                                if( (ir & (1<<i)) ) {
  2.2018 +                                    USER_R(i) = arm_read_long( operand );
  2.2019 +                                    operand -= 4;
  2.2020 +                                }
  2.2021 +                            }
  2.2022 +                        }
  2.2023 +                        break;
  2.2024 +                    case 8: /* STMIA */
  2.2025 +                        for( i=0; i< 15; i++ ) {
  2.2026 +                            if( (ir & (1<<i)) ) {
  2.2027 +                                arm_write_long( operand, armr.r[i] );
  2.2028 +                                operand += 4;
  2.2029 +                            }
  2.2030 +                        }
  2.2031 +                        if( ir & 0x8000 ) {
  2.2032 +                            arm_write_long( operand, armr.r[15]+4 );
  2.2033 +                            operand += 4;
  2.2034 +                        }
  2.2035 +                        break;
  2.2036 +                    case 9: /* LDMIA */
  2.2037 +                        for( i=0; i< 16; i++ ) {
  2.2038 +                            if( (ir & (1<<i)) ) {
  2.2039 +                                armr.r[i] = arm_read_long( operand );
  2.2040 +                                operand += 4;
  2.2041 +                            }
  2.2042 +                        }
  2.2043 +                        break;
  2.2044 +                    case 12: /* STMIA (S) */
  2.2045 +                        for( i=0; i< 15; i++ ) {
  2.2046 +                            if( (ir & (1<<i)) ) {
  2.2047 +                                arm_write_long( operand, USER_R(i) );
  2.2048 +                                operand += 4;
  2.2049 +                            }
  2.2050 +                        }
  2.2051 +                        if( ir & 0x8000 ) {
  2.2052 +                            arm_write_long( operand, armr.r[15]+4 );
  2.2053 +                            operand += 4;
  2.2054 +                        }
  2.2055 +                        break;
  2.2056 +                    case 13: /* LDMIA (S) */
  2.2057 +                        if( (ir&0x00008000) ) { /* Load PC */
  2.2058 +                            for( i=0; i < 16; i++ ) {
  2.2059 +                                if( (ir & (1<<i)) ) {
  2.2060 +                                    armr.r[i] = arm_read_long( operand );
  2.2061 +                                    operand += 4;
  2.2062 +                                }
  2.2063 +                            }
  2.2064 +                            needRestore = TRUE;
  2.2065 +                        } else {
  2.2066 +                            for( i=0; i < 16; i++ ) {
  2.2067 +                                if( (ir & (1<<i)) ) {
  2.2068 +                                    USER_R(i) = arm_read_long( operand );
  2.2069 +                                    operand += 4;
  2.2070 +                                }
  2.2071 +                            }
  2.2072 +                        }
  2.2073 +                        break;
  2.2074 +                    case 16: /* STMDB */
  2.2075 +                        if( ir & 0x8000 ) {
  2.2076 +                            operand -= 4;
  2.2077 +                            arm_write_long( operand, armr.r[15]+4 );
  2.2078 +                        }
  2.2079 +                        for( i=14; i>= 0; i-- ) {
  2.2080 +                            if( (ir & (1<<i)) ) {
  2.2081 +                                operand -= 4;
  2.2082 +                                arm_write_long( operand, armr.r[i] );
  2.2083 +                            }
  2.2084 +                        }
  2.2085 +                        break;
  2.2086 +                    case 17: /* LDMDB */
  2.2087 +                        for( i=15; i>= 0; i-- ) {
  2.2088 +                            if( (ir & (1<<i)) ) {
  2.2089 +                                operand -= 4;
  2.2090 +                                armr.r[i] = arm_read_long( operand );
  2.2091 +                            }
  2.2092 +                        }
  2.2093 +                        break;
  2.2094 +                    case 20: /* STMDB (S) */
  2.2095 +                        if( ir & 0x8000 ) {
  2.2096 +                            operand -= 4;
  2.2097 +                            arm_write_long( operand, armr.r[15]+4 );
  2.2098 +                        }
  2.2099 +                        for( i=14; i>= 0; i-- ) {
  2.2100 +                            if( (ir & (1<<i)) ) {
  2.2101 +                                operand -= 4;
  2.2102 +                                arm_write_long( operand, USER_R(i) );
  2.2103 +                            }
  2.2104 +                        }
  2.2105 +                        break;
  2.2106 +                    case 21: /* LDMDB (S) */
  2.2107 +                        if( (ir&0x00008000) ) { /* Load PC */
  2.2108 +                            for( i=15; i>= 0; i-- ) {
  2.2109 +                                if( (ir & (1<<i)) ) {
  2.2110 +                                    operand -= 4;
  2.2111 +                                    armr.r[i] = arm_read_long( operand );
  2.2112 +                                }
  2.2113 +                            }
  2.2114 +                            needRestore = TRUE;
  2.2115 +                        } else {
  2.2116 +                            for( i=15; i>= 0; i-- ) {
  2.2117 +                                if( (ir & (1<<i)) ) {
  2.2118 +                                    operand -= 4;
  2.2119 +                                    USER_R(i) = arm_read_long( operand );
  2.2120 +                                }
  2.2121 +                            }
  2.2122 +                        }
  2.2123 +                        break;
  2.2124 +                    case 24: /* STMIB */
  2.2125 +                        for( i=0; i< 15; i++ ) {
  2.2126 +                            if( (ir & (1<<i)) ) {
  2.2127 +                                operand += 4;
  2.2128 +                                arm_write_long( operand, armr.r[i] );
  2.2129 +                            }
  2.2130 +                        }
  2.2131 +                        if( ir & 0x8000 ) {
  2.2132 +                            operand += 4;
  2.2133 +                            arm_write_long( operand, armr.r[15]+4 );
  2.2134 +                        }
  2.2135 +                        break;
  2.2136 +                    case 25: /* LDMIB */
  2.2137 +                        for( i=0; i< 16; i++ ) {
  2.2138 +                            if( (ir & (1<<i)) ) {
  2.2139 +                                operand += 4;
  2.2140 +                                armr.r[i] = arm_read_long( operand );
  2.2141 +                            }
  2.2142 +                        }
  2.2143 +                        break;
  2.2144 +                    case 28: /* STMIB (S) */
  2.2145 +                        for( i=0; i< 15; i++ ) {
  2.2146 +                            if( (ir & (1<<i)) ) {
  2.2147 +                                operand += 4;
  2.2148 +                                arm_write_long( operand, USER_R(i) );
  2.2149 +                            }
  2.2150 +                        }
  2.2151 +                        if( ir & 0x8000 ) {
  2.2152 +                            operand += 4;
  2.2153 +                            arm_write_long( operand, armr.r[15]+4 );
  2.2154 +                        }
  2.2155 +                        break;
  2.2156 +                    case 29: /* LDMIB (S) */
  2.2157 +                        if( (ir&0x00008000) ) { /* Load PC */
  2.2158 +                            for( i=0; i < 16; i++ ) {
  2.2159 +                                if( (ir & (1<<i)) ) {
  2.2160 +                                    operand += 4;
  2.2161 +                                    armr.r[i] = arm_read_long( operand );
  2.2162 +                                }
  2.2163 +                            }
  2.2164 +                            needRestore = TRUE;
  2.2165 +                        } else {
  2.2166 +                            for( i=0; i < 16; i++ ) {
  2.2167 +                                if( (ir & (1<<i)) ) {
  2.2168 +                                    operand += 4;
  2.2169 +                                    USER_R(i) = arm_read_long( operand );
  2.2170 +                                }
  2.2171 +                            }
  2.2172 +                        }
  2.2173 +                        break;
  2.2174 +                    }
  2.2175 +
  2.2176 +                    if( WFLAG(ir) ) 
  2.2177 +                        LRN(ir) = operand;
  2.2178 +                    if( needRestore ) 
  2.2179 +                        arm_restore_cpsr();
  2.2180 +                }
  2.2181 +                break;
  2.2182 +            case 3: /* Copro */
  2.2183 +                if( (ir & 0x0F000000) == 0x0F000000 ) { /* SWI */
  2.2184 +                    arm_raise_exception( EXC_SOFTWARE );
  2.2185 +                } else {
  2.2186 +                    UNIMP(ir);
  2.2187 +                }
  2.2188 +                break;
  2.2189 +        }
  2.2190  
  2.2191      }
  2.2192  
  2.2193      if( armr.r[15] >= 0x00200000 ) {
  2.2194 -	armr.running = FALSE;
  2.2195 -	WARN( "ARM Halted: BRANCH to invalid address %08X at %08X", armr.r[15], pc );
  2.2196 -	return FALSE;
  2.2197 +        armr.running = FALSE;
  2.2198 +        WARN( "ARM Halted: BRANCH to invalid address %08X at %08X", armr.r[15], pc );
  2.2199 +        return FALSE;
  2.2200      }
  2.2201      return TRUE;
  2.2202  }

     3.1 --- a/src/aica/armcore.h	Mon Jul 14 07:42:45 2008 +0000
     3.2 +++ b/src/aica/armcore.h	Mon Jul 14 07:44:42 2008 +0000
     3.3 @@ -16,14 +16,18 @@
     3.4   * GNU General Public License for more details.
     3.5   */
     3.6  
     3.7 -#ifndef dream_armcore_H
     3.8 -#define dream_armcore_H 1
     3.9 +#ifndef lxdream_armcore_H
    3.10 +#define lxdream_armcore_H 1
    3.11  
    3.12  #include "lxdream.h"
    3.13  #include "mem.h"
    3.14  #include <stdint.h>
    3.15  #include <stdio.h>
    3.16  
    3.17 +#ifdef __cplusplus
    3.18 +extern "C" {
    3.19 +#endif
    3.20 +
    3.21  #define ARM_BASE_RATE 2 /* MHZ */
    3.22  extern uint32_t arm_cpu_freq;
    3.23  extern uint32_t arm_cpu_period;
    3.24 @@ -107,4 +111,9 @@
    3.25  int32_t arm_read_phys_word( uint32_t addr );
    3.26  int arm_has_page( uint32_t addr );
    3.27  void arm_mem_init(void);
    3.28 -#endif /* !dream_armcore_H */
    3.29 +
    3.30 +#ifdef __cplusplus
    3.31 +}
    3.32 +#endif
    3.33 +
    3.34 +#endif /* !lxdream_armcore_H */

     4.1 --- a/src/aica/armdasm.c	Mon Jul 14 07:42:45 2008 +0000
     4.2 +++ b/src/aica/armdasm.c	Mon Jul 14 07:44:42 2008 +0000
     4.3 @@ -48,142 +48,142 @@
     4.4  
     4.5  
     4.6  const struct reg_desc_struct arm_reg_map[] = 
     4.7 -    { {"R0", REG_INT, &armr.r[0]}, {"R1", REG_INT, &armr.r[1]},
     4.8 -    {"R2", REG_INT, &armr.r[2]}, {"R3", REG_INT, &armr.r[3]},
     4.9 -    {"R4", REG_INT, &armr.r[4]}, {"R5", REG_INT, &armr.r[5]},
    4.10 -    {"R6", REG_INT, &armr.r[6]}, {"R7", REG_INT, &armr.r[7]},
    4.11 -    {"R8", REG_INT, &armr.r[8]}, {"R9", REG_INT, &armr.r[9]},
    4.12 -    {"R10",REG_INT, &armr.r[10]}, {"R11",REG_INT, &armr.r[11]},
    4.13 -    {"R12",REG_INT, &armr.r[12]}, {"R13",REG_INT, &armr.r[13]},
    4.14 -    {"R14",REG_INT, &armr.r[14]}, {"R15",REG_INT, &armr.r[15]},
    4.15 -    {"CPSR", REG_INT, &armr.cpsr}, {"SPSR", REG_INT, &armr.spsr},
    4.16 -    {NULL, 0, NULL} };
    4.17 +{ {"R0", REG_INT, &armr.r[0]}, {"R1", REG_INT, &armr.r[1]},
    4.18 +        {"R2", REG_INT, &armr.r[2]}, {"R3", REG_INT, &armr.r[3]},
    4.19 +        {"R4", REG_INT, &armr.r[4]}, {"R5", REG_INT, &armr.r[5]},
    4.20 +        {"R6", REG_INT, &armr.r[6]}, {"R7", REG_INT, &armr.r[7]},
    4.21 +        {"R8", REG_INT, &armr.r[8]}, {"R9", REG_INT, &armr.r[9]},
    4.22 +        {"R10",REG_INT, &armr.r[10]}, {"R11",REG_INT, &armr.r[11]},
    4.23 +        {"R12",REG_INT, &armr.r[12]}, {"R13",REG_INT, &armr.r[13]},
    4.24 +        {"R14",REG_INT, &armr.r[14]}, {"R15",REG_INT, &armr.r[15]},
    4.25 +        {"CPSR", REG_INT, &armr.cpsr}, {"SPSR", REG_INT, &armr.spsr},
    4.26 +        {NULL, 0, NULL} };
    4.27  
    4.28  
    4.29  const struct cpu_desc_struct arm_cpu_desc = 
    4.30 -    { "ARM7", arm_disasm_instruction, arm_execute_instruction, arm_has_page,
    4.31 -      arm_set_breakpoint, arm_clear_breakpoint, arm_get_breakpoint, 4,
    4.32 -      (char *)&armr, sizeof(armr), arm_reg_map,
    4.33 -      &armr.r[15] };
    4.34 +{ "ARM7", arm_disasm_instruction, arm_execute_instruction, arm_has_page,
    4.35 +        arm_set_breakpoint, arm_clear_breakpoint, arm_get_breakpoint, 4,
    4.36 +        (char *)&armr, sizeof(armr), arm_reg_map,
    4.37 +        &armr.r[15] };
    4.38  const struct cpu_desc_struct armt_cpu_desc = 
    4.39 -    { "ARM7T", armt_disasm_instruction, arm_execute_instruction, arm_has_page,
    4.40 -      arm_set_breakpoint, arm_clear_breakpoint, arm_get_breakpoint, 2,
    4.41 -      (char*)&armr, sizeof(armr), arm_reg_map,
    4.42 -      &armr.r[15] };
    4.43 +{ "ARM7T", armt_disasm_instruction, arm_execute_instruction, arm_has_page,
    4.44 +        arm_set_breakpoint, arm_clear_breakpoint, arm_get_breakpoint, 2,
    4.45 +        (char*)&armr, sizeof(armr), arm_reg_map,
    4.46 +        &armr.r[15] };
    4.47  
    4.48  
    4.49  
    4.50  
    4.51  char *conditionNames[] = { "EQ", "NE", "CS", "CC", "MI", "PL", "VS", "VC", 
    4.52 -                           "HI", "LS", "GE", "LT", "GT", "LE", "  " /*AL*/, "NV" };
    4.53 -                           
    4.54 -                         /* fsxc */
    4.55 +        "HI", "LS", "GE", "LT", "GT", "LE", "  " /*AL*/, "NV" };
    4.56 +
    4.57 +/* fsxc */
    4.58  char *msrFieldMask[] = { "", "c", "x", "xc", "s", "sc", "sx", "sxc",
    4.59 -	                     "f", "fc", "fx", "fxc", "fs", "fsc", "fsx", "fsxc" };
    4.60 +        "f", "fc", "fx", "fxc", "fs", "fsc", "fsx", "fsxc" };
    4.61  char *ldmModes[] = { "DA", "IA", "DB", "IB" };
    4.62  
    4.63  #define UNIMP(ir) snprintf( buf, len, "???     " )
    4.64  
    4.65  int arm_disasm_shift_operand( uint32_t ir, char *buf, int len )
    4.66  {
    4.67 -	uint32_t operand, tmp;
    4.68 -	if( IFLAG(ir) == 0 ) {
    4.69 -		switch(SHIFT(ir)) {
    4.70 -		case 0: /* (Rm << imm) */
    4.71 -		    tmp = SHIFTIMM(ir);
    4.72 -		    if( tmp != 0 ) {
    4.73 -			return snprintf(buf, len, "R%d << %d", RM(ir), tmp );
    4.74 -		    } else {
    4.75 -			return snprintf(buf, len, "R%d", RM(ir));
    4.76 -		    }
    4.77 -		case 1: /* (Rm << Rs) */
    4.78 -			return snprintf(buf, len, "R%d << R%d", RM(ir), RS(ir) );
    4.79 -		case 2: /* (Rm >> imm) */
    4.80 -			return snprintf(buf, len, "R%d >> %d", RM(ir), SHIFTIMM(ir) );
    4.81 -		case 3: /* (Rm >> Rs) */
    4.82 -			return snprintf(buf, len, "R%d >> R%d", RM(ir), RS(ir) );
    4.83 -		case 4: /* (Rm >>> imm) */
    4.84 -			return snprintf(buf, len, "R%d >>> %d", RM(ir), SHIFTIMM(ir) );
    4.85 -		case 5: /* (Rm >>> Rs) */
    4.86 -			return snprintf(buf, len, "R%d >>> R%d", RM(ir), RS(ir) );
    4.87 -		case 6:
    4.88 -			tmp = SHIFTIMM(ir);
    4.89 -			if( tmp == 0 ) /* RRX aka rotate with carry */
    4.90 -				return snprintf(buf, len, "R%d roc 1", RM(ir) );
    4.91 -			else
    4.92 -				return snprintf(buf, len, "R%d rot %d", RM(ir), SHIFTIMM(ir) );
    4.93 -		case 7:
    4.94 -			return snprintf(buf, len, "R%d rot R%d", RM(ir), RS(ir) );
    4.95 -		}
    4.96 -	} else {
    4.97 -		operand = IMM8(ir);
    4.98 -		tmp = IMMROT(ir);
    4.99 -		operand = ROTATE_RIGHT_LONG(operand, tmp);
   4.100 -		return snprintf(buf, len, "#%08Xh", operand );
   4.101 -	}
   4.102 -	return 0;
   4.103 +    uint32_t operand, tmp;
   4.104 +    if( IFLAG(ir) == 0 ) {
   4.105 +        switch(SHIFT(ir)) {
   4.106 +        case 0: /* (Rm << imm) */
   4.107 +            tmp = SHIFTIMM(ir);
   4.108 +            if( tmp != 0 ) {
   4.109 +                return snprintf(buf, len, "R%d << %d", RM(ir), tmp );
   4.110 +            } else {
   4.111 +                return snprintf(buf, len, "R%d", RM(ir));
   4.112 +            }
   4.113 +        case 1: /* (Rm << Rs) */
   4.114 +            return snprintf(buf, len, "R%d << R%d", RM(ir), RS(ir) );
   4.115 +        case 2: /* (Rm >> imm) */
   4.116 +            return snprintf(buf, len, "R%d >> %d", RM(ir), SHIFTIMM(ir) );
   4.117 +        case 3: /* (Rm >> Rs) */
   4.118 +            return snprintf(buf, len, "R%d >> R%d", RM(ir), RS(ir) );
   4.119 +        case 4: /* (Rm >>> imm) */
   4.120 +            return snprintf(buf, len, "R%d >>> %d", RM(ir), SHIFTIMM(ir) );
   4.121 +        case 5: /* (Rm >>> Rs) */
   4.122 +            return snprintf(buf, len, "R%d >>> R%d", RM(ir), RS(ir) );
   4.123 +        case 6:
   4.124 +            tmp = SHIFTIMM(ir);
   4.125 +            if( tmp == 0 ) /* RRX aka rotate with carry */
   4.126 +                return snprintf(buf, len, "R%d roc 1", RM(ir) );
   4.127 +            else
   4.128 +                return snprintf(buf, len, "R%d rot %d", RM(ir), SHIFTIMM(ir) );
   4.129 +        case 7:
   4.130 +            return snprintf(buf, len, "R%d rot R%d", RM(ir), RS(ir) );
   4.131 +        }
   4.132 +    } else {
   4.133 +        operand = IMM8(ir);
   4.134 +        tmp = IMMROT(ir);
   4.135 +        operand = ROTATE_RIGHT_LONG(operand, tmp);
   4.136 +        return snprintf(buf, len, "#%08Xh", operand );
   4.137 +    }
   4.138 +    return 0;
   4.139  }
   4.140  
   4.141  static int arm_disasm_address_index( uint32_t ir, char *buf, int len )
   4.142  {
   4.143 -	uint32_t tmp;
   4.144 -	
   4.145 -	switch(SHIFT(ir)) {
   4.146 -	case 0: /* (Rm << imm) */
   4.147 -	    tmp = SHIFTIMM(ir);
   4.148 -	    if( tmp != 0 ) {
   4.149 -		return snprintf( buf, len, "R%d << %d", RM(ir), tmp );
   4.150 -	    } else {
   4.151 -		return snprintf( buf, len, "R%d", RM(ir) );
   4.152 -	    }
   4.153 -	case 2: /* (Rm >> imm) */
   4.154 -		return snprintf( buf, len, "R%d >> %d", RM(ir), SHIFTIMM(ir) );
   4.155 -	case 4: /* (Rm >>> imm) */
   4.156 -		return snprintf( buf, len, "R%d >>> %d", RM(ir), SHIFTIMM(ir) );
   4.157 -	case 6:
   4.158 -		tmp = SHIFTIMM(ir);
   4.159 -		if( tmp == 0 ) /* RRX aka rotate with carry */
   4.160 -			return snprintf( buf, len, "R%d roc 1", RM(ir) );
   4.161 -		else
   4.162 -			return snprintf( buf, len, "R%d rot %d", RM(ir), tmp );
   4.163 -	default: 
   4.164 -		return UNIMP(ir);
   4.165 -	}
   4.166 +    uint32_t tmp;
   4.167 +
   4.168 +    switch(SHIFT(ir)) {
   4.169 +    case 0: /* (Rm << imm) */
   4.170 +        tmp = SHIFTIMM(ir);
   4.171 +        if( tmp != 0 ) {
   4.172 +            return snprintf( buf, len, "R%d << %d", RM(ir), tmp );
   4.173 +        } else {
   4.174 +            return snprintf( buf, len, "R%d", RM(ir) );
   4.175 +        }
   4.176 +    case 2: /* (Rm >> imm) */
   4.177 +        return snprintf( buf, len, "R%d >> %d", RM(ir), SHIFTIMM(ir) );
   4.178 +    case 4: /* (Rm >>> imm) */
   4.179 +        return snprintf( buf, len, "R%d >>> %d", RM(ir), SHIFTIMM(ir) );
   4.180 +    case 6:
   4.181 +        tmp = SHIFTIMM(ir);
   4.182 +        if( tmp == 0 ) /* RRX aka rotate with carry */
   4.183 +            return snprintf( buf, len, "R%d roc 1", RM(ir) );
   4.184 +        else
   4.185 +            return snprintf( buf, len, "R%d rot %d", RM(ir), tmp );
   4.186 +    default: 
   4.187 +        return UNIMP(ir);
   4.188 +    }
   4.189  }
   4.190  
   4.191  static int arm_disasm_address_operand( uint32_t ir, char *buf, int len,  int pc )
   4.192  {
   4.193      char  shift[32];
   4.194  
   4.195 -	char sign = UFLAG(ir) ? '+' : '-';
   4.196 -	/* I P U . W */
   4.197 -	switch( (ir>>21)&0x19 ) {
   4.198 -	case 0: /* Rn -= imm offset (post-indexed) [5.2.8 A5-28] */
   4.199 -	case 1:
   4.200 -		return snprintf( buf, len, "[R%d], R%d %c= #%04Xh", RN(ir), RN(ir), sign, IMM12(ir) );
   4.201 -	case 8: /* Rn - imm offset  [5.2.2 A5-20] */
   4.202 -	    if( RN(ir) == 15 ) { /* PC relative - decode here */
   4.203 -		uint32_t addr = pc + 8 + (UFLAG(ir) ? IMM12(ir) : -IMM12(ir));
   4.204 -		return snprintf( buf, len, "[$%08Xh] <- #%08Xh", addr,
   4.205 -				 arm_read_long( addr ) );
   4.206 -	    } else {
   4.207 -		return snprintf( buf, len, "[R%d %c #%04Xh]", RN(ir), sign, IMM12(ir) );
   4.208 -	    }
   4.209 -	case 9: /* Rn -= imm offset (pre-indexed)  [5.2.5 A5-24] */
   4.210 -		return snprintf( buf, len, "[R%d %c= #%04Xh]", RN(ir), sign, IMM12(ir) );
   4.211 -	case 16: /* Rn -= Rm (post-indexed)  [5.2.10 A5-32 ] */
   4.212 -	case 17:
   4.213 -		arm_disasm_address_index( ir, shift, sizeof(shift) );
   4.214 -		return snprintf( buf, len, "[R%d], R%d %c= %s", RN(ir), RN(ir), sign, shift );
   4.215 -	case 24: /* Rn - Rm  [5.2.4 A5-23] */
   4.216 -		arm_disasm_address_index( ir, shift, sizeof(shift) );
   4.217 -		return snprintf( buf, len, "[R%d %c %s]", RN(ir), sign, shift );
   4.218 -	case 25: /* RN -= Rm (pre-indexed)  [5.2.7 A5-26] */
   4.219 -		arm_disasm_address_index( ir, shift, sizeof(shift) );
   4.220 -		return snprintf( buf, len, "[R%d %c= %s]", RN(ir), sign, shift );
   4.221 -	default:
   4.222 -		return UNIMP(ir); /* Unreachable */
   4.223 -	}
   4.224 +    char sign = UFLAG(ir) ? '+' : '-';
   4.225 +    /* I P U . W */
   4.226 +    switch( (ir>>21)&0x19 ) {
   4.227 +    case 0: /* Rn -= imm offset (post-indexed) [5.2.8 A5-28] */
   4.228 +    case 1:
   4.229 +        return snprintf( buf, len, "[R%d], R%d %c= #%04Xh", RN(ir), RN(ir), sign, IMM12(ir) );
   4.230 +    case 8: /* Rn - imm offset  [5.2.2 A5-20] */
   4.231 +        if( RN(ir) == 15 ) { /* PC relative - decode here */
   4.232 +            uint32_t addr = pc + 8 + (UFLAG(ir) ? IMM12(ir) : -IMM12(ir));
   4.233 +            return snprintf( buf, len, "[$%08Xh] <- #%08Xh", addr,
   4.234 +                    arm_read_long( addr ) );
   4.235 +        } else {
   4.236 +            return snprintf( buf, len, "[R%d %c #%04Xh]", RN(ir), sign, IMM12(ir) );
   4.237 +        }
   4.238 +    case 9: /* Rn -= imm offset (pre-indexed)  [5.2.5 A5-24] */
   4.239 +        return snprintf( buf, len, "[R%d %c= #%04Xh]", RN(ir), sign, IMM12(ir) );
   4.240 +    case 16: /* Rn -= Rm (post-indexed)  [5.2.10 A5-32 ] */
   4.241 +    case 17:
   4.242 +        arm_disasm_address_index( ir, shift, sizeof(shift) );
   4.243 +        return snprintf( buf, len, "[R%d], R%d %c= %s", RN(ir), RN(ir), sign, shift );
   4.244 +    case 24: /* Rn - Rm  [5.2.4 A5-23] */
   4.245 +        arm_disasm_address_index( ir, shift, sizeof(shift) );
   4.246 +        return snprintf( buf, len, "[R%d %c %s]", RN(ir), sign, shift );
   4.247 +    case 25: /* RN -= Rm (pre-indexed)  [5.2.7 A5-26] */
   4.248 +        arm_disasm_address_index( ir, shift, sizeof(shift) );
   4.249 +        return snprintf( buf, len, "[R%d %c= %s]", RN(ir), sign, shift );
   4.250 +    default:
   4.251 +        return UNIMP(ir); /* Unreachable */
   4.252 +    }
   4.253  }
   4.254  
   4.255  uint32_t arm_disasm_instruction( uint32_t pc, char *buf, int len, char *opcode )
   4.256 @@ -191,320 +191,320 @@
   4.257      char operand[64];
   4.258      uint32_t ir = arm_read_long(pc);
   4.259      int i,j;
   4.260 -	
   4.261 +
   4.262      sprintf( opcode, "%02X %02X %02X %02X", ir&0xFF, (ir>>8) & 0xFF,
   4.263 -	     (ir>>16)&0xFF, (ir>>24) );
   4.264 +             (ir>>16)&0xFF, (ir>>24) );
   4.265  
   4.266      if( COND(ir) == 0x0F ) {
   4.267 -    	UNIMP(ir);
   4.268 -    	return pc+4;
   4.269 +        UNIMP(ir);
   4.270 +        return pc+4;
   4.271      }
   4.272      char *cond = conditionNames[COND(ir)];
   4.273  
   4.274 -	switch( GRP(ir) ) {
   4.275 -	case 0:
   4.276 -		if( (ir & 0x0D900000) == 0x01000000 ) {
   4.277 -			/* Instructions that aren't actual data processing */
   4.278 -			switch( ir & 0x0FF000F0 ) {
   4.279 -			case 0x01200010: /* BXcc */
   4.280 -				snprintf(buf, len, "BX%s     R%d", cond, RM(ir));
   4.281 -				break;
   4.282 -			case 0x01000000: /* MRS Rd, CPSR */
   4.283 -				snprintf(buf, len, "MRS%s    R%d, CPSR", cond, RD(ir));
   4.284 -				break;
   4.285 -			case 0x01400000: /* MRS Rd, SPSR */
   4.286 -				snprintf(buf, len, "MRS%s    R%d, SPSR", cond, RD(ir));
   4.287 -				break;
   4.288 -			case 0x01200000: /* MSR CPSR, Rm */
   4.289 -				snprintf(buf, len, "MSR%s    CPSR_%s, R%d", cond, FSXC(ir), RM(ir));
   4.290 -				break;
   4.291 -			case 0x01600000: /* MSR SPSR, Rm */
   4.292 -				snprintf(buf, len, "MSR%s    SPSR_%s, R%d", cond, FSXC(ir), RM(ir));
   4.293 -				break;
   4.294 -			case 0x03200000: /* MSR CPSR, imm */
   4.295 -				snprintf(buf, len, "MSR%s    CPSR_%s, #%08X", cond, FSXC(ir), ROTIMM12(ir));
   4.296 -				break;
   4.297 -			case 0x03600000: /* MSR SPSR, imm */
   4.298 -				snprintf(buf, len, "MSR%s    SPSR_%s, #%08X", cond, FSXC(ir), ROTIMM12(ir));
   4.299 -				break;
   4.300 -			default:
   4.301 -				UNIMP();
   4.302 -			}
   4.303 -		} else if( (ir & 0x0E000090) == 0x00000090 ) {
   4.304 -			/* Neither are these */
   4.305 -			switch( (ir>>5)&0x03 ) {
   4.306 -			case 0:
   4.307 -				/* Arithmetic extension area */
   4.308 -				switch(OPCODE(ir)) {
   4.309 -				case 0: /* MUL */
   4.310 -					snprintf(buf,len, "MUL%s    R%d, R%d, R%d", cond, RN(ir), RM(ir), RS(ir) );
   4.311 -					break;
   4.312 -				case 1: /* MULS */
   4.313 -					break;
   4.314 -				case 2: /* MLA */
   4.315 -					snprintf(buf,len, "MLA%s    R%d, R%d, R%d, R%d", cond, RN(ir), RM(ir), RS(ir), RD(ir) );
   4.316 -					break;
   4.317 -				case 3: /* MLAS */
   4.318 -					break;
   4.319 -				case 8: /* UMULL */
   4.320 -					snprintf(buf,len, "UMULL%s  R%d, R%d, R%d, R%d", cond, RD(ir), RN(ir), RM(ir), RS(ir) );
   4.321 -					break;
   4.322 -				case 9: /* UMULLS */
   4.323 -					break;
   4.324 -				case 10: /* UMLAL */
   4.325 -					snprintf(buf,len, "UMLAL%s  R%d, R%d, R%d, R%d", cond, RD(ir), RN(ir), RM(ir), RS(ir) );
   4.326 -					break;
   4.327 -				case 11: /* UMLALS */
   4.328 -					break;
   4.329 -				case 12: /* SMULL */
   4.330 -					snprintf(buf,len, "SMULL%s  R%d, R%d, R%d, R%d", cond, RD(ir), RN(ir), RM(ir), RS(ir) );
   4.331 -					break;
   4.332 -				case 13: /* SMULLS */
   4.333 -					break;
   4.334 -				case 14: /* SMLAL */
   4.335 -					snprintf(buf,len, "SMLAL%s  R%d, R%d, R%d, R%d", cond, RD(ir), RN(ir), RM(ir), RS(ir) );
   4.336 -					break;
   4.337 -				case 15: /* SMLALS */
   4.338 +    switch( GRP(ir) ) {
   4.339 +    case 0:
   4.340 +        if( (ir & 0x0D900000) == 0x01000000 ) {
   4.341 +            /* Instructions that aren't actual data processing */
   4.342 +            switch( ir & 0x0FF000F0 ) {
   4.343 +            case 0x01200010: /* BXcc */
   4.344 +                snprintf(buf, len, "BX%s     R%d", cond, RM(ir));
   4.345 +                break;
   4.346 +            case 0x01000000: /* MRS Rd, CPSR */
   4.347 +                snprintf(buf, len, "MRS%s    R%d, CPSR", cond, RD(ir));
   4.348 +                break;
   4.349 +            case 0x01400000: /* MRS Rd, SPSR */
   4.350 +                snprintf(buf, len, "MRS%s    R%d, SPSR", cond, RD(ir));
   4.351 +                break;
   4.352 +            case 0x01200000: /* MSR CPSR, Rm */
   4.353 +                snprintf(buf, len, "MSR%s    CPSR_%s, R%d", cond, FSXC(ir), RM(ir));
   4.354 +                break;
   4.355 +            case 0x01600000: /* MSR SPSR, Rm */
   4.356 +                snprintf(buf, len, "MSR%s    SPSR_%s, R%d", cond, FSXC(ir), RM(ir));
   4.357 +                break;
   4.358 +            case 0x03200000: /* MSR CPSR, imm */
   4.359 +                snprintf(buf, len, "MSR%s    CPSR_%s, #%08X", cond, FSXC(ir), ROTIMM12(ir));
   4.360 +                break;
   4.361 +            case 0x03600000: /* MSR SPSR, imm */
   4.362 +                snprintf(buf, len, "MSR%s    SPSR_%s, #%08X", cond, FSXC(ir), ROTIMM12(ir));
   4.363 +                break;
   4.364 +            default:
   4.365 +                UNIMP();
   4.366 +            }
   4.367 +        } else if( (ir & 0x0E000090) == 0x00000090 ) {
   4.368 +            /* Neither are these */
   4.369 +            switch( (ir>>5)&0x03 ) {
   4.370 +            case 0:
   4.371 +                /* Arithmetic extension area */
   4.372 +                switch(OPCODE(ir)) {
   4.373 +                case 0: /* MUL */
   4.374 +                    snprintf(buf,len, "MUL%s    R%d, R%d, R%d", cond, RN(ir), RM(ir), RS(ir) );
   4.375 +                    break;
   4.376 +                case 1: /* MULS */
   4.377 +                    break;
   4.378 +                case 2: /* MLA */
   4.379 +                    snprintf(buf,len, "MLA%s    R%d, R%d, R%d, R%d", cond, RN(ir), RM(ir), RS(ir), RD(ir) );
   4.380 +                    break;
   4.381 +                case 3: /* MLAS */
   4.382 +                    break;
   4.383 +                case 8: /* UMULL */
   4.384 +                    snprintf(buf,len, "UMULL%s  R%d, R%d, R%d, R%d", cond, RD(ir), RN(ir), RM(ir), RS(ir) );
   4.385 +                    break;
   4.386 +                case 9: /* UMULLS */
   4.387 +                    break;
   4.388 +                case 10: /* UMLAL */
   4.389 +                    snprintf(buf,len, "UMLAL%s  R%d, R%d, R%d, R%d", cond, RD(ir), RN(ir), RM(ir), RS(ir) );
   4.390 +                    break;
   4.391 +                case 11: /* UMLALS */
   4.392 +                    break;
   4.393 +                case 12: /* SMULL */
   4.394 +                    snprintf(buf,len, "SMULL%s  R%d, R%d, R%d, R%d", cond, RD(ir), RN(ir), RM(ir), RS(ir) );
   4.395 +                    break;
   4.396 +                case 13: /* SMULLS */
   4.397 +                    break;
   4.398 +                case 14: /* SMLAL */
   4.399 +                    snprintf(buf,len, "SMLAL%s  R%d, R%d, R%d, R%d", cond, RD(ir), RN(ir), RM(ir), RS(ir) );
   4.400 +                    break;
   4.401 +                case 15: /* SMLALS */
   4.402  
   4.403 -					break;
   4.404 -				case 16: /* SWP */
   4.405 -					snprintf(buf,len, "SWP%s    R%d, R%d, [R%d]", cond, RD(ir), RN(ir), RM(ir) );
   4.406 -					break;
   4.407 -				case 20: /* SWPB */
   4.408 -					snprintf(buf,len, "SWPB%s   R%d, R%d, [R%d]", cond, RD(ir), RN(ir), RM(ir) );
   4.409 -					break;
   4.410 -				default:
   4.411 -					UNIMP(ir);
   4.412 -				}
   4.413 -				break;
   4.414 -			case 1:
   4.415 -				if( LFLAG(ir) ) {
   4.416 -					/* LDRH */
   4.417 -				} else {
   4.418 -					/* STRH */
   4.419 -				}
   4.420 -				UNIMP(ir);
   4.421 -				break;
   4.422 -			case 2:
   4.423 -				if( LFLAG(ir) ) {
   4.424 -					/* LDRSB */
   4.425 -				} else {
   4.426 -				}
   4.427 -				UNIMP(ir);
   4.428 -				break;
   4.429 -			case 3:
   4.430 -				if( LFLAG(ir) ) {
   4.431 -					/* LDRSH */
   4.432 -				} else {
   4.433 -				}
   4.434 -				UNIMP(ir);
   4.435 -				break;
   4.436 -			}
   4.437 -		} else {
   4.438 -			/* Data processing */
   4.439 +                    break;
   4.440 +                case 16: /* SWP */
   4.441 +                    snprintf(buf,len, "SWP%s    R%d, R%d, [R%d]", cond, RD(ir), RN(ir), RM(ir) );
   4.442 +                    break;
   4.443 +                case 20: /* SWPB */
   4.444 +                    snprintf(buf,len, "SWPB%s   R%d, R%d, [R%d]", cond, RD(ir), RN(ir), RM(ir) );
   4.445 +                    break;
   4.446 +                default:
   4.447 +                    UNIMP(ir);
   4.448 +                }
   4.449 +                break;
   4.450 +                case 1:
   4.451 +                    if( LFLAG(ir) ) {
   4.452 +                        /* LDRH */
   4.453 +                    } else {
   4.454 +                        /* STRH */
   4.455 +                    }
   4.456 +                    UNIMP(ir);
   4.457 +                    break;
   4.458 +                case 2:
   4.459 +                    if( LFLAG(ir) ) {
   4.460 +                        /* LDRSB */
   4.461 +                    } else {
   4.462 +                    }
   4.463 +                    UNIMP(ir);
   4.464 +                    break;
   4.465 +                case 3:
   4.466 +                    if( LFLAG(ir) ) {
   4.467 +                        /* LDRSH */
   4.468 +                    } else {
   4.469 +                    }
   4.470 +                    UNIMP(ir);
   4.471 +                    break;
   4.472 +            }
   4.473 +        } else {
   4.474 +            /* Data processing */
   4.475  
   4.476 -			switch(OPCODE(ir)) {
   4.477 -			case 0: /* AND Rd, Rn, operand */
   4.478 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.479 -				snprintf(buf, len, "AND%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   4.480 -				break;
   4.481 -			case 1: /* ANDS Rd, Rn, operand */
   4.482 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.483 -				snprintf(buf, len, "ANDS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   4.484 -				break;
   4.485 -			case 2: /* EOR Rd, Rn, operand */
   4.486 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.487 -				snprintf(buf, len, "EOR%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   4.488 -				break;
   4.489 -			case 3: /* EORS Rd, Rn, operand */
   4.490 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.491 -				snprintf(buf, len, "EORS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   4.492 -				break;
   4.493 -			case 4: /* SUB Rd, Rn, operand */
   4.494 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.495 -				snprintf(buf, len, "SUB%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   4.496 -				break;
   4.497 -			case 5: /* SUBS Rd, Rn, operand */
   4.498 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.499 -				snprintf(buf, len, "SUBS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   4.500 -				break;
   4.501 -			case 6: /* RSB Rd, Rn, operand */
   4.502 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.503 -				snprintf(buf, len, "RSB%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   4.504 -				break;
   4.505 -			case 7: /* RSBS Rd, Rn, operand */
   4.506 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.507 -				snprintf(buf, len, "RSBS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   4.508 -				break;
   4.509 -			case 8: /* ADD Rd, Rn, operand */
   4.510 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.511 -				snprintf(buf, len, "ADD%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   4.512 -				break;
   4.513 -			case 9: /* ADDS Rd, Rn, operand */
   4.514 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.515 -				snprintf(buf, len, "ADDS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   4.516 -				break;
   4.517 -			case 10: /* ADC Rd, Rn, operand */
   4.518 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.519 -				snprintf(buf, len, "ADC%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   4.520 -				break;
   4.521 -			case 11: /* ADCS Rd, Rn, operand */
   4.522 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.523 -				snprintf(buf, len, "ADCS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   4.524 -				break;
   4.525 -			case 12: /* SBC Rd, Rn, operand */
   4.526 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.527 -				snprintf(buf, len, "SBC%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   4.528 -				break;
   4.529 -			case 13: /* SBCS Rd, Rn, operand */
   4.530 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.531 -				snprintf(buf, len, "SBCS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   4.532 -				break;
   4.533 -			case 14: /* RSC Rd, Rn, operand */
   4.534 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.535 -				snprintf(buf, len, "RSC%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   4.536 -				break;
   4.537 -			case 15: /* RSCS Rd, Rn, operand */
   4.538 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.539 -				snprintf(buf, len, "RSCS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   4.540 -				break;
   4.541 -			case 17: /* TST Rd, Rn, operand */
   4.542 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.543 -				snprintf(buf, len, "TST%s    R%d, %s", cond, RN(ir), operand);
   4.544 -				break;
   4.545 -			case 19: /* TEQ Rd, Rn, operand */
   4.546 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.547 -				snprintf(buf, len, "TEQ%s    R%d, %s", cond, RN(ir), operand);
   4.548 -				break;
   4.549 -			case 21: /* CMP Rd, Rn, operand */
   4.550 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.551 -				snprintf(buf, len, "CMP%s    R%d, %s", cond, RN(ir), operand);
   4.552 -				break;
   4.553 -			case 23: /* CMN Rd, Rn, operand */
   4.554 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.555 -				snprintf(buf, len, "CMN%s    R%d, %s", cond, RN(ir), operand);
   4.556 -				break;
   4.557 -			case 24: /* ORR Rd, Rn, operand */
   4.558 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.559 -				snprintf(buf, len, "ORR%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   4.560 -				break;
   4.561 -			case 25: /* ORRS Rd, Rn, operand */
   4.562 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.563 -				snprintf(buf, len, "ORRS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   4.564 -				break;
   4.565 -			case 26: /* MOV Rd, operand */
   4.566 -			    if( ir == 0xE1A00000 ) {
   4.567 -				/* Not technically a different instruction,
   4.568 -				 * but this one is commonly used as a NOP,
   4.569 -				 * so... 
   4.570 -				 */
   4.571 -				snprintf(buf, len, "NOP");
   4.572 -			    } else {
   4.573 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.574 -				snprintf(buf, len, "MOV%s    R%d, %s", cond, RD(ir), operand);
   4.575 -			    }
   4.576 -			    break;
   4.577 -			case 27: /* MOVS Rd, operand */
   4.578 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.579 -				snprintf(buf, len, "MOVS%s   R%d, %s", cond, RD(ir), operand);
   4.580 -				break;
   4.581 -			case 28: /* BIC Rd, Rn, operand */
   4.582 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.583 -				snprintf(buf, len, "BIC%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   4.584 -				break;
   4.585 -			case 29: /* BICS Rd, Rn, operand */
   4.586 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.587 -				snprintf(buf, len, "BICS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   4.588 -				break;
   4.589 -			case 30: /* MVN Rd, Rn, operand */
   4.590 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.591 -				snprintf(buf, len, "MVN%s    R%d, %s", cond, RD(ir), operand);
   4.592 -				break;
   4.593 -			case 31: /* MVNS Rd, Rn, operand */
   4.594 -				arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.595 -				snprintf(buf, len, "MVNS%s   R%d, %s", cond, RD(ir), operand);
   4.596 -				break;
   4.597 -			default:
   4.598 -				UNIMP(ir);
   4.599 -			}
   4.600 -		}
   4.601 -		break;
   4.602 -	case 1: /* Load/store */
   4.603 -	    arm_disasm_address_operand( ir, operand, sizeof(operand), pc );
   4.604 -		switch( (ir>>20)&0x17 ) {
   4.605 -			case 0:
   4.606 -			case 16:
   4.607 -			case 18:
   4.608 -				snprintf(buf, len, "STR%s    R%d, %s", cond, RD(ir), operand );
   4.609 -				break;
   4.610 -			case 1:
   4.611 -			case 17:
   4.612 -			case 19:
   4.613 -				snprintf(buf, len, "LDR%s    R%d, %s", cond, RD(ir), operand );
   4.614 -				break;
   4.615 -			case 2:
   4.616 -				snprintf(buf, len, "STRT%s   R%d, %s", cond, RD(ir), operand );
   4.617 -				break;
   4.618 -			case 3:
   4.619 -				snprintf(buf, len, "LDRT%s   R%d, %s", cond, RD(ir), operand );
   4.620 -				break;
   4.621 -			case 4:
   4.622 -			case 20:
   4.623 -			case 22:
   4.624 -				snprintf(buf, len, "STRB%s   R%d, %s", cond, RD(ir), operand );
   4.625 -				break;
   4.626 -			case 5:
   4.627 -			case 21:
   4.628 -			case 23:
   4.629 -				snprintf(buf, len, "LDRB%s   R%d, %s", cond, RD(ir), operand );
   4.630 -				break;
   4.631 -			case 6:
   4.632 -				snprintf(buf, len, "STRBT%s  R%d, %s", cond, RD(ir), operand );
   4.633 -				break;
   4.634 -			case 7: 
   4.635 -				snprintf(buf, len, "LDRBT%s  R%d, %s", cond, RD(ir), operand );
   4.636 -				break;
   4.637 -		}
   4.638 -		break;
   4.639 -	case 2: 
   4.640 -	    if( (ir & 0x02000000) == 0x02000000 ) {
   4.641 -		int32_t offset = SIGNEXT24(ir&0x00FFFFFF) << 2;
   4.642 -		if( (ir & 0x01000000) == 0x01000000 ) { 
   4.643 -		    snprintf( buf, len, "BL%s     $%08Xh", cond, pc + offset + 8 );
   4.644 -		} else {
   4.645 -		    snprintf( buf, len, "B%s      $%08Xh", cond, pc + offset + 8 );
   4.646 -		}
   4.647 -	    } else {
   4.648 -		/* Load/store multiple */
   4.649 -		j = snprintf( buf, len, LFLAG(ir) ? "LDM%s%s  R%d%c,":"STM%s%s  R%d%c,", 
   4.650 -			      ldmModes[(ir>>23)&0x03], cond, RN(ir), WFLAG(ir)?'!':' ' );
   4.651 -		buf += j;
   4.652 -		len -= j;
   4.653 -		for( i = 0; i<16 && len > 2; i++ ) {
   4.654 -		    if( ir & (1<<i) ) {
   4.655 -			j = snprintf( buf, len, "R%d", i );
   4.656 -			buf+=j;
   4.657 -			len-=j;
   4.658 -		    }
   4.659 -		}
   4.660 -		if( BFLAG(ir) && len > 0 ) {
   4.661 -			buf[0] = '^';
   4.662 -			buf[1] = '\0';
   4.663 -		}
   4.664 -	    }
   4.665 -	    break;
   4.666 -	case 3: /* Copro */
   4.667 -	    if( (ir & 0x0F000000) == 0x0F000000 ) {
   4.668 -		snprintf( buf, len, "SWI%s    #%08Xh", cond, SIGNEXT24(ir) );
   4.669 -	    } else {
   4.670 -		UNIMP(ir);
   4.671 -	    }
   4.672 -	    break;
   4.673 -	}
   4.674 -	
   4.675 -	
   4.676 -	
   4.677 -	return pc+4;
   4.678 +            switch(OPCODE(ir)) {
   4.679 +            case 0: /* AND Rd, Rn, operand */
   4.680 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.681 +                snprintf(buf, len, "AND%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   4.682 +                break;
   4.683 +            case 1: /* ANDS Rd, Rn, operand */
   4.684 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.685 +                snprintf(buf, len, "ANDS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   4.686 +                break;
   4.687 +            case 2: /* EOR Rd, Rn, operand */
   4.688 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.689 +                snprintf(buf, len, "EOR%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   4.690 +                break;
   4.691 +            case 3: /* EORS Rd, Rn, operand */
   4.692 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.693 +                snprintf(buf, len, "EORS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   4.694 +                break;
   4.695 +            case 4: /* SUB Rd, Rn, operand */
   4.696 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.697 +                snprintf(buf, len, "SUB%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   4.698 +                break;
   4.699 +            case 5: /* SUBS Rd, Rn, operand */
   4.700 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.701 +                snprintf(buf, len, "SUBS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   4.702 +                break;
   4.703 +            case 6: /* RSB Rd, Rn, operand */
   4.704 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.705 +                snprintf(buf, len, "RSB%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   4.706 +                break;
   4.707 +            case 7: /* RSBS Rd, Rn, operand */
   4.708 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.709 +                snprintf(buf, len, "RSBS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   4.710 +                break;
   4.711 +            case 8: /* ADD Rd, Rn, operand */
   4.712 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.713 +                snprintf(buf, len, "ADD%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   4.714 +                break;
   4.715 +            case 9: /* ADDS Rd, Rn, operand */
   4.716 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.717 +                snprintf(buf, len, "ADDS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   4.718 +                break;
   4.719 +            case 10: /* ADC Rd, Rn, operand */
   4.720 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.721 +                snprintf(buf, len, "ADC%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   4.722 +                break;
   4.723 +            case 11: /* ADCS Rd, Rn, operand */
   4.724 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.725 +                snprintf(buf, len, "ADCS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   4.726 +                break;
   4.727 +            case 12: /* SBC Rd, Rn, operand */
   4.728 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.729 +                snprintf(buf, len, "SBC%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   4.730 +                break;
   4.731 +            case 13: /* SBCS Rd, Rn, operand */
   4.732 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.733 +                snprintf(buf, len, "SBCS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   4.734 +                break;
   4.735 +            case 14: /* RSC Rd, Rn, operand */
   4.736 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.737 +                snprintf(buf, len, "RSC%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   4.738 +                break;
   4.739 +            case 15: /* RSCS Rd, Rn, operand */
   4.740 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.741 +                snprintf(buf, len, "RSCS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   4.742 +                break;
   4.743 +            case 17: /* TST Rd, Rn, operand */
   4.744 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.745 +                snprintf(buf, len, "TST%s    R%d, %s", cond, RN(ir), operand);
   4.746 +                break;
   4.747 +            case 19: /* TEQ Rd, Rn, operand */
   4.748 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.749 +                snprintf(buf, len, "TEQ%s    R%d, %s", cond, RN(ir), operand);
   4.750 +                break;
   4.751 +            case 21: /* CMP Rd, Rn, operand */
   4.752 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.753 +                snprintf(buf, len, "CMP%s    R%d, %s", cond, RN(ir), operand);
   4.754 +                break;
   4.755 +            case 23: /* CMN Rd, Rn, operand */
   4.756 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.757 +                snprintf(buf, len, "CMN%s    R%d, %s", cond, RN(ir), operand);
   4.758 +                break;
   4.759 +            case 24: /* ORR Rd, Rn, operand */
   4.760 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.761 +                snprintf(buf, len, "ORR%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   4.762 +                break;
   4.763 +            case 25: /* ORRS Rd, Rn, operand */
   4.764 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.765 +                snprintf(buf, len, "ORRS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   4.766 +                break;
   4.767 +            case 26: /* MOV Rd, operand */
   4.768 +                if( ir == 0xE1A00000 ) {
   4.769 +                    /* Not technically a different instruction,
   4.770 +                     * but this one is commonly used as a NOP,
   4.771 +                     * so... 
   4.772 +                     */
   4.773 +                    snprintf(buf, len, "NOP");
   4.774 +                } else {
   4.775 +                    arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.776 +                    snprintf(buf, len, "MOV%s    R%d, %s", cond, RD(ir), operand);
   4.777 +                }
   4.778 +                break;
   4.779 +            case 27: /* MOVS Rd, operand */
   4.780 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.781 +                snprintf(buf, len, "MOVS%s   R%d, %s", cond, RD(ir), operand);
   4.782 +                break;
   4.783 +            case 28: /* BIC Rd, Rn, operand */
   4.784 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.785 +                snprintf(buf, len, "BIC%s    R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   4.786 +                break;
   4.787 +            case 29: /* BICS Rd, Rn, operand */
   4.788 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.789 +                snprintf(buf, len, "BICS%s   R%d, R%d, %s", cond, RD(ir), RN(ir), operand);
   4.790 +                break;
   4.791 +            case 30: /* MVN Rd, Rn, operand */
   4.792 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.793 +                snprintf(buf, len, "MVN%s    R%d, %s", cond, RD(ir), operand);
   4.794 +                break;
   4.795 +            case 31: /* MVNS Rd, Rn, operand */
   4.796 +                arm_disasm_shift_operand(ir, operand, sizeof(operand));
   4.797 +                snprintf(buf, len, "MVNS%s   R%d, %s", cond, RD(ir), operand);
   4.798 +                break;
   4.799 +            default:
   4.800 +                UNIMP(ir);
   4.801 +            }
   4.802 +        }
   4.803 +        break;
   4.804 +    case 1: /* Load/store */
   4.805 +        arm_disasm_address_operand( ir, operand, sizeof(operand), pc );
   4.806 +        switch( (ir>>20)&0x17 ) {
   4.807 +        case 0:
   4.808 +        case 16:
   4.809 +        case 18:
   4.810 +            snprintf(buf, len, "STR%s    R%d, %s", cond, RD(ir), operand );
   4.811 +            break;
   4.812 +        case 1:
   4.813 +        case 17:
   4.814 +        case 19:
   4.815 +            snprintf(buf, len, "LDR%s    R%d, %s", cond, RD(ir), operand );
   4.816 +            break;
   4.817 +        case 2:
   4.818 +            snprintf(buf, len, "STRT%s   R%d, %s", cond, RD(ir), operand );
   4.819 +            break;
   4.820 +        case 3:
   4.821 +            snprintf(buf, len, "LDRT%s   R%d, %s", cond, RD(ir), operand );
   4.822 +            break;
   4.823 +        case 4:
   4.824 +        case 20:
   4.825 +        case 22:
   4.826 +            snprintf(buf, len, "STRB%s   R%d, %s", cond, RD(ir), operand );
   4.827 +            break;
   4.828 +        case 5:
   4.829 +        case 21:
   4.830 +        case 23:
   4.831 +            snprintf(buf, len, "LDRB%s   R%d, %s", cond, RD(ir), operand );
   4.832 +            break;
   4.833 +        case 6:
   4.834 +            snprintf(buf, len, "STRBT%s  R%d, %s", cond, RD(ir), operand );
   4.835 +            break;
   4.836 +        case 7: 
   4.837 +            snprintf(buf, len, "LDRBT%s  R%d, %s", cond, RD(ir), operand );
   4.838 +            break;
   4.839 +        }
   4.840 +        break;
   4.841 +        case 2: 
   4.842 +            if( (ir & 0x02000000) == 0x02000000 ) {
   4.843 +                int32_t offset = SIGNEXT24(ir&0x00FFFFFF) << 2;
   4.844 +                if( (ir & 0x01000000) == 0x01000000 ) { 
   4.845 +                    snprintf( buf, len, "BL%s     $%08Xh", cond, pc + offset + 8 );
   4.846 +                } else {
   4.847 +                    snprintf( buf, len, "B%s      $%08Xh", cond, pc + offset + 8 );
   4.848 +                }
   4.849 +            } else {
   4.850 +                /* Load/store multiple */
   4.851 +                j = snprintf( buf, len, LFLAG(ir) ? "LDM%s%s  R%d%c,":"STM%s%s  R%d%c,", 
   4.852 +                        ldmModes[(ir>>23)&0x03], cond, RN(ir), WFLAG(ir)?'!':' ' );
   4.853 +                buf += j;
   4.854 +                len -= j;
   4.855 +                for( i = 0; i<16 && len > 2; i++ ) {
   4.856 +                    if( ir & (1<<i) ) {
   4.857 +                        j = snprintf( buf, len, "R%d", i );
   4.858 +                        buf+=j;
   4.859 +                        len-=j;
   4.860 +                    }
   4.861 +                }
   4.862 +                if( BFLAG(ir) && len > 0 ) {
   4.863 +                    buf[0] = '^';
   4.864 +                    buf[1] = '\0';
   4.865 +                }
   4.866 +            }
   4.867 +            break;
   4.868 +        case 3: /* Copro */
   4.869 +            if( (ir & 0x0F000000) == 0x0F000000 ) {
   4.870 +                snprintf( buf, len, "SWI%s    #%08Xh", cond, SIGNEXT24(ir) );
   4.871 +            } else {
   4.872 +                UNIMP(ir);
   4.873 +            }
   4.874 +            break;
   4.875 +    }
   4.876 +
   4.877 +
   4.878 +
   4.879 +    return pc+4;
   4.880  }
   4.881  
   4.882