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lxdream.org :: lxdream :: r550:a27e31340147
lxdream 0.9.1
released Jun 29
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changeset550:a27e31340147
parent549:828d103ad115
child551:07125ce718da
authornkeynes
dateThu Dec 06 10:43:30 2007 +0000 (12 years ago)
Add support for the MMIO side of the TLB (and LDTLB)
src/Makefile.am
src/Makefile.in
src/sh4/mmu.c
src/sh4/sh4core.c
src/sh4/sh4core.h
src/sh4/sh4core.in
src/sh4/sh4mem.c
src/sh4/sh4mmio.c
src/sh4/sh4mmio.h
src/sh4/sh4x86.c
src/sh4/sh4x86.in
src/test/testsh4x86.c
test/Makefile.in
test/testmmu.c
1.1 --- a/src/Makefile.am Thu Dec 06 10:40:27 2007 +0000
1.2 +++ b/src/Makefile.am Thu Dec 06 10:43:30 2007 +0000
1.3 @@ -9,7 +9,10 @@
1.4
1.5 bin_PROGRAMS = lxdream
1.6 noinst_PROGRAMS = gendec genglsl
1.7 +check_PROGRAMS = test/testxlt
1.8
1.9 +AM_CFLAGS = -D_ISOC99_SOURCE -D_BSD_SOURCE
1.10 +TESTS = test/testxlt
1.11 BUILT_SOURCES = sh4/sh4core.c sh4/sh4dasm.c sh4/sh4x86.c drivers/gl_slsrc.c
1.12
1.13 gendec_SOURCES = tools/gendec.c tools/gendec.h tools/insparse.c tools/actparse.c
1.14 @@ -24,7 +27,7 @@
1.15 gdrom/gdrom.c gdrom/gdrom.h gdrom/nrg.c gdrom/cdi.c gdrom/gdi.c \
1.16 dreamcast.c dreamcast.h eventq.c eventq.h \
1.17 sh4/sh4.c sh4/intc.c sh4/intc.h sh4/sh4mem.c sh4/timer.c sh4/dmac.c \
1.18 - sh4/sh4core.c sh4/sh4core.h sh4/sh4dasm.c sh4/sh4dasm.h \
1.19 + sh4/mmu.c sh4/sh4core.c sh4/sh4core.h sh4/sh4dasm.c sh4/sh4dasm.h \
1.20 sh4/sh4mmio.c sh4/sh4mmio.h sh4/scif.c sh4/sh4stat.c sh4/sh4stat.h \
1.21 sh4/xltcache.c sh4/xltcache.h \
1.22 aica/armcore.c aica/armcore.h aica/armdasm.c aica/armmem.c \
1.23 @@ -46,6 +49,16 @@
1.24 sh4/sh4trans.c sh4/sh4trans.h \
1.25 x86dasm/x86dasm.c x86dasm/x86dasm.h \
1.26 x86dasm/i386-dis.c x86dasm/dis-init.c x86dasm/dis-buf.c
1.27 +
1.28 +test_testsh4x86_SOURCES = test/testsh4x86.c x86dasm/x86dasm.c \
1.29 + x86dasm/x86dasm.h x86dasm/i386-dis.c x86dasm/dis-init.c \
1.30 + x86dasm/dis-buf.c \
1.31 + sh4/sh4dasm.c sh4/sh4trans.c sh4/sh4x86.c sh4/xltcache.c \
1.32 + sh4/xltcache.h mem.c util.c
1.33 +test_testsh4x86_LDADD = @GTK_LIBS@
1.34 +
1.35 +check_PROGRAMS += test/testsh4x86
1.36 +
1.37 endif
1.38
1.39 if GUI_GTK
1.40 @@ -72,21 +85,9 @@
1.41 gendec_LDADD = @GTK_LIBS@ $(INTLLIBS)
1.42 genglsl_LDADD = @GTK_LIBS@ $(INTLLIBS)
1.43
1.44 -TESTS = test/testxlt
1.45 -
1.46 -check_PROGRAMS = test/testxlt test/testsh4x86
1.47
1.48 test_testxlt_SOURCES = test/testxlt.c sh4/xltcache.c sh4/xltcache.h
1.49
1.50 -test_testsh4x86_SOURCES = test/testsh4x86.c x86dasm/x86dasm.c \
1.51 - x86dasm/x86dasm.h x86dasm/i386-dis.c x86dasm/dis-init.c \
1.52 - x86dasm/dis-buf.c \
1.53 - sh4/sh4dasm.c sh4/sh4trans.c sh4/sh4x86.c sh4/xltcache.c \
1.54 - sh4/xltcache.h mem.c util.c
1.55 -test_testsh4x86_LDADD = @PACKAGE_LIBS@
1.56 -
1.57 -AM_CFLAGS = -D_ISOC99_SOURCE -D_BSD_SOURCE
1.58 -
1.59 sh4/sh4core.c: gendec sh4/sh4.def sh4/sh4core.in
1.60 ./gendec sh4/sh4.def sh4/sh4core.in -o sh4/sh4core.c
1.61 sh4/sh4dasm.c: gendec sh4/sh4.def sh4/sh4dasm.in
2.1 --- a/src/Makefile.in Thu Dec 06 10:40:27 2007 +0000
2.2 +++ b/src/Makefile.in Thu Dec 06 10:43:30 2007 +0000
2.3 @@ -42,16 +42,17 @@
2.4 @BUILD_SH4X86_TRUE@ x86dasm/x86dasm.c x86dasm/x86dasm.h \
2.5 @BUILD_SH4X86_TRUE@ x86dasm/i386-dis.c x86dasm/dis-init.c x86dasm/dis-buf.c
2.6
2.7 -@GUI_GTK_TRUE@am__append_2 = gtkui/gtkui.c gtkui/gtkui.h \
2.8 +@BUILD_SH4X86_TRUE@am__append_2 = test/testsh4x86
2.9 +@GUI_GTK_TRUE@am__append_3 = gtkui/gtkui.c gtkui/gtkui.h \
2.10 @GUI_GTK_TRUE@ gtkui/main_win.c gtkui/gtkcb.c \
2.11 @GUI_GTK_TRUE@ gtkui/mmio_win.c gtkui/debug_win.c gtkui/dump_win.c \
2.12 @GUI_GTK_TRUE@ gtkui/ctrl_dlg.c gtkui/path_dlg.c gtkui/gdrom_menu.c \
2.13 @GUI_GTK_TRUE@ drivers/video_gtk.c drivers/video_gtk.h \
2.14 @GUI_GTK_TRUE@ drivers/video_glx.c drivers/video_glx.h
2.15
2.16 -@CDROM_LINUX_TRUE@am__append_3 = drivers/cd_linux.c
2.17 -@CDROM_LINUX_FALSE@am__append_4 = drivers/cd_none.c
2.18 -@AUDIO_ESOUND_TRUE@am__append_5 = drivers/audio_esd.c
2.19 +@CDROM_LINUX_TRUE@am__append_4 = drivers/cd_linux.c
2.20 +@CDROM_LINUX_FALSE@am__append_5 = drivers/cd_none.c
2.21 +@AUDIO_ESOUND_TRUE@am__append_6 = drivers/audio_esd.c
2.22 ACLOCAL = @ACLOCAL@
2.23 AMDEP_FALSE = @AMDEP_FALSE@
2.24 AMDEP_TRUE = @AMDEP_TRUE@
2.25 @@ -192,7 +193,10 @@
2.26
2.27 bin_PROGRAMS = lxdream
2.28 noinst_PROGRAMS = gendec genglsl
2.29 +check_PROGRAMS = test/testxlt $(am__append_2)
2.30
2.31 +AM_CFLAGS = -D_ISOC99_SOURCE -D_BSD_SOURCE
2.32 +TESTS = test/testxlt
2.33 BUILT_SOURCES = sh4/sh4core.c sh4/sh4dasm.c sh4/sh4x86.c drivers/gl_slsrc.c
2.34
2.35 gendec_SOURCES = tools/gendec.c tools/gendec.h tools/insparse.c tools/actparse.c
2.36 @@ -207,7 +211,7 @@
2.37 gdrom/gdrom.c gdrom/gdrom.h gdrom/nrg.c gdrom/cdi.c gdrom/gdi.c \
2.38 dreamcast.c dreamcast.h eventq.c eventq.h \
2.39 sh4/sh4.c sh4/intc.c sh4/intc.h sh4/sh4mem.c sh4/timer.c sh4/dmac.c \
2.40 - sh4/sh4core.c sh4/sh4core.h sh4/sh4dasm.c sh4/sh4dasm.h \
2.41 + sh4/mmu.c sh4/sh4core.c sh4/sh4core.h sh4/sh4dasm.c sh4/sh4dasm.h \
2.42 sh4/sh4mmio.c sh4/sh4mmio.h sh4/scif.c sh4/sh4stat.c sh4/sh4stat.h \
2.43 sh4/xltcache.c sh4/xltcache.h \
2.44 aica/armcore.c aica/armcore.h aica/armdasm.c aica/armmem.c \
2.45 @@ -222,35 +226,31 @@
2.46 drivers/audio_null.c drivers/video_null.c \
2.47 drivers/gl_common.c drivers/gl_common.h drivers/gl_fbo.c \
2.48 drivers/gl_sl.c drivers/gl_slsrc.c\
2.49 -$(am__append_1) $(am__append_2) $(am__append_3) $(am__append_4) $(am__append_5)
2.50 +$(am__append_1) $(am__append_3) $(am__append_4) $(am__append_5) $(am__append_6)
2.51 +
2.52 +@BUILD_SH4X86_TRUE@test_testsh4x86_SOURCES = test/testsh4x86.c x86dasm/x86dasm.c \
2.53 +@BUILD_SH4X86_TRUE@ x86dasm/x86dasm.h x86dasm/i386-dis.c x86dasm/dis-init.c \
2.54 +@BUILD_SH4X86_TRUE@ x86dasm/dis-buf.c \
2.55 +@BUILD_SH4X86_TRUE@ sh4/sh4dasm.c sh4/sh4trans.c sh4/sh4x86.c sh4/xltcache.c \
2.56 +@BUILD_SH4X86_TRUE@ sh4/xltcache.h mem.c util.c
2.57 +
2.58 +@BUILD_SH4X86_TRUE@test_testsh4x86_LDADD = @GTK_LIBS@
2.59
2.60 lxdream_LDADD = @GTK_LIBS@ @LIBPNG_LIBS@ @ESOUND_LIBS@ $(INTLLIBS)
2.61
2.62 gendec_LDADD = @GTK_LIBS@ $(INTLLIBS)
2.63 genglsl_LDADD = @GTK_LIBS@ $(INTLLIBS)
2.64
2.65 -TESTS = test/testxlt
2.66 -
2.67 -check_PROGRAMS = test/testxlt test/testsh4x86
2.68 -
2.69 test_testxlt_SOURCES = test/testxlt.c sh4/xltcache.c sh4/xltcache.h
2.70 -
2.71 -test_testsh4x86_SOURCES = test/testsh4x86.c x86dasm/x86dasm.c \
2.72 - x86dasm/x86dasm.h x86dasm/i386-dis.c x86dasm/dis-init.c \
2.73 - x86dasm/dis-buf.c \
2.74 - sh4/sh4dasm.c sh4/sh4trans.c sh4/sh4x86.c sh4/xltcache.c \
2.75 - sh4/xltcache.h mem.c util.c
2.76 -
2.77 -test_testsh4x86_LDADD = @PACKAGE_LIBS@
2.78 -
2.79 -AM_CFLAGS = -D_ISOC99_SOURCE -D_BSD_SOURCE
2.80 subdir = src
2.81 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
2.82 mkinstalldirs = $(SHELL) $(top_srcdir)/mkinstalldirs
2.83 CONFIG_HEADER = $(top_builddir)/config.h
2.84 CONFIG_CLEAN_FILES =
2.85 bin_PROGRAMS = lxdream$(EXEEXT)
2.86 -check_PROGRAMS = test/testxlt$(EXEEXT) test/testsh4x86$(EXEEXT)
2.87 +@BUILD_SH4X86_TRUE@check_PROGRAMS = test/testxlt$(EXEEXT) \
2.88 +@BUILD_SH4X86_TRUE@ test/testsh4x86$(EXEEXT)
2.89 +@BUILD_SH4X86_FALSE@check_PROGRAMS = test/testxlt$(EXEEXT)
2.90 noinst_PROGRAMS = gendec$(EXEEXT) genglsl$(EXEEXT)
2.91 PROGRAMS = $(bin_PROGRAMS) $(noinst_PROGRAMS)
2.92
2.93 @@ -268,12 +268,12 @@
2.94 gdrom/ide.c gdrom/ide.h gdrom/packet.h gdrom/gdimage.c \
2.95 gdrom/gdrom.c gdrom/gdrom.h gdrom/nrg.c gdrom/cdi.c gdrom/gdi.c \
2.96 dreamcast.c dreamcast.h eventq.c eventq.h sh4/sh4.c sh4/intc.c \
2.97 - sh4/intc.h sh4/sh4mem.c sh4/timer.c sh4/dmac.c sh4/sh4core.c \
2.98 - sh4/sh4core.h sh4/sh4dasm.c sh4/sh4dasm.h sh4/sh4mmio.c \
2.99 - sh4/sh4mmio.h sh4/scif.c sh4/sh4stat.c sh4/sh4stat.h \
2.100 - sh4/xltcache.c sh4/xltcache.h aica/armcore.c aica/armcore.h \
2.101 - aica/armdasm.c aica/armmem.c aica/aica.c aica/aica.h \
2.102 - aica/audio.c aica/audio.h pvr2/pvr2.c pvr2/pvr2.h \
2.103 + sh4/intc.h sh4/sh4mem.c sh4/timer.c sh4/dmac.c sh4/mmu.c \
2.104 + sh4/sh4core.c sh4/sh4core.h sh4/sh4dasm.c sh4/sh4dasm.h \
2.105 + sh4/sh4mmio.c sh4/sh4mmio.h sh4/scif.c sh4/sh4stat.c \
2.106 + sh4/sh4stat.h sh4/xltcache.c sh4/xltcache.h aica/armcore.c \
2.107 + aica/armcore.h aica/armdasm.c aica/armmem.c aica/aica.c \
2.108 + aica/aica.h aica/audio.c aica/audio.h pvr2/pvr2.c pvr2/pvr2.h \
2.109 pvr2/pvr2mem.c pvr2/tacore.c pvr2/render.c pvr2/rendcore.c \
2.110 pvr2/rendbkg.c pvr2/rendsort.c pvr2/texcache.c pvr2/yuv.c \
2.111 pvr2/rendsave.c maple/maple.c maple/maple.h maple/controller.c \
2.112 @@ -308,28 +308,35 @@
2.113 gdrom.$(OBJEXT) nrg.$(OBJEXT) cdi.$(OBJEXT) gdi.$(OBJEXT) \
2.114 dreamcast.$(OBJEXT) eventq.$(OBJEXT) sh4.$(OBJEXT) \
2.115 intc.$(OBJEXT) sh4mem.$(OBJEXT) timer.$(OBJEXT) dmac.$(OBJEXT) \
2.116 - sh4core.$(OBJEXT) sh4dasm.$(OBJEXT) sh4mmio.$(OBJEXT) \
2.117 - scif.$(OBJEXT) sh4stat.$(OBJEXT) xltcache.$(OBJEXT) \
2.118 - armcore.$(OBJEXT) armdasm.$(OBJEXT) armmem.$(OBJEXT) \
2.119 - aica.$(OBJEXT) audio.$(OBJEXT) pvr2.$(OBJEXT) pvr2mem.$(OBJEXT) \
2.120 - tacore.$(OBJEXT) render.$(OBJEXT) rendcore.$(OBJEXT) \
2.121 - rendbkg.$(OBJEXT) rendsort.$(OBJEXT) texcache.$(OBJEXT) \
2.122 - yuv.$(OBJEXT) rendsave.$(OBJEXT) maple.$(OBJEXT) \
2.123 - controller.$(OBJEXT) loader.$(OBJEXT) bootstrap.$(OBJEXT) \
2.124 - util.$(OBJEXT) display.$(OBJEXT) audio_null.$(OBJEXT) \
2.125 - video_null.$(OBJEXT) gl_common.$(OBJEXT) gl_fbo.$(OBJEXT) \
2.126 - gl_sl.$(OBJEXT) gl_slsrc.$(OBJEXT) $(am__objects_1) \
2.127 - $(am__objects_2) $(am__objects_3) $(am__objects_4) \
2.128 - $(am__objects_5)
2.129 + mmu.$(OBJEXT) sh4core.$(OBJEXT) sh4dasm.$(OBJEXT) \
2.130 + sh4mmio.$(OBJEXT) scif.$(OBJEXT) sh4stat.$(OBJEXT) \
2.131 + xltcache.$(OBJEXT) armcore.$(OBJEXT) armdasm.$(OBJEXT) \
2.132 + armmem.$(OBJEXT) aica.$(OBJEXT) audio.$(OBJEXT) pvr2.$(OBJEXT) \
2.133 + pvr2mem.$(OBJEXT) tacore.$(OBJEXT) render.$(OBJEXT) \
2.134 + rendcore.$(OBJEXT) rendbkg.$(OBJEXT) rendsort.$(OBJEXT) \
2.135 + texcache.$(OBJEXT) yuv.$(OBJEXT) rendsave.$(OBJEXT) \
2.136 + maple.$(OBJEXT) controller.$(OBJEXT) loader.$(OBJEXT) \
2.137 + bootstrap.$(OBJEXT) util.$(OBJEXT) display.$(OBJEXT) \
2.138 + audio_null.$(OBJEXT) video_null.$(OBJEXT) gl_common.$(OBJEXT) \
2.139 + gl_fbo.$(OBJEXT) gl_sl.$(OBJEXT) gl_slsrc.$(OBJEXT) \
2.140 + $(am__objects_1) $(am__objects_2) $(am__objects_3) \
2.141 + $(am__objects_4) $(am__objects_5)
2.142 lxdream_OBJECTS = $(am_lxdream_OBJECTS)
2.143 lxdream_DEPENDENCIES =
2.144 lxdream_LDFLAGS =
2.145 -am_test_testsh4x86_OBJECTS = testsh4x86.$(OBJEXT) x86dasm.$(OBJEXT) \
2.146 - i386-dis.$(OBJEXT) dis-init.$(OBJEXT) dis-buf.$(OBJEXT) \
2.147 - sh4dasm.$(OBJEXT) sh4trans.$(OBJEXT) sh4x86.$(OBJEXT) \
2.148 - xltcache.$(OBJEXT) mem.$(OBJEXT) util.$(OBJEXT)
2.149 +am__test_testsh4x86_SOURCES_DIST = test/testsh4x86.c x86dasm/x86dasm.c \
2.150 + x86dasm/x86dasm.h x86dasm/i386-dis.c x86dasm/dis-init.c \
2.151 + x86dasm/dis-buf.c sh4/sh4dasm.c sh4/sh4trans.c sh4/sh4x86.c \
2.152 + sh4/xltcache.c sh4/xltcache.h mem.c util.c
2.153 +@BUILD_SH4X86_TRUE@am_test_testsh4x86_OBJECTS = testsh4x86.$(OBJEXT) \
2.154 +@BUILD_SH4X86_TRUE@ x86dasm.$(OBJEXT) i386-dis.$(OBJEXT) \
2.155 +@BUILD_SH4X86_TRUE@ dis-init.$(OBJEXT) dis-buf.$(OBJEXT) \
2.156 +@BUILD_SH4X86_TRUE@ sh4dasm.$(OBJEXT) sh4trans.$(OBJEXT) \
2.157 +@BUILD_SH4X86_TRUE@ sh4x86.$(OBJEXT) xltcache.$(OBJEXT) \
2.158 +@BUILD_SH4X86_TRUE@ mem.$(OBJEXT) util.$(OBJEXT)
2.159 test_testsh4x86_OBJECTS = $(am_test_testsh4x86_OBJECTS)
2.160 -test_testsh4x86_DEPENDENCIES =
2.161 +@BUILD_SH4X86_TRUE@test_testsh4x86_DEPENDENCIES =
2.162 +@BUILD_SH4X86_FALSE@test_testsh4x86_DEPENDENCIES =
2.163 test_testsh4x86_LDFLAGS =
2.164 am__dirstamp = $(am__leading_dot)dirstamp
2.165 am_test_testxlt_OBJECTS = testxlt.$(OBJEXT) xltcache.$(OBJEXT)
2.166 @@ -365,28 +372,29 @@
2.167 @AMDEP_TRUE@ ./$(DEPDIR)/loader.Po ./$(DEPDIR)/main.Po \
2.168 @AMDEP_TRUE@ ./$(DEPDIR)/main_win.Po ./$(DEPDIR)/maple.Po \
2.169 @AMDEP_TRUE@ ./$(DEPDIR)/mem.Po ./$(DEPDIR)/mmio_win.Po \
2.170 -@AMDEP_TRUE@ ./$(DEPDIR)/nrg.Po ./$(DEPDIR)/path_dlg.Po \
2.171 -@AMDEP_TRUE@ ./$(DEPDIR)/pvr2.Po ./$(DEPDIR)/pvr2mem.Po \
2.172 -@AMDEP_TRUE@ ./$(DEPDIR)/rendbkg.Po ./$(DEPDIR)/rendcore.Po \
2.173 -@AMDEP_TRUE@ ./$(DEPDIR)/render.Po ./$(DEPDIR)/rendsave.Po \
2.174 -@AMDEP_TRUE@ ./$(DEPDIR)/rendsort.Po ./$(DEPDIR)/scif.Po \
2.175 -@AMDEP_TRUE@ ./$(DEPDIR)/sh4.Po ./$(DEPDIR)/sh4core.Po \
2.176 -@AMDEP_TRUE@ ./$(DEPDIR)/sh4dasm.Po ./$(DEPDIR)/sh4mem.Po \
2.177 -@AMDEP_TRUE@ ./$(DEPDIR)/sh4mmio.Po ./$(DEPDIR)/sh4stat.Po \
2.178 -@AMDEP_TRUE@ ./$(DEPDIR)/sh4trans.Po ./$(DEPDIR)/sh4x86.Po \
2.179 -@AMDEP_TRUE@ ./$(DEPDIR)/syscall.Po ./$(DEPDIR)/tacore.Po \
2.180 -@AMDEP_TRUE@ ./$(DEPDIR)/testsh4x86.Po ./$(DEPDIR)/testxlt.Po \
2.181 -@AMDEP_TRUE@ ./$(DEPDIR)/texcache.Po ./$(DEPDIR)/timer.Po \
2.182 -@AMDEP_TRUE@ ./$(DEPDIR)/util.Po ./$(DEPDIR)/video_glx.Po \
2.183 -@AMDEP_TRUE@ ./$(DEPDIR)/video_gtk.Po ./$(DEPDIR)/video_null.Po \
2.184 -@AMDEP_TRUE@ ./$(DEPDIR)/watch.Po ./$(DEPDIR)/x86dasm.Po \
2.185 -@AMDEP_TRUE@ ./$(DEPDIR)/xltcache.Po ./$(DEPDIR)/yuv.Po
2.186 +@AMDEP_TRUE@ ./$(DEPDIR)/mmu.Po ./$(DEPDIR)/nrg.Po \
2.187 +@AMDEP_TRUE@ ./$(DEPDIR)/path_dlg.Po ./$(DEPDIR)/pvr2.Po \
2.188 +@AMDEP_TRUE@ ./$(DEPDIR)/pvr2mem.Po ./$(DEPDIR)/rendbkg.Po \
2.189 +@AMDEP_TRUE@ ./$(DEPDIR)/rendcore.Po ./$(DEPDIR)/render.Po \
2.190 +@AMDEP_TRUE@ ./$(DEPDIR)/rendsave.Po ./$(DEPDIR)/rendsort.Po \
2.191 +@AMDEP_TRUE@ ./$(DEPDIR)/scif.Po ./$(DEPDIR)/sh4.Po \
2.192 +@AMDEP_TRUE@ ./$(DEPDIR)/sh4core.Po ./$(DEPDIR)/sh4dasm.Po \
2.193 +@AMDEP_TRUE@ ./$(DEPDIR)/sh4mem.Po ./$(DEPDIR)/sh4mmio.Po \
2.194 +@AMDEP_TRUE@ ./$(DEPDIR)/sh4stat.Po ./$(DEPDIR)/sh4trans.Po \
2.195 +@AMDEP_TRUE@ ./$(DEPDIR)/sh4x86.Po ./$(DEPDIR)/syscall.Po \
2.196 +@AMDEP_TRUE@ ./$(DEPDIR)/tacore.Po ./$(DEPDIR)/testsh4x86.Po \
2.197 +@AMDEP_TRUE@ ./$(DEPDIR)/testxlt.Po ./$(DEPDIR)/texcache.Po \
2.198 +@AMDEP_TRUE@ ./$(DEPDIR)/timer.Po ./$(DEPDIR)/util.Po \
2.199 +@AMDEP_TRUE@ ./$(DEPDIR)/video_glx.Po ./$(DEPDIR)/video_gtk.Po \
2.200 +@AMDEP_TRUE@ ./$(DEPDIR)/video_null.Po ./$(DEPDIR)/watch.Po \
2.201 +@AMDEP_TRUE@ ./$(DEPDIR)/x86dasm.Po ./$(DEPDIR)/xltcache.Po \
2.202 +@AMDEP_TRUE@ ./$(DEPDIR)/yuv.Po
2.203 COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
2.204 $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
2.205 CCLD = $(CC)
2.206 LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
2.207 DIST_SOURCES = $(gendec_SOURCES) $(genglsl_SOURCES) \
2.208 - $(am__lxdream_SOURCES_DIST) $(test_testsh4x86_SOURCES) \
2.209 + $(am__lxdream_SOURCES_DIST) $(am__test_testsh4x86_SOURCES_DIST) \
2.210 $(test_testxlt_SOURCES)
2.211 DIST_COMMON = $(srcdir)/Makefile.in Makefile.am
2.212 SOURCES = $(gendec_SOURCES) $(genglsl_SOURCES) $(lxdream_SOURCES) $(test_testsh4x86_SOURCES) $(test_testxlt_SOURCES)
2.213 @@ -504,6 +512,7 @@
2.214 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/maple.Po@am__quote@
2.215 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mem.Po@am__quote@
2.216 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mmio_win.Po@am__quote@
2.217 +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mmu.Po@am__quote@
2.218 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/nrg.Po@am__quote@
2.219 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/path_dlg.Po@am__quote@
2.220 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pvr2.Po@am__quote@
2.221 @@ -889,6 +898,28 @@
2.222 @AMDEP_TRUE@@am__fastdepCC_FALSE@ $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
2.223 @am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o dmac.obj `if test -f 'sh4/dmac.c'; then $(CYGPATH_W) 'sh4/dmac.c'; else $(CYGPATH_W) '$(srcdir)/sh4/dmac.c'; fi`
2.224
2.225 +mmu.o: sh4/mmu.c
2.226 +@am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT mmu.o -MD -MP -MF "$(DEPDIR)/mmu.Tpo" \
2.227 +@am__fastdepCC_TRUE@ -c -o mmu.o `test -f 'sh4/mmu.c' || echo '$(srcdir)/'`sh4/mmu.c; \
2.228 +@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/mmu.Tpo" "$(DEPDIR)/mmu.Po"; \
2.229 +@am__fastdepCC_TRUE@ else rm -f "$(DEPDIR)/mmu.Tpo"; exit 1; \
2.230 +@am__fastdepCC_TRUE@ fi
2.231 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='sh4/mmu.c' object='mmu.o' libtool=no @AMDEPBACKSLASH@
2.232 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ depfile='$(DEPDIR)/mmu.Po' tmpdepfile='$(DEPDIR)/mmu.TPo' @AMDEPBACKSLASH@
2.233 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
2.234 +@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o mmu.o `test -f 'sh4/mmu.c' || echo '$(srcdir)/'`sh4/mmu.c
2.235 +
2.236 +mmu.obj: sh4/mmu.c
2.237 +@am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT mmu.obj -MD -MP -MF "$(DEPDIR)/mmu.Tpo" \
2.238 +@am__fastdepCC_TRUE@ -c -o mmu.obj `if test -f 'sh4/mmu.c'; then $(CYGPATH_W) 'sh4/mmu.c'; else $(CYGPATH_W) '$(srcdir)/sh4/mmu.c'; fi`; \
2.239 +@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/mmu.Tpo" "$(DEPDIR)/mmu.Po"; \
2.240 +@am__fastdepCC_TRUE@ else rm -f "$(DEPDIR)/mmu.Tpo"; exit 1; \
2.241 +@am__fastdepCC_TRUE@ fi
2.242 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='sh4/mmu.c' object='mmu.obj' libtool=no @AMDEPBACKSLASH@
2.243 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ depfile='$(DEPDIR)/mmu.Po' tmpdepfile='$(DEPDIR)/mmu.TPo' @AMDEPBACKSLASH@
2.244 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
2.245 +@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o mmu.obj `if test -f 'sh4/mmu.c'; then $(CYGPATH_W) 'sh4/mmu.c'; else $(CYGPATH_W) '$(srcdir)/sh4/mmu.c'; fi`
2.246 +
2.247 sh4core.o: sh4/sh4core.c
2.248 @am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT sh4core.o -MD -MP -MF "$(DEPDIR)/sh4core.Tpo" \
2.249 @am__fastdepCC_TRUE@ -c -o sh4core.o `test -f 'sh4/sh4core.c' || echo '$(srcdir)/'`sh4/sh4core.c; \
3.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
3.2 +++ b/src/sh4/mmu.c Thu Dec 06 10:43:30 2007 +0000
3.3 @@ -0,0 +1,333 @@
3.4 +/**
3.5 + * $Id: mmu.c,v 1.15 2007-11-08 11:54:16 nkeynes Exp $
3.6 + *
3.7 + * MMU implementation
3.8 + *
3.9 + * Copyright (c) 2005 Nathan Keynes.
3.10 + *
3.11 + * This program is free software; you can redistribute it and/or modify
3.12 + * it under the terms of the GNU General Public License as published by
3.13 + * the Free Software Foundation; either version 2 of the License, or
3.14 + * (at your option) any later version.
3.15 + *
3.16 + * This program is distributed in the hope that it will be useful,
3.17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3.18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3.19 + * GNU General Public License for more details.
3.20 + */
3.21 +#define MODULE sh4_module
3.22 +
3.23 +#include <stdio.h>
3.24 +#include "sh4/sh4mmio.h"
3.25 +#include "sh4/sh4core.h"
3.26 +#include "mem.h"
3.27 +
3.28 +#define OCRAM_START (0x1C000000>>PAGE_BITS)
3.29 +#define OCRAM_END (0x20000000>>PAGE_BITS)
3.30 +
3.31 +#define ITLB_ENTRY_COUNT 4
3.32 +#define UTLB_ENTRY_COUNT 64
3.33 +
3.34 +/* Entry address */
3.35 +#define TLB_VALID 0x00000100
3.36 +#define TLB_USERMODE 0x00000040
3.37 +#define TLB_WRITABLE 0x00000020
3.38 +#define TLB_SIZE_MASK 0x00000090
3.39 +#define TLB_SIZE_1K 0x00000000
3.40 +#define TLB_SIZE_4K 0x00000010
3.41 +#define TLB_SIZE_64K 0x00000080
3.42 +#define TLB_SIZE_1M 0x00000090
3.43 +#define TLB_CACHEABLE 0x00000008
3.44 +#define TLB_DIRTY 0x00000004
3.45 +#define TLB_SHARE 0x00000002
3.46 +#define TLB_WRITETHRU 0x00000001
3.47 +
3.48 +
3.49 +struct itlb_entry {
3.50 + sh4addr_t vpn; // Virtual Page Number
3.51 + uint32_t asid; // Process ID
3.52 + sh4addr_t ppn; // Physical Page Number
3.53 + uint32_t flags;
3.54 +};
3.55 +
3.56 +struct utlb_entry {
3.57 + sh4addr_t vpn; // Virtual Page Number
3.58 + uint32_t asid; // Process ID
3.59 + sh4addr_t ppn; // Physical Page Number
3.60 + uint32_t flags;
3.61 + uint32_t pcmcia; // extra pcmcia data - not used
3.62 +};
3.63 +
3.64 +static struct itlb_entry mmu_itlb[ITLB_ENTRY_COUNT];
3.65 +static struct utlb_entry mmu_utlb[UTLB_ENTRY_COUNT];
3.66 +static uint32_t mmu_urc;
3.67 +static uint32_t mmu_urb;
3.68 +static uint32_t mmu_lrui;
3.69 +
3.70 +static sh4ptr_t cache = NULL;
3.71 +
3.72 +static void mmu_invalidate_tlb();
3.73 +
3.74 +
3.75 +int32_t mmio_region_MMU_read( uint32_t reg )
3.76 +{
3.77 + switch( reg ) {
3.78 + case MMUCR:
3.79 + return MMIO_READ( MMU, MMUCR) | (mmu_urc<<10) | (mmu_urb<<18) | (mmu_lrui<<26);
3.80 + default:
3.81 + return MMIO_READ( MMU, reg );
3.82 + }
3.83 +}
3.84 +
3.85 +void mmio_region_MMU_write( uint32_t reg, uint32_t val )
3.86 +{
3.87 + switch(reg) {
3.88 + case PTEH:
3.89 + val &= 0xFFFFFCFF;
3.90 + break;
3.91 + case PTEL:
3.92 + val &= 0x1FFFFDFF;
3.93 + break;
3.94 + case PTEA:
3.95 + val &= 0x0000000F;
3.96 + break;
3.97 + case MMUCR:
3.98 + if( val & MMUCR_TI ) {
3.99 + mmu_invalidate_tlb();
3.100 + }
3.101 + mmu_urc = (val >> 10) & 0x3F;
3.102 + mmu_urb = (val >> 18) & 0x3F;
3.103 + mmu_lrui = (val >> 26) & 0x3F;
3.104 + val &= 0x00000301;
3.105 + break;
3.106 + case CCR:
3.107 + mmu_set_cache_mode( val & (CCR_OIX|CCR_ORA) );
3.108 + break;
3.109 + default:
3.110 + break;
3.111 + }
3.112 + MMIO_WRITE( MMU, reg, val );
3.113 +}
3.114 +
3.115 +
3.116 +void MMU_init()
3.117 +{
3.118 + cache = mem_alloc_pages(2);
3.119 +}
3.120 +
3.121 +void MMU_reset()
3.122 +{
3.123 + mmio_region_MMU_write( CCR, 0 );
3.124 +}
3.125 +
3.126 +void MMU_save_state( FILE *f )
3.127 +{
3.128 + fwrite( cache, 4096, 2, f );
3.129 + fwrite( &mmu_itlb, sizeof(mmu_itlb), 1, f );
3.130 + fwrite( &mmu_utlb, sizeof(mmu_utlb), 1, f );
3.131 +}
3.132 +
3.133 +int MMU_load_state( FILE *f )
3.134 +{
3.135 + /* Setup the cache mode according to the saved register value
3.136 + * (mem_load runs before this point to load all MMIO data)
3.137 + */
3.138 + mmio_region_MMU_write( CCR, MMIO_READ(MMU, CCR) );
3.139 + if( fread( cache, 4096, 2, f ) != 2 ) {
3.140 + return 1;
3.141 + }
3.142 + if( fread( &mmu_itlb, sizeof(mmu_itlb), 1, f ) != 1 ) {
3.143 + return 1;
3.144 + }
3.145 + if( fread( &mmu_utlb, sizeof(mmu_utlb), 1, f ) != 1 ) {
3.146 + return 1;
3.147 + }
3.148 + return 0;
3.149 +}
3.150 +
3.151 +void mmu_set_cache_mode( int mode )
3.152 +{
3.153 + uint32_t i;
3.154 + switch( mode ) {
3.155 + case MEM_OC_INDEX0: /* OIX=0 */
3.156 + for( i=OCRAM_START; i<OCRAM_END; i++ )
3.157 + page_map[i] = cache + ((i&0x02)<<(PAGE_BITS-1));
3.158 + break;
3.159 + case MEM_OC_INDEX1: /* OIX=1 */
3.160 + for( i=OCRAM_START; i<OCRAM_END; i++ )
3.161 + page_map[i] = cache + ((i&0x02000000)>>(25-PAGE_BITS));
3.162 + break;
3.163 + default: /* disabled */
3.164 + for( i=OCRAM_START; i<OCRAM_END; i++ )
3.165 + page_map[i] = NULL;
3.166 + break;
3.167 + }
3.168 +}
3.169 +
3.170 +/* TLB maintanence */
3.171 +
3.172 +/**
3.173 + * LDTLB instruction implementation. Copies PTEH, PTEL and PTEA into the UTLB
3.174 + * entry identified by MMUCR.URC. Does not modify MMUCR or the ITLB.
3.175 + */
3.176 +void MMU_ldtlb()
3.177 +{
3.178 + mmu_utlb[mmu_urc].vpn = MMIO_READ(MMU, PTEH) & 0xFFFFFC00;
3.179 + mmu_utlb[mmu_urc].asid = MMIO_READ(MMU, PTEH) & 0x000000FF;
3.180 + mmu_utlb[mmu_urc].ppn = MMIO_READ(MMU, PTEL) & 0x1FFFFC00;
3.181 + mmu_utlb[mmu_urc].flags = MMIO_READ(MMU, PTEL) & 0x00001FF;
3.182 + mmu_utlb[mmu_urc].pcmcia = MMIO_READ(MMU, PTEA);
3.183 +}
3.184 +
3.185 +uint64_t mmu_translate_read( sh4addr_t addr )
3.186 +{
3.187 + uint32_t mmucr = MMIO_READ(MMU,MMUCR);
3.188 + if( IS_SH4_PRIVMODE() ) {
3.189 + switch( addr & 0xE0000000 ) {
3.190 + case 0x80000000: case 0xA0000000:
3.191 + /* Non-translated read P1,P2 */
3.192 + break;
3.193 + case 0xE0000000:
3.194 + /* Non-translated read P4 */
3.195 + break;
3.196 + default:
3.197 + if( mmucr&MMUCR_AT ) {
3.198 + } else {
3.199 + // direct read
3.200 + }
3.201 + }
3.202 + } else {
3.203 + if( addr & 0x80000000 ) {
3.204 + if( ((addr&0xFC000000) == 0xE0000000 ) &&
3.205 + ((mmucr&MMUCR_SQMD) == 0) ) {
3.206 + // Store queue
3.207 + return 0;
3.208 + }
3.209 +// MMU_READ_ADDR_ERROR();
3.210 + }
3.211 + if( mmucr&MMUCR_AT ) {
3.212 + uint32_t vpn = addr & 0xFFFFFC00;
3.213 + uint32_t asid = MMIO_READ(MMU,PTEH)&0xFF;
3.214 + } else {
3.215 + // direct read
3.216 + }
3.217 + }
3.218 +}
3.219 +
3.220 +static void mmu_invalidate_tlb()
3.221 +{
3.222 + int i;
3.223 + for( i=0; i<ITLB_ENTRY_COUNT; i++ ) {
3.224 + mmu_itlb[i].flags &= (~TLB_VALID);
3.225 + }
3.226 + for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
3.227 + mmu_utlb[i].flags &= (~TLB_VALID);
3.228 + }
3.229 +}
3.230 +
3.231 +#define ITLB_ENTRY(addr) ((addr>>7)&0x03)
3.232 +
3.233 +int32_t mmu_itlb_addr_read( sh4addr_t addr )
3.234 +{
3.235 + struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
3.236 + return ent->vpn | ent->asid | (ent->flags & TLB_VALID);
3.237 +}
3.238 +int32_t mmu_itlb_data_read( sh4addr_t addr )
3.239 +{
3.240 + struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
3.241 + return ent->ppn | ent->flags;
3.242 +}
3.243 +
3.244 +void mmu_itlb_addr_write( sh4addr_t addr, uint32_t val )
3.245 +{
3.246 + struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
3.247 + ent->vpn = val & 0xFFFFFC00;
3.248 + ent->asid = val & 0x000000FF;
3.249 + ent->flags = (ent->flags & ~(TLB_VALID)) | (val&TLB_VALID);
3.250 +}
3.251 +
3.252 +void mmu_itlb_data_write( sh4addr_t addr, uint32_t val )
3.253 +{
3.254 + struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
3.255 + ent->ppn = val & 0x1FFFFC00;
3.256 + ent->flags = val & 0x00001DA;
3.257 +}
3.258 +
3.259 +#define UTLB_ENTRY(addr) ((addr>>8)&0x3F)
3.260 +#define UTLB_ASSOC(addr) (addr&0x80)
3.261 +#define UTLB_DATA2(addr) (addr&0x00800000)
3.262 +
3.263 +int32_t mmu_utlb_addr_read( sh4addr_t addr )
3.264 +{
3.265 + struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
3.266 + return ent->vpn | ent->asid | (ent->flags & TLB_VALID) |
3.267 + ((ent->flags & TLB_DIRTY)<<7);
3.268 +}
3.269 +int32_t mmu_utlb_data_read( sh4addr_t addr )
3.270 +{
3.271 + struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
3.272 + if( UTLB_DATA2(addr) ) {
3.273 + return ent->pcmcia;
3.274 + } else {
3.275 + return ent->ppn | ent->flags;
3.276 + }
3.277 +}
3.278 +
3.279 +void mmu_utlb_addr_write( sh4addr_t addr, uint32_t val )
3.280 +{
3.281 + if( UTLB_ASSOC(addr) ) {
3.282 + } else {
3.283 + struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
3.284 + ent->vpn = (val & 0xFFFFFC00);
3.285 + ent->asid = (val & 0xFF);
3.286 + ent->flags = (ent->flags & ~(TLB_DIRTY|TLB_VALID));
3.287 + ent->flags |= (val & TLB_VALID);
3.288 + ent->flags |= ((val & 0x200)>>7);
3.289 + }
3.290 +}
3.291 +
3.292 +void mmu_utlb_data_write( sh4addr_t addr, uint32_t val )
3.293 +{
3.294 + struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
3.295 + if( UTLB_DATA2(addr) ) {
3.296 + ent->pcmcia = val & 0x0000000F;
3.297 + } else {
3.298 + ent->ppn = (val & 0x1FFFFC00);
3.299 + ent->flags = (val & 0x000001FF);
3.300 + }
3.301 +}
3.302 +
3.303 +/* Cache access - not implemented */
3.304 +
3.305 +int32_t mmu_icache_addr_read( sh4addr_t addr )
3.306 +{
3.307 + return 0; // not implemented
3.308 +}
3.309 +int32_t mmu_icache_data_read( sh4addr_t addr )
3.310 +{
3.311 + return 0; // not implemented
3.312 +}
3.313 +int32_t mmu_ocache_addr_read( sh4addr_t addr )
3.314 +{
3.315 + return 0; // not implemented
3.316 +}
3.317 +int32_t mmu_ocache_data_read( sh4addr_t addr )
3.318 +{
3.319 + return 0; // not implemented
3.320 +}
3.321 +
3.322 +void mmu_icache_addr_write( sh4addr_t addr, uint32_t val )
3.323 +{
3.324 +}
3.325 +
3.326 +void mmu_icache_data_write( sh4addr_t addr, uint32_t val )
3.327 +{
3.328 +}
3.329 +
3.330 +void mmu_ocache_addr_write( sh4addr_t addr, uint32_t val )
3.331 +{
3.332 +}
3.333 +
3.334 +void mmu_ocache_data_write( sh4addr_t addr, uint32_t val )
3.335 +{
3.336 +}
4.1 --- a/src/sh4/sh4core.c Thu Dec 06 10:40:27 2007 +0000
4.2 +++ b/src/sh4/sh4core.c Thu Dec 06 10:43:30 2007 +0000
4.3 @@ -1,5 +1,5 @@
4.4 /**
4.5 - * $Id: sh4core.c,v 1.50 2007-11-04 08:49:18 nkeynes Exp $
4.6 + * $Id: sh4core.in,v 1.10 2007-11-04 08:49:18 nkeynes Exp $
4.7 *
4.8 * SH4 emulation core, and parent module for all the SH4 peripheral
4.9 * modules.
4.10 @@ -417,7 +417,7 @@
4.11 break;
4.12 case 0x3:
4.13 { /* LDTLB */
4.14 - /* TODO */
4.15 + MMU_ldtlb();
4.16 }
4.17 break;
4.18 case 0x4:
5.1 --- a/src/sh4/sh4core.h Thu Dec 06 10:40:27 2007 +0000
5.2 +++ b/src/sh4/sh4core.h Thu Dec 06 10:43:30 2007 +0000
5.3 @@ -151,6 +151,7 @@
5.4 void MMU_reset( void );
5.5 void MMU_save_state( FILE *f );
5.6 int MMU_load_state( FILE *f );
5.7 +void MMU_ldtlb();
5.8 void SCIF_update_line_speed(void);
5.9
5.10 #define SIGNEXT4(n) ((((int32_t)(n))<<28)>>28)
6.1 --- a/src/sh4/sh4core.in Thu Dec 06 10:40:27 2007 +0000
6.2 +++ b/src/sh4/sh4core.in Thu Dec 06 10:43:30 2007 +0000
6.3 @@ -336,7 +336,7 @@
6.4 CLRT {: sh4r.t = 0; :}
6.5 SETT {: sh4r.t = 1; :}
6.6 CLRMAC {: sh4r.mac = 0; :}
6.7 -LDTLB {: /* TODO */ :}
6.8 +LDTLB {: MMU_ldtlb(); :}
6.9 CLRS {: sh4r.s = 0; :}
6.10 SETS {: sh4r.s = 1; :}
6.11 MOVT Rn {: sh4r.r[Rn] = sh4r.t; :}
7.1 --- a/src/sh4/sh4mem.c Thu Dec 06 10:40:27 2007 +0000
7.2 +++ b/src/sh4/sh4mem.c Thu Dec 06 10:43:30 2007 +0000
7.3 @@ -17,6 +17,7 @@
7.4 */
7.5
7.6 #define MODULE sh4_module
7.7 +#define ENABLE_TRACE_IO 1
7.8
7.9 #include <string.h>
7.10 #include <zlib.h>
7.11 @@ -73,12 +74,23 @@
7.12 {
7.13 struct mmio_region *io = P4_io[(addr&0x1FFFFFFF)>>19];
7.14 if( !io ) {
7.15 - if( (addr & 0xFF000000) != 0xF4000000 ) {
7.16 - /* OC address cache isn't implemented, but don't complain about it.
7.17 - * Complain about anything else though */
7.18 - WARN( "Attempted read from unknown P4 region: %08X", addr );
7.19 + switch( addr & 0x1F000000 ) {
7.20 + case 0x00000000: case 0x01000000: case 0x02000000: case 0x03000000:
7.21 + /* Store queue - readable? */
7.22 + return 0;
7.23 + break;
7.24 + case 0x10000000: return mmu_icache_addr_read( addr );
7.25 + case 0x11000000: return mmu_icache_data_read( addr );
7.26 + case 0x12000000: return mmu_itlb_addr_read( addr );
7.27 + case 0x13000000: return mmu_itlb_data_read( addr );
7.28 + case 0x14000000: return mmu_ocache_addr_read( addr );
7.29 + case 0x15000000: return mmu_ocache_data_read( addr );
7.30 + case 0x16000000: return mmu_utlb_addr_read( addr );
7.31 + case 0x17000000: return mmu_utlb_data_read( addr );
7.32 + default:
7.33 + WARN( "Attempted read from unknown or invalid P4 region: %08X", addr );
7.34 + return 0;
7.35 }
7.36 - return 0;
7.37 } else {
7.38 int32_t val = io->io_read( addr&0xFFF );
7.39 TRACE_P4IO( "Long read %08X <= %08X", io, (addr&0xFFF), val, addr );
7.40 @@ -90,12 +102,20 @@
7.41 {
7.42 struct mmio_region *io = P4_io[(addr&0x1FFFFFFF)>>19];
7.43 if( !io ) {
7.44 - if( (addr & 0xFC000000) == 0xE0000000 ) {
7.45 + switch( addr & 0x1F000000 ) {
7.46 + case 0x00000000: case 0x01000000: case 0x02000000: case 0x03000000:
7.47 /* Store queue */
7.48 SH4_WRITE_STORE_QUEUE( addr, val );
7.49 - } else if( (addr & 0xFF000000) != 0xF4000000 ) {
7.50 - /* OC address cache isn't implemented, but don't complain about it.
7.51 - * Complain about anything else though */
7.52 + break;
7.53 + case 0x10000000: mmu_icache_addr_write( addr, val ); break;
7.54 + case 0x11000000: mmu_icache_data_write( addr, val ); break;
7.55 + case 0x12000000: mmu_itlb_addr_write( addr, val ); break;
7.56 + case 0x13000000: mmu_itlb_data_write( addr, val ); break;
7.57 + case 0x14000000: mmu_ocache_addr_write( addr, val ); break;
7.58 + case 0x15000000: mmu_ocache_data_write( addr, val ); break;
7.59 + case 0x16000000: mmu_utlb_addr_write( addr, val ); break;
7.60 + case 0x17000000: mmu_utlb_data_write( addr, val ); break;
7.61 + default:
7.62 WARN( "Attempted write to unknown P4 region: %08X", addr );
7.63 }
7.64 } else {
8.1 --- a/src/sh4/sh4mmio.c Thu Dec 06 10:40:27 2007 +0000
8.2 +++ b/src/sh4/sh4mmio.c Thu Dec 06 10:43:30 2007 +0000
8.3 @@ -28,81 +28,6 @@
8.4 #define MMIO_IMPL
8.5 #include "sh4/sh4mmio.h"
8.6
8.7 -/********************************* MMU *************************************/
8.8 -
8.9 -MMIO_REGION_READ_DEFFN( MMU )
8.10 -
8.11 -#define OCRAM_START (0x1C000000>>PAGE_BITS)
8.12 -#define OCRAM_END (0x20000000>>PAGE_BITS)
8.13 -
8.14 -static sh4ptr_t cache = NULL;
8.15 -
8.16 -void mmio_region_MMU_write( uint32_t reg, uint32_t val )
8.17 -{
8.18 - switch(reg) {
8.19 - case MMUCR:
8.20 - if( val & MMUCR_AT ) {
8.21 - ERROR( "MMU Address translation not implemented!" );
8.22 - dreamcast_stop();
8.23 - }
8.24 - break;
8.25 - case CCR:
8.26 - mmu_set_cache_mode( val & (CCR_OIX|CCR_ORA) );
8.27 - break;
8.28 - default:
8.29 - break;
8.30 - }
8.31 - MMIO_WRITE( MMU, reg, val );
8.32 -}
8.33 -
8.34 -
8.35 -void MMU_init()
8.36 -{
8.37 - cache = mem_alloc_pages(2);
8.38 -}
8.39 -
8.40 -void MMU_reset()
8.41 -{
8.42 - mmio_region_MMU_write( CCR, 0 );
8.43 -}
8.44 -
8.45 -void MMU_save_state( FILE *f )
8.46 -{
8.47 - fwrite( cache, 4096, 2, f );
8.48 -}
8.49 -
8.50 -int MMU_load_state( FILE *f )
8.51 -{
8.52 - /* Setup the cache mode according to the saved register value
8.53 - * (mem_load runs before this point to load all MMIO data)
8.54 - */
8.55 - mmio_region_MMU_write( CCR, MMIO_READ(MMU, CCR) );
8.56 - if( fread( cache, 4096, 2, f ) != 2 ) {
8.57 - return 1;
8.58 - }
8.59 - return 0;
8.60 -}
8.61 -
8.62 -void mmu_set_cache_mode( int mode )
8.63 -{
8.64 - uint32_t i;
8.65 - switch( mode ) {
8.66 - case MEM_OC_INDEX0: /* OIX=0 */
8.67 - for( i=OCRAM_START; i<OCRAM_END; i++ )
8.68 - page_map[i] = cache + ((i&0x02)<<(PAGE_BITS-1));
8.69 - break;
8.70 - case MEM_OC_INDEX1: /* OIX=1 */
8.71 - for( i=OCRAM_START; i<OCRAM_END; i++ )
8.72 - page_map[i] = cache + ((i&0x02000000)>>(25-PAGE_BITS));
8.73 - break;
8.74 - default: /* disabled */
8.75 - for( i=OCRAM_START; i<OCRAM_END; i++ )
8.76 - page_map[i] = NULL;
8.77 - break;
8.78 - }
8.79 -}
8.80 -
8.81 -
8.82 /********************************* BSC *************************************/
8.83
8.84 uint32_t bsc_input = 0x0300;
9.1 --- a/src/sh4/sh4mmio.h Thu Dec 06 10:40:27 2007 +0000
9.2 +++ b/src/sh4/sh4mmio.h Thu Dec 06 10:43:30 2007 +0000
9.3 @@ -17,6 +17,7 @@
9.4 * GNU General Public License for more details.
9.5 */
9.6
9.7 +#include "lxdream.h"
9.8 #include "mmio.h"
9.9
9.10 #if (defined(MMIO_IMPL) && !defined(SH4MMIO_IMPL)) || \
9.11 @@ -35,8 +36,8 @@
9.12 LONG_PORT( 0x008, TTB, PORT_MRW, UNDEFINED, "Translation table base" )
9.13 LONG_PORT( 0x00C, TEA, PORT_MRW, UNDEFINED, "TLB exception address" )
9.14 LONG_PORT( 0x010, MMUCR,PORT_MRW, 0, "MMU control register" )
9.15 - BYTE_PORT( 0x14, BASRA, PORT_MRW, UNDEFINED, "Break ASID A" ) /* UBC */
9.16 - BYTE_PORT( 0x18, BASRB, PORT_MRW, UNDEFINED, "Break ASID B" ) /* UBC */
9.17 + BYTE_PORT( 0x014, BASRA, PORT_MRW, UNDEFINED, "Break ASID A" ) /* UBC */
9.18 + BYTE_PORT( 0x018, BASRB, PORT_MRW, UNDEFINED, "Break ASID B" ) /* UBC */
9.19 LONG_PORT( 0x01C, CCR, PORT_MRW, 0, "Cache control register" )
9.20 LONG_PORT( 0x020, TRA, PORT_MRW, UNDEFINED, "TRAPA exception register" )
9.21 LONG_PORT( 0x024, EXPEVT,PORT_MRW, 0, "Exception event register" )
9.22 @@ -208,7 +209,25 @@
9.23 #define MEM_OC_INDEX0 CCR_ORA
9.24 #define MEM_OC_INDEX1 CCR_ORA|CCR_OIX
9.25
9.26 +/* MMU functions */
9.27 void mmu_init(void);
9.28 void mmu_set_cache_mode( int );
9.29 +void mmu_ldtlb(void);
9.30
9.31 +int32_t mmu_icache_addr_read( sh4addr_t addr );
9.32 +int32_t mmu_icache_data_read( sh4addr_t addr );
9.33 +int32_t mmu_itlb_addr_read( sh4addr_t addr );
9.34 +int32_t mmu_itlb_data_read( sh4addr_t addr );
9.35 +int32_t mmu_ocache_addr_read( sh4addr_t addr );
9.36 +int32_t mmu_ocache_data_read( sh4addr_t addr );
9.37 +int32_t mmu_utlb_addr_read( sh4addr_t addr );
9.38 +int32_t mmu_utlb_data_read( sh4addr_t addr );
9.39 +void mmu_icache_addr_write( sh4addr_t addr, uint32_t val );
9.40 +void mmu_icache_data_write( sh4addr_t addr, uint32_t val );
9.41 +void mmu_itlb_addr_write( sh4addr_t addr, uint32_t val );
9.42 +void mmu_itlb_data_write( sh4addr_t addr, uint32_t val );
9.43 +void mmu_ocache_addr_write( sh4addr_t addr, uint32_t val );
9.44 +void mmu_ocache_data_write( sh4addr_t addr, uint32_t val );
9.45 +void mmu_utlb_addr_write( sh4addr_t addr, uint32_t val );
9.46 +void mmu_utlb_data_write( sh4addr_t addr, uint32_t val );
9.47 #endif
10.1 --- a/src/sh4/sh4x86.c Thu Dec 06 10:40:27 2007 +0000
10.2 +++ b/src/sh4/sh4x86.c Thu Dec 06 10:43:30 2007 +0000
10.3 @@ -624,6 +624,7 @@
10.4 break;
10.5 case 0x3:
10.6 { /* LDTLB */
10.7 + MMU_ldtlb();
10.8 }
10.9 break;
10.10 case 0x4:
11.1 --- a/src/sh4/sh4x86.in Thu Dec 06 10:40:27 2007 +0000
11.2 +++ b/src/sh4/sh4x86.in Thu Dec 06 10:43:30 2007 +0000
11.3 @@ -2399,7 +2399,9 @@
11.4 store_spreg( R_EAX, R_PR );
11.5 sh4_x86.tstate = TSTATE_NONE;
11.6 :}
11.7 -LDTLB {: :}
11.8 +LDTLB {:
11.9 + MMU_ldtlb();
11.10 +:}
11.11 OCBI @Rn {: :}
11.12 OCBP @Rn {: :}
11.13 OCBWB @Rn {: :}
12.1 --- a/src/test/testsh4x86.c Thu Dec 06 10:40:27 2007 +0000
12.2 +++ b/src/test/testsh4x86.c Thu Dec 06 10:43:30 2007 +0000
12.3 @@ -70,6 +70,7 @@
12.4 void event_execute() {}
12.5 void TMU_run_slice( uint32_t nanos ) {}
12.6 void SCIF_run_slice( uint32_t nanos ) {}
12.7 +void MMU_ldtlb(void) {}
12.8 void sh4_write_byte( uint32_t addr, uint32_t val ) {}
12.9 void sh4_write_word( uint32_t addr, uint32_t val ) {}
12.10 void sh4_write_long( uint32_t addr, uint32_t val ) {}
13.1 --- a/test/Makefile.in Thu Dec 06 10:40:27 2007 +0000
13.2 +++ b/test/Makefile.in Thu Dec 06 10:43:30 2007 +0000
13.3 @@ -16,7 +16,7 @@
13.4 ARMLD = @ARMLD@
13.5 ARMOBJCOPY = @ARMOBJCOPY@
13.6
13.7 -RUNTEST = ../src/lxdream -c ./lxdream.rc -puh
13.8 +RUNTEST = ../src/lxdream -c ./lxdream.rc -puh -A null
13.9
13.10
13.11 # cygwin
13.12 @@ -64,12 +64,12 @@
13.13 check: build-tests
13.14 cat testta.data testta2.data testta3.data testta4.data testta5.data | $(RUNTEST) testta
13.15 $(RUNTEST) testsh4
13.16 + $(RUNTEST) testmmu
13.17 $(RUNTEST) testregs
13.18 - $(RUNTEST) testmath
13.19 - $(RUNTEST) testide -d ../disc/test.nrg
13.20 +# $(RUNTEST) testide -d ../disc/test.nrg
13.21
13.22
13.23 -build-tests: testsh4 testmath testide testta testregs testrend testdisp testspu
13.24 +build-tests: testsh4 testmath testide testta testregs testrend testdisp testspu testmmu
13.25
13.26 testsh4: crt0.so sh4/testsh4.so timer.so interrupt.so \
13.27 sh4/add.so sh4/addc.so sh4/addv.so sh4/and.so sh4/andi.so \
13.28 @@ -86,6 +86,10 @@
13.29 $(SH4CC) $(SH4LDFLAGS) $^ -o $@ $(SH4LIBS)
13.30 $(SH4OBJCOPY) testide testide.bin
13.31
13.32 +testmmu: crt0.so testmmu.so lib.so
13.33 + $(SH4CC) $(SH4LDFLAGS) $^ -o $@ $(SH4LIBS)
13.34 + $(SH4OBJCOPY) testmmu testmmu.bin
13.35 +
13.36 testmath: crt0.so $(SHARED_OBJECTS) testmath.so math.so
13.37 $(SH4CC) $(SH4LDFLAGS) $^ -o $@ $(SH4LIBS)
13.38
14.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
14.2 +++ b/test/testmmu.c Thu Dec 06 10:43:30 2007 +0000
14.3 @@ -0,0 +1,65 @@
14.4 +#include <assert.h>
14.5 +#include <stdio.h>
14.6 +#include "lib.h"
14.7 +
14.8 +#define PTEH 0xFF000000
14.9 +#define PTEL 0xFF000004
14.10 +#define TTB 0xFF000008
14.11 +#define TEA 0xFF00000C
14.12 +#define MMUCR 0xFF000010
14.13 +#define PTEA 0xFF000034
14.14 +
14.15 +#define ITLB_ADDR(entry) (0xF2000000 + (entry<<8))
14.16 +#define ITLB_DATA(entry) (0xF3000000 + (entry<<8))
14.17 +#define UTLB_ADDR(entry) (0xF6000000 + (entry<<8))
14.18 +#define UTLB_DATA1(entry) (0xF7000000 + (entry<<8))
14.19 +#define UTLB_DATA2(entry) (0xF7800000 + (entry<<8))
14.20 +
14.21 +/* Bang on the mmio side of the TLBs to make sure the bits
14.22 + * respond appropriately (with AT disabled so we don't risk
14.23 + * doing a hard crash) */
14.24 +void test_tlb_mmio()
14.25 +{
14.26 + int entry;
14.27 + for( entry=0; entry<64; entry++ ) {
14.28 + long_write( UTLB_DATA1(entry), 0 );
14.29 + long_write( UTLB_ADDR(entry), 0xFFFFFFFF );
14.30 + assert( long_read( UTLB_ADDR(entry) ) == 0xFFFFFFFF );
14.31 + assert( long_read( UTLB_DATA1(entry) ) == 0x00000104 );
14.32 + long_write( UTLB_ADDR(entry), 0x00000000 );
14.33 + assert( long_read( UTLB_ADDR(entry) ) == 0x00000000 );
14.34 + assert( long_read( UTLB_DATA1(entry) ) == 0x00000000 );
14.35 + long_write( UTLB_DATA1(entry), 0xFFFFFFFF );
14.36 + assert( long_read( UTLB_DATA1(entry) ) == 0x1FFFFDFF );
14.37 + assert( long_read( UTLB_ADDR(entry) ) == 0x00000300 );
14.38 + long_write( UTLB_DATA1(entry), 0x00000000 );
14.39 + assert( long_read( UTLB_DATA1(entry) ) == 0x00000000 );
14.40 + assert( long_read( UTLB_ADDR(entry) ) == 0x00000000 );
14.41 + long_write( UTLB_DATA2(entry), 0xFFFFFFFF );
14.42 + assert( long_read( UTLB_DATA2(entry) ) == 0x0000000F );
14.43 + long_write( UTLB_DATA2(entry), 0x00000000 );
14.44 + assert( long_read( UTLB_DATA2(entry) ) == 0x00000000 );
14.45 + }
14.46 +
14.47 + for( entry=0; entry<4; entry++ ) {
14.48 + long_write( ITLB_DATA(entry), 0 );
14.49 + long_write( ITLB_ADDR(entry), 0xFFFFFFFF );
14.50 + assert( long_read( ITLB_ADDR(entry) ) == 0xFFFFFDFF );
14.51 + assert( long_read( ITLB_DATA(entry) ) == 0x00000100 );
14.52 + long_write( ITLB_ADDR(entry), 0x00000000 );
14.53 + assert( long_read( ITLB_ADDR(entry) ) == 0x00000000 );
14.54 + assert( long_read( ITLB_DATA(entry) ) == 0x00000000 );
14.55 + long_write( ITLB_DATA(entry), 0xFFFFFFFF );
14.56 + assert( long_read( ITLB_DATA(entry) ) == 0x1FFFFDDA );
14.57 + assert( long_read( ITLB_ADDR(entry) ) == 0x00000100 );
14.58 + long_write( ITLB_DATA(entry), 0x00000000 );
14.59 + assert( long_read( ITLB_DATA(entry) ) == 0x00000000 );
14.60 + assert( long_read( ITLB_ADDR(entry) ) == 0x00000000 );
14.61 +
14.62 + }
14.63 +}
14.64 +
14.65 +int main( int argc, char *argv[] )
14.66 +{
14.67 + test_tlb_mmio();
14.68 +}
.