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lxdream.org :: lxdream :: r671:a530ea88eebd
lxdream 0.9.1
released Jun 29
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changeset671:a530ea88eebd
parent670:5d277b7ad0df
child672:cc2c2b0ab272
authornkeynes
dateThu May 15 10:22:39 2008 +0000 (11 years ago)
Permanently add SH4 instruction statistics tracking (enabled with --enable-sh4stats)
config.h.in
configure
configure.in
src/dcload.c
src/dreamcast.c
src/gtkui/gtkcb.c
src/gtkui/main_win.c
src/main.c
src/sh4/sh4.c
src/sh4/sh4core.c
src/sh4/sh4core.in
src/sh4/sh4stat.c
src/sh4/sh4stat.h
src/sh4/sh4stat.in
src/sh4/sh4x86.c
src/sh4/sh4x86.in
1.1 --- a/config.h.in Tue May 13 08:48:15 2008 +0000
1.2 +++ b/config.h.in Thu May 15 10:22:39 2008 +0000
1.3 @@ -13,6 +13,9 @@
1.4 /* always defined to indicate that i18n is enabled */
1.5 #undef ENABLE_NLS
1.6
1.7 +/* Enable SH4 statistics */
1.8 +#undef ENABLE_SH4STATS
1.9 +
1.10 /* Enable IO tracing */
1.11 #undef ENABLE_TRACE_IO
1.12
2.1 --- a/configure Tue May 13 08:48:15 2008 +0000
2.2 +++ b/configure Thu May 15 10:22:39 2008 +0000
2.3 @@ -1375,6 +1375,7 @@
2.4 performance)
2.5 --enable-watch Enable watchpoints in the debugger (warning: hurts
2.6 performance)
2.7 + --enable-sh4stats Enable statistics on executed sh4 instructions
2.8
2.9 Optional Packages:
2.10 --with-PACKAGE[=ARG] use PACKAGE [ARG=yes]
2.11 @@ -5734,6 +5735,17 @@
2.12 fi
2.13 fi
2.14
2.15 +# Check whether --enable-sh4stats was given.
2.16 +if test "${enable_sh4stats+set}" = set; then
2.17 + enableval=$enable_sh4stats; if test "$enableval" == "yes"; then
2.18 +
2.19 +cat >>confdefs.h <<\_ACEOF
2.20 +#define ENABLE_SH4STATS 1
2.21 +_ACEOF
2.22 +
2.23 + fi
2.24 +fi
2.25 +
2.26
2.27 # Check whether --with-osmesa was given.
2.28 if test "${with_osmesa+set}" = set; then
3.1 --- a/configure.in Tue May 13 08:48:15 2008 +0000
3.2 +++ b/configure.in Thu May 15 10:22:39 2008 +0000
3.3 @@ -22,6 +22,11 @@
3.4 [if test "$enableval" == "yes"; then
3.5 AC_DEFINE(ENABLE_WATCH, 1, [Enable watchpoints])
3.6 fi] )
3.7 +AC_ARG_ENABLE( sh4stats,
3.8 + AS_HELP_STRING( [--enable-sh4stats], [Enable statistics on executed sh4 instructions]),
3.9 + [if test "$enableval" == "yes"; then
3.10 + AC_DEFINE(ENABLE_SH4STATS, 1, [Enable SH4 statistics])
3.11 + fi] )
3.12 AC_ARG_WITH( osmesa,
3.13 AS_HELP_STRING( [--with-osmesa], [Build with the osmesa GL library (software rendering)]),
3.14 [], [with_osmesa=no])
4.1 --- a/src/dcload.c Tue May 13 08:48:15 2008 +0000
4.2 +++ b/src/dcload.c Thu May 15 10:22:39 2008 +0000
4.3 @@ -145,6 +145,7 @@
4.4 break;
4.5 case SYS_EXIT:
4.6 if( dcload_allow_unsafe ) {
4.7 + dreamcast_shutdown();
4.8 exit( sh4r.r[5] );
4.9 } else {
4.10 dreamcast_stop();
5.1 --- a/src/dreamcast.c Tue May 13 08:48:15 2008 +0000
5.2 +++ b/src/dreamcast.c Thu May 15 10:22:39 2008 +0000
5.3 @@ -218,6 +218,9 @@
5.4 {
5.5 dreamcast_stop();
5.6 dreamcast_save_flash();
5.7 +#ifdef ENABLE_SH4STATS
5.8 + sh4_stats_print(stdout);
5.9 +#endif
5.10 }
5.11
5.12 void dreamcast_program_loaded( const gchar *name, sh4addr_t entry_point )
6.1 --- a/src/gtkui/gtkcb.c Tue May 13 08:48:15 2008 +0000
6.2 +++ b/src/gtkui/gtkcb.c Thu May 15 10:22:39 2008 +0000
6.3 @@ -190,6 +190,7 @@
6.4
6.5 void exit_action_callback( GtkAction *action, gpointer user_data)
6.6 {
6.7 + dreamcast_shutdown();
6.8 exit(0);
6.9 }
6.10
7.1 --- a/src/gtkui/main_win.c Tue May 13 08:48:15 2008 +0000
7.2 +++ b/src/gtkui/main_win.c Thu May 15 10:22:39 2008 +0000
7.3 @@ -209,6 +209,7 @@
7.4
7.5 static gboolean on_main_window_deleted( GtkWidget *widget, GdkEvent event, gpointer user_data )
7.6 {
7.7 + dreamcast_shutdown();
7.8 exit(0);
7.9 }
7.10
8.1 --- a/src/main.c Tue May 13 08:48:15 2008 +0000
8.2 +++ b/src/main.c Thu May 15 10:22:39 2008 +0000
8.3 @@ -207,6 +207,7 @@
8.4 if( dreamcast_can_run() ) {
8.5 if( time_nanos != 0 || time_secs != 0 ) {
8.6 dreamcast_run_for(time_secs, time_nanos);
8.7 + dreamcast_shutdown();
8.8 return 0;
8.9 } else {
8.10 dreamcast_run();
8.11 @@ -218,6 +219,7 @@
8.12 if( !headless ) {
8.13 gui_main_loop();
8.14 }
8.15 + dreamcast_shutdown();
8.16 return 0;
8.17 }
8.18
9.1 --- a/src/sh4/sh4.c Tue May 13 08:48:15 2008 +0000
9.2 +++ b/src/sh4/sh4.c Thu May 15 10:22:39 2008 +0000
9.3 @@ -20,7 +20,7 @@
9.4 #define MODULE sh4_module
9.5 #include <math.h>
9.6 #include <assert.h>
9.7 -#include "dream.h"
9.8 +#include "lxdream.h"
9.9 #include "dreamcast.h"
9.10 #include "mem.h"
9.11 #include "clock.h"
9.12 @@ -83,6 +83,9 @@
9.13 MMU_init();
9.14 TMU_init();
9.15 sh4_reset();
9.16 +#ifdef ENABLE_SH4STATS
9.17 + sh4_stats_reset();
9.18 +#endif
9.19 }
9.20
9.21 void sh4_start(void)
9.22 @@ -117,7 +120,10 @@
9.23 MMU_reset();
9.24 TMU_reset();
9.25 SCIF_reset();
9.26 +
9.27 +#ifdef ENABLE_SH4STATS
9.28 sh4_stats_reset();
9.29 +#endif
9.30 }
9.31
9.32 void sh4_stop(void)
10.1 --- a/src/sh4/sh4core.c Tue May 13 08:48:15 2008 +0000
10.2 +++ b/src/sh4/sh4core.c Thu May 15 10:22:39 2008 +0000
10.3 @@ -28,6 +28,7 @@
10.4 #include "syscall.h"
10.5 #include "sh4/sh4core.h"
10.6 #include "sh4/sh4mmio.h"
10.7 +#include "sh4/sh4stat.h"
10.8 #include "sh4/intc.h"
10.9
10.10 #define SH4_CALLTRACE 1
10.11 @@ -228,9 +229,14 @@
10.12 sh4r.in_delay_slot = 0;
10.13 pc = sh4r.pc = sh4r.pr;
10.14 sh4r.new_pc = sh4r.pc + 2;
10.15 + return TRUE;
10.16 }
10.17 CHECKRALIGN16(pc);
10.18
10.19 +#ifdef ENABLE_SH4STATS
10.20 + sh4_stats_add_by_pc(sh4r.pc);
10.21 +#endif
10.22 +
10.23 /* Read instruction */
10.24 if( !IS_IN_ICACHE(pc) ) {
10.25 if( !mmu_update_icache(pc) ) {
11.1 --- a/src/sh4/sh4core.in Tue May 13 08:48:15 2008 +0000
11.2 +++ b/src/sh4/sh4core.in Thu May 15 10:22:39 2008 +0000
11.3 @@ -28,6 +28,7 @@
11.4 #include "syscall.h"
11.5 #include "sh4/sh4core.h"
11.6 #include "sh4/sh4mmio.h"
11.7 +#include "sh4/sh4stat.h"
11.8 #include "sh4/intc.h"
11.9
11.10 #define SH4_CALLTRACE 1
11.11 @@ -228,9 +229,14 @@
11.12 sh4r.in_delay_slot = 0;
11.13 pc = sh4r.pc = sh4r.pr;
11.14 sh4r.new_pc = sh4r.pc + 2;
11.15 + return TRUE;
11.16 }
11.17 CHECKRALIGN16(pc);
11.18
11.19 +#ifdef ENABLE_SH4STATS
11.20 + sh4_stats_add_by_pc(sh4r.pc);
11.21 +#endif
11.22 +
11.23 /* Read instruction */
11.24 if( !IS_IN_ICACHE(pc) ) {
11.25 if( !mmu_update_icache(pc) ) {
12.1 --- a/src/sh4/sh4stat.c Tue May 13 08:48:15 2008 +0000
12.2 +++ b/src/sh4/sh4stat.c Thu May 15 10:22:39 2008 +0000
12.3 @@ -182,7 +182,13 @@
12.4 fprintf( out, "Total: %lld\n", sh4_stats_total );
12.5 }
12.6
12.7 -void sh4_stats_add( uint32_t pc )
12.8 +void sh4_stats_add( sh4_inst_id item )
12.9 +{
12.10 + sh4_stats[item]++;
12.11 + sh4_stats_total++;
12.12 +}
12.13 +
12.14 +void sh4_stats_add_by_pc( uint32_t pc )
12.15 {
12.16 uint16_t ir = sh4_read_word(pc);
12.17 #define UNDEF() sh4_stats[0]++
13.1 --- a/src/sh4/sh4stat.h Tue May 13 08:48:15 2008 +0000
13.2 +++ b/src/sh4/sh4stat.h Thu May 15 10:22:39 2008 +0000
13.3 @@ -16,7 +16,13 @@
13.4 * GNU General Public License for more details.
13.5 */
13.6
13.7 -enum sh4_inst_id {
13.8 +#ifndef lxdream_sh4stat_H
13.9 +#define lxdream_sh4stat_H
13.10 +
13.11 +#include <stdio.h>
13.12 +#include <stdint.h>
13.13 +
13.14 +typedef enum {
13.15 I_UNKNOWN,
13.16 I_ADD, I_ADDI, I_ADDC, I_ADDV,
13.17 I_AND, I_ANDI, I_ANDB,
13.18 @@ -51,10 +57,14 @@
13.19 I_TST, I_TSTI, I_TSTB,
13.20 I_XOR, I_XORI, I_XORB,
13.21 I_XTRCT,
13.22 - I_UNDEF };
13.23 + I_UNDEF } sh4_inst_id;
13.24
13.25 #define SH4_INSTRUCTION_COUNT I_UNDEF
13.26
13.27 void sh4_stats_reset( void );
13.28 void sh4_stats_print( FILE *out );
13.29 -void sh4_stats_add( uint32_t pc );
13.30 +void sh4_stats_add( sh4_inst_id id );
13.31 +void sh4_stats_add_by_pc( uint32_t pc );
13.32 +
13.33 +
13.34 +#endif /* !lxdream_sh4stat_H */
14.1 --- a/src/sh4/sh4stat.in Tue May 13 08:48:15 2008 +0000
14.2 +++ b/src/sh4/sh4stat.in Thu May 15 10:22:39 2008 +0000
14.3 @@ -182,7 +182,13 @@
14.4 fprintf( out, "Total: %lld\n", sh4_stats_total );
14.5 }
14.6
14.7 -void sh4_stats_add( uint32_t pc )
14.8 +void sh4_stats_add( sh4_inst_id item )
14.9 +{
14.10 + sh4_stats[item]++;
14.11 + sh4_stats_total++;
14.12 +}
14.13 +
14.14 +void sh4_stats_add_by_pc( uint32_t pc )
14.15 {
14.16 uint16_t ir = sh4_read_word(pc);
14.17 #define UNDEF() sh4_stats[0]++
15.1 --- a/src/sh4/sh4x86.c Tue May 13 08:48:15 2008 +0000
15.2 +++ b/src/sh4/sh4x86.c Thu May 15 10:22:39 2008 +0000
15.3 @@ -28,6 +28,7 @@
15.4 #include "sh4/xltcache.h"
15.5 #include "sh4/sh4core.h"
15.6 #include "sh4/sh4trans.h"
15.7 +#include "sh4/sh4stat.h"
15.8 #include "sh4/sh4mmio.h"
15.9 #include "sh4/x86op.h"
15.10 #include "clock.h"
15.11 @@ -79,6 +80,12 @@
15.12 #define TSTATE_A 7
15.13 #define TSTATE_AE 3
15.14
15.15 +#ifdef ENABLE_SH4STATS
15.16 +#define COUNT_INST(id) load_imm32(R_EAX,id); call_func1(sh4_stats_add, R_EAX); sh4_x86.tstate = TSTATE_NONE
15.17 +#else
15.18 +#define COUNT_INST(id)
15.19 +#endif
15.20 +
15.21 /** Branch if T is set (either in the current cflags, or in sh4r.t) */
15.22 #define JT_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
15.23 CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
15.24 @@ -391,6 +398,7 @@
15.25 case 0x0:
15.26 { /* STC SR, Rn */
15.27 uint32_t Rn = ((ir>>8)&0xF);
15.28 + COUNT_INST(I_STCSR);
15.29 check_priv();
15.30 call_func0(sh4_read_sr);
15.31 store_reg( R_EAX, Rn );
15.32 @@ -400,6 +408,7 @@
15.33 case 0x1:
15.34 { /* STC GBR, Rn */
15.35 uint32_t Rn = ((ir>>8)&0xF);
15.36 + COUNT_INST(I_STC);
15.37 load_spreg( R_EAX, R_GBR );
15.38 store_reg( R_EAX, Rn );
15.39 }
15.40 @@ -407,6 +416,7 @@
15.41 case 0x2:
15.42 { /* STC VBR, Rn */
15.43 uint32_t Rn = ((ir>>8)&0xF);
15.44 + COUNT_INST(I_STC);
15.45 check_priv();
15.46 load_spreg( R_EAX, R_VBR );
15.47 store_reg( R_EAX, Rn );
15.48 @@ -416,6 +426,7 @@
15.49 case 0x3:
15.50 { /* STC SSR, Rn */
15.51 uint32_t Rn = ((ir>>8)&0xF);
15.52 + COUNT_INST(I_STC);
15.53 check_priv();
15.54 load_spreg( R_EAX, R_SSR );
15.55 store_reg( R_EAX, Rn );
15.56 @@ -425,6 +436,7 @@
15.57 case 0x4:
15.58 { /* STC SPC, Rn */
15.59 uint32_t Rn = ((ir>>8)&0xF);
15.60 + COUNT_INST(I_STC);
15.61 check_priv();
15.62 load_spreg( R_EAX, R_SPC );
15.63 store_reg( R_EAX, Rn );
15.64 @@ -439,6 +451,7 @@
15.65 case 0x1:
15.66 { /* STC Rm_BANK, Rn */
15.67 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);
15.68 + COUNT_INST(I_STC);
15.69 check_priv();
15.70 load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
15.71 store_reg( R_EAX, Rn );
15.72 @@ -452,6 +465,7 @@
15.73 case 0x0:
15.74 { /* BSRF Rn */
15.75 uint32_t Rn = ((ir>>8)&0xF);
15.76 + COUNT_INST(I_BSRF);
15.77 if( sh4_x86.in_delay_slot ) {
15.78 SLOTILLEGAL();
15.79 } else {
15.80 @@ -478,6 +492,7 @@
15.81 case 0x2:
15.82 { /* BRAF Rn */
15.83 uint32_t Rn = ((ir>>8)&0xF);
15.84 + COUNT_INST(I_BRAF);
15.85 if( sh4_x86.in_delay_slot ) {
15.86 SLOTILLEGAL();
15.87 } else {
15.88 @@ -502,6 +517,7 @@
15.89 case 0x8:
15.90 { /* PREF @Rn */
15.91 uint32_t Rn = ((ir>>8)&0xF);
15.92 + COUNT_INST(I_PREF);
15.93 load_reg( R_EAX, Rn );
15.94 MOV_r32_r32( R_EAX, R_ECX );
15.95 AND_imm32_r32( 0xFC000000, R_EAX );
15.96 @@ -517,21 +533,25 @@
15.97 case 0x9:
15.98 { /* OCBI @Rn */
15.99 uint32_t Rn = ((ir>>8)&0xF);
15.100 + COUNT_INST(I_OCBI);
15.101 }
15.102 break;
15.103 case 0xA:
15.104 { /* OCBP @Rn */
15.105 uint32_t Rn = ((ir>>8)&0xF);
15.106 + COUNT_INST(I_OCBP);
15.107 }
15.108 break;
15.109 case 0xB:
15.110 { /* OCBWB @Rn */
15.111 uint32_t Rn = ((ir>>8)&0xF);
15.112 + COUNT_INST(I_OCBWB);
15.113 }
15.114 break;
15.115 case 0xC:
15.116 { /* MOVCA.L R0, @Rn */
15.117 uint32_t Rn = ((ir>>8)&0xF);
15.118 + COUNT_INST(I_MOVCA);
15.119 load_reg( R_EAX, Rn );
15.120 check_walign32( R_EAX );
15.121 MMU_TRANSLATE_WRITE( R_EAX );
15.122 @@ -548,6 +568,7 @@
15.123 case 0x4:
15.124 { /* MOV.B Rm, @(R0, Rn) */
15.125 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.126 + COUNT_INST(I_MOVB);
15.127 load_reg( R_EAX, 0 );
15.128 load_reg( R_ECX, Rn );
15.129 ADD_r32_r32( R_ECX, R_EAX );
15.130 @@ -560,6 +581,7 @@
15.131 case 0x5:
15.132 { /* MOV.W Rm, @(R0, Rn) */
15.133 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.134 + COUNT_INST(I_MOVW);
15.135 load_reg( R_EAX, 0 );
15.136 load_reg( R_ECX, Rn );
15.137 ADD_r32_r32( R_ECX, R_EAX );
15.138 @@ -573,6 +595,7 @@
15.139 case 0x6:
15.140 { /* MOV.L Rm, @(R0, Rn) */
15.141 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.142 + COUNT_INST(I_MOVL);
15.143 load_reg( R_EAX, 0 );
15.144 load_reg( R_ECX, Rn );
15.145 ADD_r32_r32( R_ECX, R_EAX );
15.146 @@ -586,6 +609,7 @@
15.147 case 0x7:
15.148 { /* MUL.L Rm, Rn */
15.149 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.150 + COUNT_INST(I_MULL);
15.151 load_reg( R_EAX, Rm );
15.152 load_reg( R_ECX, Rn );
15.153 MUL_r32( R_ECX );
15.154 @@ -597,6 +621,7 @@
15.155 switch( (ir&0xFF0) >> 4 ) {
15.156 case 0x0:
15.157 { /* CLRT */
15.158 + COUNT_INST(I_CLRT);
15.159 CLC();
15.160 SETC_t();
15.161 sh4_x86.tstate = TSTATE_C;
15.162 @@ -604,6 +629,7 @@
15.163 break;
15.164 case 0x1:
15.165 { /* SETT */
15.166 + COUNT_INST(I_SETT);
15.167 STC();
15.168 SETC_t();
15.169 sh4_x86.tstate = TSTATE_C;
15.170 @@ -611,6 +637,7 @@
15.171 break;
15.172 case 0x2:
15.173 { /* CLRMAC */
15.174 + COUNT_INST(I_CLRMAC);
15.175 XOR_r32_r32(R_EAX, R_EAX);
15.176 store_spreg( R_EAX, R_MACL );
15.177 store_spreg( R_EAX, R_MACH );
15.178 @@ -619,11 +646,13 @@
15.179 break;
15.180 case 0x3:
15.181 { /* LDTLB */
15.182 + COUNT_INST(I_LDTLB);
15.183 call_func0( MMU_ldtlb );
15.184 }
15.185 break;
15.186 case 0x4:
15.187 { /* CLRS */
15.188 + COUNT_INST(I_CLRS);
15.189 CLC();
15.190 SETC_sh4r(R_S);
15.191 sh4_x86.tstate = TSTATE_C;
15.192 @@ -631,6 +660,7 @@
15.193 break;
15.194 case 0x5:
15.195 { /* SETS */
15.196 + COUNT_INST(I_SETS);
15.197 STC();
15.198 SETC_sh4r(R_S);
15.199 sh4_x86.tstate = TSTATE_C;
15.200 @@ -645,11 +675,13 @@
15.201 switch( (ir&0xF0) >> 4 ) {
15.202 case 0x0:
15.203 { /* NOP */
15.204 + COUNT_INST(I_NOP);
15.205 /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
15.206 }
15.207 break;
15.208 case 0x1:
15.209 { /* DIV0U */
15.210 + COUNT_INST(I_DIV0U);
15.211 XOR_r32_r32( R_EAX, R_EAX );
15.212 store_spreg( R_EAX, R_Q );
15.213 store_spreg( R_EAX, R_M );
15.214 @@ -660,6 +692,7 @@
15.215 case 0x2:
15.216 { /* MOVT Rn */
15.217 uint32_t Rn = ((ir>>8)&0xF);
15.218 + COUNT_INST(I_MOVT);
15.219 load_spreg( R_EAX, R_T );
15.220 store_reg( R_EAX, Rn );
15.221 }
15.222 @@ -674,6 +707,7 @@
15.223 case 0x0:
15.224 { /* STS MACH, Rn */
15.225 uint32_t Rn = ((ir>>8)&0xF);
15.226 + COUNT_INST(I_STS);
15.227 load_spreg( R_EAX, R_MACH );
15.228 store_reg( R_EAX, Rn );
15.229 }
15.230 @@ -681,6 +715,7 @@
15.231 case 0x1:
15.232 { /* STS MACL, Rn */
15.233 uint32_t Rn = ((ir>>8)&0xF);
15.234 + COUNT_INST(I_STS);
15.235 load_spreg( R_EAX, R_MACL );
15.236 store_reg( R_EAX, Rn );
15.237 }
15.238 @@ -688,6 +723,7 @@
15.239 case 0x2:
15.240 { /* STS PR, Rn */
15.241 uint32_t Rn = ((ir>>8)&0xF);
15.242 + COUNT_INST(I_STS);
15.243 load_spreg( R_EAX, R_PR );
15.244 store_reg( R_EAX, Rn );
15.245 }
15.246 @@ -695,6 +731,7 @@
15.247 case 0x3:
15.248 { /* STC SGR, Rn */
15.249 uint32_t Rn = ((ir>>8)&0xF);
15.250 + COUNT_INST(I_STC);
15.251 check_priv();
15.252 load_spreg( R_EAX, R_SGR );
15.253 store_reg( R_EAX, Rn );
15.254 @@ -704,6 +741,7 @@
15.255 case 0x5:
15.256 { /* STS FPUL, Rn */
15.257 uint32_t Rn = ((ir>>8)&0xF);
15.258 + COUNT_INST(I_STS);
15.259 check_fpuen();
15.260 load_spreg( R_EAX, R_FPUL );
15.261 store_reg( R_EAX, Rn );
15.262 @@ -712,6 +750,7 @@
15.263 case 0x6:
15.264 { /* STS FPSCR, Rn */
15.265 uint32_t Rn = ((ir>>8)&0xF);
15.266 + COUNT_INST(I_STS);
15.267 check_fpuen();
15.268 load_spreg( R_EAX, R_FPSCR );
15.269 store_reg( R_EAX, Rn );
15.270 @@ -720,6 +759,7 @@
15.271 case 0xF:
15.272 { /* STC DBR, Rn */
15.273 uint32_t Rn = ((ir>>8)&0xF);
15.274 + COUNT_INST(I_STC);
15.275 check_priv();
15.276 load_spreg( R_EAX, R_DBR );
15.277 store_reg( R_EAX, Rn );
15.278 @@ -735,6 +775,7 @@
15.279 switch( (ir&0xFF0) >> 4 ) {
15.280 case 0x0:
15.281 { /* RTS */
15.282 + COUNT_INST(I_RTS);
15.283 if( sh4_x86.in_delay_slot ) {
15.284 SLOTILLEGAL();
15.285 } else {
15.286 @@ -755,6 +796,7 @@
15.287 break;
15.288 case 0x1:
15.289 { /* SLEEP */
15.290 + COUNT_INST(I_SLEEP);
15.291 check_priv();
15.292 call_func0( sh4_sleep );
15.293 sh4_x86.tstate = TSTATE_NONE;
15.294 @@ -764,6 +806,7 @@
15.295 break;
15.296 case 0x2:
15.297 { /* RTE */
15.298 + COUNT_INST(I_RTE);
15.299 if( sh4_x86.in_delay_slot ) {
15.300 SLOTILLEGAL();
15.301 } else {
15.302 @@ -796,6 +839,7 @@
15.303 case 0xC:
15.304 { /* MOV.B @(R0, Rm), Rn */
15.305 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.306 + COUNT_INST(I_MOVB);
15.307 load_reg( R_EAX, 0 );
15.308 load_reg( R_ECX, Rm );
15.309 ADD_r32_r32( R_ECX, R_EAX );
15.310 @@ -808,6 +852,7 @@
15.311 case 0xD:
15.312 { /* MOV.W @(R0, Rm), Rn */
15.313 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.314 + COUNT_INST(I_MOVW);
15.315 load_reg( R_EAX, 0 );
15.316 load_reg( R_ECX, Rm );
15.317 ADD_r32_r32( R_ECX, R_EAX );
15.318 @@ -821,6 +866,7 @@
15.319 case 0xE:
15.320 { /* MOV.L @(R0, Rm), Rn */
15.321 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.322 + COUNT_INST(I_MOVL);
15.323 load_reg( R_EAX, 0 );
15.324 load_reg( R_ECX, Rm );
15.325 ADD_r32_r32( R_ECX, R_EAX );
15.326 @@ -834,6 +880,7 @@
15.327 case 0xF:
15.328 { /* MAC.L @Rm+, @Rn+ */
15.329 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.330 + COUNT_INST(I_MACL);
15.331 if( Rm == Rn ) {
15.332 load_reg( R_EAX, Rm );
15.333 check_ralign32( R_EAX );
15.334 @@ -883,6 +930,7 @@
15.335 case 0x1:
15.336 { /* MOV.L Rm, @(disp, Rn) */
15.337 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;
15.338 + COUNT_INST(I_MOVL);
15.339 load_reg( R_EAX, Rn );
15.340 ADD_imm32_r32( disp, R_EAX );
15.341 check_walign32( R_EAX );
15.342 @@ -897,6 +945,7 @@
15.343 case 0x0:
15.344 { /* MOV.B Rm, @Rn */
15.345 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.346 + COUNT_INST(I_MOVB);
15.347 load_reg( R_EAX, Rn );
15.348 MMU_TRANSLATE_WRITE( R_EAX );
15.349 load_reg( R_EDX, Rm );
15.350 @@ -907,6 +956,7 @@
15.351 case 0x1:
15.352 { /* MOV.W Rm, @Rn */
15.353 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.354 + COUNT_INST(I_MOVW);
15.355 load_reg( R_EAX, Rn );
15.356 check_walign16( R_EAX );
15.357 MMU_TRANSLATE_WRITE( R_EAX )
15.358 @@ -918,6 +968,7 @@
15.359 case 0x2:
15.360 { /* MOV.L Rm, @Rn */
15.361 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.362 + COUNT_INST(I_MOVL);
15.363 load_reg( R_EAX, Rn );
15.364 check_walign32(R_EAX);
15.365 MMU_TRANSLATE_WRITE( R_EAX );
15.366 @@ -929,6 +980,7 @@
15.367 case 0x4:
15.368 { /* MOV.B Rm, @-Rn */
15.369 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.370 + COUNT_INST(I_MOVB);
15.371 load_reg( R_EAX, Rn );
15.372 ADD_imm8s_r32( -1, R_EAX );
15.373 MMU_TRANSLATE_WRITE( R_EAX );
15.374 @@ -941,6 +993,7 @@
15.375 case 0x5:
15.376 { /* MOV.W Rm, @-Rn */
15.377 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.378 + COUNT_INST(I_MOVW);
15.379 load_reg( R_EAX, Rn );
15.380 ADD_imm8s_r32( -2, R_EAX );
15.381 check_walign16( R_EAX );
15.382 @@ -954,6 +1007,7 @@
15.383 case 0x6:
15.384 { /* MOV.L Rm, @-Rn */
15.385 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.386 + COUNT_INST(I_MOVL);
15.387 load_reg( R_EAX, Rn );
15.388 ADD_imm8s_r32( -4, R_EAX );
15.389 check_walign32( R_EAX );
15.390 @@ -967,6 +1021,7 @@
15.391 case 0x7:
15.392 { /* DIV0S Rm, Rn */
15.393 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.394 + COUNT_INST(I_DIV0S);
15.395 load_reg( R_EAX, Rm );
15.396 load_reg( R_ECX, Rn );
15.397 SHR_imm8_r32( 31, R_EAX );
15.398 @@ -981,6 +1036,7 @@
15.399 case 0x8:
15.400 { /* TST Rm, Rn */
15.401 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.402 + COUNT_INST(I_TST);
15.403 load_reg( R_EAX, Rm );
15.404 load_reg( R_ECX, Rn );
15.405 TEST_r32_r32( R_EAX, R_ECX );
15.406 @@ -991,6 +1047,7 @@
15.407 case 0x9:
15.408 { /* AND Rm, Rn */
15.409 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.410 + COUNT_INST(I_AND);
15.411 load_reg( R_EAX, Rm );
15.412 load_reg( R_ECX, Rn );
15.413 AND_r32_r32( R_EAX, R_ECX );
15.414 @@ -1001,6 +1058,7 @@
15.415 case 0xA:
15.416 { /* XOR Rm, Rn */
15.417 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.418 + COUNT_INST(I_XOR);
15.419 load_reg( R_EAX, Rm );
15.420 load_reg( R_ECX, Rn );
15.421 XOR_r32_r32( R_EAX, R_ECX );
15.422 @@ -1011,6 +1069,7 @@
15.423 case 0xB:
15.424 { /* OR Rm, Rn */
15.425 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.426 + COUNT_INST(I_OR);
15.427 load_reg( R_EAX, Rm );
15.428 load_reg( R_ECX, Rn );
15.429 OR_r32_r32( R_EAX, R_ECX );
15.430 @@ -1021,6 +1080,7 @@
15.431 case 0xC:
15.432 { /* CMP/STR Rm, Rn */
15.433 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.434 + COUNT_INST(I_CMPSTR);
15.435 load_reg( R_EAX, Rm );
15.436 load_reg( R_ECX, Rn );
15.437 XOR_r32_r32( R_ECX, R_EAX );
15.438 @@ -1042,6 +1102,7 @@
15.439 case 0xD:
15.440 { /* XTRCT Rm, Rn */
15.441 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.442 + COUNT_INST(I_XTRCT);
15.443 load_reg( R_EAX, Rm );
15.444 load_reg( R_ECX, Rn );
15.445 SHL_imm8_r32( 16, R_EAX );
15.446 @@ -1054,6 +1115,7 @@
15.447 case 0xE:
15.448 { /* MULU.W Rm, Rn */
15.449 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.450 + COUNT_INST(I_MULUW);
15.451 load_reg16u( R_EAX, Rm );
15.452 load_reg16u( R_ECX, Rn );
15.453 MUL_r32( R_ECX );
15.454 @@ -1064,6 +1126,7 @@
15.455 case 0xF:
15.456 { /* MULS.W Rm, Rn */
15.457 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.458 + COUNT_INST(I_MULSW);
15.459 load_reg16s( R_EAX, Rm );
15.460 load_reg16s( R_ECX, Rn );
15.461 MUL_r32( R_ECX );
15.462 @@ -1081,6 +1144,7 @@
15.463 case 0x0:
15.464 { /* CMP/EQ Rm, Rn */
15.465 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.466 + COUNT_INST(I_CMPEQ);
15.467 load_reg( R_EAX, Rm );
15.468 load_reg( R_ECX, Rn );
15.469 CMP_r32_r32( R_EAX, R_ECX );
15.470 @@ -1091,6 +1155,7 @@
15.471 case 0x2:
15.472 { /* CMP/HS Rm, Rn */
15.473 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.474 + COUNT_INST(I_CMPHS);
15.475 load_reg( R_EAX, Rm );
15.476 load_reg( R_ECX, Rn );
15.477 CMP_r32_r32( R_EAX, R_ECX );
15.478 @@ -1101,6 +1166,7 @@
15.479 case 0x3:
15.480 { /* CMP/GE Rm, Rn */
15.481 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.482 + COUNT_INST(I_CMPGE);
15.483 load_reg( R_EAX, Rm );
15.484 load_reg( R_ECX, Rn );
15.485 CMP_r32_r32( R_EAX, R_ECX );
15.486 @@ -1111,6 +1177,7 @@
15.487 case 0x4:
15.488 { /* DIV1 Rm, Rn */
15.489 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.490 + COUNT_INST(I_DIV1);
15.491 load_spreg( R_ECX, R_M );
15.492 load_reg( R_EAX, Rn );
15.493 if( sh4_x86.tstate != TSTATE_C ) {
15.494 @@ -1139,6 +1206,7 @@
15.495 case 0x5:
15.496 { /* DMULU.L Rm, Rn */
15.497 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.498 + COUNT_INST(I_DMULU);
15.499 load_reg( R_EAX, Rm );
15.500 load_reg( R_ECX, Rn );
15.501 MUL_r32(R_ECX);
15.502 @@ -1150,6 +1218,7 @@
15.503 case 0x6:
15.504 { /* CMP/HI Rm, Rn */
15.505 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.506 + COUNT_INST(I_CMPHI);
15.507 load_reg( R_EAX, Rm );
15.508 load_reg( R_ECX, Rn );
15.509 CMP_r32_r32( R_EAX, R_ECX );
15.510 @@ -1160,6 +1229,7 @@
15.511 case 0x7:
15.512 { /* CMP/GT Rm, Rn */
15.513 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.514 + COUNT_INST(I_CMPGT);
15.515 load_reg( R_EAX, Rm );
15.516 load_reg( R_ECX, Rn );
15.517 CMP_r32_r32( R_EAX, R_ECX );
15.518 @@ -1170,6 +1240,7 @@
15.519 case 0x8:
15.520 { /* SUB Rm, Rn */
15.521 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.522 + COUNT_INST(I_SUB);
15.523 load_reg( R_EAX, Rm );
15.524 load_reg( R_ECX, Rn );
15.525 SUB_r32_r32( R_EAX, R_ECX );
15.526 @@ -1180,6 +1251,7 @@
15.527 case 0xA:
15.528 { /* SUBC Rm, Rn */
15.529 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.530 + COUNT_INST(I_SUBC);
15.531 load_reg( R_EAX, Rm );
15.532 load_reg( R_ECX, Rn );
15.533 if( sh4_x86.tstate != TSTATE_C ) {
15.534 @@ -1194,6 +1266,7 @@
15.535 case 0xB:
15.536 { /* SUBV Rm, Rn */
15.537 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.538 + COUNT_INST(I_SUBV);
15.539 load_reg( R_EAX, Rm );
15.540 load_reg( R_ECX, Rn );
15.541 SUB_r32_r32( R_EAX, R_ECX );
15.542 @@ -1205,6 +1278,7 @@
15.543 case 0xC:
15.544 { /* ADD Rm, Rn */
15.545 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.546 + COUNT_INST(I_ADD);
15.547 load_reg( R_EAX, Rm );
15.548 load_reg( R_ECX, Rn );
15.549 ADD_r32_r32( R_EAX, R_ECX );
15.550 @@ -1215,6 +1289,7 @@
15.551 case 0xD:
15.552 { /* DMULS.L Rm, Rn */
15.553 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.554 + COUNT_INST(I_DMULS);
15.555 load_reg( R_EAX, Rm );
15.556 load_reg( R_ECX, Rn );
15.557 IMUL_r32(R_ECX);
15.558 @@ -1226,6 +1301,7 @@
15.559 case 0xE:
15.560 { /* ADDC Rm, Rn */
15.561 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.562 + COUNT_INST(I_ADDC);
15.563 if( sh4_x86.tstate != TSTATE_C ) {
15.564 LDC_t();
15.565 }
15.566 @@ -1240,6 +1316,7 @@
15.567 case 0xF:
15.568 { /* ADDV Rm, Rn */
15.569 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.570 + COUNT_INST(I_ADDV);
15.571 load_reg( R_EAX, Rm );
15.572 load_reg( R_ECX, Rn );
15.573 ADD_r32_r32( R_EAX, R_ECX );
15.574 @@ -1260,6 +1337,7 @@
15.575 case 0x0:
15.576 { /* SHLL Rn */
15.577 uint32_t Rn = ((ir>>8)&0xF);
15.578 + COUNT_INST(I_SHLL);
15.579 load_reg( R_EAX, Rn );
15.580 SHL1_r32( R_EAX );
15.581 SETC_t();
15.582 @@ -1270,6 +1348,7 @@
15.583 case 0x1:
15.584 { /* DT Rn */
15.585 uint32_t Rn = ((ir>>8)&0xF);
15.586 + COUNT_INST(I_DT);
15.587 load_reg( R_EAX, Rn );
15.588 ADD_imm8s_r32( -1, R_EAX );
15.589 store_reg( R_EAX, Rn );
15.590 @@ -1280,6 +1359,7 @@
15.591 case 0x2:
15.592 { /* SHAL Rn */
15.593 uint32_t Rn = ((ir>>8)&0xF);
15.594 + COUNT_INST(I_SHAL);
15.595 load_reg( R_EAX, Rn );
15.596 SHL1_r32( R_EAX );
15.597 SETC_t();
15.598 @@ -1297,6 +1377,7 @@
15.599 case 0x0:
15.600 { /* SHLR Rn */
15.601 uint32_t Rn = ((ir>>8)&0xF);
15.602 + COUNT_INST(I_SHLR);
15.603 load_reg( R_EAX, Rn );
15.604 SHR1_r32( R_EAX );
15.605 SETC_t();
15.606 @@ -1307,6 +1388,7 @@
15.607 case 0x1:
15.608 { /* CMP/PZ Rn */
15.609 uint32_t Rn = ((ir>>8)&0xF);
15.610 + COUNT_INST(I_CMPPZ);
15.611 load_reg( R_EAX, Rn );
15.612 CMP_imm8s_r32( 0, R_EAX );
15.613 SETGE_t();
15.614 @@ -1316,6 +1398,7 @@
15.615 case 0x2:
15.616 { /* SHAR Rn */
15.617 uint32_t Rn = ((ir>>8)&0xF);
15.618 + COUNT_INST(I_SHAR);
15.619 load_reg( R_EAX, Rn );
15.620 SAR1_r32( R_EAX );
15.621 SETC_t();
15.622 @@ -1333,6 +1416,7 @@
15.623 case 0x0:
15.624 { /* STS.L MACH, @-Rn */
15.625 uint32_t Rn = ((ir>>8)&0xF);
15.626 + COUNT_INST(I_STSM);
15.627 load_reg( R_EAX, Rn );
15.628 check_walign32( R_EAX );
15.629 ADD_imm8s_r32( -4, R_EAX );
15.630 @@ -1346,6 +1430,7 @@
15.631 case 0x1:
15.632 { /* STS.L MACL, @-Rn */
15.633 uint32_t Rn = ((ir>>8)&0xF);
15.634 + COUNT_INST(I_STSM);
15.635 load_reg( R_EAX, Rn );
15.636 check_walign32( R_EAX );
15.637 ADD_imm8s_r32( -4, R_EAX );
15.638 @@ -1359,6 +1444,7 @@
15.639 case 0x2:
15.640 { /* STS.L PR, @-Rn */
15.641 uint32_t Rn = ((ir>>8)&0xF);
15.642 + COUNT_INST(I_STSM);
15.643 load_reg( R_EAX, Rn );
15.644 check_walign32( R_EAX );
15.645 ADD_imm8s_r32( -4, R_EAX );
15.646 @@ -1372,6 +1458,7 @@
15.647 case 0x3:
15.648 { /* STC.L SGR, @-Rn */
15.649 uint32_t Rn = ((ir>>8)&0xF);
15.650 + COUNT_INST(I_STCM);
15.651 check_priv();
15.652 load_reg( R_EAX, Rn );
15.653 check_walign32( R_EAX );
15.654 @@ -1386,6 +1473,7 @@
15.655 case 0x5:
15.656 { /* STS.L FPUL, @-Rn */
15.657 uint32_t Rn = ((ir>>8)&0xF);
15.658 + COUNT_INST(I_STSM);
15.659 check_fpuen();
15.660 load_reg( R_EAX, Rn );
15.661 check_walign32( R_EAX );
15.662 @@ -1400,6 +1488,7 @@
15.663 case 0x6:
15.664 { /* STS.L FPSCR, @-Rn */
15.665 uint32_t Rn = ((ir>>8)&0xF);
15.666 + COUNT_INST(I_STSM);
15.667 check_fpuen();
15.668 load_reg( R_EAX, Rn );
15.669 check_walign32( R_EAX );
15.670 @@ -1414,6 +1503,7 @@
15.671 case 0xF:
15.672 { /* STC.L DBR, @-Rn */
15.673 uint32_t Rn = ((ir>>8)&0xF);
15.674 + COUNT_INST(I_STCM);
15.675 check_priv();
15.676 load_reg( R_EAX, Rn );
15.677 check_walign32( R_EAX );
15.678 @@ -1437,6 +1527,7 @@
15.679 case 0x0:
15.680 { /* STC.L SR, @-Rn */
15.681 uint32_t Rn = ((ir>>8)&0xF);
15.682 + COUNT_INST(I_STCSRM);
15.683 check_priv();
15.684 load_reg( R_EAX, Rn );
15.685 check_walign32( R_EAX );
15.686 @@ -1453,6 +1544,7 @@
15.687 case 0x1:
15.688 { /* STC.L GBR, @-Rn */
15.689 uint32_t Rn = ((ir>>8)&0xF);
15.690 + COUNT_INST(I_STCM);
15.691 load_reg( R_EAX, Rn );
15.692 check_walign32( R_EAX );
15.693 ADD_imm8s_r32( -4, R_EAX );
15.694 @@ -1466,6 +1558,7 @@
15.695 case 0x2:
15.696 { /* STC.L VBR, @-Rn */
15.697 uint32_t Rn = ((ir>>8)&0xF);
15.698 + COUNT_INST(I_STCM);
15.699 check_priv();
15.700 load_reg( R_EAX, Rn );
15.701 check_walign32( R_EAX );
15.702 @@ -1480,6 +1573,7 @@
15.703 case 0x3:
15.704 { /* STC.L SSR, @-Rn */
15.705 uint32_t Rn = ((ir>>8)&0xF);
15.706 + COUNT_INST(I_STCM);
15.707 check_priv();
15.708 load_reg( R_EAX, Rn );
15.709 check_walign32( R_EAX );
15.710 @@ -1494,6 +1588,7 @@
15.711 case 0x4:
15.712 { /* STC.L SPC, @-Rn */
15.713 uint32_t Rn = ((ir>>8)&0xF);
15.714 + COUNT_INST(I_STCM);
15.715 check_priv();
15.716 load_reg( R_EAX, Rn );
15.717 check_walign32( R_EAX );
15.718 @@ -1513,6 +1608,7 @@
15.719 case 0x1:
15.720 { /* STC.L Rm_BANK, @-Rn */
15.721 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);
15.722 + COUNT_INST(I_STCM);
15.723 check_priv();
15.724 load_reg( R_EAX, Rn );
15.725 check_walign32( R_EAX );
15.726 @@ -1531,6 +1627,7 @@
15.727 case 0x0:
15.728 { /* ROTL Rn */
15.729 uint32_t Rn = ((ir>>8)&0xF);
15.730 + COUNT_INST(I_ROTL);
15.731 load_reg( R_EAX, Rn );
15.732 ROL1_r32( R_EAX );
15.733 store_reg( R_EAX, Rn );
15.734 @@ -1541,6 +1638,7 @@
15.735 case 0x2:
15.736 { /* ROTCL Rn */
15.737 uint32_t Rn = ((ir>>8)&0xF);
15.738 + COUNT_INST(I_ROTCL);
15.739 load_reg( R_EAX, Rn );
15.740 if( sh4_x86.tstate != TSTATE_C ) {
15.741 LDC_t();
15.742 @@ -1561,6 +1659,7 @@
15.743 case 0x0:
15.744 { /* ROTR Rn */
15.745 uint32_t Rn = ((ir>>8)&0xF);
15.746 + COUNT_INST(I_ROTR);
15.747 load_reg( R_EAX, Rn );
15.748 ROR1_r32( R_EAX );
15.749 store_reg( R_EAX, Rn );
15.750 @@ -1571,6 +1670,7 @@
15.751 case 0x1:
15.752 { /* CMP/PL Rn */
15.753 uint32_t Rn = ((ir>>8)&0xF);
15.754 + COUNT_INST(I_CMPPL);
15.755 load_reg( R_EAX, Rn );
15.756 CMP_imm8s_r32( 0, R_EAX );
15.757 SETG_t();
15.758 @@ -1580,6 +1680,7 @@
15.759 case 0x2:
15.760 { /* ROTCR Rn */
15.761 uint32_t Rn = ((ir>>8)&0xF);
15.762 + COUNT_INST(I_ROTCR);
15.763 load_reg( R_EAX, Rn );
15.764 if( sh4_x86.tstate != TSTATE_C ) {
15.765 LDC_t();
15.766 @@ -1600,6 +1701,7 @@
15.767 case 0x0:
15.768 { /* LDS.L @Rm+, MACH */
15.769 uint32_t Rm = ((ir>>8)&0xF);
15.770 + COUNT_INST(I_LDSM);
15.771 load_reg( R_EAX, Rm );
15.772 check_ralign32( R_EAX );
15.773 MMU_TRANSLATE_READ( R_EAX );
15.774 @@ -1612,6 +1714,7 @@
15.775 case 0x1:
15.776 { /* LDS.L @Rm+, MACL */
15.777 uint32_t Rm = ((ir>>8)&0xF);
15.778 + COUNT_INST(I_LDSM);
15.779 load_reg( R_EAX, Rm );
15.780 check_ralign32( R_EAX );
15.781 MMU_TRANSLATE_READ( R_EAX );
15.782 @@ -1624,6 +1727,7 @@
15.783 case 0x2:
15.784 { /* LDS.L @Rm+, PR */
15.785 uint32_t Rm = ((ir>>8)&0xF);
15.786 + COUNT_INST(I_LDSM);
15.787 load_reg( R_EAX, Rm );
15.788 check_ralign32( R_EAX );
15.789 MMU_TRANSLATE_READ( R_EAX );
15.790 @@ -1636,6 +1740,7 @@
15.791 case 0x3:
15.792 { /* LDC.L @Rm+, SGR */
15.793 uint32_t Rm = ((ir>>8)&0xF);
15.794 + COUNT_INST(I_LDCM);
15.795 check_priv();
15.796 load_reg( R_EAX, Rm );
15.797 check_ralign32( R_EAX );
15.798 @@ -1649,6 +1754,7 @@
15.799 case 0x5:
15.800 { /* LDS.L @Rm+, FPUL */
15.801 uint32_t Rm = ((ir>>8)&0xF);
15.802 + COUNT_INST(I_LDSM);
15.803 check_fpuen();
15.804 load_reg( R_EAX, Rm );
15.805 check_ralign32( R_EAX );
15.806 @@ -1662,6 +1768,7 @@
15.807 case 0x6:
15.808 { /* LDS.L @Rm+, FPSCR */
15.809 uint32_t Rm = ((ir>>8)&0xF);
15.810 + COUNT_INST(I_LDS);
15.811 check_fpuen();
15.812 load_reg( R_EAX, Rm );
15.813 check_ralign32( R_EAX );
15.814 @@ -1675,6 +1782,7 @@
15.815 case 0xF:
15.816 { /* LDC.L @Rm+, DBR */
15.817 uint32_t Rm = ((ir>>8)&0xF);
15.818 + COUNT_INST(I_LDCM);
15.819 check_priv();
15.820 load_reg( R_EAX, Rm );
15.821 check_ralign32( R_EAX );
15.822 @@ -1697,6 +1805,7 @@
15.823 case 0x0:
15.824 { /* LDC.L @Rm+, SR */
15.825 uint32_t Rm = ((ir>>8)&0xF);
15.826 + COUNT_INST(I_LDCSRM);
15.827 if( sh4_x86.in_delay_slot ) {
15.828 SLOTILLEGAL();
15.829 } else {
15.830 @@ -1716,6 +1825,7 @@
15.831 case 0x1:
15.832 { /* LDC.L @Rm+, GBR */
15.833 uint32_t Rm = ((ir>>8)&0xF);
15.834 + COUNT_INST(I_LDCM);
15.835 load_reg( R_EAX, Rm );
15.836 check_ralign32( R_EAX );
15.837 MMU_TRANSLATE_READ( R_EAX );
15.838 @@ -1728,6 +1838,7 @@
15.839 case 0x2:
15.840 { /* LDC.L @Rm+, VBR */
15.841 uint32_t Rm = ((ir>>8)&0xF);
15.842 + COUNT_INST(I_LDCM);
15.843 check_priv();
15.844 load_reg( R_EAX, Rm );
15.845 check_ralign32( R_EAX );
15.846 @@ -1741,6 +1852,7 @@
15.847 case 0x3:
15.848 { /* LDC.L @Rm+, SSR */
15.849 uint32_t Rm = ((ir>>8)&0xF);
15.850 + COUNT_INST(I_LDCM);
15.851 check_priv();
15.852 load_reg( R_EAX, Rm );
15.853 check_ralign32( R_EAX );
15.854 @@ -1754,6 +1866,7 @@
15.855 case 0x4:
15.856 { /* LDC.L @Rm+, SPC */
15.857 uint32_t Rm = ((ir>>8)&0xF);
15.858 + COUNT_INST(I_LDCM);
15.859 check_priv();
15.860 load_reg( R_EAX, Rm );
15.861 check_ralign32( R_EAX );
15.862 @@ -1772,6 +1885,7 @@
15.863 case 0x1:
15.864 { /* LDC.L @Rm+, Rn_BANK */
15.865 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);
15.866 + COUNT_INST(I_LDCM);
15.867 check_priv();
15.868 load_reg( R_EAX, Rm );
15.869 check_ralign32( R_EAX );
15.870 @@ -1789,6 +1903,7 @@
15.871 case 0x0:
15.872 { /* SHLL2 Rn */
15.873 uint32_t Rn = ((ir>>8)&0xF);
15.874 + COUNT_INST(I_SHLL);
15.875 load_reg( R_EAX, Rn );
15.876 SHL_imm8_r32( 2, R_EAX );
15.877 store_reg( R_EAX, Rn );
15.878 @@ -1798,6 +1913,7 @@
15.879 case 0x1:
15.880 { /* SHLL8 Rn */
15.881 uint32_t Rn = ((ir>>8)&0xF);
15.882 + COUNT_INST(I_SHLL);
15.883 load_reg( R_EAX, Rn );
15.884 SHL_imm8_r32( 8, R_EAX );
15.885 store_reg( R_EAX, Rn );
15.886 @@ -1807,6 +1923,7 @@
15.887 case 0x2:
15.888 { /* SHLL16 Rn */
15.889 uint32_t Rn = ((ir>>8)&0xF);
15.890 + COUNT_INST(I_SHLL);
15.891 load_reg( R_EAX, Rn );
15.892 SHL_imm8_r32( 16, R_EAX );
15.893 store_reg( R_EAX, Rn );
15.894 @@ -1823,6 +1940,7 @@
15.895 case 0x0:
15.896 { /* SHLR2 Rn */
15.897 uint32_t Rn = ((ir>>8)&0xF);
15.898 + COUNT_INST(I_SHLR);
15.899 load_reg( R_EAX, Rn );
15.900 SHR_imm8_r32( 2, R_EAX );
15.901 store_reg( R_EAX, Rn );
15.902 @@ -1832,6 +1950,7 @@
15.903 case 0x1:
15.904 { /* SHLR8 Rn */
15.905 uint32_t Rn = ((ir>>8)&0xF);
15.906 + COUNT_INST(I_SHLR);
15.907 load_reg( R_EAX, Rn );
15.908 SHR_imm8_r32( 8, R_EAX );
15.909 store_reg( R_EAX, Rn );
15.910 @@ -1841,6 +1960,7 @@
15.911 case 0x2:
15.912 { /* SHLR16 Rn */
15.913 uint32_t Rn = ((ir>>8)&0xF);
15.914 + COUNT_INST(I_SHLR);
15.915 load_reg( R_EAX, Rn );
15.916 SHR_imm8_r32( 16, R_EAX );
15.917 store_reg( R_EAX, Rn );
15.918 @@ -1857,6 +1977,7 @@
15.919 case 0x0:
15.920 { /* LDS Rm, MACH */
15.921 uint32_t Rm = ((ir>>8)&0xF);
15.922 + COUNT_INST(I_LDS);
15.923 load_reg( R_EAX, Rm );
15.924 store_spreg( R_EAX, R_MACH );
15.925 }
15.926 @@ -1864,6 +1985,7 @@
15.927 case 0x1:
15.928 { /* LDS Rm, MACL */
15.929 uint32_t Rm = ((ir>>8)&0xF);
15.930 + COUNT_INST(I_LDS);
15.931 load_reg( R_EAX, Rm );
15.932 store_spreg( R_EAX, R_MACL );
15.933 }
15.934 @@ -1871,6 +1993,7 @@
15.935 case 0x2:
15.936 { /* LDS Rm, PR */
15.937 uint32_t Rm = ((ir>>8)&0xF);
15.938 + COUNT_INST(I_LDS);
15.939 load_reg( R_EAX, Rm );
15.940 store_spreg( R_EAX, R_PR );
15.941 }
15.942 @@ -1878,6 +2001,7 @@
15.943 case 0x3:
15.944 { /* LDC Rm, SGR */
15.945 uint32_t Rm = ((ir>>8)&0xF);
15.946 + COUNT_INST(I_LDC);
15.947 check_priv();
15.948 load_reg( R_EAX, Rm );
15.949 store_spreg( R_EAX, R_SGR );
15.950 @@ -1887,6 +2011,7 @@
15.951 case 0x5:
15.952 { /* LDS Rm, FPUL */
15.953 uint32_t Rm = ((ir>>8)&0xF);
15.954 + COUNT_INST(I_LDS);
15.955 check_fpuen();
15.956 load_reg( R_EAX, Rm );
15.957 store_spreg( R_EAX, R_FPUL );
15.958 @@ -1895,6 +2020,7 @@
15.959 case 0x6:
15.960 { /* LDS Rm, FPSCR */
15.961 uint32_t Rm = ((ir>>8)&0xF);
15.962 + COUNT_INST(I_LDS);
15.963 check_fpuen();
15.964 load_reg( R_EAX, Rm );
15.965 call_func1( sh4_write_fpscr, R_EAX );
15.966 @@ -1904,6 +2030,7 @@
15.967 case 0xF:
15.968 { /* LDC Rm, DBR */
15.969 uint32_t Rm = ((ir>>8)&0xF);
15.970 + COUNT_INST(I_LDC);
15.971 check_priv();
15.972 load_reg( R_EAX, Rm );
15.973 store_spreg( R_EAX, R_DBR );
15.974 @@ -1920,6 +2047,7 @@
15.975 case 0x0:
15.976 { /* JSR @Rn */
15.977 uint32_t Rn = ((ir>>8)&0xF);
15.978 + COUNT_INST(I_JSR);
15.979 if( sh4_x86.in_delay_slot ) {
15.980 SLOTILLEGAL();
15.981 } else {
15.982 @@ -1945,6 +2073,7 @@
15.983 case 0x1:
15.984 { /* TAS.B @Rn */
15.985 uint32_t Rn = ((ir>>8)&0xF);
15.986 + COUNT_INST(I_TASB);
15.987 load_reg( R_EAX, Rn );
15.988 MMU_TRANSLATE_WRITE( R_EAX );
15.989 PUSH_realigned_r32( R_EAX );
15.990 @@ -1960,6 +2089,7 @@
15.991 case 0x2:
15.992 { /* JMP @Rn */
15.993 uint32_t Rn = ((ir>>8)&0xF);
15.994 + COUNT_INST(I_JMP);
15.995 if( sh4_x86.in_delay_slot ) {
15.996 SLOTILLEGAL();
15.997 } else {
15.998 @@ -1986,6 +2116,7 @@
15.999 case 0xC:
15.1000 { /* SHAD Rm, Rn */
15.1001 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.1002 + COUNT_INST(I_SHAD);
15.1003 /* Annoyingly enough, not directly convertible */
15.1004 load_reg( R_EAX, Rn );
15.1005 load_reg( R_ECX, Rm );
15.1006 @@ -2014,6 +2145,7 @@
15.1007 case 0xD:
15.1008 { /* SHLD Rm, Rn */
15.1009 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.1010 + COUNT_INST(I_SHLD);
15.1011 load_reg( R_EAX, Rn );
15.1012 load_reg( R_ECX, Rm );
15.1013 CMP_imm32_r32( 0, R_ECX );
15.1014 @@ -2045,6 +2177,7 @@
15.1015 case 0x0:
15.1016 { /* LDC Rm, SR */
15.1017 uint32_t Rm = ((ir>>8)&0xF);
15.1018 + COUNT_INST(I_LDCSR);
15.1019 if( sh4_x86.in_delay_slot ) {
15.1020 SLOTILLEGAL();
15.1021 } else {
15.1022 @@ -2060,6 +2193,7 @@
15.1023 case 0x1:
15.1024 { /* LDC Rm, GBR */
15.1025 uint32_t Rm = ((ir>>8)&0xF);
15.1026 + COUNT_INST(I_LDC);
15.1027 load_reg( R_EAX, Rm );
15.1028 store_spreg( R_EAX, R_GBR );
15.1029 }
15.1030 @@ -2067,6 +2201,7 @@
15.1031 case 0x2:
15.1032 { /* LDC Rm, VBR */
15.1033 uint32_t Rm = ((ir>>8)&0xF);
15.1034 + COUNT_INST(I_LDC);
15.1035 check_priv();
15.1036 load_reg( R_EAX, Rm );
15.1037 store_spreg( R_EAX, R_VBR );
15.1038 @@ -2076,6 +2211,7 @@
15.1039 case 0x3:
15.1040 { /* LDC Rm, SSR */
15.1041 uint32_t Rm = ((ir>>8)&0xF);
15.1042 + COUNT_INST(I_LDC);
15.1043 check_priv();
15.1044 load_reg( R_EAX, Rm );
15.1045 store_spreg( R_EAX, R_SSR );
15.1046 @@ -2085,6 +2221,7 @@
15.1047 case 0x4:
15.1048 { /* LDC Rm, SPC */
15.1049 uint32_t Rm = ((ir>>8)&0xF);
15.1050 + COUNT_INST(I_LDC);
15.1051 check_priv();
15.1052 load_reg( R_EAX, Rm );
15.1053 store_spreg( R_EAX, R_SPC );
15.1054 @@ -2099,6 +2236,7 @@
15.1055 case 0x1:
15.1056 { /* LDC Rm, Rn_BANK */
15.1057 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);
15.1058 + COUNT_INST(I_LDC);
15.1059 check_priv();
15.1060 load_reg( R_EAX, Rm );
15.1061 store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
15.1062 @@ -2110,6 +2248,7 @@
15.1063 case 0xF:
15.1064 { /* MAC.W @Rm+, @Rn+ */
15.1065 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.1066 + COUNT_INST(I_MACW);
15.1067 if( Rm == Rn ) {
15.1068 load_reg( R_EAX, Rm );
15.1069 check_ralign16( R_EAX );
15.1070 @@ -2172,6 +2311,7 @@
15.1071 case 0x5:
15.1072 { /* MOV.L @(disp, Rm), Rn */
15.1073 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;
15.1074 + COUNT_INST(I_MOVL);
15.1075 load_reg( R_EAX, Rm );
15.1076 ADD_imm8s_r32( disp, R_EAX );
15.1077 check_ralign32( R_EAX );
15.1078 @@ -2186,6 +2326,7 @@
15.1079 case 0x0:
15.1080 { /* MOV.B @Rm, Rn */
15.1081 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.1082 + COUNT_INST(I_MOVB);
15.1083 load_reg( R_EAX, Rm );
15.1084 MMU_TRANSLATE_READ( R_EAX );
15.1085 MEM_READ_BYTE( R_EAX, R_EAX );
15.1086 @@ -2196,6 +2337,7 @@
15.1087 case 0x1:
15.1088 { /* MOV.W @Rm, Rn */
15.1089 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.1090 + COUNT_INST(I_MOVW);
15.1091 load_reg( R_EAX, Rm );
15.1092 check_ralign16( R_EAX );
15.1093 MMU_TRANSLATE_READ( R_EAX );
15.1094 @@ -2207,6 +2349,7 @@
15.1095 case 0x2:
15.1096 { /* MOV.L @Rm, Rn */
15.1097 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.1098 + COUNT_INST(I_MOVL);
15.1099 load_reg( R_EAX, Rm );
15.1100 check_ralign32( R_EAX );
15.1101 MMU_TRANSLATE_READ( R_EAX );
15.1102 @@ -2218,6 +2361,7 @@
15.1103 case 0x3:
15.1104 { /* MOV Rm, Rn */
15.1105 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.1106 + COUNT_INST(I_MOV);
15.1107 load_reg( R_EAX, Rm );
15.1108 store_reg( R_EAX, Rn );
15.1109 }
15.1110 @@ -2225,6 +2369,7 @@
15.1111 case 0x4:
15.1112 { /* MOV.B @Rm+, Rn */
15.1113 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.1114 + COUNT_INST(I_MOVB);
15.1115 load_reg( R_EAX, Rm );
15.1116 MMU_TRANSLATE_READ( R_EAX );
15.1117 ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
15.1118 @@ -2236,6 +2381,7 @@
15.1119 case 0x5:
15.1120 { /* MOV.W @Rm+, Rn */
15.1121 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.1122 + COUNT_INST(I_MOVW);
15.1123 load_reg( R_EAX, Rm );
15.1124 check_ralign16( R_EAX );
15.1125 MMU_TRANSLATE_READ( R_EAX );
15.1126 @@ -2248,6 +2394,7 @@
15.1127 case 0x6:
15.1128 { /* MOV.L @Rm+, Rn */
15.1129 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.1130 + COUNT_INST(I_MOVL);
15.1131 load_reg( R_EAX, Rm );
15.1132 check_ralign32( R_EAX );
15.1133 MMU_TRANSLATE_READ( R_EAX );
15.1134 @@ -2260,6 +2407,7 @@
15.1135 case 0x7:
15.1136 { /* NOT Rm, Rn */
15.1137 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.1138 + COUNT_INST(I_NOT);
15.1139 load_reg( R_EAX, Rm );
15.1140 NOT_r32( R_EAX );
15.1141 store_reg( R_EAX, Rn );
15.1142 @@ -2269,6 +2417,7 @@
15.1143 case 0x8:
15.1144 { /* SWAP.B Rm, Rn */
15.1145 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.1146 + COUNT_INST(I_SWAPB);
15.1147 load_reg( R_EAX, Rm );
15.1148 XCHG_r8_r8( R_AL, R_AH ); // NB: does not touch EFLAGS
15.1149 store_reg( R_EAX, Rn );
15.1150 @@ -2277,6 +2426,7 @@
15.1151 case 0x9:
15.1152 { /* SWAP.W Rm, Rn */
15.1153 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.1154 + COUNT_INST(I_SWAPB);
15.1155 load_reg( R_EAX, Rm );
15.1156 MOV_r32_r32( R_EAX, R_ECX );
15.1157 SHL_imm8_r32( 16, R_ECX );
15.1158 @@ -2289,6 +2439,7 @@
15.1159 case 0xA:
15.1160 { /* NEGC Rm, Rn */
15.1161 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.1162 + COUNT_INST(I_NEGC);
15.1163 load_reg( R_EAX, Rm );
15.1164 XOR_r32_r32( R_ECX, R_ECX );
15.1165 LDC_t();
15.1166 @@ -2301,6 +2452,7 @@
15.1167 case 0xB:
15.1168 { /* NEG Rm, Rn */
15.1169 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.1170 + COUNT_INST(I_NEG);
15.1171 load_reg( R_EAX, Rm );
15.1172 NEG_r32( R_EAX );
15.1173 store_reg( R_EAX, Rn );
15.1174 @@ -2310,6 +2462,7 @@
15.1175 case 0xC:
15.1176 { /* EXTU.B Rm, Rn */
15.1177 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.1178 + COUNT_INST(I_EXTUB);
15.1179 load_reg( R_EAX, Rm );
15.1180 MOVZX_r8_r32( R_EAX, R_EAX );
15.1181 store_reg( R_EAX, Rn );
15.1182 @@ -2318,6 +2471,7 @@
15.1183 case 0xD:
15.1184 { /* EXTU.W Rm, Rn */
15.1185 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.1186 + COUNT_INST(I_EXTUW);
15.1187 load_reg( R_EAX, Rm );
15.1188 MOVZX_r16_r32( R_EAX, R_EAX );
15.1189 store_reg( R_EAX, Rn );
15.1190 @@ -2326,6 +2480,7 @@
15.1191 case 0xE:
15.1192 { /* EXTS.B Rm, Rn */
15.1193 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.1194 + COUNT_INST(I_EXTSB);
15.1195 load_reg( R_EAX, Rm );
15.1196 MOVSX_r8_r32( R_EAX, R_EAX );
15.1197 store_reg( R_EAX, Rn );
15.1198 @@ -2334,6 +2489,7 @@
15.1199 case 0xF:
15.1200 { /* EXTS.W Rm, Rn */
15.1201 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.1202 + COUNT_INST(I_EXTSW);
15.1203 load_reg( R_EAX, Rm );
15.1204 MOVSX_r16_r32( R_EAX, R_EAX );
15.1205 store_reg( R_EAX, Rn );
15.1206 @@ -2344,6 +2500,7 @@
15.1207 case 0x7:
15.1208 { /* ADD #imm, Rn */
15.1209 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);
15.1210 + COUNT_INST(I_ADDI);
15.1211 load_reg( R_EAX, Rn );
15.1212 ADD_imm8s_r32( imm, R_EAX );
15.1213 store_reg( R_EAX, Rn );
15.1214 @@ -2355,6 +2512,7 @@
15.1215 case 0x0:
15.1216 { /* MOV.B R0, @(disp, Rn) */
15.1217 uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);
15.1218 + COUNT_INST(I_MOVB);
15.1219 load_reg( R_EAX, Rn );
15.1220 ADD_imm32_r32( disp, R_EAX );
15.1221 MMU_TRANSLATE_WRITE( R_EAX );
15.1222 @@ -2366,6 +2524,7 @@
15.1223 case 0x1:
15.1224 { /* MOV.W R0, @(disp, Rn) */
15.1225 uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;
15.1226 + COUNT_INST(I_MOVW);
15.1227 load_reg( R_EAX, Rn );
15.1228 ADD_imm32_r32( disp, R_EAX );
15.1229 check_walign16( R_EAX );
15.1230 @@ -2378,6 +2537,7 @@
15.1231 case 0x4:
15.1232 { /* MOV.B @(disp, Rm), R0 */
15.1233 uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);
15.1234 + COUNT_INST(I_MOVB);
15.1235 load_reg( R_EAX, Rm );
15.1236 ADD_imm32_r32( disp, R_EAX );
15.1237 MMU_TRANSLATE_READ( R_EAX );
15.1238 @@ -2389,6 +2549,7 @@
15.1239 case 0x5:
15.1240 { /* MOV.W @(disp, Rm), R0 */
15.1241 uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;
15.1242 + COUNT_INST(I_MOVW);
15.1243 load_reg( R_EAX, Rm );
15.1244 ADD_imm32_r32( disp, R_EAX );
15.1245 check_ralign16( R_EAX );
15.1246 @@ -2401,6 +2562,7 @@
15.1247 case 0x8:
15.1248 { /* CMP/EQ #imm, R0 */
15.1249 int32_t imm = SIGNEXT8(ir&0xFF);
15.1250 + COUNT_INST(I_CMPEQI);
15.1251 load_reg( R_EAX, 0 );
15.1252 CMP_imm8s_r32(imm, R_EAX);
15.1253 SETE_t();
15.1254 @@ -2410,6 +2572,7 @@
15.1255 case 0x9:
15.1256 { /* BT disp */
15.1257 int32_t disp = SIGNEXT8(ir&0xFF)<<1;
15.1258 + COUNT_INST(I_BT);
15.1259 if( sh4_x86.in_delay_slot ) {
15.1260 SLOTILLEGAL();
15.1261 } else {
15.1262 @@ -2424,6 +2587,7 @@
15.1263 case 0xB:
15.1264 { /* BF disp */
15.1265 int32_t disp = SIGNEXT8(ir&0xFF)<<1;
15.1266 + COUNT_INST(I_BF);
15.1267 if( sh4_x86.in_delay_slot ) {
15.1268 SLOTILLEGAL();
15.1269 } else {
15.1270 @@ -2438,6 +2602,7 @@
15.1271 case 0xD:
15.1272 { /* BT/S disp */
15.1273 int32_t disp = SIGNEXT8(ir&0xFF)<<1;
15.1274 + COUNT_INST(I_BTS);
15.1275 if( sh4_x86.in_delay_slot ) {
15.1276 SLOTILLEGAL();
15.1277 } else {
15.1278 @@ -2471,6 +2636,7 @@
15.1279 case 0xF:
15.1280 { /* BF/S disp */
15.1281 int32_t disp = SIGNEXT8(ir&0xFF)<<1;
15.1282 + COUNT_INST(I_BFS);
15.1283 if( sh4_x86.in_delay_slot ) {
15.1284 SLOTILLEGAL();
15.1285 } else {
15.1286 @@ -2511,6 +2677,7 @@
15.1287 case 0x9:
15.1288 { /* MOV.W @(disp, PC), Rn */
15.1289 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1;
15.1290 + COUNT_INST(I_MOVW);
15.1291 if( sh4_x86.in_delay_slot ) {
15.1292 SLOTILLEGAL();
15.1293 } else {
15.1294 @@ -2534,6 +2701,7 @@
15.1295 case 0xA:
15.1296 { /* BRA disp */
15.1297 int32_t disp = SIGNEXT12(ir&0xFFF)<<1;
15.1298 + COUNT_INST(I_BRA);
15.1299 if( sh4_x86.in_delay_slot ) {
15.1300 SLOTILLEGAL();
15.1301 } else {
15.1302 @@ -2556,6 +2724,7 @@
15.1303 case 0xB:
15.1304 { /* BSR disp */
15.1305 int32_t disp = SIGNEXT12(ir&0xFFF)<<1;
15.1306 + COUNT_INST(I_BSR);
15.1307 if( sh4_x86.in_delay_slot ) {
15.1308 SLOTILLEGAL();
15.1309 } else {
15.1310 @@ -2583,6 +2752,7 @@
15.1311 case 0x0:
15.1312 { /* MOV.B R0, @(disp, GBR) */
15.1313 uint32_t disp = (ir&0xFF);
15.1314 + COUNT_INST(I_MOVB);
15.1315 load_spreg( R_EAX, R_GBR );
15.1316 ADD_imm32_r32( disp, R_EAX );
15.1317 MMU_TRANSLATE_WRITE( R_EAX );
15.1318 @@ -2594,6 +2764,7 @@
15.1319 case 0x1:
15.1320 { /* MOV.W R0, @(disp, GBR) */
15.1321 uint32_t disp = (ir&0xFF)<<1;
15.1322 + COUNT_INST(I_MOVW);
15.1323 load_spreg( R_EAX, R_GBR );
15.1324 ADD_imm32_r32( disp, R_EAX );
15.1325 check_walign16( R_EAX );
15.1326 @@ -2606,6 +2777,7 @@
15.1327 case 0x2:
15.1328 { /* MOV.L R0, @(disp, GBR) */
15.1329 uint32_t disp = (ir&0xFF)<<2;
15.1330 + COUNT_INST(I_MOVL);
15.1331 load_spreg( R_EAX, R_GBR );
15.1332 ADD_imm32_r32( disp, R_EAX );
15.1333 check_walign32( R_EAX );
15.1334 @@ -2618,6 +2790,7 @@
15.1335 case 0x3:
15.1336 { /* TRAPA #imm */
15.1337 uint32_t imm = (ir&0xFF);
15.1338 + COUNT_INST(I_TRAPA);
15.1339 if( sh4_x86.in_delay_slot ) {
15.1340 SLOTILLEGAL();
15.1341 } else {
15.1342 @@ -2635,6 +2808,7 @@
15.1343 case 0x4:
15.1344 { /* MOV.B @(disp, GBR), R0 */
15.1345 uint32_t disp = (ir&0xFF);
15.1346 + COUNT_INST(I_MOVB);
15.1347 load_spreg( R_EAX, R_GBR );
15.1348 ADD_imm32_r32( disp, R_EAX );
15.1349 MMU_TRANSLATE_READ( R_EAX );
15.1350 @@ -2646,6 +2820,7 @@
15.1351 case 0x5:
15.1352 { /* MOV.W @(disp, GBR), R0 */
15.1353 uint32_t disp = (ir&0xFF)<<1;
15.1354 + COUNT_INST(I_MOVW);
15.1355 load_spreg( R_EAX, R_GBR );
15.1356 ADD_imm32_r32( disp, R_EAX );
15.1357 check_ralign16( R_EAX );
15.1358 @@ -2658,6 +2833,7 @@
15.1359 case 0x6:
15.1360 { /* MOV.L @(disp, GBR), R0 */
15.1361 uint32_t disp = (ir&0xFF)<<2;
15.1362 + COUNT_INST(I_MOVL);
15.1363 load_spreg( R_EAX, R_GBR );
15.1364 ADD_imm32_r32( disp, R_EAX );
15.1365 check_ralign32( R_EAX );
15.1366 @@ -2670,6 +2846,7 @@
15.1367 case 0x7:
15.1368 { /* MOVA @(disp, PC), R0 */
15.1369 uint32_t disp = (ir&0xFF)<<2;
15.1370 + COUNT_INST(I_MOVA);
15.1371 if( sh4_x86.in_delay_slot ) {
15.1372 SLOTILLEGAL();
15.1373 } else {
15.1374 @@ -2683,6 +2860,7 @@
15.1375 case 0x8:
15.1376 { /* TST #imm, R0 */
15.1377 uint32_t imm = (ir&0xFF);
15.1378 + COUNT_INST(I_TSTI);
15.1379 load_reg( R_EAX, 0 );
15.1380 TEST_imm32_r32( imm, R_EAX );
15.1381 SETE_t();
15.1382 @@ -2692,6 +2870,7 @@
15.1383 case 0x9:
15.1384 { /* AND #imm, R0 */
15.1385 uint32_t imm = (ir&0xFF);
15.1386 + COUNT_INST(I_ANDI);
15.1387 load_reg( R_EAX, 0 );
15.1388 AND_imm32_r32(imm, R_EAX);
15.1389 store_reg( R_EAX, 0 );
15.1390 @@ -2701,6 +2880,7 @@
15.1391 case 0xA:
15.1392 { /* XOR #imm, R0 */
15.1393 uint32_t imm = (ir&0xFF);
15.1394 + COUNT_INST(I_XORI);
15.1395 load_reg( R_EAX, 0 );
15.1396 XOR_imm32_r32( imm, R_EAX );
15.1397 store_reg( R_EAX, 0 );
15.1398 @@ -2710,6 +2890,7 @@
15.1399 case 0xB:
15.1400 { /* OR #imm, R0 */
15.1401 uint32_t imm = (ir&0xFF);
15.1402 + COUNT_INST(I_ORI);
15.1403 load_reg( R_EAX, 0 );
15.1404 OR_imm32_r32(imm, R_EAX);
15.1405 store_reg( R_EAX, 0 );
15.1406 @@ -2719,6 +2900,7 @@
15.1407 case 0xC:
15.1408 { /* TST.B #imm, @(R0, GBR) */
15.1409 uint32_t imm = (ir&0xFF);
15.1410 + COUNT_INST(I_TSTB);
15.1411 load_reg( R_EAX, 0);
15.1412 load_reg( R_ECX, R_GBR);
15.1413 ADD_r32_r32( R_ECX, R_EAX );
15.1414 @@ -2732,6 +2914,7 @@
15.1415 case 0xD:
15.1416 { /* AND.B #imm, @(R0, GBR) */
15.1417 uint32_t imm = (ir&0xFF);
15.1418 + COUNT_INST(I_ANDB);
15.1419 load_reg( R_EAX, 0 );
15.1420 load_spreg( R_ECX, R_GBR );
15.1421 ADD_r32_r32( R_ECX, R_EAX );
15.1422 @@ -2747,6 +2930,7 @@
15.1423 case 0xE:
15.1424 { /* XOR.B #imm, @(R0, GBR) */
15.1425 uint32_t imm = (ir&0xFF);
15.1426 + COUNT_INST(I_XORB);
15.1427 load_reg( R_EAX, 0 );
15.1428 load_spreg( R_ECX, R_GBR );
15.1429 ADD_r32_r32( R_ECX, R_EAX );
15.1430 @@ -2762,6 +2946,7 @@
15.1431 case 0xF:
15.1432 { /* OR.B #imm, @(R0, GBR) */
15.1433 uint32_t imm = (ir&0xFF);
15.1434 + COUNT_INST(I_ORB);
15.1435 load_reg( R_EAX, 0 );
15.1436 load_spreg( R_ECX, R_GBR );
15.1437 ADD_r32_r32( R_ECX, R_EAX );
15.1438 @@ -2779,6 +2964,7 @@
15.1439 case 0xD:
15.1440 { /* MOV.L @(disp, PC), Rn */
15.1441 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2;
15.1442 + COUNT_INST(I_MOVLPC);
15.1443 if( sh4_x86.in_delay_slot ) {
15.1444 SLOTILLEGAL();
15.1445 } else {
15.1446 @@ -2812,6 +2998,7 @@
15.1447 case 0xE:
15.1448 { /* MOV #imm, Rn */
15.1449 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);
15.1450 + COUNT_INST(I_MOVI);
15.1451 load_imm32( R_EAX, imm );
15.1452 store_reg( R_EAX, Rn );
15.1453 }
15.1454 @@ -2821,6 +3008,7 @@
15.1455 case 0x0:
15.1456 { /* FADD FRm, FRn */
15.1457 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
15.1458 + COUNT_INST(I_FADD);
15.1459 check_fpuen();
15.1460 load_spreg( R_ECX, R_FPSCR );
15.1461 TEST_imm32_r32( FPSCR_PR, R_ECX );
15.1462 @@ -2842,6 +3030,7 @@
15.1463 case 0x1:
15.1464 { /* FSUB FRm, FRn */
15.1465 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
15.1466 + COUNT_INST(I_FSUB);
15.1467 check_fpuen();
15.1468 load_spreg( R_ECX, R_FPSCR );
15.1469 TEST_imm32_r32( FPSCR_PR, R_ECX );
15.1470 @@ -2863,6 +3052,7 @@
15.1471 case 0x2:
15.1472 { /* FMUL FRm, FRn */
15.1473 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
15.1474 + COUNT_INST(I_FMUL);
15.1475 check_fpuen();
15.1476 load_spreg( R_ECX, R_FPSCR );
15.1477 TEST_imm32_r32( FPSCR_PR, R_ECX );
15.1478 @@ -2884,6 +3074,7 @@
15.1479 case 0x3:
15.1480 { /* FDIV FRm, FRn */
15.1481 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
15.1482 + COUNT_INST(I_FDIV);
15.1483 check_fpuen();
15.1484 load_spreg( R_ECX, R_FPSCR );
15.1485 TEST_imm32_r32( FPSCR_PR, R_ECX );
15.1486 @@ -2905,6 +3096,7 @@
15.1487 case 0x4:
15.1488 { /* FCMP/EQ FRm, FRn */
15.1489 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
15.1490 + COUNT_INST(I_FCMPEQ);
15.1491 check_fpuen();
15.1492 load_spreg( R_ECX, R_FPSCR );
15.1493 TEST_imm32_r32( FPSCR_PR, R_ECX );
15.1494 @@ -2925,6 +3117,7 @@
15.1495 case 0x5:
15.1496 { /* FCMP/GT FRm, FRn */
15.1497 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
15.1498 + COUNT_INST(I_FCMPGT);
15.1499 check_fpuen();
15.1500 load_spreg( R_ECX, R_FPSCR );
15.1501 TEST_imm32_r32( FPSCR_PR, R_ECX );
15.1502 @@ -2945,6 +3138,7 @@
15.1503 case 0x6:
15.1504 { /* FMOV @(R0, Rm), FRn */
15.1505 uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.1506 + COUNT_INST(I_FMOV7);
15.1507 check_fpuen();
15.1508 load_reg( R_EAX, Rm );
15.1509 ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
15.1510 @@ -2970,6 +3164,7 @@
15.1511 case 0x7:
15.1512 { /* FMOV FRm, @(R0, Rn) */
15.1513 uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
15.1514 + COUNT_INST(I_FMOV4);
15.1515 check_fpuen();
15.1516 load_reg( R_EAX, Rn );
15.1517 ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
15.1518 @@ -2995,6 +3190,7 @@
15.1519 case 0x8:
15.1520 { /* FMOV @Rm, FRn */
15.1521 uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.1522 + COUNT_INST(I_FMOV5);
15.1523 check_fpuen();
15.1524 load_reg( R_EAX, Rm );
15.1525 check_ralign32( R_EAX );
15.1526 @@ -3018,6 +3214,7 @@
15.1527 case 0x9:
15.1528 { /* FMOV @Rm+, FRn */
15.1529 uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
15.1530 + COUNT_INST(I_FMOV6);
15.1531 check_fpuen();
15.1532 load_reg( R_EAX, Rm );
15.1533 check_ralign32( R_EAX );
15.1534 @@ -3044,6 +3241,7 @@
15.1535 case 0xA:
15.1536 { /* FMOV FRm, @Rn */
15.1537 uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
15.1538 + COUNT_INST(I_FMOV2);
15.1539 check_fpuen();
15.1540 load_reg( R_EAX, Rn );
15.1541 check_walign32( R_EAX );
15.1542 @@ -3067,6 +3265,7 @@
15.1543 case 0xB:
15.1544 { /* FMOV FRm, @-Rn */
15.1545 uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
15.1546 + COUNT_INST(I_FMOV3);
15.1547 check_fpuen();
15.1548 load_reg( R_EAX, Rn );
15.1549 check_walign32( R_EAX );
15.1550 @@ -3096,6 +3295,7 @@
15.1551 case 0xC:
15.1552 { /* FMOV FRm, FRn */
15.1553 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
15.1554 + COUNT_INST(I_FMOV1);
15.1555 /* As horrible as this looks, it's actually covering 5 separate cases:
15.1556 * 1. 32-bit fr-to-fr (PR=0)
15.1557 * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
15.1558 @@ -3124,6 +3324,7 @@
15.1559 case 0x0:
15.1560 { /* FSTS FPUL, FRn */
15.1561 uint32_t FRn = ((ir>>8)&0xF);
15.1562 + COUNT_INST(I_FSTS);
15.1563 check_fpuen();
15.1564 load_spreg( R_EAX, R_FPUL );
15.1565 store_fr( R_EAX, FRn );
15.1566 @@ -3133,6 +3334,7 @@
15.1567 case 0x1:
15.1568 { /* FLDS FRm, FPUL */
15.1569 uint32_t FRm = ((ir>>8)&0xF);
15.1570 + COUNT_INST(I_FLDS);
15.1571 check_fpuen();
15.1572 load_fr( R_EAX, FRm );
15.1573 store_spreg( R_EAX, R_FPUL );
15.1574 @@ -3142,6 +3344,7 @@
15.1575 case 0x2:
15.1576 { /* FLOAT FPUL, FRn */
15.1577 uint32_t FRn = ((ir>>8)&0xF);
15.1578 + COUNT_INST(I_FLOAT);
15.1579 check_fpuen();
15.1580 load_spreg( R_ECX, R_FPSCR );
15.1581 FILD_sh4r(R_FPUL);
15.1582 @@ -3158,6 +3361,7 @@
15.1583 case 0x3:
15.1584 { /* FTRC FRm, FPUL */
15.1585 uint32_t FRm = ((ir>>8)&0xF);
15.1586 + COUNT_INST(I_FTRC);
15.1587 check_fpuen();
15.1588 load_spreg( R_ECX, R_FPSCR );
15.1589 TEST_imm32_r32( FPSCR_PR, R_ECX );
15.1590 @@ -3195,6 +3399,7 @@
15.1591 case 0x4:
15.1592 { /* FNEG FRn */
15.1593 uint32_t FRn = ((ir>>8)&0xF);
15.1594 + COUNT_INST(I_FNEG);
15.1595 check_fpuen();
15.1596 load_spreg( R_ECX, R_FPSCR );
15.1597 TEST_imm32_r32( FPSCR_PR, R_ECX );
15.1598 @@ -3214,6 +3419,7 @@
15.1599 case 0x5:
15.1600 { /* FABS FRn */
15.1601 uint32_t FRn = ((ir>>8)&0xF);
15.1602 + COUNT_INST(I_FABS);
15.1603 check_fpuen();
15.1604 load_spreg( R_ECX, R_FPSCR );
15.1605 TEST_imm32_r32( FPSCR_PR, R_ECX );
15.1606 @@ -3233,6 +3439,7 @@
15.1607 case 0x6:
15.1608 { /* FSQRT FRn */
15.1609 uint32_t FRn = ((ir>>8)&0xF);
15.1610 + COUNT_INST(I_FSQRT);
15.1611 check_fpuen();
15.1612 load_spreg( R_ECX, R_FPSCR );
15.1613 TEST_imm32_r32( FPSCR_PR, R_ECX );
15.1614 @@ -3252,6 +3459,7 @@
15.1615 case 0x7:
15.1616 { /* FSRRA FRn */
15.1617 uint32_t FRn = ((ir>>8)&0xF);
15.1618 + COUNT_INST(I_FSRRA);
15.1619 check_fpuen();
15.1620 load_spreg( R_ECX, R_FPSCR );
15.1621 TEST_imm32_r32( FPSCR_PR, R_ECX );
15.1622 @@ -3269,6 +3477,7 @@
15.1623 { /* FLDI0 FRn */
15.1624 uint32_t FRn = ((ir>>8)&0xF);
15.1625 /* IFF PR=0 */
15.1626 + COUNT_INST(I_FLDI0);
15.1627 check_fpuen();
15.1628 load_spreg( R_ECX, R_FPSCR );
15.1629 TEST_imm32_r32( FPSCR_PR, R_ECX );
15.1630 @@ -3283,6 +3492,7 @@
15.1631 { /* FLDI1 FRn */
15.1632 uint32_t FRn = ((ir>>8)&0xF);
15.1633 /* IFF PR=0 */
15.1634 + COUNT_INST(I_FLDI1);
15.1635 check_fpuen();
15.1636 load_spreg( R_ECX, R_FPSCR );
15.1637 TEST_imm32_r32( FPSCR_PR, R_ECX );
15.1638 @@ -3296,6 +3506,7 @@
15.1639 case 0xA:
15.1640 { /* FCNVSD FPUL, FRn */
15.1641 uint32_t FRn = ((ir>>8)&0xF);
15.1642 + COUNT_INST(I_FCNVSD);
15.1643 check_fpuen();
15.1644 load_spreg( R_ECX, R_FPSCR );
15.1645 TEST_imm32_r32( FPSCR_PR, R_ECX );
15.1646 @@ -3309,6 +3520,7 @@
15.1647 case 0xB:
15.1648 { /* FCNVDS FRm, FPUL */
15.1649 uint32_t FRm = ((ir>>8)&0xF);
15.1650 + COUNT_INST(I_FCNVDS);
15.1651 check_fpuen();
15.1652 load_spreg( R_ECX, R_FPSCR );
15.1653 TEST_imm32_r32( FPSCR_PR, R_ECX );
15.1654 @@ -3322,6 +3534,7 @@
15.1655 case 0xE:
15.1656 { /* FIPR FVm, FVn */
15.1657 uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3);
15.1658 + COUNT_INST(I_FIPR);
15.1659 check_fpuen();
15.1660 load_spreg( R_ECX, R_FPSCR );
15.1661 TEST_imm32_r32( FPSCR_PR, R_ECX );
15.1662 @@ -3352,6 +3565,7 @@
15.1663 case 0x0:
15.1664 { /* FSCA FPUL, FRn */
15.1665 uint32_t FRn = ((ir>>9)&0x7)<<1;
15.1666 + COUNT_INST(I_FSCA);
15.1667 check_fpuen();
15.1668 load_spreg( R_ECX, R_FPSCR );
15.1669 TEST_imm32_r32( FPSCR_PR, R_ECX );
15.1670 @@ -3368,6 +3582,7 @@
15.1671 case 0x0:
15.1672 { /* FTRV XMTRX, FVn */
15.1673 uint32_t FVn = ((ir>>10)&0x3);
15.1674 + COUNT_INST(I_FTRV);
15.1675 check_fpuen();
15.1676 load_spreg( R_ECX, R_FPSCR );
15.1677 TEST_imm32_r32( FPSCR_PR, R_ECX );
15.1678 @@ -3382,6 +3597,7 @@
15.1679 switch( (ir&0xC00) >> 10 ) {
15.1680 case 0x0:
15.1681 { /* FSCHG */
15.1682 + COUNT_INST(I_FSCHG);
15.1683 check_fpuen();
15.1684 load_spreg( R_ECX, R_FPSCR );
15.1685 XOR_imm32_r32( FPSCR_SZ, R_ECX );
15.1686 @@ -3391,6 +3607,7 @@
15.1687 break;
15.1688 case 0x2:
15.1689 { /* FRCHG */
15.1690 + COUNT_INST(I_FRCHG);
15.1691 check_fpuen();
15.1692 load_spreg( R_ECX, R_FPSCR );
15.1693 XOR_imm32_r32( FPSCR_FR, R_ECX );
15.1694 @@ -3401,6 +3618,7 @@
15.1695 break;
15.1696 case 0x3:
15.1697 { /* UNDEF */
15.1698 + COUNT_INST(I_UNDEF);
15.1699 if( sh4_x86.in_delay_slot ) {
15.1700 SLOTILLEGAL();
15.1701 } else {
15.1702 @@ -3426,6 +3644,7 @@
15.1703 case 0xE:
15.1704 { /* FMAC FR0, FRm, FRn */
15.1705 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
15.1706 + COUNT_INST(I_FMAC);
15.1707 check_fpuen();
15.1708 load_spreg( R_ECX, R_FPSCR );
15.1709 TEST_imm32_r32( FPSCR_PR, R_ECX );
16.1 --- a/src/sh4/sh4x86.in Tue May 13 08:48:15 2008 +0000
16.2 +++ b/src/sh4/sh4x86.in Thu May 15 10:22:39 2008 +0000
16.3 @@ -28,6 +28,7 @@
16.4 #include "sh4/xltcache.h"
16.5 #include "sh4/sh4core.h"
16.6 #include "sh4/sh4trans.h"
16.7 +#include "sh4/sh4stat.h"
16.8 #include "sh4/sh4mmio.h"
16.9 #include "sh4/x86op.h"
16.10 #include "clock.h"
16.11 @@ -79,6 +80,12 @@
16.12 #define TSTATE_A 7
16.13 #define TSTATE_AE 3
16.14
16.15 +#ifdef ENABLE_SH4STATS
16.16 +#define COUNT_INST(id) load_imm32(R_EAX,id); call_func1(sh4_stats_add, R_EAX); sh4_x86.tstate = TSTATE_NONE
16.17 +#else
16.18 +#define COUNT_INST(id)
16.19 +#endif
16.20 +
16.21 /** Branch if T is set (either in the current cflags, or in sh4r.t) */
16.22 #define JT_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
16.23 CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
16.24 @@ -384,6 +391,7 @@
16.25 %%
16.26 /* ALU operations */
16.27 ADD Rm, Rn {:
16.28 + COUNT_INST(I_ADD);
16.29 load_reg( R_EAX, Rm );
16.30 load_reg( R_ECX, Rn );
16.31 ADD_r32_r32( R_EAX, R_ECX );
16.32 @@ -391,12 +399,14 @@
16.33 sh4_x86.tstate = TSTATE_NONE;
16.34 :}
16.35 ADD #imm, Rn {:
16.36 + COUNT_INST(I_ADDI);
16.37 load_reg( R_EAX, Rn );
16.38 ADD_imm8s_r32( imm, R_EAX );
16.39 store_reg( R_EAX, Rn );
16.40 sh4_x86.tstate = TSTATE_NONE;
16.41 :}
16.42 ADDC Rm, Rn {:
16.43 + COUNT_INST(I_ADDC);
16.44 if( sh4_x86.tstate != TSTATE_C ) {
16.45 LDC_t();
16.46 }
16.47 @@ -408,6 +418,7 @@
16.48 sh4_x86.tstate = TSTATE_C;
16.49 :}
16.50 ADDV Rm, Rn {:
16.51 + COUNT_INST(I_ADDV);
16.52 load_reg( R_EAX, Rm );
16.53 load_reg( R_ECX, Rn );
16.54 ADD_r32_r32( R_EAX, R_ECX );
16.55 @@ -416,6 +427,7 @@
16.56 sh4_x86.tstate = TSTATE_O;
16.57 :}
16.58 AND Rm, Rn {:
16.59 + COUNT_INST(I_AND);
16.60 load_reg( R_EAX, Rm );
16.61 load_reg( R_ECX, Rn );
16.62 AND_r32_r32( R_EAX, R_ECX );
16.63 @@ -423,12 +435,14 @@
16.64 sh4_x86.tstate = TSTATE_NONE;
16.65 :}
16.66 AND #imm, R0 {:
16.67 + COUNT_INST(I_ANDI);
16.68 load_reg( R_EAX, 0 );
16.69 AND_imm32_r32(imm, R_EAX);
16.70 store_reg( R_EAX, 0 );
16.71 sh4_x86.tstate = TSTATE_NONE;
16.72 :}
16.73 AND.B #imm, @(R0, GBR) {:
16.74 + COUNT_INST(I_ANDB);
16.75 load_reg( R_EAX, 0 );
16.76 load_spreg( R_ECX, R_GBR );
16.77 ADD_r32_r32( R_ECX, R_EAX );
16.78 @@ -441,6 +455,7 @@
16.79 sh4_x86.tstate = TSTATE_NONE;
16.80 :}
16.81 CMP/EQ Rm, Rn {:
16.82 + COUNT_INST(I_CMPEQ);
16.83 load_reg( R_EAX, Rm );
16.84 load_reg( R_ECX, Rn );
16.85 CMP_r32_r32( R_EAX, R_ECX );
16.86 @@ -448,12 +463,14 @@
16.87 sh4_x86.tstate = TSTATE_E;
16.88 :}
16.89 CMP/EQ #imm, R0 {:
16.90 + COUNT_INST(I_CMPEQI);
16.91 load_reg( R_EAX, 0 );
16.92 CMP_imm8s_r32(imm, R_EAX);
16.93 SETE_t();
16.94 sh4_x86.tstate = TSTATE_E;
16.95 :}
16.96 CMP/GE Rm, Rn {:
16.97 + COUNT_INST(I_CMPGE);
16.98 load_reg( R_EAX, Rm );
16.99 load_reg( R_ECX, Rn );
16.100 CMP_r32_r32( R_EAX, R_ECX );
16.101 @@ -461,6 +478,7 @@
16.102 sh4_x86.tstate = TSTATE_GE;
16.103 :}
16.104 CMP/GT Rm, Rn {:
16.105 + COUNT_INST(I_CMPGT);
16.106 load_reg( R_EAX, Rm );
16.107 load_reg( R_ECX, Rn );
16.108 CMP_r32_r32( R_EAX, R_ECX );
16.109 @@ -468,6 +486,7 @@
16.110 sh4_x86.tstate = TSTATE_G;
16.111 :}
16.112 CMP/HI Rm, Rn {:
16.113 + COUNT_INST(I_CMPHI);
16.114 load_reg( R_EAX, Rm );
16.115 load_reg( R_ECX, Rn );
16.116 CMP_r32_r32( R_EAX, R_ECX );
16.117 @@ -475,6 +494,7 @@
16.118 sh4_x86.tstate = TSTATE_A;
16.119 :}
16.120 CMP/HS Rm, Rn {:
16.121 + COUNT_INST(I_CMPHS);
16.122 load_reg( R_EAX, Rm );
16.123 load_reg( R_ECX, Rn );
16.124 CMP_r32_r32( R_EAX, R_ECX );
16.125 @@ -482,18 +502,21 @@
16.126 sh4_x86.tstate = TSTATE_AE;
16.127 :}
16.128 CMP/PL Rn {:
16.129 + COUNT_INST(I_CMPPL);
16.130 load_reg( R_EAX, Rn );
16.131 CMP_imm8s_r32( 0, R_EAX );
16.132 SETG_t();
16.133 sh4_x86.tstate = TSTATE_G;
16.134 :}
16.135 CMP/PZ Rn {:
16.136 + COUNT_INST(I_CMPPZ);
16.137 load_reg( R_EAX, Rn );
16.138 CMP_imm8s_r32( 0, R_EAX );
16.139 SETGE_t();
16.140 sh4_x86.tstate = TSTATE_GE;
16.141 :}
16.142 CMP/STR Rm, Rn {:
16.143 + COUNT_INST(I_CMPSTR);
16.144 load_reg( R_EAX, Rm );
16.145 load_reg( R_ECX, Rn );
16.146 XOR_r32_r32( R_ECX, R_EAX );
16.147 @@ -512,6 +535,7 @@
16.148 sh4_x86.tstate = TSTATE_E;
16.149 :}
16.150 DIV0S Rm, Rn {:
16.151 + COUNT_INST(I_DIV0S);
16.152 load_reg( R_EAX, Rm );
16.153 load_reg( R_ECX, Rn );
16.154 SHR_imm8_r32( 31, R_EAX );
16.155 @@ -523,6 +547,7 @@
16.156 sh4_x86.tstate = TSTATE_NE;
16.157 :}
16.158 DIV0U {:
16.159 + COUNT_INST(I_DIV0U);
16.160 XOR_r32_r32( R_EAX, R_EAX );
16.161 store_spreg( R_EAX, R_Q );
16.162 store_spreg( R_EAX, R_M );
16.163 @@ -530,6 +555,7 @@
16.164 sh4_x86.tstate = TSTATE_C; // works for DIV1
16.165 :}
16.166 DIV1 Rm, Rn {:
16.167 + COUNT_INST(I_DIV1);
16.168 load_spreg( R_ECX, R_M );
16.169 load_reg( R_EAX, Rn );
16.170 if( sh4_x86.tstate != TSTATE_C ) {
16.171 @@ -555,6 +581,7 @@
16.172 sh4_x86.tstate = TSTATE_NONE;
16.173 :}
16.174 DMULS.L Rm, Rn {:
16.175 + COUNT_INST(I_DMULS);
16.176 load_reg( R_EAX, Rm );
16.177 load_reg( R_ECX, Rn );
16.178 IMUL_r32(R_ECX);
16.179 @@ -563,6 +590,7 @@
16.180 sh4_x86.tstate = TSTATE_NONE;
16.181 :}
16.182 DMULU.L Rm, Rn {:
16.183 + COUNT_INST(I_DMULU);
16.184 load_reg( R_EAX, Rm );
16.185 load_reg( R_ECX, Rn );
16.186 MUL_r32(R_ECX);
16.187 @@ -571,6 +599,7 @@
16.188 sh4_x86.tstate = TSTATE_NONE;
16.189 :}
16.190 DT Rn {:
16.191 + COUNT_INST(I_DT);
16.192 load_reg( R_EAX, Rn );
16.193 ADD_imm8s_r32( -1, R_EAX );
16.194 store_reg( R_EAX, Rn );
16.195 @@ -578,26 +607,31 @@
16.196 sh4_x86.tstate = TSTATE_E;
16.197 :}
16.198 EXTS.B Rm, Rn {:
16.199 + COUNT_INST(I_EXTSB);
16.200 load_reg( R_EAX, Rm );
16.201 MOVSX_r8_r32( R_EAX, R_EAX );
16.202 store_reg( R_EAX, Rn );
16.203 :}
16.204 EXTS.W Rm, Rn {:
16.205 + COUNT_INST(I_EXTSW);
16.206 load_reg( R_EAX, Rm );
16.207 MOVSX_r16_r32( R_EAX, R_EAX );
16.208 store_reg( R_EAX, Rn );
16.209 :}
16.210 EXTU.B Rm, Rn {:
16.211 + COUNT_INST(I_EXTUB);
16.212 load_reg( R_EAX, Rm );
16.213 MOVZX_r8_r32( R_EAX, R_EAX );
16.214 store_reg( R_EAX, Rn );
16.215 :}
16.216 EXTU.W Rm, Rn {:
16.217 + COUNT_INST(I_EXTUW);
16.218 load_reg( R_EAX, Rm );
16.219 MOVZX_r16_r32( R_EAX, R_EAX );
16.220 store_reg( R_EAX, Rn );
16.221 :}
16.222 MAC.L @Rm+, @Rn+ {:
16.223 + COUNT_INST(I_MACL);
16.224 if( Rm == Rn ) {
16.225 load_reg( R_EAX, Rm );
16.226 check_ralign32( R_EAX );
16.227 @@ -639,6 +673,7 @@
16.228 sh4_x86.tstate = TSTATE_NONE;
16.229 :}
16.230 MAC.W @Rm+, @Rn+ {:
16.231 + COUNT_INST(I_MACW);
16.232 if( Rm == Rn ) {
16.233 load_reg( R_EAX, Rm );
16.234 check_ralign16( R_EAX );
16.235 @@ -696,10 +731,12 @@
16.236 sh4_x86.tstate = TSTATE_NONE;
16.237 :}
16.238 MOVT Rn {:
16.239 + COUNT_INST(I_MOVT);
16.240 load_spreg( R_EAX, R_T );
16.241 store_reg( R_EAX, Rn );
16.242 :}
16.243 MUL.L Rm, Rn {:
16.244 + COUNT_INST(I_MULL);
16.245 load_reg( R_EAX, Rm );
16.246 load_reg( R_ECX, Rn );
16.247 MUL_r32( R_ECX );
16.248 @@ -707,6 +744,7 @@
16.249 sh4_x86.tstate = TSTATE_NONE;
16.250 :}
16.251 MULS.W Rm, Rn {:
16.252 + COUNT_INST(I_MULSW);
16.253 load_reg16s( R_EAX, Rm );
16.254 load_reg16s( R_ECX, Rn );
16.255 MUL_r32( R_ECX );
16.256 @@ -714,6 +752,7 @@
16.257 sh4_x86.tstate = TSTATE_NONE;
16.258 :}
16.259 MULU.W Rm, Rn {:
16.260 + COUNT_INST(I_MULUW);
16.261 load_reg16u( R_EAX, Rm );
16.262 load_reg16u( R_ECX, Rn );
16.263 MUL_r32( R_ECX );
16.264 @@ -721,12 +760,14 @@
16.265 sh4_x86.tstate = TSTATE_NONE;
16.266 :}
16.267 NEG Rm, Rn {:
16.268 + COUNT_INST(I_NEG);
16.269 load_reg( R_EAX, Rm );
16.270 NEG_r32( R_EAX );
16.271 store_reg( R_EAX, Rn );
16.272 sh4_x86.tstate = TSTATE_NONE;
16.273 :}
16.274 NEGC Rm, Rn {:
16.275 + COUNT_INST(I_NEGC);
16.276 load_reg( R_EAX, Rm );
16.277 XOR_r32_r32( R_ECX, R_ECX );
16.278 LDC_t();
16.279 @@ -736,12 +777,14 @@
16.280 sh4_x86.tstate = TSTATE_C;
16.281 :}
16.282 NOT Rm, Rn {:
16.283 + COUNT_INST(I_NOT);
16.284 load_reg( R_EAX, Rm );
16.285 NOT_r32( R_EAX );
16.286 store_reg( R_EAX, Rn );
16.287 sh4_x86.tstate = TSTATE_NONE;
16.288 :}
16.289 OR Rm, Rn {:
16.290 + COUNT_INST(I_OR);
16.291 load_reg( R_EAX, Rm );
16.292 load_reg( R_ECX, Rn );
16.293 OR_r32_r32( R_EAX, R_ECX );
16.294 @@ -749,12 +792,14 @@
16.295 sh4_x86.tstate = TSTATE_NONE;
16.296 :}
16.297 OR #imm, R0 {:
16.298 + COUNT_INST(I_ORI);
16.299 load_reg( R_EAX, 0 );
16.300 OR_imm32_r32(imm, R_EAX);
16.301 store_reg( R_EAX, 0 );
16.302 sh4_x86.tstate = TSTATE_NONE;
16.303 :}
16.304 OR.B #imm, @(R0, GBR) {:
16.305 + COUNT_INST(I_ORB);
16.306 load_reg( R_EAX, 0 );
16.307 load_spreg( R_ECX, R_GBR );
16.308 ADD_r32_r32( R_ECX, R_EAX );
16.309 @@ -767,6 +812,7 @@
16.310 sh4_x86.tstate = TSTATE_NONE;
16.311 :}
16.312 ROTCL Rn {:
16.313 + COUNT_INST(I_ROTCL);
16.314 load_reg( R_EAX, Rn );
16.315 if( sh4_x86.tstate != TSTATE_C ) {
16.316 LDC_t();
16.317 @@ -777,6 +823,7 @@
16.318 sh4_x86.tstate = TSTATE_C;
16.319 :}
16.320 ROTCR Rn {:
16.321 + COUNT_INST(I_ROTCR);
16.322 load_reg( R_EAX, Rn );
16.323 if( sh4_x86.tstate != TSTATE_C ) {
16.324 LDC_t();
16.325 @@ -787,6 +834,7 @@
16.326 sh4_x86.tstate = TSTATE_C;
16.327 :}
16.328 ROTL Rn {:
16.329 + COUNT_INST(I_ROTL);
16.330 load_reg( R_EAX, Rn );
16.331 ROL1_r32( R_EAX );
16.332 store_reg( R_EAX, Rn );
16.333 @@ -794,6 +842,7 @@
16.334 sh4_x86.tstate = TSTATE_C;
16.335 :}
16.336 ROTR Rn {:
16.337 + COUNT_INST(I_ROTR);
16.338 load_reg( R_EAX, Rn );
16.339 ROR1_r32( R_EAX );
16.340 store_reg( R_EAX, Rn );
16.341 @@ -801,6 +850,7 @@
16.342 sh4_x86.tstate = TSTATE_C;
16.343 :}
16.344 SHAD Rm, Rn {:
16.345 + COUNT_INST(I_SHAD);
16.346 /* Annoyingly enough, not directly convertible */
16.347 load_reg( R_EAX, Rn );
16.348 load_reg( R_ECX, Rm );
16.349 @@ -826,6 +876,7 @@
16.350 sh4_x86.tstate = TSTATE_NONE;
16.351 :}
16.352 SHLD Rm, Rn {:
16.353 + COUNT_INST(I_SHLD);
16.354 load_reg( R_EAX, Rn );
16.355 load_reg( R_ECX, Rm );
16.356 CMP_imm32_r32( 0, R_ECX );
16.357 @@ -850,6 +901,7 @@
16.358 sh4_x86.tstate = TSTATE_NONE;
16.359 :}
16.360 SHAL Rn {:
16.361 + COUNT_INST(I_SHAL);
16.362 load_reg( R_EAX, Rn );
16.363 SHL1_r32( R_EAX );
16.364 SETC_t();
16.365 @@ -857,6 +909,7 @@
16.366 sh4_x86.tstate = TSTATE_C;
16.367 :}
16.368 SHAR Rn {:
16.369 + COUNT_INST(I_SHAR);
16.370 load_reg( R_EAX, Rn );
16.371 SAR1_r32( R_EAX );
16.372 SETC_t();
16.373 @@ -864,6 +917,7 @@
16.374 sh4_x86.tstate = TSTATE_C;
16.375 :}
16.376 SHLL Rn {:
16.377 + COUNT_INST(I_SHLL);
16.378 load_reg( R_EAX, Rn );
16.379 SHL1_r32( R_EAX );
16.380 SETC_t();
16.381 @@ -871,24 +925,28 @@
16.382 sh4_x86.tstate = TSTATE_C;
16.383 :}
16.384 SHLL2 Rn {:
16.385 + COUNT_INST(I_SHLL);
16.386 load_reg( R_EAX, Rn );
16.387 SHL_imm8_r32( 2, R_EAX );
16.388 store_reg( R_EAX, Rn );
16.389 sh4_x86.tstate = TSTATE_NONE;
16.390 :}
16.391 SHLL8 Rn {:
16.392 + COUNT_INST(I_SHLL);
16.393 load_reg( R_EAX, Rn );
16.394 SHL_imm8_r32( 8, R_EAX );
16.395 store_reg( R_EAX, Rn );
16.396 sh4_x86.tstate = TSTATE_NONE;
16.397 :}
16.398 SHLL16 Rn {:
16.399 + COUNT_INST(I_SHLL);
16.400 load_reg( R_EAX, Rn );
16.401 SHL_imm8_r32( 16, R_EAX );
16.402 store_reg( R_EAX, Rn );
16.403 sh4_x86.tstate = TSTATE_NONE;
16.404 :}
16.405 SHLR Rn {:
16.406 + COUNT_INST(I_SHLR);
16.407 load_reg( R_EAX, Rn );
16.408 SHR1_r32( R_EAX );
16.409 SETC_t();
16.410 @@ -896,24 +954,28 @@
16.411 sh4_x86.tstate = TSTATE_C;
16.412 :}
16.413 SHLR2 Rn {:
16.414 + COUNT_INST(I_SHLR);
16.415 load_reg( R_EAX, Rn );
16.416 SHR_imm8_r32( 2, R_EAX );
16.417 store_reg( R_EAX, Rn );
16.418 sh4_x86.tstate = TSTATE_NONE;
16.419 :}
16.420 SHLR8 Rn {:
16.421 + COUNT_INST(I_SHLR);
16.422 load_reg( R_EAX, Rn );
16.423 SHR_imm8_r32( 8, R_EAX );
16.424 store_reg( R_EAX, Rn );
16.425 sh4_x86.tstate = TSTATE_NONE;
16.426 :}
16.427 SHLR16 Rn {:
16.428 + COUNT_INST(I_SHLR);
16.429 load_reg( R_EAX, Rn );
16.430 SHR_imm8_r32( 16, R_EAX );
16.431 store_reg( R_EAX, Rn );
16.432 sh4_x86.tstate = TSTATE_NONE;
16.433 :}
16.434 SUB Rm, Rn {:
16.435 + COUNT_INST(I_SUB);
16.436 load_reg( R_EAX, Rm );
16.437 load_reg( R_ECX, Rn );
16.438 SUB_r32_r32( R_EAX, R_ECX );
16.439 @@ -921,6 +983,7 @@
16.440 sh4_x86.tstate = TSTATE_NONE;
16.441 :}
16.442 SUBC Rm, Rn {:
16.443 + COUNT_INST(I_SUBC);
16.444 load_reg( R_EAX, Rm );
16.445 load_reg( R_ECX, Rn );
16.446 if( sh4_x86.tstate != TSTATE_C ) {
16.447 @@ -932,6 +995,7 @@
16.448 sh4_x86.tstate = TSTATE_C;
16.449 :}
16.450 SUBV Rm, Rn {:
16.451 + COUNT_INST(I_SUBV);
16.452 load_reg( R_EAX, Rm );
16.453 load_reg( R_ECX, Rn );
16.454 SUB_r32_r32( R_EAX, R_ECX );
16.455 @@ -940,11 +1004,13 @@
16.456 sh4_x86.tstate = TSTATE_O;
16.457 :}
16.458 SWAP.B Rm, Rn {:
16.459 + COUNT_INST(I_SWAPB);
16.460 load_reg( R_EAX, Rm );
16.461 XCHG_r8_r8( R_AL, R_AH ); // NB: does not touch EFLAGS
16.462 store_reg( R_EAX, Rn );
16.463 :}
16.464 SWAP.W Rm, Rn {:
16.465 + COUNT_INST(I_SWAPB);
16.466 load_reg( R_EAX, Rm );
16.467 MOV_r32_r32( R_EAX, R_ECX );
16.468 SHL_imm8_r32( 16, R_ECX );
16.469 @@ -954,6 +1020,7 @@
16.470 sh4_x86.tstate = TSTATE_NONE;
16.471 :}
16.472 TAS.B @Rn {:
16.473 + COUNT_INST(I_TASB);
16.474 load_reg( R_EAX, Rn );
16.475 MMU_TRANSLATE_WRITE( R_EAX );
16.476 PUSH_realigned_r32( R_EAX );
16.477 @@ -966,6 +1033,7 @@
16.478 sh4_x86.tstate = TSTATE_NONE;
16.479 :}
16.480 TST Rm, Rn {:
16.481 + COUNT_INST(I_TST);
16.482 load_reg( R_EAX, Rm );
16.483 load_reg( R_ECX, Rn );
16.484 TEST_r32_r32( R_EAX, R_ECX );
16.485 @@ -973,12 +1041,14 @@
16.486 sh4_x86.tstate = TSTATE_E;
16.487 :}
16.488 TST #imm, R0 {:
16.489 + COUNT_INST(I_TSTI);
16.490 load_reg( R_EAX, 0 );
16.491 TEST_imm32_r32( imm, R_EAX );
16.492 SETE_t();
16.493 sh4_x86.tstate = TSTATE_E;
16.494 :}
16.495 TST.B #imm, @(R0, GBR) {:
16.496 + COUNT_INST(I_TSTB);
16.497 load_reg( R_EAX, 0);
16.498 load_reg( R_ECX, R_GBR);
16.499 ADD_r32_r32( R_ECX, R_EAX );
16.500 @@ -989,6 +1059,7 @@
16.501 sh4_x86.tstate = TSTATE_E;
16.502 :}
16.503 XOR Rm, Rn {:
16.504 + COUNT_INST(I_XOR);
16.505 load_reg( R_EAX, Rm );
16.506 load_reg( R_ECX, Rn );
16.507 XOR_r32_r32( R_EAX, R_ECX );
16.508 @@ -996,12 +1067,14 @@
16.509 sh4_x86.tstate = TSTATE_NONE;
16.510 :}
16.511 XOR #imm, R0 {:
16.512 + COUNT_INST(I_XORI);
16.513 load_reg( R_EAX, 0 );
16.514 XOR_imm32_r32( imm, R_EAX );
16.515 store_reg( R_EAX, 0 );
16.516 sh4_x86.tstate = TSTATE_NONE;
16.517 :}
16.518 XOR.B #imm, @(R0, GBR) {:
16.519 + COUNT_INST(I_XORB);
16.520 load_reg( R_EAX, 0 );
16.521 load_spreg( R_ECX, R_GBR );
16.522 ADD_r32_r32( R_ECX, R_EAX );
16.523 @@ -1014,6 +1087,7 @@
16.524 sh4_x86.tstate = TSTATE_NONE;
16.525 :}
16.526 XTRCT Rm, Rn {:
16.527 + COUNT_INST(I_XTRCT);
16.528 load_reg( R_EAX, Rm );
16.529 load_reg( R_ECX, Rn );
16.530 SHL_imm8_r32( 16, R_EAX );
16.531 @@ -1025,14 +1099,17 @@
16.532
16.533 /* Data move instructions */
16.534 MOV Rm, Rn {:
16.535 + COUNT_INST(I_MOV);
16.536 load_reg( R_EAX, Rm );
16.537 store_reg( R_EAX, Rn );
16.538 :}
16.539 MOV #imm, Rn {:
16.540 + COUNT_INST(I_MOVI);
16.541 load_imm32( R_EAX, imm );
16.542 store_reg( R_EAX, Rn );
16.543 :}
16.544 MOV.B Rm, @Rn {:
16.545 + COUNT_INST(I_MOVB);
16.546 load_reg( R_EAX, Rn );
16.547 MMU_TRANSLATE_WRITE( R_EAX );
16.548 load_reg( R_EDX, Rm );
16.549 @@ -1040,6 +1117,7 @@
16.550 sh4_x86.tstate = TSTATE_NONE;
16.551 :}
16.552 MOV.B Rm, @-Rn {:
16.553 + COUNT_INST(I_MOVB);
16.554 load_reg( R_EAX, Rn );
16.555 ADD_imm8s_r32( -1, R_EAX );
16.556 MMU_TRANSLATE_WRITE( R_EAX );
16.557 @@ -1049,6 +1127,7 @@
16.558 sh4_x86.tstate = TSTATE_NONE;
16.559 :}
16.560 MOV.B Rm, @(R0, Rn) {:
16.561 + COUNT_INST(I_MOVB);
16.562 load_reg( R_EAX, 0 );
16.563 load_reg( R_ECX, Rn );
16.564 ADD_r32_r32( R_ECX, R_EAX );
16.565 @@ -1058,6 +1137,7 @@
16.566 sh4_x86.tstate = TSTATE_NONE;
16.567 :}
16.568 MOV.B R0, @(disp, GBR) {:
16.569 + COUNT_INST(I_MOVB);
16.570 load_spreg( R_EAX, R_GBR );
16.571 ADD_imm32_r32( disp, R_EAX );
16.572 MMU_TRANSLATE_WRITE( R_EAX );
16.573 @@ -1066,6 +1146,7 @@
16.574 sh4_x86.tstate = TSTATE_NONE;
16.575 :}
16.576 MOV.B R0, @(disp, Rn) {:
16.577 + COUNT_INST(I_MOVB);
16.578 load_reg( R_EAX, Rn );
16.579 ADD_imm32_r32( disp, R_EAX );
16.580 MMU_TRANSLATE_WRITE( R_EAX );
16.581 @@ -1074,6 +1155,7 @@
16.582 sh4_x86.tstate = TSTATE_NONE;
16.583 :}
16.584 MOV.B @Rm, Rn {:
16.585 + COUNT_INST(I_MOVB);
16.586 load_reg( R_EAX, Rm );
16.587 MMU_TRANSLATE_READ( R_EAX );
16.588 MEM_READ_BYTE( R_EAX, R_EAX );
16.589 @@ -1081,6 +1163,7 @@
16.590 sh4_x86.tstate = TSTATE_NONE;
16.591 :}
16.592 MOV.B @Rm+, Rn {:
16.593 + COUNT_INST(I_MOVB);
16.594 load_reg( R_EAX, Rm );
16.595 MMU_TRANSLATE_READ( R_EAX );
16.596 ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
16.597 @@ -1089,6 +1172,7 @@
16.598 sh4_x86.tstate = TSTATE_NONE;
16.599 :}
16.600 MOV.B @(R0, Rm), Rn {:
16.601 + COUNT_INST(I_MOVB);
16.602 load_reg( R_EAX, 0 );
16.603 load_reg( R_ECX, Rm );
16.604 ADD_r32_r32( R_ECX, R_EAX );
16.605 @@ -1098,6 +1182,7 @@
16.606 sh4_x86.tstate = TSTATE_NONE;
16.607 :}
16.608 MOV.B @(disp, GBR), R0 {:
16.609 + COUNT_INST(I_MOVB);
16.610 load_spreg( R_EAX, R_GBR );
16.611 ADD_imm32_r32( disp, R_EAX );
16.612 MMU_TRANSLATE_READ( R_EAX );
16.613 @@ -1106,6 +1191,7 @@
16.614 sh4_x86.tstate = TSTATE_NONE;
16.615 :}
16.616 MOV.B @(disp, Rm), R0 {:
16.617 + COUNT_INST(I_MOVB);
16.618 load_reg( R_EAX, Rm );
16.619 ADD_imm32_r32( disp, R_EAX );
16.620 MMU_TRANSLATE_READ( R_EAX );
16.621 @@ -1114,6 +1200,7 @@
16.622 sh4_x86.tstate = TSTATE_NONE;
16.623 :}
16.624 MOV.L Rm, @Rn {:
16.625 + COUNT_INST(I_MOVL);
16.626 load_reg( R_EAX, Rn );
16.627 check_walign32(R_EAX);
16.628 MMU_TRANSLATE_WRITE( R_EAX );
16.629 @@ -1122,6 +1209,7 @@
16.630 sh4_x86.tstate = TSTATE_NONE;
16.631 :}
16.632 MOV.L Rm, @-Rn {:
16.633 + COUNT_INST(I_MOVL);
16.634 load_reg( R_EAX, Rn );
16.635 ADD_imm8s_r32( -4, R_EAX );
16.636 check_walign32( R_EAX );
16.637 @@ -1132,6 +1220,7 @@
16.638 sh4_x86.tstate = TSTATE_NONE;
16.639 :}
16.640 MOV.L Rm, @(R0, Rn) {:
16.641 + COUNT_INST(I_MOVL);
16.642 load_reg( R_EAX, 0 );
16.643 load_reg( R_ECX, Rn );
16.644 ADD_r32_r32( R_ECX, R_EAX );
16.645 @@ -1142,6 +1231,7 @@
16.646 sh4_x86.tstate = TSTATE_NONE;
16.647 :}
16.648 MOV.L R0, @(disp, GBR) {:
16.649 + COUNT_INST(I_MOVL);
16.650 load_spreg( R_EAX, R_GBR );
16.651 ADD_imm32_r32( disp, R_EAX );
16.652 check_walign32( R_EAX );
16.653 @@ -1151,6 +1241,7 @@
16.654 sh4_x86.tstate = TSTATE_NONE;
16.655 :}
16.656 MOV.L Rm, @(disp, Rn) {:
16.657 + COUNT_INST(I_MOVL);
16.658 load_reg( R_EAX, Rn );
16.659 ADD_imm32_r32( disp, R_EAX );
16.660 check_walign32( R_EAX );
16.661 @@ -1160,6 +1251,7 @@
16.662 sh4_x86.tstate = TSTATE_NONE;
16.663 :}
16.664 MOV.L @Rm, Rn {:
16.665 + COUNT_INST(I_MOVL);
16.666 load_reg( R_EAX, Rm );
16.667 check_ralign32( R_EAX );
16.668 MMU_TRANSLATE_READ( R_EAX );
16.669 @@ -1168,6 +1260,7 @@
16.670 sh4_x86.tstate = TSTATE_NONE;
16.671 :}
16.672 MOV.L @Rm+, Rn {:
16.673 + COUNT_INST(I_MOVL);
16.674 load_reg( R_EAX, Rm );
16.675 check_ralign32( R_EAX );
16.676 MMU_TRANSLATE_READ( R_EAX );
16.677 @@ -1177,6 +1270,7 @@
16.678 sh4_x86.tstate = TSTATE_NONE;
16.679 :}
16.680 MOV.L @(R0, Rm), Rn {:
16.681 + COUNT_INST(I_MOVL);
16.682 load_reg( R_EAX, 0 );
16.683 load_reg( R_ECX, Rm );
16.684 ADD_r32_r32( R_ECX, R_EAX );
16.685 @@ -1187,6 +1281,7 @@
16.686 sh4_x86.tstate = TSTATE_NONE;
16.687 :}
16.688 MOV.L @(disp, GBR), R0 {:
16.689 + COUNT_INST(I_MOVL);
16.690 load_spreg( R_EAX, R_GBR );
16.691 ADD_imm32_r32( disp, R_EAX );
16.692 check_ralign32( R_EAX );
16.693 @@ -1196,6 +1291,7 @@
16.694 sh4_x86.tstate = TSTATE_NONE;
16.695 :}
16.696 MOV.L @(disp, PC), Rn {:
16.697 + COUNT_INST(I_MOVLPC);
16.698 if( sh4_x86.in_delay_slot ) {
16.699 SLOTILLEGAL();
16.700 } else {
16.701 @@ -1226,6 +1322,7 @@
16.702 }
16.703 :}
16.704 MOV.L @(disp, Rm), Rn {:
16.705 + COUNT_INST(I_MOVL);
16.706 load_reg( R_EAX, Rm );
16.707 ADD_imm8s_r32( disp, R_EAX );
16.708 check_ralign32( R_EAX );
16.709 @@ -1235,6 +1332,7 @@
16.710 sh4_x86.tstate = TSTATE_NONE;
16.711 :}
16.712 MOV.W Rm, @Rn {:
16.713 + COUNT_INST(I_MOVW);
16.714 load_reg( R_EAX, Rn );
16.715 check_walign16( R_EAX );
16.716 MMU_TRANSLATE_WRITE( R_EAX )
16.717 @@ -1243,6 +1341,7 @@
16.718 sh4_x86.tstate = TSTATE_NONE;
16.719 :}
16.720 MOV.W Rm, @-Rn {:
16.721 + COUNT_INST(I_MOVW);
16.722 load_reg( R_EAX, Rn );
16.723 ADD_imm8s_r32( -2, R_EAX );
16.724 check_walign16( R_EAX );
16.725 @@ -1253,6 +1352,7 @@
16.726 sh4_x86.tstate = TSTATE_NONE;
16.727 :}
16.728 MOV.W Rm, @(R0, Rn) {:
16.729 + COUNT_INST(I_MOVW);
16.730 load_reg( R_EAX, 0 );
16.731 load_reg( R_ECX, Rn );
16.732 ADD_r32_r32( R_ECX, R_EAX );
16.733 @@ -1263,6 +1363,7 @@
16.734 sh4_x86.tstate = TSTATE_NONE;
16.735 :}
16.736 MOV.W R0, @(disp, GBR) {:
16.737 + COUNT_INST(I_MOVW);
16.738 load_spreg( R_EAX, R_GBR );
16.739 ADD_imm32_r32( disp, R_EAX );
16.740 check_walign16( R_EAX );
16.741 @@ -1272,6 +1373,7 @@
16.742 sh4_x86.tstate = TSTATE_NONE;
16.743 :}
16.744 MOV.W R0, @(disp, Rn) {:
16.745 + COUNT_INST(I_MOVW);
16.746 load_reg( R_EAX, Rn );
16.747 ADD_imm32_r32( disp, R_EAX );
16.748 check_walign16( R_EAX );
16.749 @@ -1281,6 +1383,7 @@
16.750 sh4_x86.tstate = TSTATE_NONE;
16.751 :}
16.752 MOV.W @Rm, Rn {:
16.753 + COUNT_INST(I_MOVW);
16.754 load_reg( R_EAX, Rm );
16.755 check_ralign16( R_EAX );
16.756 MMU_TRANSLATE_READ( R_EAX );
16.757 @@ -1289,6 +1392,7 @@
16.758 sh4_x86.tstate = TSTATE_NONE;
16.759 :}
16.760 MOV.W @Rm+, Rn {:
16.761 + COUNT_INST(I_MOVW);
16.762 load_reg( R_EAX, Rm );
16.763 check_ralign16( R_EAX );
16.764 MMU_TRANSLATE_READ( R_EAX );
16.765 @@ -1298,6 +1402,7 @@
16.766 sh4_x86.tstate = TSTATE_NONE;
16.767 :}
16.768 MOV.W @(R0, Rm), Rn {:
16.769 + COUNT_INST(I_MOVW);
16.770 load_reg( R_EAX, 0 );
16.771 load_reg( R_ECX, Rm );
16.772 ADD_r32_r32( R_ECX, R_EAX );
16.773 @@ -1308,6 +1413,7 @@
16.774 sh4_x86.tstate = TSTATE_NONE;
16.775 :}
16.776 MOV.W @(disp, GBR), R0 {:
16.777 + COUNT_INST(I_MOVW);
16.778 load_spreg( R_EAX, R_GBR );
16.779 ADD_imm32_r32( disp, R_EAX );
16.780 check_ralign16( R_EAX );
16.781 @@ -1317,6 +1423,7 @@
16.782 sh4_x86.tstate = TSTATE_NONE;
16.783 :}
16.784 MOV.W @(disp, PC), Rn {:
16.785 + COUNT_INST(I_MOVW);
16.786 if( sh4_x86.in_delay_slot ) {
16.787 SLOTILLEGAL();
16.788 } else {
16.789 @@ -1337,6 +1444,7 @@
16.790 }
16.791 :}
16.792 MOV.W @(disp, Rm), R0 {:
16.793 + COUNT_INST(I_MOVW);
16.794 load_reg( R_EAX, Rm );
16.795 ADD_imm32_r32( disp, R_EAX );
16.796 check_ralign16( R_EAX );
16.797 @@ -1346,6 +1454,7 @@
16.798 sh4_x86.tstate = TSTATE_NONE;
16.799 :}
16.800 MOVA @(disp, PC), R0 {:
16.801 + COUNT_INST(I_MOVA);
16.802 if( sh4_x86.in_delay_slot ) {
16.803 SLOTILLEGAL();
16.804 } else {
16.805 @@ -1356,6 +1465,7 @@
16.806 }
16.807 :}
16.808 MOVCA.L R0, @Rn {:
16.809 + COUNT_INST(I_MOVCA);
16.810 load_reg( R_EAX, Rn );
16.811 check_walign32( R_EAX );
16.812 MMU_TRANSLATE_WRITE( R_EAX );
16.813 @@ -1366,6 +1476,7 @@
16.814
16.815 /* Control transfer instructions */
16.816 BF disp {:
16.817 + COUNT_INST(I_BF);
16.818 if( sh4_x86.in_delay_slot ) {
16.819 SLOTILLEGAL();
16.820 } else {
16.821 @@ -1377,6 +1488,7 @@
16.822 }
16.823 :}
16.824 BF/S disp {:
16.825 + COUNT_INST(I_BFS);
16.826 if( sh4_x86.in_delay_slot ) {
16.827 SLOTILLEGAL();
16.828 } else {
16.829 @@ -1409,6 +1521,7 @@
16.830 }
16.831 :}
16.832 BRA disp {:
16.833 + COUNT_INST(I_BRA);
16.834 if( sh4_x86.in_delay_slot ) {
16.835 SLOTILLEGAL();
16.836 } else {
16.837 @@ -1428,6 +1541,7 @@
16.838 }
16.839 :}
16.840 BRAF Rn {:
16.841 + COUNT_INST(I_BRAF);
16.842 if( sh4_x86.in_delay_slot ) {
16.843 SLOTILLEGAL();
16.844 } else {
16.845 @@ -1449,6 +1563,7 @@
16.846 }
16.847 :}
16.848 BSR disp {:
16.849 + COUNT_INST(I_BSR);
16.850 if( sh4_x86.in_delay_slot ) {
16.851 SLOTILLEGAL();
16.852 } else {
16.853 @@ -1471,6 +1586,7 @@
16.854 }
16.855 :}
16.856 BSRF Rn {:
16.857 + COUNT_INST(I_BSRF);
16.858 if( sh4_x86.in_delay_slot ) {
16.859 SLOTILLEGAL();
16.860 } else {
16.861 @@ -1494,6 +1610,7 @@
16.862 }
16.863 :}
16.864 BT disp {:
16.865 + COUNT_INST(I_BT);
16.866 if( sh4_x86.in_delay_slot ) {
16.867 SLOTILLEGAL();
16.868 } else {
16.869 @@ -1505,6 +1622,7 @@
16.870 }
16.871 :}
16.872 BT/S disp {:
16.873 + COUNT_INST(I_BTS);
16.874 if( sh4_x86.in_delay_slot ) {
16.875 SLOTILLEGAL();
16.876 } else {
16.877 @@ -1535,6 +1653,7 @@
16.878 }
16.879 :}
16.880 JMP @Rn {:
16.881 + COUNT_INST(I_JMP);
16.882 if( sh4_x86.in_delay_slot ) {
16.883 SLOTILLEGAL();
16.884 } else {
16.885 @@ -1553,6 +1672,7 @@
16.886 }
16.887 :}
16.888 JSR @Rn {:
16.889 + COUNT_INST(I_JSR);
16.890 if( sh4_x86.in_delay_slot ) {
16.891 SLOTILLEGAL();
16.892 } else {
16.893 @@ -1575,6 +1695,7 @@
16.894 }
16.895 :}
16.896 RTE {:
16.897 + COUNT_INST(I_RTE);
16.898 if( sh4_x86.in_delay_slot ) {
16.899 SLOTILLEGAL();
16.900 } else {
16.901 @@ -1599,6 +1720,7 @@
16.902 }
16.903 :}
16.904 RTS {:
16.905 + COUNT_INST(I_RTS);
16.906 if( sh4_x86.in_delay_slot ) {
16.907 SLOTILLEGAL();
16.908 } else {
16.909 @@ -1617,6 +1739,7 @@
16.910 }
16.911 :}
16.912 TRAPA #imm {:
16.913 + COUNT_INST(I_TRAPA);
16.914 if( sh4_x86.in_delay_slot ) {
16.915 SLOTILLEGAL();
16.916 } else {
16.917 @@ -1631,6 +1754,7 @@
16.918 }
16.919 :}
16.920 UNDEF {:
16.921 + COUNT_INST(I_UNDEF);
16.922 if( sh4_x86.in_delay_slot ) {
16.923 SLOTILLEGAL();
16.924 } else {
16.925 @@ -1640,27 +1764,32 @@
16.926 :}
16.927
16.928 CLRMAC {:
16.929 + COUNT_INST(I_CLRMAC);
16.930 XOR_r32_r32(R_EAX, R_EAX);
16.931 store_spreg( R_EAX, R_MACL );
16.932 store_spreg( R_EAX, R_MACH );
16.933 sh4_x86.tstate = TSTATE_NONE;
16.934 :}
16.935 CLRS {:
16.936 + COUNT_INST(I_CLRS);
16.937 CLC();
16.938 SETC_sh4r(R_S);
16.939 sh4_x86.tstate = TSTATE_C;
16.940 :}
16.941 CLRT {:
16.942 + COUNT_INST(I_CLRT);
16.943 CLC();
16.944 SETC_t();
16.945 sh4_x86.tstate = TSTATE_C;
16.946 :}
16.947 SETS {:
16.948 + COUNT_INST(I_SETS);
16.949 STC();
16.950 SETC_sh4r(R_S);
16.951 sh4_x86.tstate = TSTATE_C;
16.952 :}
16.953 SETT {:
16.954 + COUNT_INST(I_SETT);
16.955 STC();
16.956 SETC_t();
16.957 sh4_x86.tstate = TSTATE_C;
16.958 @@ -1668,6 +1797,7 @@
16.959
16.960 /* Floating point moves */
16.961 FMOV FRm, FRn {:
16.962 + COUNT_INST(I_FMOV1);
16.963 /* As horrible as this looks, it's actually covering 5 separate cases:
16.964 * 1. 32-bit fr-to-fr (PR=0)
16.965 * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
16.966 @@ -1691,6 +1821,7 @@
16.967 sh4_x86.tstate = TSTATE_NONE;
16.968 :}
16.969 FMOV FRm, @Rn {:
16.970 + COUNT_INST(I_FMOV2);
16.971 check_fpuen();
16.972 load_reg( R_EAX, Rn );
16.973 check_walign32( R_EAX );
16.974 @@ -1711,6 +1842,7 @@
16.975 sh4_x86.tstate = TSTATE_NONE;
16.976 :}
16.977 FMOV @Rm, FRn {:
16.978 + COUNT_INST(I_FMOV5);
16.979 check_fpuen();
16.980 load_reg( R_EAX, Rm );
16.981 check_ralign32( R_EAX );
16.982 @@ -1731,6 +1863,7 @@
16.983 sh4_x86.tstate = TSTATE_NONE;
16.984 :}
16.985 FMOV FRm, @-Rn {:
16.986 + COUNT_INST(I_FMOV3);
16.987 check_fpuen();
16.988 load_reg( R_EAX, Rn );
16.989 check_walign32( R_EAX );
16.990 @@ -1757,6 +1890,7 @@
16.991 sh4_x86.tstate = TSTATE_NONE;
16.992 :}
16.993 FMOV @Rm+, FRn {:
16.994 + COUNT_INST(I_FMOV6);
16.995 check_fpuen();
16.996 load_reg( R_EAX, Rm );
16.997 check_ralign32( R_EAX );
16.998 @@ -1780,6 +1914,7 @@
16.999 sh4_x86.tstate = TSTATE_NONE;
16.1000 :}
16.1001 FMOV FRm, @(R0, Rn) {:
16.1002 + COUNT_INST(I_FMOV4);
16.1003 check_fpuen();
16.1004 load_reg( R_EAX, Rn );
16.1005 ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
16.1006 @@ -1802,6 +1937,7 @@
16.1007 sh4_x86.tstate = TSTATE_NONE;
16.1008 :}
16.1009 FMOV @(R0, Rm), FRn {:
16.1010 + COUNT_INST(I_FMOV7);
16.1011 check_fpuen();
16.1012 load_reg( R_EAX, Rm );
16.1013 ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
16.1014 @@ -1824,6 +1960,7 @@
16.1015 sh4_x86.tstate = TSTATE_NONE;
16.1016 :}
16.1017 FLDI0 FRn {: /* IFF PR=0 */
16.1018 + COUNT_INST(I_FLDI0);
16.1019 check_fpuen();
16.1020 load_spreg( R_ECX, R_FPSCR );
16.1021 TEST_imm32_r32( FPSCR_PR, R_ECX );
16.1022 @@ -1834,6 +1971,7 @@
16.1023 sh4_x86.tstate = TSTATE_NONE;
16.1024 :}
16.1025 FLDI1 FRn {: /* IFF PR=0 */
16.1026 + COUNT_INST(I_FLDI1);
16.1027 check_fpuen();
16.1028 load_spreg( R_ECX, R_FPSCR );
16.1029 TEST_imm32_r32( FPSCR_PR, R_ECX );
16.1030 @@ -1845,6 +1983,7 @@
16.1031 :}
16.1032
16.1033 FLOAT FPUL, FRn {:
16.1034 + COUNT_INST(I_FLOAT);
16.1035 check_fpuen();
16.1036 load_spreg( R_ECX, R_FPSCR );
16.1037 FILD_sh4r(R_FPUL);
16.1038 @@ -1858,6 +1997,7 @@
16.1039 sh4_x86.tstate = TSTATE_NONE;
16.1040 :}
16.1041 FTRC FRm, FPUL {:
16.1042 + COUNT_INST(I_FTRC);
16.1043 check_fpuen();
16.1044 load_spreg( R_ECX, R_FPSCR );
16.1045 TEST_imm32_r32( FPSCR_PR, R_ECX );
16.1046 @@ -1892,18 +2032,21 @@
16.1047 sh4_x86.tstate = TSTATE_NONE;
16.1048 :}
16.1049 FLDS FRm, FPUL {:
16.1050 + COUNT_INST(I_FLDS);
16.1051 check_fpuen();
16.1052 load_fr( R_EAX, FRm );
16.1053 store_spreg( R_EAX, R_FPUL );
16.1054 sh4_x86.tstate = TSTATE_NONE;
16.1055 :}
16.1056 FSTS FPUL, FRn {:
16.1057 + COUNT_INST(I_FSTS);
16.1058 check_fpuen();
16.1059 load_spreg( R_EAX, R_FPUL );
16.1060 store_fr( R_EAX, FRn );
16.1061 sh4_x86.tstate = TSTATE_NONE;
16.1062 :}
16.1063 FCNVDS FRm, FPUL {:
16.1064 + COUNT_INST(I_FCNVDS);
16.1065 check_fpuen();
16.1066 load_spreg( R_ECX, R_FPSCR );
16.1067 TEST_imm32_r32( FPSCR_PR, R_ECX );
16.1068 @@ -1914,6 +2057,7 @@
16.1069 sh4_x86.tstate = TSTATE_NONE;
16.1070 :}
16.1071 FCNVSD FPUL, FRn {:
16.1072 + COUNT_INST(I_FCNVSD);
16.1073 check_fpuen();
16.1074 load_spreg( R_ECX, R_FPSCR );
16.1075 TEST_imm32_r32( FPSCR_PR, R_ECX );
16.1076 @@ -1926,6 +2070,7 @@
16.1077
16.1078 /* Floating point instructions */
16.1079 FABS FRn {:
16.1080 + COUNT_INST(I_FABS);
16.1081 check_fpuen();
16.1082 load_spreg( R_ECX, R_FPSCR );
16.1083 TEST_imm32_r32( FPSCR_PR, R_ECX );
16.1084 @@ -1942,6 +2087,7 @@
16.1085 sh4_x86.tstate = TSTATE_NONE;
16.1086 :}
16.1087 FADD FRm, FRn {:
16.1088 + COUNT_INST(I_FADD);
16.1089 check_fpuen();
16.1090 load_spreg( R_ECX, R_FPSCR );
16.1091 TEST_imm32_r32( FPSCR_PR, R_ECX );
16.1092 @@ -1960,6 +2106,7 @@
16.1093 sh4_x86.tstate = TSTATE_NONE;
16.1094 :}
16.1095 FDIV FRm, FRn {:
16.1096 + COUNT_INST(I_FDIV);
16.1097 check_fpuen();
16.1098 load_spreg( R_ECX, R_FPSCR );
16.1099 TEST_imm32_r32( FPSCR_PR, R_ECX );
16.1100 @@ -1978,6 +2125,7 @@
16.1101 sh4_x86.tstate = TSTATE_NONE;
16.1102 :}
16.1103 FMAC FR0, FRm, FRn {:
16.1104 + COUNT_INST(I_FMAC);
16.1105 check_fpuen();
16.1106 load_spreg( R_ECX, R_FPSCR );
16.1107 TEST_imm32_r32( FPSCR_PR, R_ECX );
16.1108 @@ -2001,6 +2149,7 @@
16.1109 :}
16.1110
16.1111 FMUL FRm, FRn {:
16.1112 + COUNT_INST(I_FMUL);
16.1113 check_fpuen();
16.1114 load_spreg( R_ECX, R_FPSCR );
16.1115 TEST_imm32_r32( FPSCR_PR, R_ECX );
16.1116 @@ -2019,6 +2168,7 @@
16.1117 sh4_x86.tstate = TSTATE_NONE;
16.1118 :}
16.1119 FNEG FRn {:
16.1120 + COUNT_INST(I_FNEG);
16.1121 check_fpuen();
16.1122 load_spreg( R_ECX, R_FPSCR );
16.1123 TEST_imm32_r32( FPSCR_PR, R_ECX );
16.1124 @@ -2035,6 +2185,7 @@
16.1125 sh4_x86.tstate = TSTATE_NONE;
16.1126 :}
16.1127 FSRRA FRn {:
16.1128 + COUNT_INST(I_FSRRA);
16.1129 check_fpuen();
16.1130 load_spreg( R_ECX, R_FPSCR );
16.1131 TEST_imm32_r32( FPSCR_PR, R_ECX );
16.1132 @@ -2048,6 +2199,7 @@
16.1133 sh4_x86.tstate = TSTATE_NONE;
16.1134 :}
16.1135 FSQRT FRn {:
16.1136 + COUNT_INST(I_FSQRT);
16.1137 check_fpuen();
16.1138 load_spreg( R_ECX, R_FPSCR );
16.1139 TEST_imm32_r32( FPSCR_PR, R_ECX );
16.1140 @@ -2064,6 +2216,7 @@
16.1141 sh4_x86.tstate = TSTATE_NONE;
16.1142 :}
16.1143 FSUB FRm, FRn {:
16.1144 + COUNT_INST(I_FSUB);
16.1145 check_fpuen();
16.1146 load_spreg( R_ECX, R_FPSCR );
16.1147 TEST_imm32_r32( FPSCR_PR, R_ECX );
16.1148 @@ -2083,6 +2236,7 @@
16.1149 :}
16.1150
16.1151 FCMP/EQ FRm, FRn {:
16.1152 + COUNT_INST(I_FCMPEQ);
16.1153 check_fpuen();
16.1154 load_spreg( R_ECX, R_FPSCR );
16.1155 TEST_imm32_r32( FPSCR_PR, R_ECX );
16.1156 @@ -2100,6 +2254,7 @@
16.1157 sh4_x86.tstate = TSTATE_NONE;
16.1158 :}
16.1159 FCMP/GT FRm, FRn {:
16.1160 + COUNT_INST(I_FCMPGT);
16.1161 check_fpuen();
16.1162 load_spreg( R_ECX, R_FPSCR );
16.1163 TEST_imm32_r32( FPSCR_PR, R_ECX );
16.1164 @@ -2118,6 +2273,7 @@
16.1165 :}
16.1166
16.1167 FSCA FPUL, FRn {:
16.1168 + COUNT_INST(I_FSCA);
16.1169 check_fpuen();
16.1170 load_spreg( R_ECX, R_FPSCR );
16.1171 TEST_imm32_r32( FPSCR_PR, R_ECX );
16.1172 @@ -2129,6 +2285,7 @@
16.1173 sh4_x86.tstate = TSTATE_NONE;
16.1174 :}
16.1175 FIPR FVm, FVn {:
16.1176 + COUNT_INST(I_FIPR);
16.1177 check_fpuen();
16.1178 load_spreg( R_ECX, R_FPSCR );
16.1179 TEST_imm32_r32( FPSCR_PR, R_ECX );
16.1180 @@ -2154,6 +2311,7 @@
16.1181 sh4_x86.tstate = TSTATE_NONE;
16.1182 :}
16.1183 FTRV XMTRX, FVn {:
16.1184 + COUNT_INST(I_FTRV);
16.1185 check_fpuen();
16.1186 load_spreg( R_ECX, R_FPSCR );
16.1187 TEST_imm32_r32( FPSCR_PR, R_ECX );
16.1188 @@ -2165,6 +2323,7 @@
16.1189 :}
16.1190
16.1191 FRCHG {:
16.1192 + COUNT_INST(I_FRCHG);
16.1193 check_fpuen();
16.1194 load_spreg( R_ECX, R_FPSCR );
16.1195 XOR_imm32_r32( FPSCR_FR, R_ECX );
16.1196 @@ -2173,6 +2332,7 @@
16.1197 sh4_x86.tstate = TSTATE_NONE;
16.1198 :}
16.1199 FSCHG {:
16.1200 + COUNT_INST(I_FSCHG);
16.1201 check_fpuen();
16.1202 load_spreg( R_ECX, R_FPSCR );
16.1203 XOR_imm32_r32( FPSCR_SZ, R_ECX );
16.1204 @@ -2182,6 +2342,7 @@
16.1205
16.1206 /* Processor control instructions */
16.1207 LDC Rm, SR {:
16.1208 + COUNT_INST(I_LDCSR);
16.1209 if( sh4_x86.in_delay_slot ) {
16.1210 SLOTILLEGAL();
16.1211 } else {
16.1212 @@ -2194,46 +2355,54 @@
16.1213 }
16.1214 :}
16.1215 LDC Rm, GBR {:
16.1216 + COUNT_INST(I_LDC);
16.1217 load_reg( R_EAX, Rm );
16.1218 store_spreg( R_EAX, R_GBR );
16.1219 :}
16.1220 LDC Rm, VBR {:
16.1221 + COUNT_INST(I_LDC);
16.1222 check_priv();
16.1223 load_reg( R_EAX, Rm );
16.1224 store_spreg( R_EAX, R_VBR );
16.1225 sh4_x86.tstate = TSTATE_NONE;
16.1226 :}
16.1227 LDC Rm, SSR {:
16.1228 + COUNT_INST(I_LDC);
16.1229 check_priv();
16.1230 load_reg( R_EAX, Rm );
16.1231 store_spreg( R_EAX, R_SSR );
16.1232 sh4_x86.tstate = TSTATE_NONE;
16.1233 :}
16.1234 LDC Rm, SGR {:
16.1235 + COUNT_INST(I_LDC);
16.1236 check_priv();
16.1237 load_reg( R_EAX, Rm );
16.1238 store_spreg( R_EAX, R_SGR );
16.1239 sh4_x86.tstate = TSTATE_NONE;
16.1240 :}
16.1241 LDC Rm, SPC {:
16.1242 + COUNT_INST(I_LDC);
16.1243 check_priv();
16.1244 load_reg( R_EAX, Rm );
16.1245 store_spreg( R_EAX, R_SPC );
16.1246 sh4_x86.tstate = TSTATE_NONE;
16.1247 :}
16.1248 LDC Rm, DBR {:
16.1249 + COUNT_INST(I_LDC);
16.1250 check_priv();
16.1251 load_reg( R_EAX, Rm );
16.1252 store_spreg( R_EAX, R_DBR );
16.1253 sh4_x86.tstate = TSTATE_NONE;
16.1254 :}
16.1255 LDC Rm, Rn_BANK {:
16.1256 + COUNT_INST(I_LDC);
16.1257 check_priv();
16.1258 load_reg( R_EAX, Rm );
16.1259 store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
16.1260 sh4_x86.tstate = TSTATE_NONE;
16.1261 :}
16.1262 LDC.L @Rm+, GBR {:
16.1263 + COUNT_INST(I_LDCM);
16.1264 load_reg( R_EAX, Rm );
16.1265 check_ralign32( R_EAX );
16.1266 MMU_TRANSLATE_READ( R_EAX );
16.1267 @@ -2243,6 +2412,7 @@
16.1268 sh4_x86.tstate = TSTATE_NONE;
16.1269 :}
16.1270 LDC.L @Rm+, SR {:
16.1271 + COUNT_INST(I_LDCSRM);
16.1272 if( sh4_x86.in_delay_slot ) {
16.1273 SLOTILLEGAL();
16.1274 } else {
16.1275 @@ -2259,6 +2429,7 @@
16.1276 }
16.1277 :}
16.1278 LDC.L @Rm+, VBR {:
16.1279 + COUNT_INST(I_LDCM);
16.1280 check_priv();
16.1281 load_reg( R_EAX, Rm );
16.1282 check_ralign32( R_EAX );
16.1283 @@ -2269,6 +2440,7 @@
16.1284 sh4_x86.tstate = TSTATE_NONE;
16.1285 :}
16.1286 LDC.L @Rm+, SSR {:
16.1287 + COUNT_INST(I_LDCM);
16.1288 check_priv();
16.1289 load_reg( R_EAX, Rm );
16.1290 check_ralign32( R_EAX );
16.1291 @@ -2279,6 +2451,7 @@
16.1292 sh4_x86.tstate = TSTATE_NONE;
16.1293 :}
16.1294 LDC.L @Rm+, SGR {:
16.1295 + COUNT_INST(I_LDCM);
16.1296 check_priv();
16.1297 load_reg( R_EAX, Rm );
16.1298 check_ralign32( R_EAX );
16.1299 @@ -2289,6 +2462,7 @@
16.1300 sh4_x86.tstate = TSTATE_NONE;
16.1301 :}
16.1302 LDC.L @Rm+, SPC {:
16.1303 + COUNT_INST(I_LDCM);
16.1304 check_priv();
16.1305 load_reg( R_EAX, Rm );
16.1306 check_ralign32( R_EAX );
16.1307 @@ -2299,6 +2473,7 @@
16.1308 sh4_x86.tstate = TSTATE_NONE;
16.1309 :}
16.1310 LDC.L @Rm+, DBR {:
16.1311 + COUNT_INST(I_LDCM);
16.1312 check_priv();
16.1313 load_reg( R_EAX, Rm );
16.1314 check_ralign32( R_EAX );
16.1315 @@ -2309,6 +2484,7 @@
16.1316 sh4_x86.tstate = TSTATE_NONE;
16.1317 :}
16.1318 LDC.L @Rm+, Rn_BANK {:
16.1319 + COUNT_INST(I_LDCM);
16.1320 check_priv();
16.1321 load_reg( R_EAX, Rm );
16.1322 check_ralign32( R_EAX );
16.1323 @@ -2319,12 +2495,14 @@
16.1324 sh4_x86.tstate = TSTATE_NONE;
16.1325 :}
16.1326 LDS Rm, FPSCR {:
16.1327 + COUNT_INST(I_LDS);
16.1328 check_fpuen();
16.1329 load_reg( R_EAX, Rm );
16.1330 call_func1( sh4_write_fpscr, R_EAX );
16.1331 sh4_x86.tstate = TSTATE_NONE;
16.1332 :}
16.1333 LDS.L @Rm+, FPSCR {:
16.1334 + COUNT_INST(I_LDS);
16.1335 check_fpuen();
16.1336 load_reg( R_EAX, Rm );
16.1337 check_ralign32( R_EAX );
16.1338 @@ -2335,11 +2513,13 @@
16.1339 sh4_x86.tstate = TSTATE_NONE;
16.1340 :}
16.1341 LDS Rm, FPUL {:
16.1342 + COUNT_INST(I_LDS);
16.1343 check_fpuen();
16.1344 load_reg( R_EAX, Rm );
16.1345 store_spreg( R_EAX, R_FPUL );
16.1346 :}
16.1347 LDS.L @Rm+, FPUL {:
16.1348 + COUNT_INST(I_LDSM);
16.1349 check_fpuen();
16.1350 load_reg( R_EAX, Rm );
16.1351 check_ralign32( R_EAX );
16.1352 @@ -2350,10 +2530,12 @@
16.1353 sh4_x86.tstate = TSTATE_NONE;
16.1354 :}
16.1355 LDS Rm, MACH {:
16.1356 + COUNT_INST(I_LDS);
16.1357 load_reg( R_EAX, Rm );
16.1358 store_spreg( R_EAX, R_MACH );
16.1359 :}
16.1360 LDS.L @Rm+, MACH {:
16.1361 + COUNT_INST(I_LDSM);
16.1362 load_reg( R_EAX, Rm );
16.1363 check_ralign32( R_EAX );
16.1364 MMU_TRANSLATE_READ( R_EAX );
16.1365 @@ -2363,10 +2545,12 @@
16.1366 sh4_x86.tstate = TSTATE_NONE;
16.1367 :}
16.1368 LDS Rm, MACL {:
16.1369 + COUNT_INST(I_LDS);
16.1370 load_reg( R_EAX, Rm );
16.1371 store_spreg( R_EAX, R_MACL );
16.1372 :}
16.1373 LDS.L @Rm+, MACL {:
16.1374 + COUNT_INST(I_LDSM);
16.1375 load_reg( R_EAX, Rm );
16.1376 check_ralign32( R_EAX );
16.1377 MMU_TRANSLATE_READ( R_EAX );
16.1378 @@ -2376,10 +2560,12 @@
16.1379 sh4_x86.tstate = TSTATE_NONE;
16.1380 :}
16.1381 LDS Rm, PR {:
16.1382 + COUNT_INST(I_LDS);
16.1383 load_reg( R_EAX, Rm );
16.1384 store_spreg( R_EAX, R_PR );
16.1385 :}
16.1386 LDS.L @Rm+, PR {:
16.1387 + COUNT_INST(I_LDSM);
16.1388 load_reg( R_EAX, Rm );
16.1389 check_ralign32( R_EAX );
16.1390 MMU_TRANSLATE_READ( R_EAX );
16.1391 @@ -2389,12 +2575,20 @@
16.1392 sh4_x86.tstate = TSTATE_NONE;
16.1393 :}
16.1394 LDTLB {:
16.1395 + COUNT_INST(I_LDTLB);
16.1396 call_func0( MMU_ldtlb );
16.1397 :}
16.1398 -OCBI @Rn {: :}
16.1399 -OCBP @Rn {: :}
16.1400 -OCBWB @Rn {: :}
16.1401 +OCBI @Rn {:
16.1402 + COUNT_INST(I_OCBI);
16.1403 +:}
16.1404 +OCBP @Rn {:
16.1405 + COUNT_INST(I_OCBP);
16.1406 +:}
16.1407 +OCBWB @Rn {:
16.1408 + COUNT_INST(I_OCBWB);
16.1409 +:}
16.1410 PREF @Rn {:
16.1411 + COUNT_INST(I_PREF);
16.1412 load_reg( R_EAX, Rn );
16.1413 MOV_r32_r32( R_EAX, R_ECX );
16.1414 AND_imm32_r32( 0xFC000000, R_EAX );
16.1415 @@ -2407,6 +2601,7 @@
16.1416 sh4_x86.tstate = TSTATE_NONE;
16.1417 :}
16.1418 SLEEP {:
16.1419 + COUNT_INST(I_SLEEP);
16.1420 check_priv();
16.1421 call_func0( sh4_sleep );
16.1422 sh4_x86.tstate = TSTATE_NONE;
16.1423 @@ -2414,52 +2609,61 @@
16.1424 return 2;
16.1425 :}
16.1426 STC SR, Rn {:
16.1427 + COUNT_INST(I_STCSR);
16.1428 check_priv();
16.1429 call_func0(sh4_read_sr);
16.1430 store_reg( R_EAX, Rn );
16.1431 sh4_x86.tstate = TSTATE_NONE;
16.1432 :}
16.1433 STC GBR, Rn {:
16.1434 + COUNT_INST(I_STC);
16.1435 load_spreg( R_EAX, R_GBR );
16.1436 store_reg( R_EAX, Rn );
16.1437 :}
16.1438 STC VBR, Rn {:
16.1439 + COUNT_INST(I_STC);
16.1440 check_priv();
16.1441 load_spreg( R_EAX, R_VBR );
16.1442 store_reg( R_EAX, Rn );
16.1443 sh4_x86.tstate = TSTATE_NONE;
16.1444 :}
16.1445 STC SSR, Rn {:
16.1446 + COUNT_INST(I_STC);
16.1447 check_priv();
16.1448 load_spreg( R_EAX, R_SSR );
16.1449 store_reg( R_EAX, Rn );
16.1450 sh4_x86.tstate = TSTATE_NONE;
16.1451 :}
16.1452 STC SPC, Rn {:
16.1453 + COUNT_INST(I_STC);
16.1454 check_priv();
16.1455 load_spreg( R_EAX, R_SPC );
16.1456 store_reg( R_EAX, Rn );
16.1457 sh4_x86.tstate = TSTATE_NONE;
16.1458 :}
16.1459 STC SGR, Rn {:
16.1460 + COUNT_INST(I_STC);
16.1461 check_priv();
16.1462 load_spreg( R_EAX, R_SGR );
16.1463 store_reg( R_EAX, Rn );
16.1464 sh4_x86.tstate = TSTATE_NONE;
16.1465 :}
16.1466 STC DBR, Rn {:
16.1467 + COUNT_INST(I_STC);
16.1468 check_priv();
16.1469 load_spreg( R_EAX, R_DBR );
16.1470 store_reg( R_EAX, Rn );
16.1471 sh4_x86.tstate = TSTATE_NONE;
16.1472 :}
16.1473 STC Rm_BANK, Rn {:
16.1474 + COUNT_INST(I_STC);
16.1475 check_priv();
16.1476 load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
16.1477 store_reg( R_EAX, Rn );
16.1478 sh4_x86.tstate = TSTATE_NONE;
16.1479 :}
16.1480 STC.L SR, @-Rn {:
16.1481 + COUNT_INST(I_STCSRM);
16.1482 check_priv();
16.1483 load_reg( R_EAX, Rn );
16.1484 check_walign32( R_EAX );
16.1485 @@ -2473,6 +2677,7 @@
16.1486 sh4_x86.tstate = TSTATE_NONE;
16.1487 :}
16.1488 STC.L VBR, @-Rn {:
16.1489 + COUNT_INST(I_STCM);
16.1490 check_priv();
16.1491 load_reg( R_EAX, Rn );
16.1492 check_walign32( R_EAX );
16.1493 @@ -2484,6 +2689,7 @@
16.1494 sh4_x86.tstate = TSTATE_NONE;
16.1495 :}
16.1496 STC.L SSR, @-Rn {:
16.1497 + COUNT_INST(I_STCM);
16.1498 check_priv();
16.1499 load_reg( R_EAX, Rn );
16.1500 check_walign32( R_EAX );
16.1501 @@ -2495,6 +2701,7 @@
16.1502 sh4_x86.tstate = TSTATE_NONE;
16.1503 :}
16.1504 STC.L SPC, @-Rn {:
16.1505 + COUNT_INST(I_STCM);
16.1506 check_priv();
16.1507 load_reg( R_EAX, Rn );
16.1508 check_walign32( R_EAX );
16.1509 @@ -2506,6 +2713,7 @@
16.1510 sh4_x86.tstate = TSTATE_NONE;
16.1511 :}
16.1512 STC.L SGR, @-Rn {:
16.1513 + COUNT_INST(I_STCM);
16.1514 check_priv();
16.1515 load_reg( R_EAX, Rn );
16.1516 check_walign32( R_EAX );
16.1517 @@ -2517,6 +2725,7 @@
16.1518 sh4_x86.tstate = TSTATE_NONE;
16.1519 :}
16.1520 STC.L DBR, @-Rn {:
16.1521 + COUNT_INST(I_STCM);
16.1522 check_priv();
16.1523 load_reg( R_EAX, Rn );
16.1524 check_walign32( R_EAX );
16.1525 @@ -2528,6 +2737,7 @@
16.1526 sh4_x86.tstate = TSTATE_NONE;
16.1527 :}
16.1528 STC.L Rm_BANK, @-Rn {:
16.1529 + COUNT_INST(I_STCM);
16.1530 check_priv();
16.1531 load_reg( R_EAX, Rn );
16.1532 check_walign32( R_EAX );
16.1533 @@ -2539,6 +2749,7 @@
16.1534 sh4_x86.tstate = TSTATE_NONE;
16.1535 :}
16.1536 STC.L GBR, @-Rn {:
16.1537 + COUNT_INST(I_STCM);
16.1538 load_reg( R_EAX, Rn );
16.1539 check_walign32( R_EAX );
16.1540 ADD_imm8s_r32( -4, R_EAX );
16.1541 @@ -2549,11 +2760,13 @@
16.1542 sh4_x86.tstate = TSTATE_NONE;
16.1543 :}
16.1544 STS FPSCR, Rn {:
16.1545 + COUNT_INST(I_STS);
16.1546 check_fpuen();
16.1547 load_spreg( R_EAX, R_FPSCR );
16.1548 store_reg( R_EAX, Rn );
16.1549 :}
16.1550 STS.L FPSCR, @-Rn {:
16.1551 + COUNT_INST(I_STSM);
16.1552 check_fpuen();
16.1553 load_reg( R_EAX, Rn );
16.1554 check_walign32( R_EAX );
16.1555 @@ -2565,11 +2778,13 @@
16.1556 sh4_x86.tstate = TSTATE_NONE;
16.1557 :}
16.1558 STS FPUL, Rn {:
16.1559 + COUNT_INST(I_STS);
16.1560 check_fpuen();
16.1561 load_spreg( R_EAX, R_FPUL );
16.1562 store_reg( R_EAX, Rn );
16.1563 :}
16.1564 STS.L FPUL, @-Rn {:
16.1565 + COUNT_INST(I_STSM);
16.1566 check_fpuen();
16.1567 load_reg( R_EAX, Rn );
16.1568 check_walign32( R_EAX );
16.1569 @@ -2581,10 +2796,12 @@
16.1570 sh4_x86.tstate = TSTATE_NONE;
16.1571 :}
16.1572 STS MACH, Rn {:
16.1573 + COUNT_INST(I_STS);
16.1574 load_spreg( R_EAX, R_MACH );
16.1575 store_reg( R_EAX, Rn );
16.1576 :}
16.1577 STS.L MACH, @-Rn {:
16.1578 + COUNT_INST(I_STSM);
16.1579 load_reg( R_EAX, Rn );
16.1580 check_walign32( R_EAX );
16.1581 ADD_imm8s_r32( -4, R_EAX );
16.1582 @@ -2595,10 +2812,12 @@
16.1583 sh4_x86.tstate = TSTATE_NONE;
16.1584 :}
16.1585 STS MACL, Rn {:
16.1586 + COUNT_INST(I_STS);
16.1587 load_spreg( R_EAX, R_MACL );
16.1588 store_reg( R_EAX, Rn );
16.1589 :}
16.1590 STS.L MACL, @-Rn {:
16.1591 + COUNT_INST(I_STSM);
16.1592 load_reg( R_EAX, Rn );
16.1593 check_walign32( R_EAX );
16.1594 ADD_imm8s_r32( -4, R_EAX );
16.1595 @@ -2609,10 +2828,12 @@
16.1596 sh4_x86.tstate = TSTATE_NONE;
16.1597 :}
16.1598 STS PR, Rn {:
16.1599 + COUNT_INST(I_STS);
16.1600 load_spreg( R_EAX, R_PR );
16.1601 store_reg( R_EAX, Rn );
16.1602 :}
16.1603 STS.L PR, @-Rn {:
16.1604 + COUNT_INST(I_STSM);
16.1605 load_reg( R_EAX, Rn );
16.1606 check_walign32( R_EAX );
16.1607 ADD_imm8s_r32( -4, R_EAX );
16.1608 @@ -2623,7 +2844,10 @@
16.1609 sh4_x86.tstate = TSTATE_NONE;
16.1610 :}
16.1611
16.1612 -NOP {: /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */ :}
16.1613 +NOP {:
16.1614 + COUNT_INST(I_NOP);
16.1615 + /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
16.1616 +:}
16.1617 %%
16.1618 sh4_x86.in_delay_slot = DELAY_NONE;
16.1619 return 0;
.