1.1 --- a/test/Makefile	Fri Jan 12 10:16:02 2007 +0000
     1.2 +++ b/test/Makefile	Sun Jan 14 02:53:11 2007 +0000
     1.3 @@ -69,7 +69,7 @@
     1.4  	$(RUNTEST) testta < testta.data < testta2.data < testta3.data < testta4.data < testta5.data
     1.5  	$(RUNTEST) testregs
     1.6  
     1.7 -build-tests: testsh4 testmath testide testta testregs testrend testdisp
     1.8 +build-tests: testsh4 testmath testide testta testregs testrend testdisp testspu
     1.9  
    1.10  testsh4: crt0.so sh4/testsh4.so timer.so interrupt.so \
    1.11  	 sh4/add.so sh4/addc.so sh4/addv.so sh4/and.so sh4/andi.so \
    1.12 @@ -101,6 +101,14 @@
    1.13  	$(SH4CC) $(SH4LDFLAGS) $^  -o $@ $(SH4LIBS)
    1.14  	$(SH4OBJCOPY) testdisp testdisp.bin
    1.15  
    1.16 +testyuv: crt0.so $(SHARED_OBJECTS) testyuv.so pvr.so asic.so lib.so testdata.so timer.so dmac.so
    1.17 +	$(SH4CC) $(SH4LDFLAGS) $^  -o $@ $(SH4LIBS)
    1.18 +	$(SH4OBJCOPY) testyuv testyuv.bin
    1.19 +
    1.20 +testspu: crt0.so $(SHARED_OBJECTS) testspu.so asic.so lib.so testdata.so timer.so dmac.so
    1.21 +	$(SH4CC) $(SH4LDFLAGS) $^  -o $@ $(SH4LIBS)
    1.22 +	$(SH4OBJCOPY) testspu testspu.bin
    1.23 +
    1.24  readdata: crt0.so readdata.so
    1.25  	$(SH4CC) $(SH4LDFLAGS) $^ -o $@ $(SH4LIBS)
    1.26  

     2.1 --- a/test/lib.h	Fri Jan 12 10:16:02 2007 +0000
     2.2 +++ b/test/lib.h	Sun Jan 14 02:53:11 2007 +0000
     2.3 @@ -59,5 +59,6 @@
     2.4  int is_start_pressed();
     2.5  
     2.6  #define CHECK_IEQUALS( a, b ) if( a != b ) { fprintf(stderr, "Assertion failed at %s:%d: expected %08X, but was %08X\n", __FILE__, __LINE__, a, b ); return -1; }
     2.7 +#define DMA_ALIGN(x)   ((void *)((((unsigned int)(x))+0x1F)&0xFFFFFFE0))
     2.8  
     2.9  #endif

     3.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     3.2 +++ b/test/testspu.c	Sun Jan 14 02:53:11 2007 +0000
     3.3 @@ -0,0 +1,137 @@
     3.4 +
     3.5 +#include <stdlib.h>
     3.6 +#include "asic.h"
     3.7 +#include "lib.h"
     3.8 +#include "testdata.h"
     3.9 +
    3.10 +#define SPUBASE 0xA05F7800
    3.11 +#define SPUBASERAM 0x00800000
    3.12 +#define SPUWAIT  (SPUBASE+0x90)
    3.13 +#define SPUMAGIC (SPUBASE+0xBC)
    3.14 +
    3.15 +
    3.16 +#define SPUDMAEXT(x) (SPUBASE+(0x20*(x)))
    3.17 +#define SPUDMAHOST(x) (SPUBASE+(0x20*(x))+0x04)
    3.18 +#define SPUDMASIZE(x) (SPUBASE+(0x20*(x))+0x08)
    3.19 +#define SPUDMADIR(x) (SPUBASE+(0x20*(x))+0x0C)
    3.20 +#define SPUDMAMODE(x) (SPUBASE+(0x20*(x))+0x10)
    3.21 +#define SPUDMACTL1(x) (SPUBASE+(0x20*(x))+0x14)
    3.22 +#define SPUDMACTL2(x) (SPUBASE+(0x20*(x))+0x18)
    3.23 +#define SPUDMASTOP(x) (SPUBASE+(0x20*(x))+0x1C)
    3.24 +
    3.25 +void dump_spu_regs()
    3.26 +{
    3.27 +    fwrite_dump( stderr, (char *)(0xA05F7800), 0x100 );
    3.28 +}    
    3.29 +
    3.30 +int dma_to_spu( int chan, uint32_t target, char *data, uint32_t size )
    3.31 +{
    3.32 +    long_write( SPUWAIT, 0 );
    3.33 +    long_write( SPUMAGIC, 0x4659404f );
    3.34 +    long_write( SPUDMACTL1(chan), 0 );
    3.35 +    long_write( SPUDMACTL2(chan), 0 );
    3.36 +    long_write( SPUDMAHOST(chan), ((uint32_t)data)&0x1FFFFFE0 );
    3.37 +    long_write( SPUDMASIZE(chan), size | 0x80000000 );
    3.38 +    long_write( SPUDMAEXT(chan), target );
    3.39 +    long_write( SPUDMADIR(chan), 0 );
    3.40 +    long_write( SPUDMAMODE(chan), 0 );
    3.41 +    
    3.42 +    long_write( SPUDMACTL1(chan), 1 );
    3.43 +    long_write( SPUDMACTL2(chan), 1 );
    3.44 +    if( asic_wait( EVENT_SPU_DMA0 + chan ) != 0 ) {
    3.45 +	fprintf( stderr, "Timeout waiting for DMA event\n" );
    3.46 +	dump_spu_regs();
    3.47 +	return -1;
    3.48 +    }
    3.49 +    return 0;
    3.50 +}
    3.51 +
    3.52 +int dma_from_spu( int chan, char *data, uint32_t src, uint32_t size )
    3.53 +{
    3.54 +    long_write( SPUWAIT, 0 );
    3.55 +    long_write( SPUMAGIC, 0x4659404f );
    3.56 +    long_write( SPUDMACTL1(chan), 0 );
    3.57 +    long_write( SPUDMACTL2(chan), 0 );
    3.58 +    long_write( SPUDMAHOST(chan), ((uint32_t)data)&0x1FFFFFE0 );
    3.59 +    long_write( SPUDMASIZE(chan), size | 0x80000000 );
    3.60 +    long_write( SPUDMAEXT(chan), src );
    3.61 +    long_write( SPUDMADIR(chan), 1 );
    3.62 +    long_write( SPUDMAMODE(chan), 5 );
    3.63 +    
    3.64 +    long_write( SPUDMACTL1(chan), 1 );
    3.65 +    long_write( SPUDMACTL2(chan), 1 );
    3.66 +    if( asic_wait( EVENT_SPU_DMA0 + chan ) != 0 ) {
    3.67 +	fprintf( stderr, "Timeout waiting for DMA event\n" );
    3.68 +	dump_spu_regs();
    3.69 +	return -1;
    3.70 +    }
    3.71 +    return 0;
    3.72 +}
    3.73 +
    3.74 +#define SPUTARGETADDR (SPUBASERAM+0x10000)
    3.75 +#define SPUTARGET ((char *)(SPUTARGETADDR))
    3.76 +
    3.77 +int test_spu_dma_channel( int chan )
    3.78 +{
    3.79 +    char sampledata1[256+32];
    3.80 +    char sampledata2[256+32];
    3.81 +    char resultdata[256+32];
    3.82 +
    3.83 +    int i;
    3.84 +    char *p1 = DMA_ALIGN(sampledata1), *p2 = DMA_ALIGN(sampledata2);
    3.85 +    char *r = DMA_ALIGN(resultdata);
    3.86 +
    3.87 +    for( i=0; i<256; i++ ) {
    3.88 +	p1[i] = (char)(i*i);
    3.89 +	p2[i] = 256 - i;
    3.90 +    }
    3.91 +
    3.92 +    if( dma_to_spu( chan, SPUTARGETADDR, p1, 256 ) != 0 ) {
    3.93 +	return -1;
    3.94 +    }
    3.95 +
    3.96 +    if( memcmp( p1, SPUTARGET, 256 ) != 0 ) {
    3.97 +	fprintf( stderr, "First data mismatch:\n" );
    3.98 +	fwrite_diff( stderr, p1, 256, SPUTARGET, 256 );
    3.99 +	return -1;
   3.100 +    }
   3.101 +
   3.102 +    if( dma_to_spu( chan, SPUTARGETADDR, p2, 256 ) != 0 ) {
   3.103 +	return -1;
   3.104 +    }
   3.105 +
   3.106 +    if( memcmp( p2, SPUTARGET, 256 ) != 0 ) {
   3.107 +	fprintf( stderr, "Second data mismatch:\n" );
   3.108 +	fwrite_diff( stderr, p2, 256, SPUTARGET, 256 );
   3.109 +	return -1;
   3.110 +    }
   3.111 +
   3.112 +    memset( r, 0, 256 );
   3.113 +    if( dma_from_spu( chan, r, SPUTARGETADDR, 256 ) != 0 ) {
   3.114 +	return -1;
   3.115 +    }
   3.116 +
   3.117 +    if( memcmp( p2, r, 256 ) != 0 ) {
   3.118 +	fprintf( stderr, "Read data mismatch:\n" );
   3.119 +	fwrite_diff( stderr, p2, 256, r, 256 );
   3.120 +	return -1;
   3.121 +    }
   3.122 +}
   3.123 +
   3.124 +
   3.125 +int test_spu_dma()
   3.126 +{
   3.127 +    int i; 
   3.128 +    for( i=0; i<4; i++ ) {
   3.129 +	if( test_spu_dma_channel(i) != 0 ) {
   3.130 +	    return -1;
   3.131 +	}
   3.132 +    }
   3.133 +}
   3.134 +
   3.135 +test_func_t tests[] = { test_spu_dma, NULL };
   3.136 +
   3.137 +int main()
   3.138 +{
   3.139 +    return run_tests(tests);
   3.140 +}