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lxdream.org :: lxdream :: r231:a9e61a96a885
lxdream 0.9.1
released Jun 29
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changeset231:a9e61a96a885
parent230:dc79fdf5257c
child232:9c8ef78376ed
authornkeynes
dateTue Sep 26 11:05:38 2006 +0000 (14 years ago)
Add BT, BT/S, CMP/EQ, CMP/GE, CMP/GT, CMP/HI, CMP/HS tests
Add general slot-illegal exception test
test/Makefile
test/sh4/add.s
test/sh4/addc.s
test/sh4/addv.s
test/sh4/and.s
test/sh4/bf.s
test/sh4/bt.s
test/sh4/cmp.s
test/sh4/excslot.s
test/sh4/inc.s
test/sh4/testsh4.c
1.1 --- a/test/Makefile Mon Sep 25 12:20:58 2006 +0000
1.2 +++ b/test/Makefile Tue Sep 26 11:05:38 2006 +0000
1.3 @@ -73,7 +73,8 @@
1.4
1.5 testsh4: crt0.so sh4/testsh4.so timer.so interrupt.so \
1.6 sh4/add.so sh4/addc.so sh4/addv.so sh4/and.so sh4/andi.so \
1.7 - sh4/bf.so
1.8 + sh4/bf.so sh4/bt.so sh4/cmp.so \
1.9 + sh4/excslot.so
1.10 $(SH4CC) $(SH4LDFLAGS) $^ -o $@ $(SH4LIBS)
1.11 $(SH4OBJCOPY) testsh4 testsh4.bin
1.12
2.1 --- a/test/sh4/add.s Mon Sep 25 12:20:58 2006 +0000
2.2 +++ b/test/sh4/add.s Tue Sep 26 11:05:38 2006 +0000
2.3 @@ -69,17 +69,17 @@
2.4
2.5 test_add_5: ! test carry neither used nor set (ala ADDC)
2.6 add #1, r12
2.7 - mov.l test_add_5_op1, r8
2.8 - mov.l test_add_5_op2, r9
2.9 - stc sr, r10
2.10 + mov.l test_add_5_op1, r4
2.11 + mov.l test_add_5_op2, r5
2.12 + stc sr, r6
2.13 xor r0,r0
2.14 add #1, r0
2.15 stc sr, r1
2.16 - or r0,r10
2.17 - ldc r10, sr
2.18 - add r9,r8
2.19 - mov.l test_add_5_result, r11
2.20 - cmp/eq r11, r8
2.21 + or r0,r6
2.22 + ldc r6, sr
2.23 + add r5,r4
2.24 + mov.l test_add_5_result, r7
2.25 + cmp/eq r7, r4
2.26 bt test_add_5_b
2.27 fail test_add_str_k
2.28 bra test_add_6
3.1 --- a/test/sh4/addc.s Mon Sep 25 12:20:58 2006 +0000
3.2 +++ b/test/sh4/addc.s Tue Sep 26 11:05:38 2006 +0000
3.3 @@ -99,17 +99,17 @@
3.4
3.5 test_addc_5: ! test carry used and cleared
3.6 add #1, r12
3.7 - mov.l test_addc_5_op1, r8
3.8 - mov.l test_addc_5_op2, r9
3.9 - stc sr, r10
3.10 + mov.l test_addc_5_op1, r4
3.11 + mov.l test_addc_5_op2, r5
3.12 + stc sr, r6
3.13 xor r0,r0
3.14 add #1, r0
3.15 - or r0,r10
3.16 - ldc r10, sr
3.17 - addc r9,r8
3.18 + or r0,r6
3.19 + ldc r6, sr
3.20 + addc r5,r4
3.21 stc sr, r1
3.22 - mov.l test_addc_5_result, r11
3.23 - cmp/eq r11, r8
3.24 + mov.l test_addc_5_result, r7
3.25 + cmp/eq r7, r4
3.26 bt test_addc_5_b
3.27 fail test_addc_str_k
3.28 bra test_addc_6
4.1 --- a/test/sh4/addv.s Mon Sep 25 12:20:58 2006 +0000
4.2 +++ b/test/sh4/addv.s Tue Sep 26 11:05:38 2006 +0000
4.3 @@ -37,6 +37,7 @@
4.4 nop
4.5
4.6 test_addv_end:
4.7 + mov.l @r15+, r11
4.8 end_test test_addv_str_k
4.9
4.10 .align 4
5.1 --- a/test/sh4/and.s Mon Sep 25 12:20:58 2006 +0000
5.2 +++ b/test/sh4/and.s Tue Sep 26 11:05:38 2006 +0000
5.3 @@ -39,6 +39,7 @@
5.4 nop
5.5
5.6 test_and_end:
5.7 + mov.l @r15+, r11
5.8 end_test test_and_str_k
5.9
5.10 .align 4
6.1 --- a/test/sh4/bf.s Mon Sep 25 12:20:58 2006 +0000
6.2 +++ b/test/sh4/bf.s Tue Sep 26 11:05:38 2006 +0000
6.3 @@ -42,6 +42,7 @@
6.4 fail test_bf_str_k
6.5 bra test_bf_4
6.6 nop
6.7 +
6.8 test_bf_4: ! Test branch not taken w/ delay
6.9 add #1, r12
6.10 setc
6.11 @@ -74,19 +75,63 @@
6.12 bt test_bf_6
6.13 fail test_bf_str_k
6.14
6.15 -test_bf_6:
6.16 +test_bf_6: ! Test back-branch taken w/ delay
6.17 + add #1, r12
6.18 + clc
6.19 + xor r0, r0
6.20 + bra test_bf_6_b
6.21 + nop
6.22 + fail test_bf_str_k
6.23 + bra test_bf_7
6.24 + nop
6.25 + add #1, r13
6.26 +test_bf_6_c:
6.27 + mov #1, r1
6.28 + cmp/eq r0, r1
6.29 + bt test_bf_7
6.30 + fail test_bf_str_k
6.31 + bra test_bf_7
6.32 + nop
6.33 + fail test_bf_str_k
6.34 + bra test_bf_7
6.35 + nop
6.36 + add #1, r13
6.37 +test_bf_6_b:
6.38 + nop
6.39 + bf/s test_bf_6_c
6.40 + add #1, r0
6.41 + fail test_bf_str_k
6.42 + bra test_bf_7
6.43 + nop
6.44 +
6.45 +test_bf_7:
6.46 add #1, r12
6.47 expect_exc 0x000001A0 ! BF is slot illegal
6.48 -test_bf_6_exc:
6.49 - bra test_bf_6_b
6.50 - bf test_bf_6_b
6.51 - assert_exc_caught test_bf_str_k test_bf_6_exc
6.52 +test_bf_7_exc:
6.53 + bra test_bf_7_b
6.54 + bf test_bf_7_b
6.55 + assert_exc_caught test_bf_str_k test_bf_7_exc
6.56 + bra test_bf_8
6.57 + nop
6.58 +test_bf_7_b:
6.59 +test_bf_7_c:
6.60 + fail test_bf_str_k
6.61 +
6.62 +test_bf_8:
6.63 + add #1, r12
6.64 + expect_exc 0x000001A0 ! BF/S is slot illegal
6.65 +test_bf_8_exc:
6.66 + bra test_bf_8_b
6.67 + bf/s test_bf_8_b
6.68 + nop
6.69 + assert_exc_caught test_bf_str_k test_bf_8_exc
6.70 bra test_bf_end
6.71 nop
6.72 -test_bf_6_b:
6.73 -test_bf_6_c:
6.74 +test_bf_8_b:
6.75 +test_bf_8_c:
6.76 fail test_bf_str_k
6.77 -
6.78 +
6.79 +
6.80 test_bf_end:
6.81 end_test test_bf_str_k
6.82
7.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
7.2 +++ b/test/sh4/bt.s Tue Sep 26 11:05:38 2006 +0000
7.3 @@ -0,0 +1,140 @@
7.4 +.section .text
7.5 +.include "sh4/inc.s"
7.6 +!
7.7 +! Test bt pcrel
7.8 +! Test bt/s pcrel
7.9 +
7.10 +.global _test_bt
7.11 +_test_bt:
7.12 + start_test
7.13 +
7.14 +test_bt_1: ! Test branch not taken
7.15 + add #1, r12
7.16 + clc
7.17 + bt test_bt_1_b
7.18 + bra test_bt_2
7.19 + nop
7.20 +test_bt_1_b:
7.21 + fail test_bt_str_k
7.22 +
7.23 +test_bt_2: ! Test branch taken
7.24 + add #1, r12
7.25 + setc
7.26 + bt test_bt_3
7.27 + fail test_bt_str_k
7.28 +
7.29 +test_bt_3: ! Test branch taken (backwards)
7.30 + add #1, r12
7.31 + setc
7.32 + bra test_bt_3_b
7.33 + nop
7.34 + fail test_bt_str_k
7.35 + bra test_bt_4
7.36 +test_bt_3_c:
7.37 + nop
7.38 + bra test_bt_4
7.39 + nop
7.40 + fail test_bt_str_k
7.41 + bra test_bt_4
7.42 +test_bt_3_b:
7.43 + nop
7.44 + bt test_bt_3_c
7.45 + fail test_bt_str_k
7.46 + bra test_bt_4
7.47 + nop
7.48 +test_bt_4: ! Test branch not taken w/ delay
7.49 + add #1, r12
7.50 + clc
7.51 + xor r0, r0
7.52 + bt/s test_bt_4_b
7.53 + add #1, r0
7.54 + bra test_bt_4_c
7.55 + nop
7.56 +test_bt_4_b:
7.57 + fail test_bt_str_k
7.58 + bra test_bt_5
7.59 + nop
7.60 +test_bt_4_c:
7.61 + xor r1,r1
7.62 + add #1, r1
7.63 + cmp/eq r0, r1
7.64 +
7.65 +test_bt_5: ! Test branch taken w/ delay
7.66 + add #1, r12
7.67 + setc
7.68 + xor r0,r0
7.69 + bt/s test_bt_5_b
7.70 + add #1, r0
7.71 + fail test_bt_str_k
7.72 + bra test_bt_6
7.73 +test_bt_5_b:
7.74 + xor r1,r1
7.75 + add #1, r1
7.76 + cmp/eq r0,r1
7.77 + bt test_bt_6
7.78 + fail test_bt_str_k
7.79 +
7.80 +test_bt_6: ! Test back-branch taken w/ delay
7.81 + add #1, r12
7.82 + setc
7.83 + xor r0, r0
7.84 + bra test_bt_6_b
7.85 + nop
7.86 + fail test_bt_str_k
7.87 + bra test_bt_7
7.88 + nop
7.89 + add #1, r13
7.90 +test_bt_6_c:
7.91 + mov #1, r1
7.92 + cmp/eq r0, r1
7.93 + bt test_bt_7
7.94 + fail test_bt_str_k
7.95 + bra test_bt_7
7.96 + nop
7.97 + fail test_bt_str_k
7.98 + bra test_bt_7
7.99 +test_bt_6_b:
7.100 + nop
7.101 + bt/s test_bt_6_c
7.102 + add #1, r0
7.103 + fail test_bt_str_k
7.104 + bra test_bt_7
7.105 + nop
7.106 +
7.107 +test_bt_7:
7.108 + add #1, r12
7.109 + expect_exc 0x000001A0 ! BT is slot illegal
7.110 +test_bt_7_exc:
7.111 + bra test_bt_7_b
7.112 + bt test_bt_7_b
7.113 + assert_exc_caught test_bt_str_k test_bt_7_exc
7.114 + bra test_bt_8
7.115 + nop
7.116 +test_bt_7_b:
7.117 +test_bt_7_c:
7.118 + fail test_bt_str_k
7.119 +
7.120 +test_bt_8:
7.121 + add #1, r12
7.122 + expect_exc 0x000001A0 ! BT/S is slot illegal
7.123 +test_bt_8_exc:
7.124 + bra test_bt_8_b
7.125 + bt/s test_bt_8_b
7.126 + nop
7.127 + assert_exc_caught test_bt_str_k test_bt_8_exc
7.128 + bra test_bt_end
7.129 + nop
7.130 +test_bt_8_b:
7.131 +test_bt_8_c:
7.132 + fail test_bt_str_k
7.133 +
7.134 +test_bt_end:
7.135 + end_test test_bt_str_k
7.136 +
7.137 +test_bt_str:
7.138 + .string "BT"
7.139 +
7.140 +.align 4
7.141 +test_bt_str_k:
7.142 + .long test_bt_str
7.143 +
7.144 \ No newline at end of file
8.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
8.2 +++ b/test/sh4/cmp.s Tue Sep 26 11:05:38 2006 +0000
8.3 @@ -0,0 +1,198 @@
8.4 +.section .text
8.5 +.include "sh4/inc.s"
8.6 +!
8.7 +! Test cmp/xx
8.8 +
8.9 +.global _test_cmp
8.10 +_test_cmp:
8.11 + start_test
8.12 +
8.13 +test_cmpeq_1: ! CMP/EQ 0, 0
8.14 + add #1, r12
8.15 + xor r0, r0
8.16 + xor r1, r1
8.17 + cmp/eq r0, r1
8.18 + bt test_cmpeq_2
8.19 + fail test_cmpeq_str_k
8.20 +
8.21 +test_cmpeq_2: ! CMP/EQ !0, 0
8.22 + add #1, r12
8.23 + mov #50, r2
8.24 + cmp/eq r1, r2
8.25 + bf test_cmpeq_3
8.26 + fail test_cmpeq_str_k
8.27 +
8.28 +test_cmpeq_3: ! CMP/EQ -50, 50
8.29 + add #1, r12
8.30 + mov #-50, r3
8.31 + cmp/eq r3, r2
8.32 + bf test_cmpeq_4
8.33 + fail test_cmpeq_str_k
8.34 +
8.35 +test_cmpeq_4: ! CMP/EQ 50, 50
8.36 + add #1, r12
8.37 + mov #50, r6
8.38 + cmp/eq r6, r2
8.39 + bt test_cmpeq_5
8.40 + fail test_cmpeq_str_k
8.41 +
8.42 +test_cmpeq_5:
8.43 +
8.44 +test_cmpeq_6:
8.45 +
8.46 +test_cmpge_1:
8.47 + add #1, r12
8.48 + cmp/ge r2, r6
8.49 + bt test_cmpge_2
8.50 + fail test_cmpge_str_k
8.51 +
8.52 +test_cmpge_2:
8.53 + add #1, r12
8.54 + cmp/ge r3, r2
8.55 + bt test_cmpge_3
8.56 + fail test_cmpge_str_k
8.57 +
8.58 +test_cmpge_3:
8.59 + add #1, r12
8.60 + cmp/ge r2, r3
8.61 + bf test_cmpge_4
8.62 + fail test_cmpge_str_k
8.63 +
8.64 +test_cmpge_4:
8.65 + add #1, r12
8.66 + mov #75, r5
8.67 + cmp/ge r2, r5
8.68 + bt test_cmpge_5
8.69 + fail test_cmpge_str_k
8.70 +
8.71 +test_cmpge_5:
8.72 + add #1, r12
8.73 + cmp/ge r5, r2
8.74 + bf test_cmpgt_1
8.75 + fail test_cmpge_str_k
8.76 +
8.77 +test_cmpgt_1:
8.78 + add #1, r12
8.79 + cmp/gt r2, r6
8.80 + bf test_cmpgt_2
8.81 + fail test_cmpgt_str_k
8.82 +
8.83 +test_cmpgt_2:
8.84 + add #1, r12
8.85 + cmp/gt r3, r2
8.86 + bt test_cmpgt_3
8.87 + fail test_cmpgt_str_k
8.88 +
8.89 +test_cmpgt_3:
8.90 + add #1, r12
8.91 + cmp/gt r2, r3
8.92 + bf test_cmpgt_4
8.93 + fail test_cmpgt_str_k
8.94 +
8.95 +test_cmpgt_4:
8.96 + add #1, r12
8.97 + mov #75, r5
8.98 + cmp/gt r2, r5
8.99 + bt test_cmpgt_5
8.100 + fail test_cmpgt_str_k
8.101 +
8.102 +test_cmpgt_5:
8.103 + add #1, r12
8.104 + cmp/gt r5, r2
8.105 + bf test_cmphi_1
8.106 + fail test_cmpgt_str_k
8.107 +
8.108 +
8.109 +test_cmphi_1:
8.110 + add #1, r12
8.111 + cmp/hi r2, r6
8.112 + bf test_cmphi_2
8.113 + fail test_cmphi_str_k
8.114 +
8.115 +test_cmphi_2:
8.116 + add #1, r12
8.117 + cmp/hi r3, r2
8.118 + bf test_cmphi_3
8.119 + fail test_cmphi_str_k
8.120 +
8.121 +test_cmphi_3:
8.122 + add #1, r12
8.123 + cmp/hi r2, r3
8.124 + bt test_cmphi_4
8.125 + fail test_cmphi_str_k
8.126 +
8.127 +test_cmphi_4:
8.128 + add #1, r12
8.129 + mov #75, r5
8.130 + cmp/hi r2, r5
8.131 + bt test_cmphi_5
8.132 + fail test_cmphi_str_k
8.133 +
8.134 +test_cmphi_5:
8.135 + add #1, r12
8.136 + cmp/hi r5, r2
8.137 + bf test_cmphs_1
8.138 + fail test_cmphi_str_k
8.139 +
8.140 +test_cmphs_1:
8.141 + add #1, r12
8.142 + cmp/hs r2, r6
8.143 + bt test_cmphs_2
8.144 + fail test_cmphs_str_k
8.145 +
8.146 +test_cmphs_2:
8.147 + add #1, r12
8.148 + cmp/hs r3, r2
8.149 + bf test_cmphs_3
8.150 + fail test_cmphs_str_k
8.151 +
8.152 +test_cmphs_3:
8.153 + add #1, r12
8.154 + cmp/hs r2, r3
8.155 + bt test_cmphs_4
8.156 + fail test_cmphs_str_k
8.157 +
8.158 +test_cmphs_4:
8.159 + add #1, r12
8.160 + mov #75, r5
8.161 + cmp/hs r2, r5
8.162 + bt test_cmphs_5
8.163 + fail test_cmphs_str_k
8.164 +
8.165 +test_cmphs_5:
8.166 + add #1, r12
8.167 + cmp/hs r5, r2
8.168 + bf test_cmppl_1
8.169 + fail test_cmphs_str_k
8.170 +
8.171 +test_cmppl_1:
8.172 +
8.173 +test_cmp_end:
8.174 + end_test test_cmp_str_k
8.175 +test_cmpeq_str:
8.176 + .string "CMP/EQ"
8.177 +test_cmpge_str:
8.178 + .string "CMP/GE"
8.179 +test_cmpgt_str:
8.180 + .string "CMP/GT"
8.181 +test_cmphi_str:
8.182 + .string "CMP/HI"
8.183 +test_cmphs_str:
8.184 + .string "CMP/HS"
8.185 +test_cmp_str:
8.186 + .string "CMP"
8.187 +
8.188 +.align 4
8.189 +test_cmp_str_k:
8.190 + .long test_cmp_str
8.191 +test_cmpeq_str_k:
8.192 + .long test_cmpeq_str
8.193 +test_cmpge_str_k:
8.194 + .long test_cmpge_str
8.195 +test_cmpgt_str_k:
8.196 + .long test_cmpgt_str
8.197 +test_cmphi_str_k:
8.198 + .long test_cmphi_str
8.199 +test_cmphs_str_k:
8.200 + .long test_cmphs_str
8.201 +
8.202 \ No newline at end of file
9.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
9.2 +++ b/test/sh4/excslot.s Tue Sep 26 11:05:38 2006 +0000
9.3 @@ -0,0 +1,189 @@
9.4 +.section .text
9.5 +.include "sh4/inc.s"
9.6 +!
9.7 +! Test for all cases that raise a slot-illegal exception (according to the SH4
9.8 +! manual). See Page 103 of the Hitachi manual
9.9 +
9.10 +.global _test_slot_illegal
9.11 +_test_slot_illegal:
9.12 + start_test
9.13 +
9.14 +! First the easy ones - instructions not permitted in delay slots at any
9.15 +! time:
9.16 +! JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF, BT/S, BF/S, TRAPA,
9.17 +! LDC (to SR), MOV pcrel, MOVA
9.18 +!
9.19 +! Note that the tests use BSR as the branch instruction, and assume it
9.20 +! functions correctly.
9.21 +
9.22 +test_slot_1: !JMP
9.23 + add #1, r12
9.24 + expect_exc 0x000001A0
9.25 +test_slot_1_pc:
9.26 + bsr test_slot_fail
9.27 + jmp @r3
9.28 + assert_exc_caught test_slot_str_k1 test_slot_1_pc
9.29 +
9.30 +test_slot_2: ! JSR
9.31 + add #1, r12
9.32 + expect_exc 0x000001A0
9.33 +test_slot_2_pc:
9.34 + bsr test_slot_fail
9.35 + jsr @r3
9.36 + assert_exc_caught test_slot_str_k1 test_slot_2_pc
9.37 + bra test_slot_3
9.38 + nop
9.39 +test_slot_str_k1:
9.40 + .long test_slot_str
9.41 +
9.42 +test_slot_3: ! BRA
9.43 + add #1, r12
9.44 + expect_exc 0x000001A0
9.45 +test_slot_3_pc:
9.46 + bsr test_slot_fail
9.47 + bra test_slot_fail
9.48 + assert_exc_caught test_slot_str_k test_slot_3_pc
9.49 +
9.50 +test_slot_4: ! BRAF
9.51 + add #1, r12
9.52 + expect_exc 0x000001A0
9.53 +test_slot_4_pc:
9.54 + bsr test_slot_fail
9.55 + braf r3
9.56 + assert_exc_caught test_slot_str_k test_slot_4_pc
9.57 +
9.58 +test_slot_5: ! BSR
9.59 + add #1, r12
9.60 + expect_exc 0x000001A0
9.61 +test_slot_5_pc:
9.62 + bsr test_slot_fail
9.63 + bsr test_slot_fail
9.64 + assert_exc_caught test_slot_str_k test_slot_5_pc
9.65 +
9.66 +test_slot_6: ! BSRF
9.67 + add #1, r12
9.68 + expect_exc 0x000001A0
9.69 +test_slot_6_pc:
9.70 + bsr test_slot_fail
9.71 + bsrf r3
9.72 + assert_exc_caught test_slot_str_k test_slot_6_pc
9.73 +
9.74 +test_slot_7: ! BF
9.75 + add #1, r12
9.76 + expect_exc 0x000001A0
9.77 +test_slot_7_pc:
9.78 + bsr test_slot_fail
9.79 + bf test_slot_7_fail
9.80 +test_slot_7_fail:
9.81 + assert_exc_caught test_slot_str_k test_slot_7_pc
9.82 +
9.83 +test_slot_8: ! BT
9.84 + add #1, r12
9.85 + expect_exc 0x000001A0
9.86 +test_slot_8_pc:
9.87 + bsr test_slot_fail
9.88 + bt test_slot_8_fail
9.89 +test_slot_8_fail:
9.90 + assert_exc_caught test_slot_str_k test_slot_8_pc
9.91 +
9.92 +test_slot_9: ! BF/S
9.93 + add #1, r12
9.94 + expect_exc 0x000001A0
9.95 +test_slot_9_pc:
9.96 + bsr test_slot_fail
9.97 + bf/s test_slot_9_fail
9.98 +test_slot_9_fail:
9.99 + assert_exc_caught test_slot_str_k test_slot_9_pc
9.100 +
9.101 +test_slot_10: ! BT/S
9.102 + add #1, r12
9.103 + expect_exc 0x000001A0
9.104 +test_slot_10_pc:
9.105 + bsr test_slot_fail
9.106 + bt/s test_slot_10_fail
9.107 +test_slot_10_fail:
9.108 + assert_exc_caught test_slot_str_k test_slot_10_pc
9.109 +
9.110 +test_slot_11: ! TRAPA
9.111 + add #1, r12
9.112 + expect_exc 0x000001A0
9.113 +test_slot_11_pc:
9.114 + bsr test_slot_fail
9.115 + trapa #12
9.116 + assert_exc_caught test_slot_str_k test_slot_11_pc
9.117 +
9.118 +test_slot_12: ! LDC r0, sr
9.119 + add #1, r12
9.120 + expect_exc 0x000001A0
9.121 + stc sr, r0
9.122 +test_slot_12_pc:
9.123 + bsr test_slot_fail
9.124 + ldc r0, sr
9.125 + assert_exc_caught test_slot_str_k test_slot_12_pc
9.126 +
9.127 +test_slot_13: ! LDC @r0, sr
9.128 + add #1, r12
9.129 + expect_exc 0x000001A0
9.130 + stc sr, r1
9.131 + mova test_slot_13_temp, r0
9.132 + mov.l r1, @r0
9.133 +test_slot_13_pc:
9.134 + bsr test_slot_fail
9.135 + ldc.l @r0+, sr
9.136 + assert_exc_caught test_slot_str_k test_slot_13_pc
9.137 + bra test_slot_14
9.138 + nop
9.139 +test_slot_13_temp:
9.140 + .long 0
9.141 +
9.142 +test_slot_14: ! MOVA
9.143 + add #1, r12
9.144 + expect_exc 0x000001A0
9.145 +test_slot_14_pc:
9.146 + bsr test_slot_fail
9.147 + mova test_slot_15, r0
9.148 + assert_exc_caught test_slot_str_k test_slot_14_pc
9.149 +
9.150 +test_slot_15: ! MOV.W pcrel, Rn
9.151 + add #1, r12
9.152 + expect_exc 0x000001A0
9.153 +test_slot_15_pc:
9.154 + bsr test_slot_fail
9.155 + mov.w test_slot_16, r0
9.156 + assert_exc_caught test_slot_str_k test_slot_15_pc
9.157 +
9.158 +test_slot_16: ! MOV.L pcrel, Rn
9.159 + add #1, r12
9.160 + expect_exc 0x000001A0
9.161 +test_slot_16_pc:
9.162 + bsr test_slot_fail
9.163 + mov.l test_slot_str_k, r0
9.164 + assert_exc_caught test_slot_str_k test_slot_16_pc
9.165 +
9.166 +test_slot_17: ! "Undefined" 0xFFFD
9.167 + add #1, r12
9.168 + expect_exc 0x000001A0
9.169 +test_slot_17_pc:
9.170 + bsr test_slot_fail
9.171 + .word 0xFFFD
9.172 + assert_exc_caught test_slot_str_k test_slot_17_pc
9.173 +
9.174 +!
9.175 +! Ok now the privilege tests. These should raise SLOT_ILLEGAL when executed
9.176 +! in a delay slot (otherwise it's GENERAL_ILLEGAL)
9.177 +! TODO: need mode-switch code
9.178 +
9.179 +test_slot_end:
9.180 + end_test test_slot_str_k
9.181 +
9.182 +! Returns after the delay slot, which should hit the "no exception" test
9.183 +test_slot_fail:
9.184 + rts
9.185 + nop
9.186 +
9.187 +test_slot_str_k:
9.188 + .long test_slot_str
9.189 +test_slot_str:
9.190 + .string "SLOT-ILLEGAL"
9.191 +
9.192 +
9.193 \ No newline at end of file
10.1 --- a/test/sh4/inc.s Mon Sep 25 12:20:58 2006 +0000
10.2 +++ b/test/sh4/inc.s Tue Sep 26 11:05:38 2006 +0000
10.3 @@ -186,7 +186,7 @@
10.4 .endm
10.5
10.6 .macro assert_exc_caught testname, expectpc
10.7 -LOCAL L1, L2
10.8 +LOCAL L1, L2, L3
10.9 mov.l L1, r3
10.10 mov.l \testname, r4
10.11 mov r12, r5
11.1 --- a/test/sh4/testsh4.c Mon Sep 25 12:20:58 2006 +0000
11.2 +++ b/test/sh4/testsh4.c Tue Sep 26 11:05:38 2006 +0000
11.3 @@ -5,7 +5,7 @@
11.4
11.5 int test_print_result( char *testname, int failed, int total )
11.6 {
11.7 - fprintf( stderr, "%s: %d/%d tests passed\n", testname, total-failed, total );
11.8 + fprintf( stdout, "%s: %d/%d tests passed\n", testname, total-failed, total );
11.9 total_tests += total;
11.10 total_fails += failed;
11.11 return failed;
11.12 @@ -44,6 +44,7 @@
11.13
11.14 int main()
11.15 {
11.16 + fprintf( stdout, "Instruction tests...\n" );
11.17 install_interrupt_handler();
11.18 test_add();
11.19 test_addc();
11.20 @@ -51,8 +52,16 @@
11.21 test_and();
11.22 test_andi();
11.23 test_bf();
11.24 + test_bt();
11.25 + test_cmp();
11.26 + fprintf( stdout, "--> %d/%d instruction tests passed (%d%%)\n\n",
11.27 + total_tests-total_fails, total_tests,
11.28 + ((total_tests-total_fails)*100)/total_tests );
11.29 +
11.30 + fprintf( stdout, "Exception tests...\n" );
11.31 + test_slot_illegal();
11.32 remove_interrupt_handler();
11.33
11.34 - fprintf( stderr, "Total: %d/%d tests passed (%d%%)\n", total_tests-total_fails,
11.35 + fprintf( stdout, "Total: %d/%d tests passed (%d%%)\n", total_tests-total_fails,
11.36 total_tests, ((total_tests-total_fails)*100)/total_tests );
11.37 }
.