lxdream 0.9.1revision 231:a9e61a96a885
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raw | bz2 | zip | gz | changeset | 231:a9e61a96a885 |
| parent | 230:dc79fdf5257c |
| child | 232:9c8ef78376ed |
| author | nkeynes |
| date | Tue Sep 26 11:05:38 2006 +0000 (16 years ago) |
Add BT, BT/S, CMP/EQ, CMP/GE, CMP/GT, CMP/HI, CMP/HS tests
Add general slot-illegal exception test
Add general slot-illegal exception test
 | test/Makefile | view | annotate | diff | log | |
| test/sh4/add.s | view | annotate | diff | log | |
| test/sh4/addc.s | view | annotate | diff | log | |
| test/sh4/addv.s | view | annotate | diff | log | |
| test/sh4/and.s | view | annotate | diff | log | |
| test/sh4/bf.s | view | annotate | diff | log | |
| test/sh4/bt.s | view | annotate | diff | log | |
| test/sh4/cmp.s | view | annotate | diff | log | |
| test/sh4/excslot.s | view | annotate | diff | log | |
| test/sh4/inc.s | view | annotate | diff | log | |
| test/sh4/testsh4.c | view | annotate | diff | log |
1.1 --- a/test/Makefile Mon Sep 25 12:20:58 2006 +00001.2 +++ b/test/Makefile Tue Sep 26 11:05:38 2006 +00001.3 @@ -73,7 +73,8 @@1.5 testsh4: crt0.so sh4/testsh4.so timer.so interrupt.so \1.6 sh4/add.so sh4/addc.so sh4/addv.so sh4/and.so sh4/andi.so \1.7 - sh4/bf.so1.8 + sh4/bf.so sh4/bt.so sh4/cmp.so \1.9 + sh4/excslot.so1.10 $(SH4CC) $(SH4LDFLAGS) $^ -o $@ $(SH4LIBS)1.11 $(SH4OBJCOPY) testsh4 testsh4.bin
2.1 --- a/test/sh4/add.s Mon Sep 25 12:20:58 2006 +00002.2 +++ b/test/sh4/add.s Tue Sep 26 11:05:38 2006 +00002.3 @@ -69,17 +69,17 @@2.5 test_add_5: ! test carry neither used nor set (ala ADDC)2.6 add #1, r122.7 - mov.l test_add_5_op1, r82.8 - mov.l test_add_5_op2, r92.9 - stc sr, r102.10 + mov.l test_add_5_op1, r42.11 + mov.l test_add_5_op2, r52.12 + stc sr, r62.13 xor r0,r02.14 add #1, r02.15 stc sr, r12.16 - or r0,r102.17 - ldc r10, sr2.18 - add r9,r82.19 - mov.l test_add_5_result, r112.20 - cmp/eq r11, r82.21 + or r0,r62.22 + ldc r6, sr2.23 + add r5,r42.24 + mov.l test_add_5_result, r72.25 + cmp/eq r7, r42.26 bt test_add_5_b2.27 fail test_add_str_k2.28 bra test_add_6
3.1 --- a/test/sh4/addc.s Mon Sep 25 12:20:58 2006 +00003.2 +++ b/test/sh4/addc.s Tue Sep 26 11:05:38 2006 +00003.3 @@ -99,17 +99,17 @@3.5 test_addc_5: ! test carry used and cleared3.6 add #1, r123.7 - mov.l test_addc_5_op1, r83.8 - mov.l test_addc_5_op2, r93.9 - stc sr, r103.10 + mov.l test_addc_5_op1, r43.11 + mov.l test_addc_5_op2, r53.12 + stc sr, r63.13 xor r0,r03.14 add #1, r03.15 - or r0,r103.16 - ldc r10, sr3.17 - addc r9,r83.18 + or r0,r63.19 + ldc r6, sr3.20 + addc r5,r43.21 stc sr, r13.22 - mov.l test_addc_5_result, r113.23 - cmp/eq r11, r83.24 + mov.l test_addc_5_result, r73.25 + cmp/eq r7, r43.26 bt test_addc_5_b3.27 fail test_addc_str_k3.28 bra test_addc_6
4.1 --- a/test/sh4/addv.s Mon Sep 25 12:20:58 2006 +00004.2 +++ b/test/sh4/addv.s Tue Sep 26 11:05:38 2006 +00004.3 @@ -37,6 +37,7 @@4.4 nop4.6 test_addv_end:4.7 + mov.l @r15+, r114.8 end_test test_addv_str_k4.10 .align 4
5.1 --- a/test/sh4/and.s Mon Sep 25 12:20:58 2006 +00005.2 +++ b/test/sh4/and.s Tue Sep 26 11:05:38 2006 +00005.3 @@ -39,6 +39,7 @@5.4 nop5.6 test_and_end:5.7 + mov.l @r15+, r115.8 end_test test_and_str_k5.10 .align 4
6.1 --- a/test/sh4/bf.s Mon Sep 25 12:20:58 2006 +00006.2 +++ b/test/sh4/bf.s Tue Sep 26 11:05:38 2006 +00006.3 @@ -42,6 +42,7 @@6.4 fail test_bf_str_k6.5 bra test_bf_46.6 nop6.7 +6.8 test_bf_4: ! Test branch not taken w/ delay6.9 add #1, r126.10 setc6.11 @@ -74,19 +75,63 @@6.12 bt test_bf_66.13 fail test_bf_str_k6.15 -test_bf_6:6.16 +test_bf_6: ! Test back-branch taken w/ delay6.17 + add #1, r126.18 + clc6.19 + xor r0, r06.20 + bra test_bf_6_b6.21 + nop6.22 + fail test_bf_str_k6.23 + bra test_bf_76.24 + nop6.25 + add #1, r136.26 +test_bf_6_c:6.27 + mov #1, r16.28 + cmp/eq r0, r16.29 + bt test_bf_76.30 + fail test_bf_str_k6.31 + bra test_bf_76.32 + nop6.33 + fail test_bf_str_k6.34 + bra test_bf_76.35 + nop6.36 + add #1, r136.37 +test_bf_6_b:6.38 + nop6.39 + bf/s test_bf_6_c6.40 + add #1, r06.41 + fail test_bf_str_k6.42 + bra test_bf_76.43 + nop6.44 +6.45 +test_bf_7:6.46 add #1, r126.47 expect_exc 0x000001A0 ! BF is slot illegal6.48 -test_bf_6_exc:6.49 - bra test_bf_6_b6.50 - bf test_bf_6_b6.51 - assert_exc_caught test_bf_str_k test_bf_6_exc6.52 +test_bf_7_exc:6.53 + bra test_bf_7_b6.54 + bf test_bf_7_b6.55 + assert_exc_caught test_bf_str_k test_bf_7_exc6.56 + bra test_bf_86.57 + nop6.58 +test_bf_7_b:6.59 +test_bf_7_c:6.60 + fail test_bf_str_k6.61 +6.62 +test_bf_8:6.63 + add #1, r126.64 + expect_exc 0x000001A0 ! BF/S is slot illegal6.65 +test_bf_8_exc:6.66 + bra test_bf_8_b6.67 + bf/s test_bf_8_b6.68 + nop6.69 + assert_exc_caught test_bf_str_k test_bf_8_exc6.70 bra test_bf_end6.71 nop6.72 -test_bf_6_b:6.73 -test_bf_6_c:6.74 +test_bf_8_b:6.75 +test_bf_8_c:6.76 fail test_bf_str_k6.77 -6.78 +6.79 +6.80 test_bf_end:6.81 end_test test_bf_str_k
7.1 --- /dev/null Thu Jan 01 00:00:00 1970 +00007.2 +++ b/test/sh4/bt.s Tue Sep 26 11:05:38 2006 +00007.3 @@ -0,0 +1,140 @@7.4 +.section .text7.5 +.include "sh4/inc.s"7.6 +!7.7 +! Test bt pcrel7.8 +! Test bt/s pcrel7.9 +7.10 +.global _test_bt7.11 +_test_bt:7.12 + start_test7.13 +7.14 +test_bt_1: ! Test branch not taken7.15 + add #1, r127.16 + clc7.17 + bt test_bt_1_b7.18 + bra test_bt_27.19 + nop7.20 +test_bt_1_b:7.21 + fail test_bt_str_k7.22 +7.23 +test_bt_2: ! Test branch taken7.24 + add #1, r127.25 + setc7.26 + bt test_bt_37.27 + fail test_bt_str_k7.28 +7.29 +test_bt_3: ! Test branch taken (backwards)7.30 + add #1, r127.31 + setc7.32 + bra test_bt_3_b7.33 + nop7.34 + fail test_bt_str_k7.35 + bra test_bt_47.36 +test_bt_3_c:7.37 + nop7.38 + bra test_bt_47.39 + nop7.40 + fail test_bt_str_k7.41 + bra test_bt_47.42 +test_bt_3_b:7.43 + nop7.44 + bt test_bt_3_c7.45 + fail test_bt_str_k7.46 + bra test_bt_47.47 + nop7.48 +test_bt_4: ! Test branch not taken w/ delay7.49 + add #1, r127.50 + clc7.51 + xor r0, r07.52 + bt/s test_bt_4_b7.53 + add #1, r07.54 + bra test_bt_4_c7.55 + nop7.56 +test_bt_4_b:7.57 + fail test_bt_str_k7.58 + bra test_bt_57.59 + nop7.60 +test_bt_4_c:7.61 + xor r1,r17.62 + add #1, r17.63 + cmp/eq r0, r17.64 +7.65 +test_bt_5: ! Test branch taken w/ delay7.66 + add #1, r127.67 + setc7.68 + xor r0,r07.69 + bt/s test_bt_5_b7.70 + add #1, r07.71 + fail test_bt_str_k7.72 + bra test_bt_67.73 +test_bt_5_b:7.74 + xor r1,r17.75 + add #1, r17.76 + cmp/eq r0,r17.77 + bt test_bt_67.78 + fail test_bt_str_k7.79 +7.80 +test_bt_6: ! Test back-branch taken w/ delay7.81 + add #1, r127.82 + setc7.83 + xor r0, r07.84 + bra test_bt_6_b7.85 + nop7.86 + fail test_bt_str_k7.87 + bra test_bt_77.88 + nop7.89 + add #1, r137.90 +test_bt_6_c:7.91 + mov #1, r17.92 + cmp/eq r0, r17.93 + bt test_bt_77.94 + fail test_bt_str_k7.95 + bra test_bt_77.96 + nop7.97 + fail test_bt_str_k7.98 + bra test_bt_77.99 +test_bt_6_b:7.100 + nop7.101 + bt/s test_bt_6_c7.102 + add #1, r07.103 + fail test_bt_str_k7.104 + bra test_bt_77.105 + nop7.106 +7.107 +test_bt_7:7.108 + add #1, r127.109 + expect_exc 0x000001A0 ! BT is slot illegal7.110 +test_bt_7_exc:7.111 + bra test_bt_7_b7.112 + bt test_bt_7_b7.113 + assert_exc_caught test_bt_str_k test_bt_7_exc7.114 + bra test_bt_87.115 + nop7.116 +test_bt_7_b:7.117 +test_bt_7_c:7.118 + fail test_bt_str_k7.119 +7.120 +test_bt_8:7.121 + add #1, r127.122 + expect_exc 0x000001A0 ! BT/S is slot illegal7.123 +test_bt_8_exc:7.124 + bra test_bt_8_b7.125 + bt/s test_bt_8_b7.126 + nop7.127 + assert_exc_caught test_bt_str_k test_bt_8_exc7.128 + bra test_bt_end7.129 + nop7.130 +test_bt_8_b:7.131 +test_bt_8_c:7.132 + fail test_bt_str_k7.133 +7.134 +test_bt_end:7.135 + end_test test_bt_str_k7.136 +7.137 +test_bt_str:7.138 + .string "BT"7.139 +7.140 +.align 47.141 +test_bt_str_k:7.142 + .long test_bt_str7.143 +7.144 \ No newline at end of file
8.1 --- /dev/null Thu Jan 01 00:00:00 1970 +00008.2 +++ b/test/sh4/cmp.s Tue Sep 26 11:05:38 2006 +00008.3 @@ -0,0 +1,198 @@8.4 +.section .text8.5 +.include "sh4/inc.s"8.6 +!8.7 +! Test cmp/xx8.8 +8.9 +.global _test_cmp8.10 +_test_cmp:8.11 + start_test8.12 +8.13 +test_cmpeq_1: ! CMP/EQ 0, 08.14 + add #1, r128.15 + xor r0, r08.16 + xor r1, r18.17 + cmp/eq r0, r18.18 + bt test_cmpeq_28.19 + fail test_cmpeq_str_k8.20 +8.21 +test_cmpeq_2: ! CMP/EQ !0, 08.22 + add #1, r128.23 + mov #50, r28.24 + cmp/eq r1, r28.25 + bf test_cmpeq_38.26 + fail test_cmpeq_str_k8.27 +8.28 +test_cmpeq_3: ! CMP/EQ -50, 508.29 + add #1, r128.30 + mov #-50, r38.31 + cmp/eq r3, r28.32 + bf test_cmpeq_48.33 + fail test_cmpeq_str_k8.34 +8.35 +test_cmpeq_4: ! CMP/EQ 50, 508.36 + add #1, r128.37 + mov #50, r68.38 + cmp/eq r6, r28.39 + bt test_cmpeq_58.40 + fail test_cmpeq_str_k8.41 +8.42 +test_cmpeq_5:8.43 +8.44 +test_cmpeq_6:8.45 +8.46 +test_cmpge_1:8.47 + add #1, r128.48 + cmp/ge r2, r68.49 + bt test_cmpge_28.50 + fail test_cmpge_str_k8.51 +8.52 +test_cmpge_2:8.53 + add #1, r128.54 + cmp/ge r3, r28.55 + bt test_cmpge_38.56 + fail test_cmpge_str_k8.57 +8.58 +test_cmpge_3:8.59 + add #1, r128.60 + cmp/ge r2, r38.61 + bf test_cmpge_48.62 + fail test_cmpge_str_k8.63 +8.64 +test_cmpge_4:8.65 + add #1, r128.66 + mov #75, r58.67 + cmp/ge r2, r58.68 + bt test_cmpge_58.69 + fail test_cmpge_str_k8.70 +8.71 +test_cmpge_5:8.72 + add #1, r128.73 + cmp/ge r5, r28.74 + bf test_cmpgt_18.75 + fail test_cmpge_str_k8.76 +8.77 +test_cmpgt_1:8.78 + add #1, r128.79 + cmp/gt r2, r68.80 + bf test_cmpgt_28.81 + fail test_cmpgt_str_k8.82 +8.83 +test_cmpgt_2:8.84 + add #1, r128.85 + cmp/gt r3, r28.86 + bt test_cmpgt_38.87 + fail test_cmpgt_str_k8.88 +8.89 +test_cmpgt_3:8.90 + add #1, r128.91 + cmp/gt r2, r38.92 + bf test_cmpgt_48.93 + fail test_cmpgt_str_k8.94 +8.95 +test_cmpgt_4:8.96 + add #1, r128.97 + mov #75, r58.98 + cmp/gt r2, r58.99 + bt test_cmpgt_58.100 + fail test_cmpgt_str_k8.101 +8.102 +test_cmpgt_5:8.103 + add #1, r128.104 + cmp/gt r5, r28.105 + bf test_cmphi_18.106 + fail test_cmpgt_str_k8.107 +8.108 +8.109 +test_cmphi_1:8.110 + add #1, r128.111 + cmp/hi r2, r68.112 + bf test_cmphi_28.113 + fail test_cmphi_str_k8.114 +8.115 +test_cmphi_2:8.116 + add #1, r128.117 + cmp/hi r3, r28.118 + bf test_cmphi_38.119 + fail test_cmphi_str_k8.120 +8.121 +test_cmphi_3:8.122 + add #1, r128.123 + cmp/hi r2, r38.124 + bt test_cmphi_48.125 + fail test_cmphi_str_k8.126 +8.127 +test_cmphi_4:8.128 + add #1, r128.129 + mov #75, r58.130 + cmp/hi r2, r58.131 + bt test_cmphi_58.132 + fail test_cmphi_str_k8.133 +8.134 +test_cmphi_5:8.135 + add #1, r128.136 + cmp/hi r5, r28.137 + bf test_cmphs_18.138 + fail test_cmphi_str_k8.139 +8.140 +test_cmphs_1:8.141 + add #1, r128.142 + cmp/hs r2, r68.143 + bt test_cmphs_28.144 + fail test_cmphs_str_k8.145 +8.146 +test_cmphs_2:8.147 + add #1, r128.148 + cmp/hs r3, r28.149 + bf test_cmphs_38.150 + fail test_cmphs_str_k8.151 +8.152 +test_cmphs_3:8.153 + add #1, r128.154 + cmp/hs r2, r38.155 + bt test_cmphs_48.156 + fail test_cmphs_str_k8.157 +8.158 +test_cmphs_4:8.159 + add #1, r128.160 + mov #75, r58.161 + cmp/hs r2, r58.162 + bt test_cmphs_58.163 + fail test_cmphs_str_k8.164 +8.165 +test_cmphs_5:8.166 + add #1, r128.167 + cmp/hs r5, r28.168 + bf test_cmppl_18.169 + fail test_cmphs_str_k8.170 +8.171 +test_cmppl_1:8.172 +8.173 +test_cmp_end:8.174 + end_test test_cmp_str_k8.175 +test_cmpeq_str:8.176 + .string "CMP/EQ"8.177 +test_cmpge_str:8.178 + .string "CMP/GE"8.179 +test_cmpgt_str:8.180 + .string "CMP/GT"8.181 +test_cmphi_str:8.182 + .string "CMP/HI"8.183 +test_cmphs_str:8.184 + .string "CMP/HS"8.185 +test_cmp_str:8.186 + .string "CMP"8.187 +8.188 +.align 48.189 +test_cmp_str_k:8.190 + .long test_cmp_str8.191 +test_cmpeq_str_k:8.192 + .long test_cmpeq_str8.193 +test_cmpge_str_k:8.194 + .long test_cmpge_str8.195 +test_cmpgt_str_k:8.196 + .long test_cmpgt_str8.197 +test_cmphi_str_k:8.198 + .long test_cmphi_str8.199 +test_cmphs_str_k:8.200 + .long test_cmphs_str8.201 +8.202 \ No newline at end of file
9.1 --- /dev/null Thu Jan 01 00:00:00 1970 +00009.2 +++ b/test/sh4/excslot.s Tue Sep 26 11:05:38 2006 +00009.3 @@ -0,0 +1,189 @@9.4 +.section .text9.5 +.include "sh4/inc.s"9.6 +!9.7 +! Test for all cases that raise a slot-illegal exception (according to the SH49.8 +! manual). See Page 103 of the Hitachi manual9.9 +9.10 +.global _test_slot_illegal9.11 +_test_slot_illegal:9.12 + start_test9.13 +9.14 +! First the easy ones - instructions not permitted in delay slots at any9.15 +! time:9.16 +! JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF, BT/S, BF/S, TRAPA,9.17 +! LDC (to SR), MOV pcrel, MOVA9.18 +!9.19 +! Note that the tests use BSR as the branch instruction, and assume it9.20 +! functions correctly.9.21 +9.22 +test_slot_1: !JMP9.23 + add #1, r129.24 + expect_exc 0x000001A09.25 +test_slot_1_pc:9.26 + bsr test_slot_fail9.27 + jmp @r39.28 + assert_exc_caught test_slot_str_k1 test_slot_1_pc9.29 +9.30 +test_slot_2: ! JSR9.31 + add #1, r129.32 + expect_exc 0x000001A09.33 +test_slot_2_pc:9.34 + bsr test_slot_fail9.35 + jsr @r39.36 + assert_exc_caught test_slot_str_k1 test_slot_2_pc9.37 + bra test_slot_39.38 + nop9.39 +test_slot_str_k1:9.40 + .long test_slot_str9.41 +9.42 +test_slot_3: ! BRA9.43 + add #1, r129.44 + expect_exc 0x000001A09.45 +test_slot_3_pc:9.46 + bsr test_slot_fail9.47 + bra test_slot_fail9.48 + assert_exc_caught test_slot_str_k test_slot_3_pc9.49 +9.50 +test_slot_4: ! BRAF9.51 + add #1, r129.52 + expect_exc 0x000001A09.53 +test_slot_4_pc:9.54 + bsr test_slot_fail9.55 + braf r39.56 + assert_exc_caught test_slot_str_k test_slot_4_pc9.57 +9.58 +test_slot_5: ! BSR9.59 + add #1, r129.60 + expect_exc 0x000001A09.61 +test_slot_5_pc:9.62 + bsr test_slot_fail9.63 + bsr test_slot_fail9.64 + assert_exc_caught test_slot_str_k test_slot_5_pc9.65 +9.66 +test_slot_6: ! BSRF9.67 + add #1, r129.68 + expect_exc 0x000001A09.69 +test_slot_6_pc:9.70 + bsr test_slot_fail9.71 + bsrf r39.72 + assert_exc_caught test_slot_str_k test_slot_6_pc9.73 +9.74 +test_slot_7: ! BF9.75 + add #1, r129.76 + expect_exc 0x000001A09.77 +test_slot_7_pc:9.78 + bsr test_slot_fail9.79 + bf test_slot_7_fail9.80 +test_slot_7_fail:9.81 + assert_exc_caught test_slot_str_k test_slot_7_pc9.82 +9.83 +test_slot_8: ! BT9.84 + add #1, r129.85 + expect_exc 0x000001A09.86 +test_slot_8_pc:9.87 + bsr test_slot_fail9.88 + bt test_slot_8_fail9.89 +test_slot_8_fail:9.90 + assert_exc_caught test_slot_str_k test_slot_8_pc9.91 +9.92 +test_slot_9: ! BF/S9.93 + add #1, r129.94 + expect_exc 0x000001A09.95 +test_slot_9_pc:9.96 + bsr test_slot_fail9.97 + bf/s test_slot_9_fail9.98 +test_slot_9_fail:9.99 + assert_exc_caught test_slot_str_k test_slot_9_pc9.100 +9.101 +test_slot_10: ! BT/S9.102 + add #1, r129.103 + expect_exc 0x000001A09.104 +test_slot_10_pc:9.105 + bsr test_slot_fail9.106 + bt/s test_slot_10_fail9.107 +test_slot_10_fail:9.108 + assert_exc_caught test_slot_str_k test_slot_10_pc9.109 +9.110 +test_slot_11: ! TRAPA9.111 + add #1, r129.112 + expect_exc 0x000001A09.113 +test_slot_11_pc:9.114 + bsr test_slot_fail9.115 + trapa #129.116 + assert_exc_caught test_slot_str_k test_slot_11_pc9.117 +9.118 +test_slot_12: ! LDC r0, sr9.119 + add #1, r129.120 + expect_exc 0x000001A09.121 + stc sr, r09.122 +test_slot_12_pc:9.123 + bsr test_slot_fail9.124 + ldc r0, sr9.125 + assert_exc_caught test_slot_str_k test_slot_12_pc9.126 +9.127 +test_slot_13: ! LDC @r0, sr9.128 + add #1, r129.129 + expect_exc 0x000001A09.130 + stc sr, r19.131 + mova test_slot_13_temp, r09.132 + mov.l r1, @r09.133 +test_slot_13_pc:9.134 + bsr test_slot_fail9.135 + ldc.l @r0+, sr9.136 + assert_exc_caught test_slot_str_k test_slot_13_pc9.137 + bra test_slot_149.138 + nop9.139 +test_slot_13_temp:9.140 + .long 09.141 +9.142 +test_slot_14: ! MOVA9.143 + add #1, r129.144 + expect_exc 0x000001A09.145 +test_slot_14_pc:9.146 + bsr test_slot_fail9.147 + mova test_slot_15, r09.148 + assert_exc_caught test_slot_str_k test_slot_14_pc9.149 +9.150 +test_slot_15: ! MOV.W pcrel, Rn9.151 + add #1, r129.152 + expect_exc 0x000001A09.153 +test_slot_15_pc:9.154 + bsr test_slot_fail9.155 + mov.w test_slot_16, r09.156 + assert_exc_caught test_slot_str_k test_slot_15_pc9.157 +9.158 +test_slot_16: ! MOV.L pcrel, Rn9.159 + add #1, r129.160 + expect_exc 0x000001A09.161 +test_slot_16_pc:9.162 + bsr test_slot_fail9.163 + mov.l test_slot_str_k, r09.164 + assert_exc_caught test_slot_str_k test_slot_16_pc9.165 +9.166 +test_slot_17: ! "Undefined" 0xFFFD9.167 + add #1, r129.168 + expect_exc 0x000001A09.169 +test_slot_17_pc:9.170 + bsr test_slot_fail9.171 + .word 0xFFFD9.172 + assert_exc_caught test_slot_str_k test_slot_17_pc9.173 +9.174 +!9.175 +! Ok now the privilege tests. These should raise SLOT_ILLEGAL when executed9.176 +! in a delay slot (otherwise it's GENERAL_ILLEGAL)9.177 +! TODO: need mode-switch code9.178 +9.179 +test_slot_end:9.180 + end_test test_slot_str_k9.181 +9.182 +! Returns after the delay slot, which should hit the "no exception" test9.183 +test_slot_fail:9.184 + rts9.185 + nop9.186 +9.187 +test_slot_str_k:9.188 + .long test_slot_str9.189 +test_slot_str:9.190 + .string "SLOT-ILLEGAL"9.191 +9.192 +9.193 \ No newline at end of file
10.1 --- a/test/sh4/inc.s Mon Sep 25 12:20:58 2006 +000010.2 +++ b/test/sh4/inc.s Tue Sep 26 11:05:38 2006 +000010.3 @@ -186,7 +186,7 @@10.4 .endm10.6 .macro assert_exc_caught testname, expectpc10.7 -LOCAL L1, L210.8 +LOCAL L1, L2, L310.9 mov.l L1, r310.10 mov.l \testname, r410.11 mov r12, r5
11.1 --- a/test/sh4/testsh4.c Mon Sep 25 12:20:58 2006 +000011.2 +++ b/test/sh4/testsh4.c Tue Sep 26 11:05:38 2006 +000011.3 @@ -5,7 +5,7 @@11.5 int test_print_result( char *testname, int failed, int total )11.6 {11.7 - fprintf( stderr, "%s: %d/%d tests passed\n", testname, total-failed, total );11.8 + fprintf( stdout, "%s: %d/%d tests passed\n", testname, total-failed, total );11.9 total_tests += total;11.10 total_fails += failed;11.11 return failed;11.12 @@ -44,6 +44,7 @@11.14 int main()11.15 {11.16 + fprintf( stdout, "Instruction tests...\n" );11.17 install_interrupt_handler();11.18 test_add();11.19 test_addc();11.20 @@ -51,8 +52,16 @@11.21 test_and();11.22 test_andi();11.23 test_bf();11.24 + test_bt();11.25 + test_cmp();11.26 + fprintf( stdout, "--> %d/%d instruction tests passed (%d%%)\n\n",11.27 + total_tests-total_fails, total_tests,11.28 + ((total_tests-total_fails)*100)/total_tests );11.29 +11.30 + fprintf( stdout, "Exception tests...\n" );11.31 + test_slot_illegal();11.32 remove_interrupt_handler();11.34 - fprintf( stderr, "Total: %d/%d tests passed (%d%%)\n", total_tests-total_fails,11.35 + fprintf( stdout, "Total: %d/%d tests passed (%d%%)\n", total_tests-total_fails,11.36 total_tests, ((total_tests-total_fails)*100)/total_tests );11.37 }
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