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lxdream.org :: lxdream :: r669:ab344e42bca9
lxdream 0.9.1
released Jun 29
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changeset669:ab344e42bca9
parent668:c62dff190859
child670:5d277b7ad0df
authornkeynes
dateMon May 12 10:00:13 2008 +0000 (11 years ago)
Cleanup most of the -Wall warnings (getting a bit sloppy...)
Convert FP code to use fixed banks rather than indirect pointer
(3-4% faster this way now)
src/dcload.c
src/display.h
src/dreamcast.c
src/drivers/audio_alsa.c
src/drivers/gl_fbo.c
src/drivers/joy_linux.c
src/drivers/video_gdk.c
src/drivers/video_gl.c
src/drivers/video_gl.h
src/drivers/video_glx.c
src/drivers/video_gtk.c
src/drivers/video_null.c
src/gdrom/edc_ecc.c
src/gdrom/gdimage.c
src/gtkui/ctrl_dlg.c
src/gtkui/debug_win.c
src/gtkui/dump_win.c
src/gtkui/gtkcb.c
src/gtkui/gtkui.c
src/gtkui/gtkui.h
src/gtkui/main_win.c
src/main.c
src/maple/mouse.c
src/mem.c
src/mem.h
src/pvr2/gl_sl.c
src/pvr2/glrender.c
src/pvr2/glutil.h
src/pvr2/pvr2.c
src/pvr2/pvr2.h
src/pvr2/pvr2mem.c
src/pvr2/rendsave.c
src/pvr2/rendsort.c
src/pvr2/scene.c
src/pvr2/scene.h
src/pvr2/tacore.c
src/sh4/ia32abi.h
src/sh4/ia32mac.h
src/sh4/ia64abi.h
src/sh4/mmu.c
src/sh4/sh4.c
src/sh4/sh4.h
src/sh4/sh4core.c
src/sh4/sh4core.h
src/sh4/sh4core.in
src/sh4/sh4dasm.c
src/sh4/sh4dasm.in
src/sh4/sh4trans.c
src/sh4/sh4trans.h
src/sh4/sh4x86.c
src/sh4/sh4x86.in
src/sh4/x86op.h
src/syscall.c
src/test/testsh4x86.c
1.1 --- a/src/dcload.c Sun Apr 20 05:30:07 2008 +0000
1.2 +++ b/src/dcload.c Mon May 12 10:00:13 2008 +0000
1.3 @@ -162,5 +162,5 @@
1.4 open_fds[1] = 1;
1.5 open_fds[2] = 2;
1.6 syscall_add_hook_vector( 0xF0, SYSCALL_ADDR, dcload_syscall );
1.7 - sh4_write_long( SYS_MAGIC_ADDR, SYS_MAGIC );
1.8 + mem_write_long( SYS_MAGIC_ADDR, SYS_MAGIC );
1.9 }
2.1 --- a/src/display.h Sun Apr 20 05:30:07 2008 +0000
2.2 +++ b/src/display.h Mon May 12 10:00:13 2008 +0000
2.3 @@ -20,6 +20,8 @@
2.4 #ifndef dream_video_H
2.5 #define dream_video_H
2.6
2.7 +#define GL_GLEXT_PROTOTYPES 1
2.8 +
2.9 #include <stdint.h>
2.10 #include <glib.h>
2.11 #include "lxdream.h"
2.12 @@ -153,13 +155,13 @@
2.13 /**
2.14 * Display a single frame using a previously rendered GL buffer.
2.15 */
2.16 - gboolean (*display_render_buffer)( render_buffer_t buffer );
2.17 + void (*display_render_buffer)( render_buffer_t buffer );
2.18
2.19 /**
2.20 * Display a single blanked frame using a fixed colour for the
2.21 * entire frame (specified in BGR888 format).
2.22 */
2.23 - gboolean (*display_blank)( uint32_t rgb );
2.24 + void (*display_blank)( uint32_t rgb );
2.25
2.26 /**
2.27 * Copy the image data from the GL buffer to the target memory buffer,
3.1 --- a/src/dreamcast.c Sun Apr 20 05:30:07 2008 +0000
3.2 +++ b/src/dreamcast.c Mon May 12 10:00:13 2008 +0000
3.3 @@ -19,14 +19,16 @@
3.4
3.5 #include <errno.h>
3.6 #include <glib.h>
3.7 -#include "dream.h"
3.8 -#include "config.h"
3.9 +#include "lxdream.h"
3.10 #include "mem.h"
3.11 +#include "dreamcast.h"
3.12 +#include "asic.h"
3.13 +#include "syscall.h"
3.14 +#include "gui.h"
3.15 #include "aica/aica.h"
3.16 -#include "asic.h"
3.17 -#include "dreamcast.h"
3.18 #include "gdrom/ide.h"
3.19 #include "maple/maple.h"
3.20 +#include "sh4/sh4.h"
3.21 #include "sh4/sh4trans.h"
3.22
3.23 /**
4.1 --- a/src/drivers/audio_alsa.c Sun Apr 20 05:30:07 2008 +0000
4.2 +++ b/src/drivers/audio_alsa.c Mon May 12 10:00:13 2008 +0000
4.3 @@ -28,7 +28,6 @@
4.4
4.5
4.6 static snd_pcm_t *_soundDevice = NULL;
4.7 -static int frames;
4.8 static int frame_bytes;
4.9
4.10
4.11 @@ -40,21 +39,16 @@
4.12
4.13 gboolean audio_alsa_init( )
4.14 {
4.15 - int err;
4.16 -
4.17 return TRUE;
4.18 }
4.19
4.20
4.21 gboolean audio_alsa_set_format( uint32_t rate, uint32_t format )
4.22 {
4.23 - int i;
4.24 int err;
4.25 snd_pcm_hw_params_t *hw_params;
4.26 snd_pcm_sw_params_t *sw_params;
4.27 snd_pcm_uframes_t frames;
4.28 - unsigned int resample = 1;
4.29 - unsigned int actualRate = rate;
4.30 snd_pcm_uframes_t bufferSize;
4.31 int dir;
4.32
4.33 @@ -187,8 +181,6 @@
4.34
4.35 gboolean audio_alsa_close( )
4.36 {
4.37 - int err;
4.38 -
4.39 return TRUE;
4.40 }
4.41
5.1 --- a/src/drivers/gl_fbo.c Sun Apr 20 05:30:07 2008 +0000
5.2 +++ b/src/drivers/gl_fbo.c Mon May 12 10:00:13 2008 +0000
5.3 @@ -38,9 +38,9 @@
5.4 static render_buffer_t gl_fbo_create_render_buffer( uint32_t width, uint32_t height );
5.5 static void gl_fbo_destroy_render_buffer( render_buffer_t buffer );
5.6 static gboolean gl_fbo_set_render_target( render_buffer_t buffer );
5.7 -static gboolean gl_fbo_display_render_buffer( render_buffer_t buffer );
5.8 +static void gl_fbo_display_render_buffer( render_buffer_t buffer );
5.9 static void gl_fbo_load_frame_buffer( frame_buffer_t frame, render_buffer_t buffer );
5.10 -static gboolean gl_fbo_display_blank( uint32_t colour );
5.11 +static void gl_fbo_display_blank( uint32_t colour );
5.12 static gboolean gl_fbo_read_render_buffer( unsigned char *target, render_buffer_t buffer, int rowstride, int format );
5.13
5.14 extern uint32_t video_width, video_height;
5.15 @@ -241,7 +241,6 @@
5.16 gl_fbo_attach_texture( fb, buffer->buf_id );
5.17 /* setup the gl context */
5.18 glViewport( 0, 0, buffer->width, buffer->height );
5.19 - glsl_enable_shader(TRUE);
5.20
5.21 return TRUE;
5.22 }
5.23 @@ -250,29 +249,25 @@
5.24 * Render the texture holding the given buffer to the front window
5.25 * buffer.
5.26 */
5.27 -static gboolean gl_fbo_display_render_buffer( render_buffer_t buffer )
5.28 +static void gl_fbo_display_render_buffer( render_buffer_t buffer )
5.29 {
5.30 glFinish();
5.31 gl_fbo_detach();
5.32 - glsl_enable_shader(FALSE);
5.33 gl_display_render_buffer( buffer );
5.34 - return TRUE;
5.35 }
5.36
5.37 static void gl_fbo_load_frame_buffer( frame_buffer_t frame, render_buffer_t buffer )
5.38 {
5.39 glFinish();
5.40 gl_fbo_detach();
5.41 - glsl_enable_shader(FALSE);
5.42 gl_load_frame_buffer( frame, buffer->buf_id );
5.43 }
5.44
5.45 -static gboolean gl_fbo_display_blank( uint32_t colour )
5.46 +static void gl_fbo_display_blank( uint32_t colour )
5.47 {
5.48 glFinish();
5.49 gl_fbo_detach();
5.50 - glsl_enable_shader(FALSE);
5.51 - return gl_display_blank( colour );
5.52 + gl_display_blank( colour );
5.53 }
5.54
5.55 void gl_fbo_detach()
6.1 --- a/src/drivers/joy_linux.c Sun Apr 20 05:30:07 2008 +0000
6.2 +++ b/src/drivers/joy_linux.c Mon May 12 10:00:13 2008 +0000
6.3 @@ -23,6 +23,8 @@
6.4 #include <stdio.h>
6.5 #include <signal.h>
6.6 #include <string.h>
6.7 +#include <stdlib.h>
6.8 +#include <unistd.h>
6.9 #include <fcntl.h>
6.10 #include <dirent.h>
6.11 #include <ctype.h>
6.12 @@ -33,6 +35,8 @@
6.13
6.14 #include "lxdream.h"
6.15 #include "display.h"
6.16 +#include "maple/maple.h"
6.17 +#include "drivers/joy_linux.h"
6.18
6.19 #define INPUT_PATH "/dev/input"
6.20
6.21 @@ -48,7 +52,8 @@
6.22
6.23 static gboolean linux_joystick_callback( GIOChannel *source, GIOCondition condition,
6.24 gpointer data );
6.25 -static linux_joystick_t linux_joystick_add( const gchar *filename, int fd );
6.26 +static int linux_joystick_scan();
6.27 +static linux_joystick_t linux_joystick_new( const gchar *filename, int fd );
6.28 static uint16_t linux_joystick_resolve_keysym( input_driver_t dev, const gchar *str );
6.29 static gchar *linux_joystick_keysym_for_keycode( input_driver_t dev, uint16_t keycode );
6.30 static void linux_joystick_destroy( input_driver_t joy );
6.31 @@ -157,8 +162,8 @@
6.32 }
6.33 }
6.34 }
6.35 - return TRUE;
6.36 }
6.37 + return TRUE;
6.38 }
6.39
6.40 /**
6.41 @@ -166,7 +171,7 @@
6.42 * descriptor. The joystick is automatically added to the watch list.
6.43 * @return The new joystick, or NULL if an error occurred.
6.44 */
6.45 -linux_joystick_t linux_joystick_new( const gchar *filename, int fd )
6.46 +static linux_joystick_t linux_joystick_new( const gchar *filename, int fd )
6.47 {
6.48 linux_joystick_t joy = g_malloc0(sizeof(struct linux_joystick));
6.49 joy->filename = filename;
6.50 @@ -196,13 +201,7 @@
6.51 return joy;
6.52 }
6.53
6.54 -int linux_joystick_init()
6.55 -{
6.56 - linux_joystick_install_watch(INPUT_PATH);
6.57 - linux_joystick_scan();
6.58 -}
6.59 -
6.60 -int linux_joystick_scan()
6.61 +static int linux_joystick_scan()
6.62 {
6.63 int joysticks = 0;
6.64 struct dirent *ent;
6.65 @@ -233,6 +232,15 @@
6.66 return joysticks;
6.67 }
6.68
6.69 +gboolean linux_joystick_init()
6.70 +{
6.71 + if( !linux_joystick_install_watch(INPUT_PATH) ) {
6.72 + return FALSE;
6.73 + }
6.74 + linux_joystick_scan();
6.75 + return TRUE;
6.76 +}
6.77 +
6.78 void linux_joystick_shutdown(void)
6.79 {
6.80 linux_joystick_uninstall_watch();
6.81 @@ -275,6 +283,7 @@
6.82 }
6.83 watch_dir_fd = fd;
6.84 g_timeout_add( 500, gtk_loop_check_input, NULL );
6.85 + return TRUE;
6.86 }
6.87
6.88 static void linux_joystick_uninstall_watch(void)
7.1 --- a/src/drivers/video_gdk.c Sun Apr 20 05:30:07 2008 +0000
7.2 +++ b/src/drivers/video_gdk.c Mon May 12 10:00:13 2008 +0000
7.3 @@ -34,9 +34,9 @@
7.4 static render_buffer_t gdk_pixbuf_create_render_buffer( uint32_t width, uint32_t height );
7.5 static void gdk_pixbuf_destroy_render_buffer( render_buffer_t buffer );
7.6 static gboolean gdk_pixbuf_set_render_target( render_buffer_t buffer );
7.7 -static gboolean gdk_pixbuf_display_render_buffer( render_buffer_t buffer );
7.8 +static void gdk_pixbuf_display_render_buffer( render_buffer_t buffer );
7.9 static void gdk_pixbuf_load_frame_buffer( frame_buffer_t frame, render_buffer_t buffer );
7.10 -static gboolean gdk_pixbuf_display_blank( uint32_t colour );
7.11 +static void gdk_pixbuf_display_blank( uint32_t colour );
7.12 static gboolean gdk_pixbuf_read_render_buffer( unsigned char *target, render_buffer_t buffer, int rowstride, int format );
7.13
7.14 static void *pixbuf_array[MAX_PIXBUF];
7.15 @@ -107,7 +107,7 @@
7.16 }
7.17 }
7.18
7.19 -static gboolean gdk_pixbuf_display_render_buffer( render_buffer_t buffer )
7.20 +static void gdk_pixbuf_display_render_buffer( render_buffer_t buffer )
7.21 {
7.22 glFinish();
7.23
7.24 @@ -150,7 +150,7 @@
7.25 }
7.26 }
7.27
7.28 -static gboolean gdk_pixbuf_display_blank( uint32_t colour )
7.29 +static void gdk_pixbuf_display_blank( uint32_t colour )
7.30 {
7.31 GdkGC *gc = gtk_video_drawable->style->fg_gc[GTK_STATE_NORMAL];
7.32 GdkColor col = { };
7.33 @@ -158,7 +158,6 @@
7.34 gdk_gc_set_foreground( gc, &col );
7.35 gdk_gc_set_background( gc, &col );
7.36 gdk_draw_rectangle( gtk_video_drawable->window, gc, TRUE, 0, 0, video_width, video_height );
7.37 - return TRUE;
7.38 }
7.39
7.40 static gboolean gdk_pixbuf_set_render_target( render_buffer_t buffer )
8.1 --- a/src/drivers/video_gl.c Sun Apr 20 05:30:07 2008 +0000
8.2 +++ b/src/drivers/video_gl.c Mon May 12 10:00:13 2008 +0000
8.3 @@ -134,13 +134,12 @@
8.4 return TRUE;
8.5 }
8.6
8.7 -gboolean gl_display_blank( uint32_t colour )
8.8 +void gl_display_blank( uint32_t colour )
8.9 {
8.10 gl_reset_state();
8.11 glColor3ub( (colour >> 16) & 0xFF, (colour >> 8) & 0xFF, colour & 0xFF );
8.12 glRecti(0,0, video_width, video_height );
8.13 glFlush();
8.14 - return TRUE;
8.15 }
8.16
8.17 /**
9.1 --- a/src/drivers/video_gl.h Sun Apr 20 05:30:07 2008 +0000
9.2 +++ b/src/drivers/video_gl.h Mon May 12 10:00:13 2008 +0000
9.3 @@ -25,9 +25,14 @@
9.4 gboolean gl_load_frame_buffer( frame_buffer_t frame, int tex_id );
9.5
9.6 /**
9.7 + * Reset the GL state to its initial values
9.8 + */
9.9 +void gl_reset_state();
9.10 +
9.11 +/**
9.12 * Generic GL routine to blank the display view with the specified colour.
9.13 */
9.14 -gboolean gl_display_blank( uint32_t colour );
9.15 +void gl_display_blank( uint32_t colour );
9.16
9.17 /**
9.18 * Write a rectangular texture (GL_TEXTURE_RECTANGLE_ARB) to the display frame
10.1 --- a/src/drivers/video_glx.c Sun Apr 20 05:30:07 2008 +0000
10.2 +++ b/src/drivers/video_glx.c Mon May 12 10:00:13 2008 +0000
10.3 @@ -31,7 +31,6 @@
10.4 */
10.5 Display *video_x11_display = NULL;
10.6 Window video_x11_window = 0;
10.7 -static gboolean glsl_loaded = FALSE;
10.8
10.9 static int glx_version = 100;
10.10 static XVisualInfo *glx_visual = NULL;
10.11 @@ -40,16 +39,16 @@
10.12 static gboolean glx_is_initialized = FALSE;
10.13 static gboolean glx_fbconfig_supported = FALSE;
10.14 static gboolean glx_pbuffer_supported = FALSE;
10.15 -static int glx_pbuffer_texture = 0;
10.16 +static GLuint glx_pbuffer_texture = 0;
10.17
10.18 /* Prototypes for pbuffer support methods */
10.19 static void glx_pbuffer_init( display_driver_t driver );
10.20 static render_buffer_t glx_pbuffer_create_render_buffer( uint32_t width, uint32_t height );
10.21 static void glx_pbuffer_destroy_render_buffer( render_buffer_t buffer );
10.22 static gboolean glx_pbuffer_set_render_target( render_buffer_t buffer );
10.23 -static gboolean glx_pbuffer_display_render_buffer( render_buffer_t buffer );
10.24 +static void glx_pbuffer_display_render_buffer( render_buffer_t buffer );
10.25 static void glx_pbuffer_load_frame_buffer( frame_buffer_t frame, render_buffer_t buffer );
10.26 -static gboolean glx_pbuffer_display_blank( uint32_t colour );
10.27 +static void glx_pbuffer_display_blank( uint32_t colour );
10.28 static gboolean glx_pbuffer_read_render_buffer( unsigned char *target, render_buffer_t buffer, int rowstride, int format );
10.29
10.30 /**
10.31 @@ -300,7 +299,7 @@
10.32 * Render the texture holding the given buffer to the front window
10.33 * buffer.
10.34 */
10.35 -static gboolean glx_pbuffer_display_render_buffer( render_buffer_t buffer )
10.36 +static void glx_pbuffer_display_render_buffer( render_buffer_t buffer )
10.37 {
10.38 glFinish();
10.39 glReadBuffer( GL_FRONT );
10.40 @@ -310,7 +309,6 @@
10.41 glCopyTexImage2D(GL_TEXTURE_RECTANGLE_ARB, 0, GL_RGBA, 0, 0, buffer->width, buffer->height, 0 );
10.42 video_glx_make_window_current();
10.43 gl_texture_window( buffer->width, buffer->height, glx_pbuffer_texture, buffer->inverted );
10.44 - return TRUE;
10.45 }
10.46
10.47 static void glx_pbuffer_load_frame_buffer( frame_buffer_t frame, render_buffer_t buffer )
10.48 @@ -330,11 +328,11 @@
10.49 glFlush();
10.50 }
10.51
10.52 -static gboolean glx_pbuffer_display_blank( uint32_t colour )
10.53 +static void glx_pbuffer_display_blank( uint32_t colour )
10.54 {
10.55 glFinish();
10.56 video_glx_make_window_current();
10.57 - return gl_display_blank( colour );
10.58 + gl_display_blank( colour );
10.59 }
10.60
10.61 static gboolean glx_pbuffer_read_render_buffer( unsigned char *target, render_buffer_t buffer,
11.1 --- a/src/drivers/video_gtk.c Sun Apr 20 05:30:07 2008 +0000
11.2 +++ b/src/drivers/video_gtk.c Mon May 12 10:00:13 2008 +0000
11.3 @@ -23,6 +23,7 @@
11.4 #include "display.h"
11.5 #include "dckeysyms.h"
11.6 #include "drivers/video_gl.h"
11.7 +#include "drivers/joy_linux.h"
11.8 #include "pvr2/pvr2.h"
11.9 #include "gtkui/gtkui.h"
11.10
11.11 @@ -120,7 +121,7 @@
11.12
11.13 gboolean video_gtk_init();
11.14 void video_gtk_shutdown();
11.15 -gboolean video_gtk_display_blank( uint32_t colour );
11.16 +void video_gtk_display_blank( uint32_t colour );
11.17 uint16_t video_gtk_resolve_keysym( const gchar *keysym );
11.18 uint16_t video_gtk_keycode_to_dckeysym(uint16_t keycode);
11.19
11.20 @@ -304,7 +305,7 @@
11.21 return TRUE;
11.22 }
11.23
11.24 -gboolean video_gtk_display_blank( uint32_t colour )
11.25 +void video_gtk_display_blank( uint32_t colour )
11.26 {
11.27 GdkGC *gc = gdk_gc_new(gtk_video_drawable->window);
11.28 GdkColor color = {0, ((colour>>16)&0xFF)*257, ((colour>>8)&0xFF)*257, ((colour)&0xFF)*257 };
12.1 --- a/src/drivers/video_null.c Sun Apr 20 05:30:07 2008 +0000
12.2 +++ b/src/drivers/video_null.c Mon May 12 10:00:13 2008 +0000
12.3 @@ -21,40 +21,37 @@
12.4
12.5 #include "display.h"
12.6
12.7 -render_buffer_t video_null_create_render_buffer( uint32_t hres, uint32_t vres )
12.8 +static render_buffer_t video_null_create_render_buffer( uint32_t hres, uint32_t vres )
12.9 {
12.10 return NULL;
12.11 }
12.12
12.13 -void video_null_destroy_render_buffer( render_buffer_t buffer )
12.14 +static void video_null_destroy_render_buffer( render_buffer_t buffer )
12.15 {
12.16 }
12.17
12.18 -gboolean video_null_set_render_target( render_buffer_t buffer )
12.19 +static gboolean video_null_set_render_target( render_buffer_t buffer )
12.20 {
12.21 return TRUE;
12.22 }
12.23
12.24 -gboolean video_null_display_render_buffer( render_buffer_t buffer )
12.25 +static void video_null_display_render_buffer( render_buffer_t buffer )
12.26 +{
12.27 +}
12.28 +
12.29 +static gboolean video_null_read_render_buffer( unsigned char *target,
12.30 + render_buffer_t buffer,
12.31 + int rowstride, int format )
12.32 {
12.33 return TRUE;
12.34 }
12.35
12.36 -gboolean video_null_read_render_buffer( unsigned char *target, render_buffer_t buffer, int rowstride, int format )
12.37 -{
12.38 - return TRUE;
12.39 -}
12.40 -
12.41 -void video_null_load_frame_buffer( frame_buffer_t frame, render_buffer_t buffer )
12.42 +static void video_null_load_frame_buffer( frame_buffer_t frame,
12.43 + render_buffer_t buffer )
12.44 {
12.45 }
12.46
12.47 -gboolean video_null_display_blank( uint32_t colour )
12.48 -{
12.49 - return TRUE;
12.50 -}
12.51 -
12.52 -void video_null_display_back_buffer( void )
12.53 +static void video_null_display_blank( uint32_t colour )
12.54 {
12.55 }
12.56
13.1 --- a/src/gdrom/edc_ecc.c Sun Apr 20 05:30:07 2008 +0000
13.2 +++ b/src/gdrom/edc_ecc.c Mon May 12 10:00:13 2008 +0000
13.3 @@ -1,6 +1,6 @@
13.4 /*
13.5 * Note: This file has been extracted from crkit 1.1.6 and modified to work within
13.6 - * lxdream, but is otherwise unchanged.
13.7 + * lxdream.
13.8 */
13.9 /*
13.10 * This file has been modified for the cdrkit suite.
13.11 @@ -48,13 +48,28 @@
13.12
13.13 #define xaligned(a, s) ((((uintptr_t)(a)) & (s)) == 0 )
13.14
13.15 -/* these prototypes will become public when the function are implemented */
13.16 -static int do_decode_L2(unsigned char in[(L2_RAW+L2_Q+L2_P)],
13.17 - unsigned char out[L2_RAW]);
13.18 +int do_encode_L2(unsigned char inout[(12 + 4 + L2_RAW+4+8+L2_Q+L2_P)],
13.19 + int sectortype, unsigned address);
13.20
13.21 -static int do_decode_L1(unsigned char in[(L1_RAW+L1_Q+L1_P)*FRAMES_PER_SECTOR],
13.22 - unsigned char out[L1_RAW*FRAMES_PER_SECTOR],
13.23 - int delay1, int delay2, int delay3, int scramble);
13.24 +int do_encode_L1(unsigned char in[L1_RAW*FRAMES_PER_SECTOR],
13.25 + unsigned char out[(L1_RAW+L1_Q+L1_P)*FRAMES_PER_SECTOR],
13.26 + int delay1, int delay2, int delay3, int permute);
13.27 +
13.28 +int do_encode_sub(unsigned char in[LSUB_RAW*PACKETS_PER_SUBCHANNELFRAME],
13.29 + unsigned char out[(LSUB_RAW+LSUB_Q+LSUB_P)*PACKETS_PER_SUBCHANNELFRAME],
13.30 + int delay1, int permute);
13.31 +
13.32 +int do_decode_L2(unsigned char in[(L2_RAW+L2_Q+L2_P)],
13.33 + unsigned char out[L2_RAW]);
13.34 +
13.35 +int do_decode_L1(unsigned char in[(L1_RAW+L1_Q+L1_P)*FRAMES_PER_SECTOR],
13.36 + unsigned char out[L1_RAW*FRAMES_PER_SECTOR],
13.37 + int delay1, int delay2, int delay3, int permute);
13.38 +
13.39 +int do_decode_sub(unsigned char in[(LSUB_RAW+LSUB_Q+LSUB_P)*PACKETS_PER_SUBCHANNELFRAME],
13.40 + unsigned char out[LSUB_RAW*PACKETS_PER_SUBCHANNELFRAME],
13.41 + int delay1, int permute);
13.42 +
13.43
13.44
13.45 /* ------------- tables generated by gen_encodes --------------*/
13.46 @@ -240,12 +255,9 @@
13.47 }
13.48
13.49 /* Layer 2 Product code en/decoder */
13.50 +
13.51 int do_encode_L2(unsigned char inout[(12 + 4 + L2_RAW+4+8+L2_Q+L2_P)],
13.52 - int sectortype, unsigned address);
13.53 -
13.54 -int
13.55 -do_encode_L2(unsigned char inout[(12 + 4 + L2_RAW+4+8+L2_Q+L2_P)],
13.56 - int sectortype, unsigned address)
13.57 + int sectortype, unsigned address)
13.58 {
13.59 unsigned int result;
13.60
13.61 @@ -502,10 +514,6 @@
13.62 static unsigned char l1_delay_line3[MAX_L1_DEL3][L1_RAW+L1_Q+L1_P];
13.63 static unsigned l1_del_index;
13.64
13.65 -int do_encode_L1(unsigned char in[L1_RAW*FRAMES_PER_SECTOR],
13.66 - unsigned char out[(L1_RAW+L1_Q+L1_P)*FRAMES_PER_SECTOR],
13.67 - int delay1, int delay2, int delay3, int permute);
13.68 -
13.69 int do_encode_L1(unsigned char in[L1_RAW*FRAMES_PER_SECTOR],
13.70 unsigned char out[(L1_RAW+L1_Q+L1_P)*FRAMES_PER_SECTOR],
13.71 int delay1, int delay2, int delay3, int permute)
13.72 @@ -583,16 +591,9 @@
13.73 return (0);
13.74 }
13.75
13.76 -static
13.77 -int do_decode_L1(unsigned char in[(L1_RAW+L1_Q+L1_P)*FRAMES_PER_SECTOR],
13.78 - unsigned char out[L1_RAW*FRAMES_PER_SECTOR],
13.79 - int delay1, int delay2, int delay3, int permute);
13.80 -
13.81 -static /* XXX should be non static XXX*/
13.82 -
13.83 int do_decode_L1(unsigned char in[(L1_RAW+L1_Q+L1_P)*FRAMES_PER_SECTOR],
13.84 - unsigned char out[L1_RAW*FRAMES_PER_SECTOR],
13.85 - int delay1, int delay2, int delay3, int permute)
13.86 + unsigned char out[L1_RAW*FRAMES_PER_SECTOR],
13.87 + int delay1, int delay2, int delay3, int permute)
13.88 {
13.89 int i;
13.90
13.91 @@ -667,10 +668,7 @@
13.92 return (0);
13.93 }
13.94
13.95 -static int do_decode_L2(unsigned char in[(L2_RAW+L2_Q+L2_P)],
13.96 - unsigned char out[L2_RAW]);
13.97 -
13.98 -static int do_decode_L2(unsigned char in[(L2_RAW+L2_Q+L2_P)],
13.99 +int do_decode_L2(unsigned char in[(L2_RAW+L2_Q+L2_P)],
13.100 unsigned char out[L2_RAW])
13.101 {
13.102 return (0);
13.103 @@ -684,10 +682,6 @@
13.104
13.105 /* R-W Subchannel en/decoder */
13.106
13.107 -int do_encode_sub(unsigned char in[LSUB_RAW*PACKETS_PER_SUBCHANNELFRAME],
13.108 - unsigned char out[(LSUB_RAW+LSUB_Q+LSUB_P)*PACKETS_PER_SUBCHANNELFRAME],
13.109 - int delay1, int permute);
13.110 -
13.111 int do_encode_sub(unsigned char in[LSUB_RAW*PACKETS_PER_SUBCHANNELFRAME],
13.112 unsigned char out[(LSUB_RAW+LSUB_Q+LSUB_P)*PACKETS_PER_SUBCHANNELFRAME],
13.113 int delay1, int permute)
13.114 @@ -732,16 +726,9 @@
13.115 return (0);
13.116 }
13.117
13.118 -int
13.119 -do_decode_sub(
13.120 - unsigned char in[(LSUB_RAW+LSUB_Q+LSUB_P)*PACKETS_PER_SUBCHANNELFRAME],
13.121 - unsigned char out[LSUB_RAW*PACKETS_PER_SUBCHANNELFRAME],
13.122 - int delay1, int permute);
13.123 -
13.124 -int
13.125 -do_decode_sub(unsigned char in[(LSUB_RAW+LSUB_Q+LSUB_P)*PACKETS_PER_SUBCHANNELFRAME],
13.126 - unsigned char out[LSUB_RAW*PACKETS_PER_SUBCHANNELFRAME],
13.127 - int delay1, int permute)
13.128 +int do_decode_sub(unsigned char in[(LSUB_RAW+LSUB_Q+LSUB_P)*PACKETS_PER_SUBCHANNELFRAME],
13.129 + unsigned char out[LSUB_RAW*PACKETS_PER_SUBCHANNELFRAME],
13.130 + int delay1, int permute)
13.131 {
13.132 int i;
13.133
13.134 @@ -812,168 +799,3 @@
13.135 }
13.136 }
13.137
13.138 -/* ------------- --------------*/
13.139 -#ifdef MAIN
13.140 -
13.141 -#define DO_L1 1
13.142 -#define DO_L2 2
13.143 -#define DO_SUB 4
13.144 -
13.145 -static const unsigned sect_size[8][2] = {
13.146 -/* nothing */
13.147 -{0,0},
13.148 -/* Layer 1 decode/encode */
13.149 -{ (L1_RAW+L1_Q+L1_P)*FRAMES_PER_SECTOR, L1_RAW*FRAMES_PER_SECTOR},
13.150 -/* Layer 2 decode/encode */
13.151 -{ 16+L2_RAW+12+L2_Q+L2_P, L2_RAW},
13.152 -/* Layer 1 and 2 decode/encode */
13.153 -{ (L1_RAW+L1_Q+L1_P)*FRAMES_PER_SECTOR, L1_RAW*FRAMES_PER_SECTOR},
13.154 -/* Subchannel decode/encode */
13.155 -{ (LSUB_RAW+LSUB_Q+LSUB_P)*PACKETS_PER_SUBCHANNELFRAME,
13.156 - LSUB_RAW*PACKETS_PER_SUBCHANNELFRAME},
13.157 -/* Layer 1 and subchannel decode/encode */
13.158 -{ (L1_RAW+L1_Q+L1_P)*FRAMES_PER_SECTOR +
13.159 - (LSUB_RAW+LSUB_Q+LSUB_P)*PACKETS_PER_SUBCHANNELFRAME,
13.160 - LSUB_RAW*PACKETS_PER_SUBCHANNELFRAME +
13.161 - L1_RAW*FRAMES_PER_SECTOR},
13.162 -/* Layer 2 and subchannel decode/encode */
13.163 -{ L2_RAW+L2_Q+L2_P+
13.164 - (LSUB_RAW+LSUB_Q+LSUB_P)*PACKETS_PER_SUBCHANNELFRAME,
13.165 - LSUB_RAW*PACKETS_PER_SUBCHANNELFRAME +
13.166 - L2_RAW},
13.167 -/* Layer 1, 2 and subchannel decode/encode */
13.168 -{ (L1_RAW+L1_Q+L1_P)*FRAMES_PER_SECTOR +
13.169 - (LSUB_RAW+LSUB_Q+LSUB_P)*PACKETS_PER_SUBCHANNELFRAME,
13.170 - LSUB_RAW*PACKETS_PER_SUBCHANNELFRAME +
13.171 - L1_RAW*FRAMES_PER_SECTOR},
13.172 -};
13.173 -
13.174 -int main(int argc, char *argv[])
13.175 -{
13.176 - int encode = 1;
13.177 - int mask = DO_L2;
13.178 - FILE *infp;
13.179 - FILE *outfp;
13.180 - unsigned address = 0;
13.181 - unsigned char *l1_inbuf;
13.182 - unsigned char *l1_outbuf;
13.183 - unsigned char *l2_inbuf;
13.184 - unsigned char *l2_outbuf;
13.185 - unsigned char *sub_inbuf;
13.186 - unsigned char *sub_outbuf;
13.187 - unsigned char *last_outbuf;
13.188 - unsigned char inbuf[(LSUB_RAW+LSUB_Q+LSUB_P)*PACKETS_PER_SUBCHANNELFRAME +
13.189 - (L1_RAW+L1_Q+L1_P)*FRAMES_PER_SECTOR];
13.190 - unsigned char outbuf[(LSUB_RAW+LSUB_Q+LSUB_P)*PACKETS_PER_SUBCHANNELFRAME +
13.191 - (L1_RAW+L1_Q+L1_P)*FRAMES_PER_SECTOR];
13.192 - unsigned load_offset;
13.193 -
13.194 - l1_inbuf = l2_inbuf = sub_inbuf = inbuf;
13.195 - l1_outbuf = l2_outbuf = sub_outbuf = last_outbuf = outbuf;
13.196 -
13.197 - infp = fopen("sectors_in", "rb");
13.198 - outfp = fopen("sectors_out", "wb");
13.199 -
13.200 - sectortype= MODE_1;
13.201 - address = 0 + 75*2;
13.202 -
13.203 - switch (sectortype) {
13.204 -
13.205 - case MODE_1:
13.206 - case MODE_2:
13.207 - load_offset = 16;
13.208 - break;
13.209 - case MODE_2_FORM_1:
13.210 - case MODE_2_FORM_2:
13.211 - load_offset = 24;
13.212 - break;
13.213 - default:
13.214 - load_offset = 0;
13.215 - }
13.216 - while(1) {
13.217 -
13.218 - if (1 != fread(inbuf+load_offset,
13.219 - sect_size[mask][encode], 1, infp)) {
13.220 - perror("");
13.221 - break;
13.222 - }
13.223 - if (encode == 1) {
13.224 - if (mask & DO_L2) {
13.225 - switch (sectortype) {
13.226 -
13.227 - case MODE_0:
13.228 - break;
13.229 - case MODE_1:
13.230 - break;
13.231 - case MODE_2:
13.232 - if (1 !=
13.233 - fread(inbuf+load_offset+
13.234 - sect_size[mask][encode],
13.235 - 2336 - sect_size[mask][encode],
13.236 - 1, infp)) { perror(""); break; }
13.237 - break;
13.238 - case MODE_2_FORM_1:
13.239 - break;
13.240 - case MODE_2_FORM_2:
13.241 - if (1 !=
13.242 - fread(inbuf+load_offset+
13.243 - sect_size[mask][encode],
13.244 - 2324 - sect_size[mask][encode],
13.245 - 1, infp)) { perror(""); break; }
13.246 - break;
13.247 - default:
13.248 - if (1 !=
13.249 - fread(inbuf+load_offset+
13.250 - sect_size[mask][encode],
13.251 - 2448 - sect_size[mask][encode],
13.252 - 1, infp)) { perror(""); break; }
13.253 - memset(inbuf,0,16);
13.254 - /*memset(inbuf+16+2048,0,12+272);*/
13.255 - break;
13.256 - }
13.257 - do_encode_L2(l2_inbuf, MODE_1, address);
13.258 - if (0) scramble_L2(l2_inbuf);
13.259 - last_outbuf = l1_inbuf = l2_inbuf;
13.260 - l1_outbuf = l2_inbuf;
13.261 - sub_inbuf = l2_inbuf + L2_RAW;
13.262 - sub_outbuf = l2_outbuf + 12 + 4+ L2_RAW+4+ 8+ L2_Q+L2_P;
13.263 - }
13.264 - if (mask & DO_L1) {
13.265 - do_encode_L1(l1_inbuf, l1_outbuf,1,1,1,1);
13.266 - last_outbuf = l1_outbuf;
13.267 - sub_inbuf = l1_inbuf + L1_RAW*FRAMES_PER_SECTOR;
13.268 - sub_outbuf = l1_outbuf + (L1_RAW+L1_Q+L1_P)*FRAMES_PER_SECTOR;
13.269 - }
13.270 - if (mask & DO_SUB) {
13.271 - do_encode_sub(sub_inbuf, sub_outbuf, 0, 0);
13.272 - }
13.273 - } else {
13.274 - if (mask & DO_L1) {
13.275 - do_decode_L1(l1_inbuf, l1_outbuf,1,1,1,1);
13.276 - last_outbuf = l2_inbuf = l1_outbuf;
13.277 - l2_outbuf = l1_inbuf;
13.278 - sub_inbuf = l1_inbuf + (L1_RAW+L1_Q+L1_P)*FRAMES_PER_SECTOR;
13.279 - sub_outbuf = l1_outbuf + L1_RAW*FRAMES_PER_SECTOR;
13.280 - }
13.281 - if (mask & DO_L2) {
13.282 - do_decode_L2(l2_inbuf, l2_outbuf);
13.283 - last_outbuf = l2_outbuf;
13.284 - sub_inbuf = l2_inbuf + L2_RAW+L2_Q+L2_P;
13.285 - sub_outbuf = l2_outbuf + L2_RAW;
13.286 - }
13.287 - if (mask & DO_SUB) {
13.288 - do_decode_sub(sub_inbuf, sub_outbuf, 1, 1);
13.289 - }
13.290 - }
13.291 - if (1 != fwrite(last_outbuf, sect_size[mask][1 - encode], 1, outfp)) {
13.292 - perror("");
13.293 - break;
13.294 - }
13.295 - address++;
13.296 - }
13.297 -#if 0
13.298 - /* flush the data from the delay lines with zeroed sectors, if necessary */
13.299 -#endif
13.300 - return (0);
13.301 -}
13.302 -#endif
14.1 --- a/src/gdrom/gdimage.c Sun Apr 20 05:30:07 2008 +0000
14.2 +++ b/src/gdrom/gdimage.c Mon May 12 10:00:13 2008 +0000
14.3 @@ -151,7 +151,7 @@
14.4 int size = -file_offset;
14.5 if( size >= length ) {
14.6 memset( buf, 0, length );
14.7 - return;
14.8 + return TRUE;
14.9 } else {
14.10 memset( buf, 0, size );
14.11 file_offset = 0;
14.12 @@ -288,7 +288,6 @@
14.13 break;
14.14 }
14.15
14.16 - int mode_restrict = READ_CD_MODE(mode);
14.17 if( !gdrom_is_compatible_read_mode(sector_mode, READ_CD_MODE(mode)) ) {
14.18 return PKT_ERR_BADREADMODE;
14.19 }
15.1 --- a/src/gtkui/ctrl_dlg.c Sun Apr 20 05:30:07 2008 +0000
15.2 +++ b/src/gtkui/ctrl_dlg.c Mon May 12 10:00:13 2008 +0000
15.3 @@ -18,6 +18,7 @@
15.4 */
15.5
15.6 #include <assert.h>
15.7 +#include <string.h>
15.8 #include <gtk/gtk.h>
15.9 #include <gdk/gdkkeysyms.h>
15.10
16.1 --- a/src/gtkui/debug_win.c Sun Apr 20 05:30:07 2008 +0000
16.2 +++ b/src/gtkui/debug_win.c Mon May 12 10:00:13 2008 +0000
16.3 @@ -23,6 +23,7 @@
16.4 #include <gdk/gdkkeysyms.h>
16.5 #include "mem.h"
16.6 #include "cpu.h"
16.7 +#include "dreamcast.h"
16.8 #include "gtkui/gtkui.h"
16.9 #include "sh4/sh4dasm.h"
16.10 #include "aica/armdasm.h"
17.1 --- a/src/gtkui/dump_win.c Sun Apr 20 05:30:07 2008 +0000
17.2 +++ b/src/gtkui/dump_win.c Mon May 12 10:00:13 2008 +0000
17.3 @@ -19,6 +19,7 @@
17.4 #include <ctype.h>
17.5 #include <assert.h>
17.6 #include <string.h>
17.7 +#include <stdlib.h>
17.8 #include <glib/gi18n.h>
17.9 #include "mem.h"
17.10 #include "gtkui/gtkui.h"
18.1 --- a/src/gtkui/gtkcb.c Sun Apr 20 05:30:07 2008 +0000
18.2 +++ b/src/gtkui/gtkcb.c Mon May 12 10:00:13 2008 +0000
18.3 @@ -135,7 +135,7 @@
18.4 GtkWidget *file, *preview, *frame, *align;
18.5 GtkRequisition size;
18.6 const gchar *dir = lxdream_get_config_value(CONFIG_SAVE_PATH);
18.7 - const gchar *path = get_absolute_path(dir);
18.8 + gchar *path = get_absolute_path(dir);
18.9 file = gtk_file_chooser_dialog_new( _("Load state..."), NULL,
18.10 GTK_FILE_CHOOSER_ACTION_OPEN,
18.11 GTK_STOCK_CANCEL, GTK_RESPONSE_CANCEL,
19.1 --- a/src/gtkui/gtkui.c Sun Apr 20 05:30:07 2008 +0000
19.2 +++ b/src/gtkui/gtkui.c Mon May 12 10:00:13 2008 +0000
19.3 @@ -19,6 +19,7 @@
19.4 #include "lxdream.h"
19.5 #include <sys/time.h>
19.6 #include <time.h>
19.7 +#include <unistd.h>
19.8 #include <glib/gi18n.h>
19.9 #include <gtk/gtkversion.h>
19.10 #include "dreamcast.h"
19.11 @@ -319,15 +320,6 @@
19.12 return mmio_win;
19.13 }
19.14
19.15 -GtkWidget *gtk_gui_get_renderarea()
19.16 -{
19.17 - if( main_win == NULL ) {
19.18 - return NULL;
19.19 - } else {
19.20 - return main_window_get_renderarea(main_win);
19.21 - }
19.22 -}
19.23 -
19.24 /**
19.25 * Hook called when DC starts running. Just disables the run/step buttons
19.26 * and enables the stop button.
20.1 --- a/src/gtkui/gtkui.h Sun Apr 20 05:30:07 2008 +0000
20.2 +++ b/src/gtkui/gtkui.h Mon May 12 10:00:13 2008 +0000
20.3 @@ -115,9 +115,9 @@
20.4 void gdrom_menu_init();
20.5 GtkWidget *gdrom_menu_new();
20.6
20.7 -/******************** Video driver hooks *********************/
20.8 +/******************** Video driver hook *********************/
20.9
20.10 -GtkWidget *gtk_gui_get_renderarea();
20.11 +GtkWidget *video_gtk_create_drawable();
20.12
20.13 /******************* Callback declarations *******************/
20.14
21.1 --- a/src/gtkui/main_win.c Sun Apr 20 05:30:07 2008 +0000
21.2 +++ b/src/gtkui/main_win.c Mon May 12 10:00:13 2008 +0000
21.3 @@ -31,6 +31,8 @@
21.4 #include <X11/Xutil.h>
21.5
21.6 #include "lxdream.h"
21.7 +#include "dreamcast.h"
21.8 +#include "display.h"
21.9 #include "gtkui/gtkui.h"
21.10
21.11
21.12 @@ -192,7 +194,6 @@
21.13 static gboolean on_video_window_key_released( GtkWidget *widget, GdkEventKey *event,
21.14 gpointer user_data )
21.15 {
21.16 - main_window_t win = (main_window_t)user_data;
21.17 input_event_keyup( NULL, gtk_get_unmodified_keyval(event), 0 );
21.18 return TRUE;
21.19 }
21.20 @@ -201,6 +202,7 @@
21.21 gpointer user_data )
21.22 {
21.23 display_set_focused(event->in);
21.24 + return TRUE;
21.25 }
21.26
21.27 /*************************** Main window (frame) ******************************/
22.1 --- a/src/main.c Sun Apr 20 05:30:07 2008 +0000
22.2 +++ b/src/main.c Mon May 12 10:00:13 2008 +0000
22.3 @@ -19,8 +19,8 @@
22.4
22.5 #include <unistd.h>
22.6 #include <getopt.h>
22.7 -#include "dream.h"
22.8 -#include "config.h"
22.9 +#include <glib/gi18n.h>
22.10 +#include "lxdream.h"
22.11 #include "syscall.h"
22.12 #include "mem.h"
22.13 #include "dreamcast.h"
22.14 @@ -54,7 +54,7 @@
22.15
22.16 int main (int argc, char *argv[])
22.17 {
22.18 - int opt, i;
22.19 + int opt;
22.20 double t;
22.21 gboolean display_ok;
22.22
23.1 --- a/src/maple/mouse.c Sun Apr 20 05:30:07 2008 +0000
23.2 +++ b/src/maple/mouse.c Mon May 12 10:00:13 2008 +0000
23.3 @@ -18,6 +18,7 @@
23.4 #include <stdlib.h>
23.5 #include <stdio.h>
23.6 #include <string.h>
23.7 +#include "display.h"
23.8 #include "maple/maple.h"
23.9
23.10 #define MOUSE_IDENT { 0x00, 0x00, 0x02, 0x00, 0x02, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,\
24.1 --- a/src/mem.c Sun Apr 20 05:30:07 2008 +0000
24.2 +++ b/src/mem.c Mon May 12 10:00:13 2008 +0000
24.3 @@ -365,6 +365,13 @@
24.4 }
24.5 }
24.6
24.7 +void mem_write_long( sh4addr_t addr, uint32_t value )
24.8 +{
24.9 + sh4ptr_t ptr = mem_get_region(addr);
24.10 + assert(ptr != NULL);
24.11 + *((uint32_t *)ptr) = value;
24.12 +}
24.13 +
24.14 struct mmio_region *mem_get_io_region( uint32_t addr )
24.15 {
24.16 if( addr > 0xFF000000 ) {
25.1 --- a/src/mem.h Sun Apr 20 05:30:07 2008 +0000
25.2 +++ b/src/mem.h Mon May 12 10:00:13 2008 +0000
25.3 @@ -69,6 +69,13 @@
25.4 void mem_copy_from_sh4( sh4ptr_t dest, sh4addr_t src, size_t count );
25.5 void mem_copy_to_sh4( sh4addr_t dest, sh4ptr_t src, size_t count );
25.6
25.7 +/**
25.8 + * Write a long value directly to SH4-addressable memory.
25.9 + * @param dest a valid, writable physical memory address, relative to the SH4
25.10 + * @param value the value to write.
25.11 + */
25.12 +void mem_write_long( sh4addr_t dest, uint32_t value );
25.13 +
25.14 #define ENABLE_DEBUG_MODE 1
25.15
25.16 typedef enum { BREAK_NONE=0, BREAK_ONESHOT=1, BREAK_KEEP=2 } breakpoint_type_t;
26.1 --- a/src/pvr2/gl_sl.c Sun Apr 20 05:30:07 2008 +0000
26.2 +++ b/src/pvr2/gl_sl.c Mon May 12 10:00:13 2008 +0000
26.3 @@ -18,8 +18,6 @@
26.4 * GNU General Public License for more details.
26.5 */
26.6
26.7 -#define GL_GLEXT_PROTOTYPES 1
26.8 -
26.9 #include "lxdream.h"
26.10 #include "display.h"
26.11 #include "pvr2/glutil.h"
26.12 @@ -107,7 +105,7 @@
26.13 return pok;
26.14 }
26.15
26.16 -void glsl_enable_shader(gboolean en)
26.17 +void glsl_enable_shaders(gboolean en)
26.18 {
26.19 if( glsl_program != 0 ) {
26.20 if( en ) {
26.21 @@ -200,7 +198,7 @@
26.22 }
26.23
26.24
26.25 -void glsl_enable_shader(gboolean en)
26.26 +void glsl_enable_shaders(gboolean en)
26.27 {
26.28 if( glsl_program != 0 ) {
26.29 if( en ) {
26.30 @@ -231,4 +229,7 @@
26.31 {
26.32 }
26.33
26.34 +void glsl_enable_shaders( gboolean enable )
26.35 +{
26.36 +}
26.37 #endif
27.1 --- a/src/pvr2/glrender.c Sun Apr 20 05:30:07 2008 +0000
27.2 +++ b/src/pvr2/glrender.c Mon May 12 10:00:13 2008 +0000
27.3 @@ -17,6 +17,7 @@
27.4 */
27.5
27.6 #include <assert.h>
27.7 +#include <sys/time.h>
27.8 #include "display.h"
27.9 #include "pvr2/pvr2.h"
27.10 #include "pvr2/scene.h"
27.11 @@ -153,8 +154,6 @@
27.12
27.13
27.14 if( POLY1_TEXTURED(poly1) ) {
27.15 - int width = POLY2_TEX_WIDTH(poly2);
27.16 - int height = POLY2_TEX_HEIGHT(poly2);
27.17 glEnable(GL_TEXTURE_2D);
27.18 glTexEnvi( GL_TEXTURE_ENV, GL_TEXTURE_ENV_MODE, pvr2_poly_texblend[POLY2_TEX_BLEND(poly2)] );
27.19 if( POLY2_TEX_CLAMP_U(poly2) ) {
27.20 @@ -271,6 +270,9 @@
27.21 glInterleavedArrays(GL_T2F_C4UB_V3F, sizeof(struct vertex_struct), pvr2_scene.vertex_array);
27.22 glSecondaryColorPointerEXT(3, GL_UNSIGNED_BYTE, sizeof(struct vertex_struct), &pvr2_scene.vertex_array[0].offset_rgba );
27.23
27.24 + /* Turn on the shaders (if available) */
27.25 + glsl_enable_shaders(TRUE);
27.26 +
27.27 uint32_t bgplane_mode = MMIO_READ(PVR2, RENDER_BGPLANE);
27.28 uint32_t *bgplane = pvr2_scene.pvr2_pbuf + (((bgplane_mode & 0x00FFFFFF)) >> 3) ;
27.29 render_backplane( bgplane, pvr2_scene.buffer_width, pvr2_scene.buffer_height, bgplane_mode );
27.30 @@ -283,7 +285,7 @@
27.31 int tilex = SEGMENT_X(segment->control);
27.32 int tiley = SEGMENT_Y(segment->control);
27.33
27.34 - int tile_bounds[4] = { tilex << 5, (tilex+1)<<5, tiley<<5, (tiley+1)<<5 };
27.35 + uint32_t tile_bounds[4] = { tilex << 5, (tilex+1)<<5, tiley<<5, (tiley+1)<<5 };
27.36 if( !clip_tile_bounds(tile_bounds, pvr2_scene.bounds) ) {
27.37 continue; // fully clipped, skip tile
27.38 }
27.39 @@ -310,6 +312,8 @@
27.40 } while( !IS_LAST_SEGMENT(segment++) );
27.41 glDisable( GL_SCISSOR_TEST );
27.42
27.43 + glsl_enable_shaders(FALSE);
27.44 +
27.45 gettimeofday( &end_tv, NULL );
27.46 ms = (end_tv.tv_sec - tex_tv.tv_sec) * 1000 +
27.47 (end_tv.tv_usec - tex_tv.tv_usec)/1000;
28.1 --- a/src/pvr2/glutil.h Sun Apr 20 05:30:07 2008 +0000
28.2 +++ b/src/pvr2/glutil.h Mon May 12 10:00:13 2008 +0000
28.3 @@ -41,6 +41,7 @@
28.4 gboolean glsl_is_supported(void);
28.5 gboolean glsl_load_shaders( const char *vert_shader, const char *frag_shader );
28.6 void glsl_unload_shaders(void);
28.7 +void glsl_enable_shaders( gboolean enable );
28.8
28.9 extern const char *glsl_vertex_shader_src;
28.10 extern const char *glsl_fragment_shader_src;
29.1 --- a/src/pvr2/pvr2.c Sun Apr 20 05:30:07 2008 +0000
29.2 +++ b/src/pvr2/pvr2.c Mon May 12 10:00:13 2008 +0000
29.3 @@ -25,6 +25,7 @@
29.4 #include "asic.h"
29.5 #include "clock.h"
29.6 #include "pvr2/pvr2.h"
29.7 +#include "pvr2/scene.h"
29.8 #include "sh4/sh4.h"
29.9 #define MMIO_IMPL
29.10 #include "pvr2/pvr2mmio.h"
30.1 --- a/src/pvr2/pvr2.h Sun Apr 20 05:30:07 2008 +0000
30.2 +++ b/src/pvr2/pvr2.h Mon May 12 10:00:13 2008 +0000
30.3 @@ -244,31 +244,24 @@
30.4
30.5 /********************************* Renderer ******************************/
30.6
30.7 -void pvr2_read_scene( void );
30.8 -
30.9 /**
30.10 * Render the current scene stored in PVR ram to the GL back buffer.
30.11 */
30.12 -void pvr2_render_scene( render_buffer_t buffer );
30.13 +void pvr2_scene_render( render_buffer_t buffer );
30.14
30.15 /**
30.16 - * Display the scene rendered to the supplied address.
30.17 - * @return TRUE if there was an available render that was displayed,
30.18 - * otherwise FALSE (and no action was taken)
30.19 + * Perform the initial once-off GL setup, usually immediately after the GL
30.20 + * context is first bound.
30.21 */
30.22 -gboolean pvr2_render_display_frame( uint32_t address );
30.23 -
30.24 +void pvr2_setup_gl_context();
30.25
30.26 void render_backplane( uint32_t *polygon, uint32_t width, uint32_t height, uint32_t mode );
30.27
30.28 +void render_autosort_tile( pvraddr_t tile_entry, int render_mode );
30.29 +
30.30 void render_set_context( uint32_t *context, int render_mode );
30.31
30.32 -void pvr2_render_tilebuffer( int width, int height, int clipx1, int clipy1,
30.33 - int clipx2, int clipy2 );
30.34 -
30.35 -void pvr2_render_find_z_range( float *min, float *max );
30.36 -
30.37 -void pvr2_render_getsize( int *x, int *y );
30.38 +void gl_render_tilelist( pvraddr_t tile_entry );
30.39
30.40 /**
30.41 * Structure to hold a complete unpacked vertex (excluding modifier
31.1 --- a/src/pvr2/pvr2mem.c Sun Apr 20 05:30:07 2008 +0000
31.2 +++ b/src/pvr2/pvr2mem.c Mon May 12 10:00:13 2008 +0000
31.3 @@ -20,6 +20,7 @@
31.4 #include <errno.h>
31.5 #include "pvr2.h"
31.6 #include "asic.h"
31.7 +#include "dream.h"
31.8
31.9 extern unsigned char *video_base;
31.10
32.1 --- a/src/pvr2/rendsave.c Sun Apr 20 05:30:07 2008 +0000
32.2 +++ b/src/pvr2/rendsave.c Mon May 12 10:00:13 2008 +0000
32.3 @@ -19,6 +19,7 @@
32.4 #include <stdio.h>
32.5 #include <errno.h>
32.6 #include <time.h>
32.7 +#include <string.h>
32.8 #include "pvr2/pvr2.h"
32.9 #include "dreamcast.h"
32.10
33.1 --- a/src/pvr2/rendsort.c Sun Apr 20 05:30:07 2008 +0000
33.2 +++ b/src/pvr2/rendsort.c Mon May 12 10:00:13 2008 +0000
33.3 @@ -22,8 +22,6 @@
33.4 #include "pvr2/scene.h"
33.5 #include "asic.h"
33.6
33.7 -extern char *video_base;
33.8 -
33.9 #define MIN3( a,b,c ) ((a) < (b) ? ( (a) < (c) ? (a) : (c) ) : ((b) < (c) ? (b) : (c)) )
33.10 #define MAX3( a,b,c ) ((a) > (b) ? ( (a) > (c) ? (a) : (c) ) : ((b) > (c) ? (b) : (c)) )
33.11
34.1 --- a/src/pvr2/scene.c Sun Apr 20 05:30:07 2008 +0000
34.2 +++ b/src/pvr2/scene.c Mon May 12 10:00:13 2008 +0000
34.3 @@ -54,7 +54,10 @@
34.4 struct pvr2_scene_struct pvr2_scene;
34.5
34.6 static gboolean vbo_init = FALSE;
34.7 +
34.8 +#ifdef ENABLE_VERTEX_BUFFER
34.9 static gboolean vbo_supported = FALSE;
34.10 +#endif
34.11
34.12 /**
34.13 * Test for VBO support, and allocate all the system memory needed for the
34.14 @@ -618,7 +621,7 @@
34.15 fprintf( f, "Polygons: %d\n", pvr2_scene.poly_count );
34.16 for( i=0; i<pvr2_scene.poly_count; i++ ) {
34.17 struct polygon_struct *poly = &pvr2_scene.poly_array[i];
34.18 - fprintf( f, " %08X ", ((char *)poly->context) - video_base );
34.19 + fprintf( f, " %08X ", ((unsigned char *)poly->context) - video_base );
34.20 switch( poly->vertex_count ) {
34.21 case 3: fprintf( f, "Tri " ); break;
34.22 case 4: fprintf( f, "Quad " ); break;
35.1 --- a/src/pvr2/scene.h Sun Apr 20 05:30:07 2008 +0000
35.2 +++ b/src/pvr2/scene.h Mon May 12 10:00:13 2008 +0000
35.3 @@ -50,7 +50,10 @@
35.4 void pvr2_scene_read(void);
35.5 void pvr2_scene_shutdown();
35.6
35.7 -extern char *video_base;
35.8 +uint32_t pvr2_scene_buffer_width();
35.9 +uint32_t pvr2_scene_buffer_height();
35.10 +
35.11 +extern unsigned char *video_base;
35.12
35.13 /**
35.14 * Maximum possible size of the vertex buffer. This is figured as follows:
36.1 --- a/src/pvr2/tacore.c Sun Apr 20 05:30:07 2008 +0000
36.2 +++ b/src/pvr2/tacore.c Mon May 12 10:00:13 2008 +0000
36.3 @@ -16,8 +16,10 @@
36.4 * GNU General Public License for more details.
36.5 */
36.6 #include <string.h>
36.7 +#include "lxdream.h"
36.8 #include "pvr2.h"
36.9 #include "asic.h"
36.10 +#include "dream.h"
36.11
36.12 #define STATE_IDLE 0
36.13 #define STATE_IN_LIST 1
37.1 --- a/src/sh4/ia32abi.h Sun Apr 20 05:30:07 2008 +0000
37.2 +++ b/src/sh4/ia32abi.h Mon May 12 10:00:13 2008 +0000
37.3 @@ -98,7 +98,7 @@
37.4 {
37.5 PUSH_r32(R_EBP);
37.6 /* mov &sh4r, ebp */
37.7 - load_ptr( R_EBP, &sh4r );
37.8 + load_ptr( R_EBP, ((uint8_t *)&sh4r) + 128 );
37.9
37.10 sh4_x86.in_delay_slot = FALSE;
37.11 sh4_x86.priv_checked = FALSE;
37.12 @@ -282,7 +282,7 @@
37.13 "frame_found: movl 0x4(%%eax), %0\n"
37.14 "frame_not_found:"
37.15 : "=r" (result)
37.16 - : "r" (&sh4r)
37.17 + : "r" (((uint8_t *)&sh4r) + 128 )
37.18 : "eax", "ecx", "edx" );
37.19 return result;
37.20 }
38.1 --- a/src/sh4/ia32mac.h Sun Apr 20 05:30:07 2008 +0000
38.2 +++ b/src/sh4/ia32mac.h Mon May 12 10:00:13 2008 +0000
38.3 @@ -123,7 +123,7 @@
38.4 {
38.5 PUSH_r32(R_EBP);
38.6 /* mov &sh4r, ebp */
38.7 - load_ptr( R_EBP, &sh4r );
38.8 + load_ptr( R_EBP, ((uint8_t *)&sh4r) + 128 );
38.9
38.10 sh4_x86.in_delay_slot = FALSE;
38.11 sh4_x86.priv_checked = FALSE;
38.12 @@ -306,7 +306,7 @@
38.13 "frame_found: movl 0x4(%%eax), %0\n"
38.14 "frame_not_found:"
38.15 : "=r" (result)
38.16 - : "r" (&sh4r)
38.17 + : "r" (((uint8_t *)&sh4r) + 128 )
38.18 : "eax", "ecx", "edx" );
38.19 return result;
38.20 }
39.1 --- a/src/sh4/ia64abi.h Sun Apr 20 05:30:07 2008 +0000
39.2 +++ b/src/sh4/ia64abi.h Mon May 12 10:00:13 2008 +0000
39.3 @@ -95,7 +95,7 @@
39.4 {
39.5 PUSH_r32(R_EBP);
39.6 /* mov &sh4r, ebp */
39.7 - load_ptr( R_EBP, &sh4r );
39.8 + load_ptr( R_EBP, ((uint8_t *)&sh4r) + 128 );
39.9
39.10 sh4_x86.in_delay_slot = FALSE;
39.11 sh4_x86.priv_checked = FALSE;
39.12 @@ -259,7 +259,8 @@
39.13 _Unwind_Reason_Code xlat_check_frame( struct _Unwind_Context *context, void *arg )
39.14 {
39.15 void *rbp = (void *)_Unwind_GetGR(context, 6);
39.16 - if( rbp == (void *)&sh4r ) {
39.17 + void *expect = (((uint8_t *)&sh4r) + 128 )
39.18 + if( rbp == expect ) {
39.19 void **result = (void **)arg;
39.20 *result = (void *)_Unwind_GetIP(context);
39.21 return _URC_NORMAL_STOP;
40.1 --- a/src/sh4/mmu.c Sun Apr 20 05:30:07 2008 +0000
40.2 +++ b/src/sh4/mmu.c Mon May 12 10:00:13 2008 +0000
40.3 @@ -20,6 +20,7 @@
40.4 #include <stdio.h>
40.5 #include "sh4/sh4mmio.h"
40.6 #include "sh4/sh4core.h"
40.7 +#include "sh4/sh4trans.h"
40.8 #include "mem.h"
40.9
40.10 #define VMA_TO_EXT_ADDR(vma) ((vma)&0x1FFFFFFF)
40.11 @@ -119,6 +120,7 @@
40.12 case TLB_SIZE_4K: return MASK_4K;
40.13 case TLB_SIZE_64K: return MASK_64K;
40.14 case TLB_SIZE_1M: return MASK_1M;
40.15 + default: return 0; /* Unreachable */
40.16 }
40.17 }
40.18
40.19 @@ -327,7 +329,7 @@
40.20 * Find a UTLB entry for the associative TLB write - same as the normal
40.21 * lookup but ignores the valid bit.
40.22 */
40.23 -static inline mmu_utlb_lookup_assoc( uint32_t vpn, uint32_t asid )
40.24 +static inline int mmu_utlb_lookup_assoc( uint32_t vpn, uint32_t asid )
40.25 {
40.26 int result = -1;
40.27 unsigned int i;
40.28 @@ -349,7 +351,7 @@
40.29 * Find a ITLB entry for the associative TLB write - same as the normal
40.30 * lookup but ignores the valid bit.
40.31 */
40.32 -static inline mmu_itlb_lookup_assoc( uint32_t vpn, uint32_t asid )
40.33 +static inline int mmu_itlb_lookup_assoc( uint32_t vpn, uint32_t asid )
40.34 {
40.35 int result = -1;
40.36 unsigned int i;
41.1 --- a/src/sh4/sh4.c Sun Apr 20 05:30:07 2008 +0000
41.2 +++ b/src/sh4/sh4.c Mon May 12 10:00:13 2008 +0000
41.3 @@ -22,15 +22,16 @@
41.4 #include <assert.h>
41.5 #include "dream.h"
41.6 #include "dreamcast.h"
41.7 +#include "mem.h"
41.8 +#include "clock.h"
41.9 +#include "eventq.h"
41.10 +#include "syscall.h"
41.11 +#include "sh4/intc.h"
41.12 #include "sh4/sh4core.h"
41.13 #include "sh4/sh4mmio.h"
41.14 -#include "sh4/intc.h"
41.15 -#include "sh4/xltcache.h"
41.16 #include "sh4/sh4stat.h"
41.17 #include "sh4/sh4trans.h"
41.18 -#include "mem.h"
41.19 -#include "clock.h"
41.20 -#include "syscall.h"
41.21 +#include "sh4/xltcache.h"
41.22
41.23 void sh4_init( void );
41.24 void sh4_xlat_init( void );
41.25 @@ -61,7 +62,7 @@
41.26 #ifdef SH4_TRANSLATOR
41.27 if( use ) {
41.28 xlat_cache_init();
41.29 - sh4_x86_init();
41.30 + sh4_translate_init();
41.31 sh4_module.run_time_slice = sh4_xlat_run_slice;
41.32 } else {
41.33 sh4_module.run_time_slice = sh4_run_slice;
41.34 @@ -106,7 +107,6 @@
41.35 sh4r.vbr = 0x00000000;
41.36 sh4r.fpscr = 0x00040001;
41.37 sh4r.sr = 0x700000F0;
41.38 - sh4r.fr_bank = &sh4r.fr[0][0];
41.39
41.40 /* Mem reset will do this, but if we want to reset _just_ the SH4... */
41.41 MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
41.42 @@ -151,7 +151,6 @@
41.43 xlat_flush_cache();
41.44 }
41.45 fread( &sh4r, sizeof(sh4r), 1, f );
41.46 - sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0]; // Fixup internal FR pointer
41.47 MMU_load_state( f );
41.48 INTC_load_state( f );
41.49 TMU_load_state( f );
41.50 @@ -218,6 +217,16 @@
41.51 memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
41.52 }
41.53
41.54 +void sh4_switch_fr_banks()
41.55 +{
41.56 + int i;
41.57 + for( i=0; i<16; i++ ) {
41.58 + float tmp = sh4r.fr[0][i];
41.59 + sh4r.fr[0][i] = sh4r.fr[1][i];
41.60 + sh4r.fr[1][i] = tmp;
41.61 + }
41.62 +}
41.63 +
41.64 void sh4_write_sr( uint32_t newval )
41.65 {
41.66 int oldbank = (sh4r.sr&SR_MDRB) == SR_MDRB;
41.67 @@ -232,6 +241,14 @@
41.68 intc_mask_changed();
41.69 }
41.70
41.71 +void sh4_write_fpscr( uint32_t newval )
41.72 +{
41.73 + if( (sh4r.fpscr ^ newval) & FPSCR_FR ) {
41.74 + sh4_switch_fr_banks();
41.75 + }
41.76 + sh4r.fpscr = newval;
41.77 +}
41.78 +
41.79 uint32_t sh4_read_sr( void )
41.80 {
41.81 /* synchronize sh4r.sr with the various bitflags */
41.82 @@ -286,6 +303,7 @@
41.83 sh4r.new_pc = sh4r.pc + 2;
41.84 sh4_write_sr( (sh4r.sr|SR_MD|SR_BL|SR_RB|SR_IMASK)
41.85 &(~SR_FD) );
41.86 + return TRUE;
41.87 }
41.88
41.89 gboolean sh4_raise_trap( int trap )
41.90 @@ -408,17 +426,17 @@
41.91 * Compute the matrix tranform of fv given the matrix xf.
41.92 * Both fv and xf are word-swapped as per the sh4r.fr banks
41.93 */
41.94 -void sh4_ftrv( float *target, float *xf )
41.95 +void sh4_ftrv( float *target )
41.96 {
41.97 float fv[4] = { target[1], target[0], target[3], target[2] };
41.98 - target[1] = xf[1] * fv[0] + xf[5]*fv[1] +
41.99 - xf[9]*fv[2] + xf[13]*fv[3];
41.100 - target[0] = xf[0] * fv[0] + xf[4]*fv[1] +
41.101 - xf[8]*fv[2] + xf[12]*fv[3];
41.102 - target[3] = xf[3] * fv[0] + xf[7]*fv[1] +
41.103 - xf[11]*fv[2] + xf[15]*fv[3];
41.104 - target[2] = xf[2] * fv[0] + xf[6]*fv[1] +
41.105 - xf[10]*fv[2] + xf[14]*fv[3];
41.106 + target[1] = sh4r.fr[1][1] * fv[0] + sh4r.fr[1][5]*fv[1] +
41.107 + sh4r.fr[1][9]*fv[2] + sh4r.fr[1][13]*fv[3];
41.108 + target[0] = sh4r.fr[1][0] * fv[0] + sh4r.fr[1][4]*fv[1] +
41.109 + sh4r.fr[1][8]*fv[2] + sh4r.fr[1][12]*fv[3];
41.110 + target[3] = sh4r.fr[1][3] * fv[0] + sh4r.fr[1][7]*fv[1] +
41.111 + sh4r.fr[1][11]*fv[2] + sh4r.fr[1][15]*fv[3];
41.112 + target[2] = sh4r.fr[1][2] * fv[0] + sh4r.fr[1][6]*fv[1] +
41.113 + sh4r.fr[1][10]*fv[2] + sh4r.fr[1][14]*fv[3];
41.114 }
41.115
41.116 gboolean sh4_has_page( sh4vma_t vma )
42.1 --- a/src/sh4/sh4.h Sun Apr 20 05:30:07 2008 +0000
42.2 +++ b/src/sh4/sh4.h Mon May 12 10:00:13 2008 +0000
42.3 @@ -66,8 +66,11 @@
42.4 uint32_t r[16];
42.5 uint32_t sr, pr, pc, fpscr;
42.6 uint32_t t, m, q, s; /* really boolean - 0 or 1 */
42.7 - int32_t fpul;
42.8 - float *fr_bank;
42.9 + union {
42.10 + int32_t i;
42.11 + float f;
42.12 + } fpul;
42.13 + float *pad;
42.14 float fr[2][16];
42.15 uint64_t mac;
42.16 uint32_t gbr, ssr, spc, sgr, dbr, vbr;
43.1 --- a/src/sh4/sh4core.c Sun Apr 20 05:30:07 2008 +0000
43.2 +++ b/src/sh4/sh4core.c Mon May 12 10:00:13 2008 +0000
43.3 @@ -482,7 +482,7 @@
43.4 { /* STS FPUL, Rn */
43.5 uint32_t Rn = ((ir>>8)&0xF);
43.6 CHECKFPUEN();
43.7 - sh4r.r[Rn] = sh4r.fpul;
43.8 + sh4r.r[Rn] = FPULi;
43.9 }
43.10 break;
43.11 case 0x6:
43.12 @@ -916,7 +916,7 @@
43.13 uint32_t Rn = ((ir>>8)&0xF);
43.14 CHECKFPUEN();
43.15 CHECKWALIGN32( sh4r.r[Rn] );
43.16 - MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.fpul );
43.17 + MEM_WRITE_LONG( sh4r.r[Rn]-4, FPULi );
43.18 sh4r.r[Rn] -= 4;
43.19 }
43.20 break;
43.21 @@ -1105,7 +1105,7 @@
43.22 uint32_t Rm = ((ir>>8)&0xF);
43.23 CHECKFPUEN();
43.24 CHECKRALIGN32( sh4r.r[Rm] );
43.25 - MEM_READ_LONG(sh4r.r[Rm], sh4r.fpul);
43.26 + MEM_READ_LONG(sh4r.r[Rm], FPULi);
43.27 sh4r.r[Rm] +=4;
43.28 }
43.29 break;
43.30 @@ -1114,9 +1114,9 @@
43.31 uint32_t Rm = ((ir>>8)&0xF);
43.32 CHECKFPUEN();
43.33 CHECKRALIGN32( sh4r.r[Rm] );
43.34 - MEM_READ_LONG(sh4r.r[Rm], sh4r.fpscr);
43.35 + MEM_READ_LONG(sh4r.r[Rm], tmp);
43.36 sh4r.r[Rm] +=4;
43.37 - sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
43.38 + sh4_write_fpscr( tmp );
43.39 }
43.40 break;
43.41 case 0xF:
43.42 @@ -1282,15 +1282,14 @@
43.43 { /* LDS Rm, FPUL */
43.44 uint32_t Rm = ((ir>>8)&0xF);
43.45 CHECKFPUEN();
43.46 - sh4r.fpul = sh4r.r[Rm];
43.47 + FPULi = sh4r.r[Rm];
43.48 }
43.49 break;
43.50 case 0x6:
43.51 { /* LDS Rm, FPSCR */
43.52 uint32_t Rm = ((ir>>8)&0xF);
43.53 CHECKFPUEN();
43.54 - sh4r.fpscr = sh4r.r[Rm];
43.55 - sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
43.56 + sh4_write_fpscr( sh4r.r[Rm] );
43.57 }
43.58 break;
43.59 case 0xF:
43.60 @@ -2111,20 +2110,7 @@
43.61 uint32_t FVn = ((ir>>10)&0x3);
43.62 CHECKFPUEN();
43.63 if( !IS_FPU_DOUBLEPREC() ) {
43.64 - sh4_ftrv(&(DRF(FVn<<1)), &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0]);
43.65 - /*
43.66 - tmp = FVn<<2;
43.67 - float *xf = &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0];
43.68 - float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
43.69 - FR(tmp) = xf[1] * fv[0] + xf[5]*fv[1] +
43.70 - xf[9]*fv[2] + xf[13]*fv[3];
43.71 - FR(tmp+1) = xf[0] * fv[0] + xf[4]*fv[1] +
43.72 - xf[8]*fv[2] + xf[12]*fv[3];
43.73 - FR(tmp+2) = xf[3] * fv[0] + xf[7]*fv[1] +
43.74 - xf[11]*fv[2] + xf[15]*fv[3];
43.75 - FR(tmp+3) = xf[2] * fv[0] + xf[6]*fv[1] +
43.76 - xf[10]*fv[2] + xf[14]*fv[3];
43.77 - */
43.78 + sh4_ftrv(&(DRF(FVn<<1)) );
43.79 }
43.80 }
43.81 break;
43.82 @@ -2139,7 +2125,7 @@
43.83 { /* FRCHG */
43.84 CHECKFPUEN();
43.85 sh4r.fpscr ^= FPSCR_FR;
43.86 - sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
43.87 + sh4_switch_fr_banks();
43.88 }
43.89 break;
43.90 case 0x3:
44.1 --- a/src/sh4/sh4core.h Sun Apr 20 05:30:07 2008 +0000
44.2 +++ b/src/sh4/sh4core.h Mon May 12 10:00:13 2008 +0000
44.3 @@ -100,6 +100,7 @@
44.4 void SCIF_save_state( FILE *f );
44.5 int SCIF_load_state( FILE *f );
44.6 void SCIF_update_line_speed(void);
44.7 +void TMU_init( void );
44.8 void TMU_reset( void );
44.9 void TMU_run_slice( uint32_t );
44.10 void TMU_save_state( FILE * );
44.11 @@ -109,9 +110,11 @@
44.12 /* SH4 instruction support methods */
44.13 void sh4_sleep( void );
44.14 void sh4_fsca( uint32_t angle, float *fr );
44.15 -void sh4_ftrv( float *fv, float *xmtrx );
44.16 +void sh4_ftrv( float *fv );
44.17 uint32_t sh4_read_sr(void);
44.18 void sh4_write_sr(uint32_t val);
44.19 +void sh4_write_fpscr(uint32_t val);
44.20 +void sh4_switch_fr_banks(void);
44.21 void signsat48(void);
44.22 gboolean sh4_has_page( sh4vma_t vma );
44.23
44.24 @@ -216,14 +219,14 @@
44.25 #define IS_FPU_DOUBLESIZE() (sh4r.fpscr&FPSCR_SZ)
44.26 #define IS_FPU_ENABLED() ((sh4r.sr&SR_FD)==0)
44.27
44.28 -#define FR(x) sh4r.fr_bank[(x)^1]
44.29 -#define DRF(x) ((double *)sh4r.fr_bank)[x]
44.30 -#define XF(x) sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][(x)^1]
44.31 -#define XDR(x) ((double *)(sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21]))[x]
44.32 -#define DRb(x,b) ((double *)(sh4r.fr[((b ? (~sh4r.fpscr) : sh4r.fpscr)&FPSCR_FR)>>21]))[x]
44.33 -#define DR(x) DRb((x>>1), (x&1))
44.34 -#define FPULf *((float *)&sh4r.fpul)
44.35 -#define FPULi (sh4r.fpul)
44.36 +#define FR(x) sh4r.fr[0][(x)^1]
44.37 +#define DRF(x) *((double *)&sh4r.fr[0][(x)<<1])
44.38 +#define XF(x) sh4r.fr[1][(x)^1]
44.39 +#define XDR(x) *((double *)&sh4r.fr[1][(x)<<1])
44.40 +#define DRb(x,b) *((double *)&sh4r.fr[b][(x)<<1])
44.41 +#define DR(x) *((double *)&sh4r.fr[x&1][x&0x0E])
44.42 +#define FPULf (sh4r.fpul.f)
44.43 +#define FPULi (sh4r.fpul.i)
44.44
44.45 #define SH4_WRITE_STORE_QUEUE(addr,val) sh4r.store_queue[(addr>>2)&0xF] = val;
44.46
45.1 --- a/src/sh4/sh4core.in Sun Apr 20 05:30:07 2008 +0000
45.2 +++ b/src/sh4/sh4core.in Mon May 12 10:00:13 2008 +0000
45.3 @@ -853,23 +853,23 @@
45.4 :}
45.5 STS FPUL, Rn {:
45.6 CHECKFPUEN();
45.7 - sh4r.r[Rn] = sh4r.fpul;
45.8 + sh4r.r[Rn] = FPULi;
45.9 :}
45.10 STS.L FPUL, @-Rn {:
45.11 CHECKFPUEN();
45.12 CHECKWALIGN32( sh4r.r[Rn] );
45.13 - MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.fpul );
45.14 + MEM_WRITE_LONG( sh4r.r[Rn]-4, FPULi );
45.15 sh4r.r[Rn] -= 4;
45.16 :}
45.17 LDS.L @Rm+, FPUL {:
45.18 CHECKFPUEN();
45.19 CHECKRALIGN32( sh4r.r[Rm] );
45.20 - MEM_READ_LONG(sh4r.r[Rm], sh4r.fpul);
45.21 + MEM_READ_LONG(sh4r.r[Rm], FPULi);
45.22 sh4r.r[Rm] +=4;
45.23 :}
45.24 LDS Rm, FPUL {:
45.25 CHECKFPUEN();
45.26 - sh4r.fpul = sh4r.r[Rm];
45.27 + FPULi = sh4r.r[Rm];
45.28 :}
45.29 STS FPSCR, Rn {:
45.30 CHECKFPUEN();
45.31 @@ -884,14 +884,13 @@
45.32 LDS.L @Rm+, FPSCR {:
45.33 CHECKFPUEN();
45.34 CHECKRALIGN32( sh4r.r[Rm] );
45.35 - MEM_READ_LONG(sh4r.r[Rm], sh4r.fpscr);
45.36 + MEM_READ_LONG(sh4r.r[Rm], tmp);
45.37 sh4r.r[Rm] +=4;
45.38 - sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
45.39 + sh4_write_fpscr( tmp );
45.40 :}
45.41 LDS Rm, FPSCR {:
45.42 CHECKFPUEN();
45.43 - sh4r.fpscr = sh4r.r[Rm];
45.44 - sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
45.45 + sh4_write_fpscr( sh4r.r[Rm] );
45.46 :}
45.47 STC DBR, Rn {: CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr; :}
45.48 STC.L DBR, @-Rn {:
45.49 @@ -1106,7 +1105,7 @@
45.50 FRCHG {:
45.51 CHECKFPUEN();
45.52 sh4r.fpscr ^= FPSCR_FR;
45.53 - sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
45.54 + sh4_switch_fr_banks();
45.55 :}
45.56 FSCHG {: CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ; :}
45.57 FCNVSD FPUL, FRn {:
45.58 @@ -1153,20 +1152,7 @@
45.59 FTRV XMTRX, FVn {:
45.60 CHECKFPUEN();
45.61 if( !IS_FPU_DOUBLEPREC() ) {
45.62 - sh4_ftrv(&(DRF(FVn<<1)), &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0]);
45.63 - /*
45.64 - tmp = FVn<<2;
45.65 - float *xf = &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0];
45.66 - float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
45.67 - FR(tmp) = xf[1] * fv[0] + xf[5]*fv[1] +
45.68 - xf[9]*fv[2] + xf[13]*fv[3];
45.69 - FR(tmp+1) = xf[0] * fv[0] + xf[4]*fv[1] +
45.70 - xf[8]*fv[2] + xf[12]*fv[3];
45.71 - FR(tmp+2) = xf[3] * fv[0] + xf[7]*fv[1] +
45.72 - xf[11]*fv[2] + xf[15]*fv[3];
45.73 - FR(tmp+3) = xf[2] * fv[0] + xf[6]*fv[1] +
45.74 - xf[10]*fv[2] + xf[14]*fv[3];
45.75 - */
45.76 + sh4_ftrv(&(DRF(FVn<<1)) );
45.77 }
45.78 :}
45.79 UNDEF {:
46.1 --- a/src/sh4/sh4dasm.c Sun Apr 20 05:30:07 2008 +0000
46.2 +++ b/src/sh4/sh4dasm.c Mon May 12 10:00:13 2008 +0000
46.3 @@ -38,7 +38,7 @@
46.4 {"VBR",REG_INT, &sh4r.vbr},
46.5 {"PC", REG_INT, &sh4r.pc}, {"PR", REG_INT, &sh4r.pr},
46.6 {"MACL",REG_INT, &sh4r.mac},{"MACH",REG_INT, ((uint32_t *)&sh4r.mac)+1},
46.7 - {"FPUL", REG_INT, &sh4r.fpul}, {"FPSCR", REG_INT, &sh4r.fpscr},
46.8 + {"FPUL", REG_INT, &sh4r.fpul.i}, {"FPSCR", REG_INT, &sh4r.fpscr},
46.9 {NULL, 0, NULL} };
46.10
46.11
47.1 --- a/src/sh4/sh4dasm.in Sun Apr 20 05:30:07 2008 +0000
47.2 +++ b/src/sh4/sh4dasm.in Mon May 12 10:00:13 2008 +0000
47.3 @@ -38,7 +38,7 @@
47.4 {"VBR",REG_INT, &sh4r.vbr},
47.5 {"PC", REG_INT, &sh4r.pc}, {"PR", REG_INT, &sh4r.pr},
47.6 {"MACL",REG_INT, &sh4r.mac},{"MACH",REG_INT, ((uint32_t *)&sh4r.mac)+1},
47.7 - {"FPUL", REG_INT, &sh4r.fpul}, {"FPSCR", REG_INT, &sh4r.fpscr},
47.8 + {"FPUL", REG_INT, &sh4r.fpul.i}, {"FPSCR", REG_INT, &sh4r.fpscr},
47.9 {NULL, 0, NULL} };
47.10
47.11
48.1 --- a/src/sh4/sh4trans.c Sun Apr 20 05:30:07 2008 +0000
48.2 +++ b/src/sh4/sh4trans.c Mon May 12 10:00:13 2008 +0000
48.3 @@ -21,6 +21,7 @@
48.4 #include "eventq.h"
48.5 #include "syscall.h"
48.6 #include "clock.h"
48.7 +#include "dreamcast.h"
48.8 #include "sh4/sh4core.h"
48.9 #include "sh4/sh4trans.h"
48.10 #include "sh4/xltcache.h"
48.11 @@ -90,7 +91,6 @@
48.12 code = sh4_translate_basic_block( sh4r.pc );
48.13 }
48.14 }
48.15 - uint32_t oldpc = sh4r.pc;
48.16 code = code();
48.17 }
48.18
49.1 --- a/src/sh4/sh4trans.h Sun Apr 20 05:30:07 2008 +0000
49.2 +++ b/src/sh4/sh4trans.h Mon May 12 10:00:13 2008 +0000
49.3 @@ -71,11 +71,22 @@
49.4 gboolean sh4_xlat_is_running();
49.5
49.6 /**
49.7 + * Initialize the translation engine (if required). Note xlat cache
49.8 + * must already be initialized.
49.9 + */
49.10 +void sh4_xlat_init();
49.11 +
49.12 +/**
49.13 * Translate the specified block of code starting from the specified start
49.14 * address until the first branch/jump instruction.
49.15 */
49.16 void *sh4_translate_basic_block( sh4addr_t start );
49.17
49.18 +/**
49.19 + * Add a recovery record for the current code generation position, with the
49.20 + * specified instruction count
49.21 + */
49.22 +void sh4_translate_add_recovery( uint32_t icount );
49.23
49.24 extern uint8_t *xlat_output;
49.25 extern struct xlat_recovery_record xlat_recovery[MAX_RECOVERY_SIZE];
49.26 @@ -90,10 +101,12 @@
49.27 #define TARGET_X86 1
49.28 #define TARGET_X86_64 2
49.29
49.30 +void sh4_translate_init( void );
49.31 void sh4_translate_begin_block( sh4addr_t pc );
49.32 uint32_t sh4_translate_instruction( sh4addr_t pc );
49.33 void sh4_translate_end_block( sh4addr_t pc );
49.34 uint32_t sh4_translate_end_block_size();
49.35 +void sh4_translate_emit_breakpoint( sh4vma_t pc );
49.36
49.37 typedef void (*unwind_thunk_t)(void);
49.38
49.39 @@ -121,6 +134,13 @@
49.40 void sh4_translate_exit( int exit_code );
49.41
49.42 /**
49.43 + * From within the translator, exit the current block at the end of the
49.44 + * current instruction, flush the translation cache (completely) and return
49.45 + * control to sh4_xlat_run_slice.
49.46 + */
49.47 +void sh4_translate_flush_cache( void );
49.48 +
49.49 +/**
49.50 * Support function called from the translator when a breakpoint is hit.
49.51 * Either returns immediately (to skip the breakpoint), or aborts the current
49.52 * cycle and never returns.
50.1 --- a/src/sh4/sh4x86.c Sun Apr 20 05:30:07 2008 +0000
50.2 +++ b/src/sh4/sh4x86.c Mon May 12 10:00:13 2008 +0000
50.3 @@ -80,15 +80,14 @@
50.4 #define TSTATE_AE 3
50.5
50.6 /** Branch if T is set (either in the current cflags, or in sh4r.t) */
50.7 -#define JT_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
50.8 +#define JT_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
50.9 CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
50.10 - OP(0x70+sh4_x86.tstate); OP(rel8); \
50.11 - MARK_JMP(rel8,label)
50.12 + OP(0x70+sh4_x86.tstate); MARK_JMP8(label); OP(-1)
50.13 +
50.14 /** Branch if T is clear (either in the current cflags or in sh4r.t) */
50.15 -#define JF_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
50.16 +#define JF_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
50.17 CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
50.18 - OP(0x70+ (sh4_x86.tstate^1)); OP(rel8); \
50.19 - MARK_JMP(rel8, label)
50.20 + OP(0x70+ (sh4_x86.tstate^1)); MARK_JMP8(label); OP(-1)
50.21
50.22 static struct sh4_x86_state sh4_x86;
50.23
50.24 @@ -97,7 +96,7 @@
50.25 static uint32_t save_fcw; /* save value for fpu control word */
50.26 static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
50.27
50.28 -void sh4_x86_init()
50.29 +void sh4_translate_init(void)
50.30 {
50.31 sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
50.32 sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
50.33 @@ -169,7 +168,6 @@
50.34 OP64(value);
50.35 }
50.36
50.37 -
50.38 /**
50.39 * Emit an instruction to store an SH4 reg (RN)
50.40 */
50.41 @@ -180,97 +178,42 @@
50.42 OP(REG_OFFSET(r[sh4reg]));
50.43 }
50.44
50.45 -#define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
50.46 -
50.47 /**
50.48 * Load an FR register (single-precision floating point) into an integer x86
50.49 * register (eg for register-to-register moves)
50.50 */
50.51 -void static inline load_fr( int bankreg, int x86reg, int frm )
50.52 -{
50.53 - OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
50.54 -}
50.55 +#define load_fr(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[0][(frm)^1]) )
50.56 +#define load_xf(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[1][(frm)^1]) )
50.57
50.58 /**
50.59 - * Store an FR register (single-precision floating point) into an integer x86
50.60 + * Load the low half of a DR register (DR or XD) into an integer x86 register
50.61 + */
50.62 +#define load_dr0(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
50.63 +#define load_dr1(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
50.64 +
50.65 +/**
50.66 + * Store an FR register (single-precision floating point) from an integer x86+
50.67 * register (eg for register-to-register moves)
50.68 */
50.69 -void static inline store_fr( int bankreg, int x86reg, int frn )
50.70 -{
50.71 - OP(0x89); OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
50.72 -}
50.73 +#define store_fr(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[0][(frm)^1]) )
50.74 +#define store_xf(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[1][(frm)^1]) )
50.75
50.76 +#define store_dr0(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
50.77 +#define store_dr1(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
50.78
50.79 -/**
50.80 - * Load a pointer to the back fp back into the specified x86 register. The
50.81 - * bankreg must have been previously loaded with FPSCR.
50.82 - * NB: 12 bytes
50.83 - */
50.84 -static inline void load_xf_bank( int bankreg )
50.85 -{
50.86 - NOT_r32( bankreg );
50.87 - SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
50.88 - AND_imm8s_r32( 0x40, bankreg ); // Complete extraction
50.89 - OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
50.90 -}
50.91
50.92 -/**
50.93 - * Update the fr_bank pointer based on the current fpscr value.
50.94 - */
50.95 -static inline void update_fr_bank( int fpscrreg )
50.96 -{
50.97 - SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
50.98 - AND_imm8s_r32( 0x40, fpscrreg ); // Complete extraction
50.99 - OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
50.100 - store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
50.101 -}
50.102 -/**
50.103 - * Push FPUL (as a 32-bit float) onto the FPU stack
50.104 - */
50.105 -static inline void push_fpul( )
50.106 -{
50.107 - OP(0xD9); OP(0x45); OP(R_FPUL);
50.108 -}
50.109 +#define push_fpul() FLDF_sh4r(R_FPUL)
50.110 +#define pop_fpul() FSTPF_sh4r(R_FPUL)
50.111 +#define push_fr(frm) FLDF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
50.112 +#define pop_fr(frm) FSTPF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
50.113 +#define push_xf(frm) FLDF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
50.114 +#define pop_xf(frm) FSTPF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
50.115 +#define push_dr(frm) FLDD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
50.116 +#define pop_dr(frm) FSTPD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
50.117 +#define push_xdr(frm) FLDD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
50.118 +#define pop_xdr(frm) FSTPD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
50.119
50.120 -/**
50.121 - * Pop FPUL (as a 32-bit float) from the FPU stack
50.122 - */
50.123 -static inline void pop_fpul( )
50.124 -{
50.125 - OP(0xD9); OP(0x5D); OP(R_FPUL);
50.126 -}
50.127
50.128 -/**
50.129 - * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
50.130 - * with the location of the current fp bank.
50.131 - */
50.132 -static inline void push_fr( int bankreg, int frm )
50.133 -{
50.134 - OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2); // FLD.S [bankreg + frm^1*4]
50.135 -}
50.136 -
50.137 -/**
50.138 - * Pop a 32-bit float from the FPU stack and store it back into the fp bank,
50.139 - * with bankreg previously loaded with the location of the current fp bank.
50.140 - */
50.141 -static inline void pop_fr( int bankreg, int frm )
50.142 -{
50.143 - OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
50.144 -}
50.145 -
50.146 -/**
50.147 - * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
50.148 - * with the location of the current fp bank.
50.149 - */
50.150 -static inline void push_dr( int bankreg, int frm )
50.151 -{
50.152 - OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
50.153 -}
50.154 -
50.155 -static inline void pop_dr( int bankreg, int frm )
50.156 -{
50.157 - OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
50.158 -}
50.159
50.160 /* Exception checks - Note that all exception checks will clobber EAX */
50.161
50.162 @@ -563,7 +506,7 @@
50.163 MOV_r32_r32( R_EAX, R_ECX );
50.164 AND_imm32_r32( 0xFC000000, R_EAX );
50.165 CMP_imm32_r32( 0xE0000000, R_EAX );
50.166 - JNE_rel8(8+CALL_FUNC1_SIZE, end);
50.167 + JNE_rel8(end);
50.168 call_func1( sh4_flush_store_queue, R_ECX );
50.169 TEST_r32_r32( R_EAX, R_EAX );
50.170 JE_exc(-1);
50.171 @@ -926,7 +869,7 @@
50.172
50.173 load_spreg( R_ECX, R_S );
50.174 TEST_r32_r32(R_ECX, R_ECX);
50.175 - JE_rel8( CALL_FUNC0_SIZE, nosat );
50.176 + JE_rel8( nosat );
50.177 call_func0( signsat48 );
50.178 JMP_TARGET( nosat );
50.179 sh4_x86.tstate = TSTATE_NONE;
50.180 @@ -1082,13 +1025,13 @@
50.181 load_reg( R_ECX, Rn );
50.182 XOR_r32_r32( R_ECX, R_EAX );
50.183 TEST_r8_r8( R_AL, R_AL );
50.184 - JE_rel8(13, target1);
50.185 - TEST_r8_r8( R_AH, R_AH ); // 2
50.186 - JE_rel8(9, target2);
50.187 - SHR_imm8_r32( 16, R_EAX ); // 3
50.188 - TEST_r8_r8( R_AL, R_AL ); // 2
50.189 - JE_rel8(2, target3);
50.190 - TEST_r8_r8( R_AH, R_AH ); // 2
50.191 + JE_rel8(target1);
50.192 + TEST_r8_r8( R_AH, R_AH );
50.193 + JE_rel8(target2);
50.194 + SHR_imm8_r32( 16, R_EAX );
50.195 + TEST_r8_r8( R_AL, R_AL );
50.196 + JE_rel8(target3);
50.197 + TEST_r8_r8( R_AH, R_AH );
50.198 JMP_TARGET(target1);
50.199 JMP_TARGET(target2);
50.200 JMP_TARGET(target3);
50.201 @@ -1176,9 +1119,9 @@
50.202 RCL1_r32( R_EAX );
50.203 SETC_r8( R_DL ); // Q'
50.204 CMP_sh4r_r32( R_Q, R_ECX );
50.205 - JE_rel8(5, mqequal);
50.206 + JE_rel8(mqequal);
50.207 ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
50.208 - JMP_rel8(3, end);
50.209 + JMP_rel8(end);
50.210 JMP_TARGET(mqequal);
50.211 SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
50.212 JMP_TARGET(end);
50.213 @@ -1725,8 +1668,7 @@
50.214 MMU_TRANSLATE_READ( R_EAX );
50.215 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
50.216 MEM_READ_LONG( R_EAX, R_EAX );
50.217 - store_spreg( R_EAX, R_FPSCR );
50.218 - update_fr_bank( R_EAX );
50.219 + call_func1( sh4_write_fpscr, R_EAX );
50.220 sh4_x86.tstate = TSTATE_NONE;
50.221 }
50.222 break;
50.223 @@ -1955,8 +1897,7 @@
50.224 uint32_t Rm = ((ir>>8)&0xF);
50.225 check_fpuen();
50.226 load_reg( R_EAX, Rm );
50.227 - store_spreg( R_EAX, R_FPSCR );
50.228 - update_fr_bank( R_EAX );
50.229 + call_func1( sh4_write_fpscr, R_EAX );
50.230 sh4_x86.tstate = TSTATE_NONE;
50.231 }
50.232 break;
50.233 @@ -2049,17 +1990,17 @@
50.234 load_reg( R_EAX, Rn );
50.235 load_reg( R_ECX, Rm );
50.236 CMP_imm32_r32( 0, R_ECX );
50.237 - JGE_rel8(16, doshl);
50.238 + JGE_rel8(doshl);
50.239
50.240 NEG_r32( R_ECX ); // 2
50.241 AND_imm8_r8( 0x1F, R_CL ); // 3
50.242 - JE_rel8( 4, emptysar); // 2
50.243 + JE_rel8(emptysar); // 2
50.244 SAR_r32_CL( R_EAX ); // 2
50.245 - JMP_rel8(10, end); // 2
50.246 + JMP_rel8(end); // 2
50.247
50.248 JMP_TARGET(emptysar);
50.249 SAR_imm8_r32(31, R_EAX ); // 3
50.250 - JMP_rel8(5, end2);
50.251 + JMP_rel8(end2);
50.252
50.253 JMP_TARGET(doshl);
50.254 AND_imm8_r8( 0x1F, R_CL ); // 3
50.255 @@ -2076,17 +2017,17 @@
50.256 load_reg( R_EAX, Rn );
50.257 load_reg( R_ECX, Rm );
50.258 CMP_imm32_r32( 0, R_ECX );
50.259 - JGE_rel8(15, doshl);
50.260 + JGE_rel8(doshl);
50.261
50.262 NEG_r32( R_ECX ); // 2
50.263 AND_imm8_r8( 0x1F, R_CL ); // 3
50.264 - JE_rel8( 4, emptyshr );
50.265 + JE_rel8(emptyshr );
50.266 SHR_r32_CL( R_EAX ); // 2
50.267 - JMP_rel8(9, end); // 2
50.268 + JMP_rel8(end); // 2
50.269
50.270 JMP_TARGET(emptyshr);
50.271 XOR_r32_r32( R_EAX, R_EAX );
50.272 - JMP_rel8(5, end2);
50.273 + JMP_rel8(end2);
50.274
50.275 JMP_TARGET(doshl);
50.276 AND_imm8_r8( 0x1F, R_CL ); // 3
50.277 @@ -2201,21 +2142,21 @@
50.278
50.279 load_spreg( R_ECX, R_S );
50.280 TEST_r32_r32( R_ECX, R_ECX );
50.281 - JE_rel8( 47, nosat );
50.282 + JE_rel8( nosat );
50.283
50.284 ADD_r32_sh4r( R_EAX, R_MACL ); // 6
50.285 - JNO_rel8( 51, end ); // 2
50.286 + JNO_rel8( end ); // 2
50.287 load_imm32( R_EDX, 1 ); // 5
50.288 store_spreg( R_EDX, R_MACH ); // 6
50.289 - JS_rel8( 13, positive ); // 2
50.290 + JS_rel8( positive ); // 2
50.291 load_imm32( R_EAX, 0x80000000 );// 5
50.292 store_spreg( R_EAX, R_MACL ); // 6
50.293 - JMP_rel8( 25, end2 ); // 2
50.294 + JMP_rel8(end2); // 2
50.295
50.296 JMP_TARGET(positive);
50.297 load_imm32( R_EAX, 0x7FFFFFFF );// 5
50.298 store_spreg( R_EAX, R_MACL ); // 6
50.299 - JMP_rel8( 12, end3); // 2
50.300 + JMP_rel8(end3); // 2
50.301
50.302 JMP_TARGET(nosat);
50.303 ADD_r32_sh4r( R_EAX, R_MACL ); // 6
50.304 @@ -2473,7 +2414,7 @@
50.305 SLOTILLEGAL();
50.306 } else {
50.307 sh4vma_t target = disp + pc + 4;
50.308 - JF_rel8( EXIT_BLOCK_REL_SIZE(target), nottaken );
50.309 + JF_rel8( nottaken );
50.310 exit_block_rel(target, pc+2 );
50.311 JMP_TARGET(nottaken);
50.312 return 2;
50.313 @@ -2487,7 +2428,7 @@
50.314 SLOTILLEGAL();
50.315 } else {
50.316 sh4vma_t target = disp + pc + 4;
50.317 - JT_rel8( EXIT_BLOCK_REL_SIZE(target), nottaken );
50.318 + JT_rel8( nottaken );
50.319 exit_block_rel(target, pc+2 );
50.320 JMP_TARGET(nottaken);
50.321 return 2;
50.322 @@ -2503,7 +2444,7 @@
50.323 sh4_x86.in_delay_slot = DELAY_PC;
50.324 if( UNTRANSLATABLE(pc+2) ) {
50.325 load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
50.326 - JF_rel8(6,nottaken);
50.327 + JF_rel8(nottaken);
50.328 ADD_imm32_r32( disp, R_EAX );
50.329 JMP_TARGET(nottaken);
50.330 ADD_sh4r_r32( R_PC, R_EAX );
50.331 @@ -2536,7 +2477,7 @@
50.332 sh4_x86.in_delay_slot = DELAY_PC;
50.333 if( UNTRANSLATABLE(pc+2) ) {
50.334 load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
50.335 - JT_rel8(6,nottaken);
50.336 + JT_rel8(nottaken);
50.337 ADD_imm32_r32( disp, R_EAX );
50.338 JMP_TARGET(nottaken);
50.339 ADD_sh4r_r32( R_PC, R_EAX );
50.340 @@ -2883,18 +2824,17 @@
50.341 check_fpuen();
50.342 load_spreg( R_ECX, R_FPSCR );
50.343 TEST_imm32_r32( FPSCR_PR, R_ECX );
50.344 - load_fr_bank( R_EDX );
50.345 - JNE_rel8(13,doubleprec);
50.346 - push_fr(R_EDX, FRm);
50.347 - push_fr(R_EDX, FRn);
50.348 + JNE_rel8(doubleprec);
50.349 + push_fr(FRm);
50.350 + push_fr(FRn);
50.351 FADDP_st(1);
50.352 - pop_fr(R_EDX, FRn);
50.353 - JMP_rel8(11,end);
50.354 + pop_fr(FRn);
50.355 + JMP_rel8(end);
50.356 JMP_TARGET(doubleprec);
50.357 - push_dr(R_EDX, FRm);
50.358 - push_dr(R_EDX, FRn);
50.359 + push_dr(FRm);
50.360 + push_dr(FRn);
50.361 FADDP_st(1);
50.362 - pop_dr(R_EDX, FRn);
50.363 + pop_dr(FRn);
50.364 JMP_TARGET(end);
50.365 sh4_x86.tstate = TSTATE_NONE;
50.366 }
50.367 @@ -2905,18 +2845,17 @@
50.368 check_fpuen();
50.369 load_spreg( R_ECX, R_FPSCR );
50.370 TEST_imm32_r32( FPSCR_PR, R_ECX );
50.371 - load_fr_bank( R_EDX );
50.372 - JNE_rel8(13, doubleprec);
50.373 - push_fr(R_EDX, FRn);
50.374 - push_fr(R_EDX, FRm);
50.375 + JNE_rel8(doubleprec);
50.376 + push_fr(FRn);
50.377 + push_fr(FRm);
50.378 FSUBP_st(1);
50.379 - pop_fr(R_EDX, FRn);
50.380 - JMP_rel8(11, end);
50.381 + pop_fr(FRn);
50.382 + JMP_rel8(end);
50.383 JMP_TARGET(doubleprec);
50.384 - push_dr(R_EDX, FRn);
50.385 - push_dr(R_EDX, FRm);
50.386 + push_dr(FRn);
50.387 + push_dr(FRm);
50.388 FSUBP_st(1);
50.389 - pop_dr(R_EDX, FRn);
50.390 + pop_dr(FRn);
50.391 JMP_TARGET(end);
50.392 sh4_x86.tstate = TSTATE_NONE;
50.393 }
50.394 @@ -2927,18 +2866,17 @@
50.395 check_fpuen();
50.396 load_spreg( R_ECX, R_FPSCR );
50.397 TEST_imm32_r32( FPSCR_PR, R_ECX );
50.398 - load_fr_bank( R_EDX );
50.399 - JNE_rel8(13, doubleprec);
50.400 - push_fr(R_EDX, FRm);
50.401 - push_fr(R_EDX, FRn);
50.402 + JNE_rel8(doubleprec);
50.403 + push_fr(FRm);
50.404 + push_fr(FRn);
50.405 FMULP_st(1);
50.406 - pop_fr(R_EDX, FRn);
50.407 - JMP_rel8(11, end);
50.408 + pop_fr(FRn);
50.409 + JMP_rel8(end);
50.410 JMP_TARGET(doubleprec);
50.411 - push_dr(R_EDX, FRm);
50.412 - push_dr(R_EDX, FRn);
50.413 + push_dr(FRm);
50.414 + push_dr(FRn);
50.415 FMULP_st(1);
50.416 - pop_dr(R_EDX, FRn);
50.417 + pop_dr(FRn);
50.418 JMP_TARGET(end);
50.419 sh4_x86.tstate = TSTATE_NONE;
50.420 }
50.421 @@ -2949,18 +2887,17 @@
50.422 check_fpuen();
50.423 load_spreg( R_ECX, R_FPSCR );
50.424 TEST_imm32_r32( FPSCR_PR, R_ECX );
50.425 - load_fr_bank( R_EDX );
50.426 - JNE_rel8(13, doubleprec);
50.427 - push_fr(R_EDX, FRn);
50.428 - push_fr(R_EDX, FRm);
50.429 + JNE_rel8(doubleprec);
50.430 + push_fr(FRn);
50.431 + push_fr(FRm);
50.432 FDIVP_st(1);
50.433 - pop_fr(R_EDX, FRn);
50.434 - JMP_rel8(11, end);
50.435 + pop_fr(FRn);
50.436 + JMP_rel8(end);
50.437 JMP_TARGET(doubleprec);
50.438 - push_dr(R_EDX, FRn);
50.439 - push_dr(R_EDX, FRm);
50.440 + push_dr(FRn);
50.441 + push_dr(FRm);
50.442 FDIVP_st(1);
50.443 - pop_dr(R_EDX, FRn);
50.444 + pop_dr(FRn);
50.445 JMP_TARGET(end);
50.446 sh4_x86.tstate = TSTATE_NONE;
50.447 }
50.448 @@ -2971,14 +2908,13 @@
50.449 check_fpuen();
50.450 load_spreg( R_ECX, R_FPSCR );
50.451 TEST_imm32_r32( FPSCR_PR, R_ECX );
50.452 - load_fr_bank( R_EDX );
50.453 - JNE_rel8(8, doubleprec);
50.454 - push_fr(R_EDX, FRm);
50.455 - push_fr(R_EDX, FRn);
50.456 - JMP_rel8(6, end);
50.457 + JNE_rel8(doubleprec);
50.458 + push_fr(FRm);
50.459 + push_fr(FRn);
50.460 + JMP_rel8(end);
50.461 JMP_TARGET(doubleprec);
50.462 - push_dr(R_EDX, FRm);
50.463 - push_dr(R_EDX, FRn);
50.464 + push_dr(FRm);
50.465 + push_dr(FRn);
50.466 JMP_TARGET(end);
50.467 FCOMIP_st(1);
50.468 SETE_t();
50.469 @@ -2992,14 +2928,13 @@
50.470 check_fpuen();
50.471 load_spreg( R_ECX, R_FPSCR );
50.472 TEST_imm32_r32( FPSCR_PR, R_ECX );
50.473 - load_fr_bank( R_EDX );
50.474 - JNE_rel8(8, doubleprec);
50.475 - push_fr(R_EDX, FRm);
50.476 - push_fr(R_EDX, FRn);
50.477 - JMP_rel8(6, end);
50.478 + JNE_rel8(doubleprec);
50.479 + push_fr(FRm);
50.480 + push_fr(FRn);
50.481 + JMP_rel8(end);
50.482 JMP_TARGET(doubleprec);
50.483 - push_dr(R_EDX, FRm);
50.484 - push_dr(R_EDX, FRn);
50.485 + push_dr(FRm);
50.486 + push_dr(FRn);
50.487 JMP_TARGET(end);
50.488 FCOMIP_st(1);
50.489 SETA_t();
50.490 @@ -3017,28 +2952,18 @@
50.491 MMU_TRANSLATE_READ( R_EAX );
50.492 load_spreg( R_EDX, R_FPSCR );
50.493 TEST_imm32_r32( FPSCR_SZ, R_EDX );
50.494 - JNE_rel8(8 + MEM_READ_SIZE, doublesize);
50.495 + JNE_rel8(doublesize);
50.496 +
50.497 MEM_READ_LONG( R_EAX, R_EAX );
50.498 - load_fr_bank( R_EDX );
50.499 - store_fr( R_EDX, R_EAX, FRn );
50.500 - if( FRn&1 ) {
50.501 - JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end);
50.502 - JMP_TARGET(doublesize);
50.503 - MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
50.504 - load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
50.505 - load_xf_bank( R_EDX );
50.506 - store_fr( R_EDX, R_ECX, FRn&0x0E );
50.507 - store_fr( R_EDX, R_EAX, FRn|0x01 );
50.508 - JMP_TARGET(end);
50.509 - } else {
50.510 - JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end);
50.511 - JMP_TARGET(doublesize);
50.512 - MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
50.513 - load_fr_bank( R_EDX );
50.514 - store_fr( R_EDX, R_ECX, FRn&0x0E );
50.515 - store_fr( R_EDX, R_EAX, FRn|0x01 );
50.516 - JMP_TARGET(end);
50.517 - }
50.518 + store_fr( R_EAX, FRn );
50.519 + JMP_rel8(end);
50.520 +
50.521 + JMP_TARGET(doublesize);
50.522 + MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
50.523 + store_dr0( R_ECX, FRn );
50.524 + store_dr1( R_EAX, FRn );
50.525 + JMP_TARGET(end);
50.526 +
50.527 sh4_x86.tstate = TSTATE_NONE;
50.528 }
50.529 break;
50.530 @@ -3052,27 +2977,18 @@
50.531 MMU_TRANSLATE_WRITE( R_EAX );
50.532 load_spreg( R_EDX, R_FPSCR );
50.533 TEST_imm32_r32( FPSCR_SZ, R_EDX );
50.534 - JNE_rel8(8 + MEM_WRITE_SIZE, doublesize);
50.535 - load_fr_bank( R_EDX );
50.536 - load_fr( R_EDX, R_ECX, FRm );
50.537 + JNE_rel8(doublesize);
50.538 +
50.539 + load_fr( R_ECX, FRm );
50.540 MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
50.541 - if( FRm&1 ) {
50.542 - JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end );
50.543 - JMP_TARGET(doublesize);
50.544 - load_xf_bank( R_EDX );
50.545 - load_fr( R_EDX, R_ECX, FRm&0x0E );
50.546 - load_fr( R_EDX, R_EDX, FRm|0x01 );
50.547 - MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
50.548 - JMP_TARGET(end);
50.549 - } else {
50.550 - JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end );
50.551 - JMP_TARGET(doublesize);
50.552 - load_fr_bank( R_EDX );
50.553 - load_fr( R_EDX, R_ECX, FRm&0x0E );
50.554 - load_fr( R_EDX, R_EDX, FRm|0x01 );
50.555 - MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
50.556 - JMP_TARGET(end);
50.557 - }
50.558 + JMP_rel8(end);
50.559 +
50.560 + JMP_TARGET(doublesize);
50.561 + load_dr0( R_ECX, FRm );
50.562 + load_dr1( R_EDX, FRm );
50.563 + MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
50.564 + JMP_TARGET(end);
50.565 +
50.566 sh4_x86.tstate = TSTATE_NONE;
50.567 }
50.568 break;
50.569 @@ -3085,28 +3001,17 @@
50.570 MMU_TRANSLATE_READ( R_EAX );
50.571 load_spreg( R_EDX, R_FPSCR );
50.572 TEST_imm32_r32( FPSCR_SZ, R_EDX );
50.573 - JNE_rel8(8 + MEM_READ_SIZE, doublesize);
50.574 + JNE_rel8(doublesize);
50.575 +
50.576 MEM_READ_LONG( R_EAX, R_EAX );
50.577 - load_fr_bank( R_EDX );
50.578 - store_fr( R_EDX, R_EAX, FRn );
50.579 - if( FRn&1 ) {
50.580 - JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end);
50.581 - JMP_TARGET(doublesize);
50.582 - MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
50.583 - load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
50.584 - load_xf_bank( R_EDX );
50.585 - store_fr( R_EDX, R_ECX, FRn&0x0E );
50.586 - store_fr( R_EDX, R_EAX, FRn|0x01 );
50.587 - JMP_TARGET(end);
50.588 - } else {
50.589 - JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end);
50.590 - JMP_TARGET(doublesize);
50.591 - MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
50.592 - load_fr_bank( R_EDX );
50.593 - store_fr( R_EDX, R_ECX, FRn&0x0E );
50.594 - store_fr( R_EDX, R_EAX, FRn|0x01 );
50.595 - JMP_TARGET(end);
50.596 - }
50.597 + store_fr( R_EAX, FRn );
50.598 + JMP_rel8(end);
50.599 +
50.600 + JMP_TARGET(doublesize);
50.601 + MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
50.602 + store_dr0( R_ECX, FRn );
50.603 + store_dr1( R_EAX, FRn );
50.604 + JMP_TARGET(end);
50.605 sh4_x86.tstate = TSTATE_NONE;
50.606 }
50.607 break;
50.608 @@ -3119,30 +3024,20 @@
50.609 MMU_TRANSLATE_READ( R_EAX );
50.610 load_spreg( R_EDX, R_FPSCR );
50.611 TEST_imm32_r32( FPSCR_SZ, R_EDX );
50.612 - JNE_rel8(12 + MEM_READ_SIZE, doublesize);
50.613 + JNE_rel8(doublesize);
50.614 +
50.615 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
50.616 MEM_READ_LONG( R_EAX, R_EAX );
50.617 - load_fr_bank( R_EDX );
50.618 - store_fr( R_EDX, R_EAX, FRn );
50.619 - if( FRn&1 ) {
50.620 - JMP_rel8(25 + MEM_READ_DOUBLE_SIZE, end);
50.621 - JMP_TARGET(doublesize);
50.622 - ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
50.623 - MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
50.624 - load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
50.625 - load_xf_bank( R_EDX );
50.626 - store_fr( R_EDX, R_ECX, FRn&0x0E );
50.627 - store_fr( R_EDX, R_EAX, FRn|0x01 );
50.628 - JMP_TARGET(end);
50.629 - } else {
50.630 - JMP_rel8(13 + MEM_READ_DOUBLE_SIZE, end);
50.631 - ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
50.632 - MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
50.633 - load_fr_bank( R_EDX );
50.634 - store_fr( R_EDX, R_ECX, FRn&0x0E );
50.635 - store_fr( R_EDX, R_EAX, FRn|0x01 );
50.636 - JMP_TARGET(end);
50.637 - }
50.638 + store_fr( R_EAX, FRn );
50.639 + JMP_rel8(end);
50.640 +
50.641 + JMP_TARGET(doublesize);
50.642 + ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
50.643 + MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
50.644 + store_dr0( R_ECX, FRn );
50.645 + store_dr1( R_EAX, FRn );
50.646 + JMP_TARGET(end);
50.647 +
50.648 sh4_x86.tstate = TSTATE_NONE;
50.649 }
50.650 break;
50.651 @@ -3155,27 +3050,17 @@
50.652 MMU_TRANSLATE_WRITE( R_EAX );
50.653 load_spreg( R_EDX, R_FPSCR );
50.654 TEST_imm32_r32( FPSCR_SZ, R_EDX );
50.655 - JNE_rel8(8 + MEM_WRITE_SIZE, doublesize);
50.656 - load_fr_bank( R_EDX );
50.657 - load_fr( R_EDX, R_ECX, FRm );
50.658 + JNE_rel8(doublesize);
50.659 +
50.660 + load_fr( R_ECX, FRm );
50.661 MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
50.662 - if( FRm&1 ) {
50.663 - JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end );
50.664 - JMP_TARGET(doublesize);
50.665 - load_xf_bank( R_EDX );
50.666 - load_fr( R_EDX, R_ECX, FRm&0x0E );
50.667 - load_fr( R_EDX, R_EDX, FRm|0x01 );
50.668 - MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
50.669 - JMP_TARGET(end);
50.670 - } else {
50.671 - JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end );
50.672 - JMP_TARGET(doublesize);
50.673 - load_fr_bank( R_EDX );
50.674 - load_fr( R_EDX, R_ECX, FRm&0x0E );
50.675 - load_fr( R_EDX, R_EDX, FRm|0x01 );
50.676 - MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
50.677 - JMP_TARGET(end);
50.678 - }
50.679 + JMP_rel8(end);
50.680 +
50.681 + JMP_TARGET(doublesize);
50.682 + load_dr0( R_ECX, FRm );
50.683 + load_dr1( R_EDX, FRm );
50.684 + MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
50.685 + JMP_TARGET(end);
50.686 sh4_x86.tstate = TSTATE_NONE;
50.687 }
50.688 break;
50.689 @@ -3187,36 +3072,24 @@
50.690 check_walign32( R_EAX );
50.691 load_spreg( R_EDX, R_FPSCR );
50.692 TEST_imm32_r32( FPSCR_SZ, R_EDX );
50.693 - JNE_rel8(15 + MEM_WRITE_SIZE + MMU_TRANSLATE_SIZE, doublesize);
50.694 + JNE_rel8(doublesize);
50.695 +
50.696 ADD_imm8s_r32( -4, R_EAX );
50.697 MMU_TRANSLATE_WRITE( R_EAX );
50.698 - load_fr_bank( R_EDX );
50.699 - load_fr( R_EDX, R_ECX, FRm );
50.700 + load_fr( R_ECX, FRm );
50.701 ADD_imm8s_sh4r(-4,REG_OFFSET(r[Rn]));
50.702 - MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
50.703 - if( FRm&1 ) {
50.704 - JMP_rel8( 25 + MEM_WRITE_DOUBLE_SIZE + MMU_TRANSLATE_SIZE, end );
50.705 - JMP_TARGET(doublesize);
50.706 - ADD_imm8s_r32(-8,R_EAX);
50.707 - MMU_TRANSLATE_WRITE( R_EAX );
50.708 - load_xf_bank( R_EDX );
50.709 - load_fr( R_EDX, R_ECX, FRm&0x0E );
50.710 - load_fr( R_EDX, R_EDX, FRm|0x01 );
50.711 - ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
50.712 - MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
50.713 - JMP_TARGET(end);
50.714 - } else {
50.715 - JMP_rel8( 16 + MEM_WRITE_DOUBLE_SIZE + MMU_TRANSLATE_SIZE, end );
50.716 - JMP_TARGET(doublesize);
50.717 - ADD_imm8s_r32(-8,R_EAX);
50.718 - MMU_TRANSLATE_WRITE( R_EAX );
50.719 - load_fr_bank( R_EDX );
50.720 - load_fr( R_EDX, R_ECX, FRm&0x0E );
50.721 - load_fr( R_EDX, R_EDX, FRm|0x01 );
50.722 - ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
50.723 - MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
50.724 - JMP_TARGET(end);
50.725 - }
50.726 + MEM_WRITE_LONG( R_EAX, R_ECX );
50.727 + JMP_rel8(end);
50.728 +
50.729 + JMP_TARGET(doublesize);
50.730 + ADD_imm8s_r32(-8,R_EAX);
50.731 + MMU_TRANSLATE_WRITE( R_EAX );
50.732 + load_dr0( R_ECX, FRm );
50.733 + load_dr1( R_EDX, FRm );
50.734 + ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
50.735 + MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
50.736 + JMP_TARGET(end);
50.737 +
50.738 sh4_x86.tstate = TSTATE_NONE;
50.739 }
50.740 break;
50.741 @@ -3232,44 +3105,17 @@
50.742 */
50.743 check_fpuen();
50.744 load_spreg( R_ECX, R_FPSCR );
50.745 - load_fr_bank( R_EDX );
50.746 TEST_imm32_r32( FPSCR_SZ, R_ECX );
50.747 - JNE_rel8(8, doublesize);
50.748 - load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
50.749 - store_fr( R_EDX, R_EAX, FRn );
50.750 - if( FRm&1 ) {
50.751 - JMP_rel8(24, end);
50.752 - JMP_TARGET(doublesize);
50.753 - load_xf_bank( R_ECX );
50.754 - load_fr( R_ECX, R_EAX, FRm-1 );
50.755 - if( FRn&1 ) {
50.756 - load_fr( R_ECX, R_EDX, FRm );
50.757 - store_fr( R_ECX, R_EAX, FRn-1 );
50.758 - store_fr( R_ECX, R_EDX, FRn );
50.759 - } else /* FRn&1 == 0 */ {
50.760 - load_fr( R_ECX, R_ECX, FRm );
50.761 - store_fr( R_EDX, R_EAX, FRn );
50.762 - store_fr( R_EDX, R_ECX, FRn+1 );
50.763 - }
50.764 - JMP_TARGET(end);
50.765 - } else /* FRm&1 == 0 */ {
50.766 - if( FRn&1 ) {
50.767 - JMP_rel8(24, end);
50.768 - load_xf_bank( R_ECX );
50.769 - load_fr( R_EDX, R_EAX, FRm );
50.770 - load_fr( R_EDX, R_EDX, FRm+1 );
50.771 - store_fr( R_ECX, R_EAX, FRn-1 );
50.772 - store_fr( R_ECX, R_EDX, FRn );
50.773 - JMP_TARGET(end);
50.774 - } else /* FRn&1 == 0 */ {
50.775 - JMP_rel8(12, end);
50.776 - load_fr( R_EDX, R_EAX, FRm );
50.777 - load_fr( R_EDX, R_ECX, FRm+1 );
50.778 - store_fr( R_EDX, R_EAX, FRn );
50.779 - store_fr( R_EDX, R_ECX, FRn+1 );
50.780 - JMP_TARGET(end);
50.781 - }
50.782 - }
50.783 + JNE_rel8(doublesize);
50.784 + load_fr( R_EAX, FRm ); // PR=0 branch
50.785 + store_fr( R_EAX, FRn );
50.786 + JMP_rel8(end);
50.787 + JMP_TARGET(doublesize);
50.788 + load_dr0( R_EAX, FRm );
50.789 + load_dr1( R_ECX, FRm );
50.790 + store_dr0( R_EAX, FRn );
50.791 + store_dr1( R_ECX, FRn );
50.792 + JMP_TARGET(end);
50.793 sh4_x86.tstate = TSTATE_NONE;
50.794 }
50.795 break;
50.796 @@ -3279,9 +3125,8 @@
50.797 { /* FSTS FPUL, FRn */
50.798 uint32_t FRn = ((ir>>8)&0xF);
50.799 check_fpuen();
50.800 - load_fr_bank( R_ECX );
50.801 load_spreg( R_EAX, R_FPUL );
50.802 - store_fr( R_ECX, R_EAX, FRn );
50.803 + store_fr( R_EAX, FRn );
50.804 sh4_x86.tstate = TSTATE_NONE;
50.805 }
50.806 break;
50.807 @@ -3289,8 +3134,7 @@
50.808 { /* FLDS FRm, FPUL */
50.809 uint32_t FRm = ((ir>>8)&0xF);
50.810 check_fpuen();
50.811 - load_fr_bank( R_ECX );
50.812 - load_fr( R_ECX, R_EAX, FRm );
50.813 + load_fr( R_EAX, FRm );
50.814 store_spreg( R_EAX, R_FPUL );
50.815 sh4_x86.tstate = TSTATE_NONE;
50.816 }
50.817 @@ -3300,14 +3144,13 @@
50.818 uint32_t FRn = ((ir>>8)&0xF);
50.819 check_fpuen();
50.820 load_spreg( R_ECX, R_FPSCR );
50.821 - load_spreg(R_EDX, REG_OFFSET(fr_bank));
50.822 FILD_sh4r(R_FPUL);
50.823 TEST_imm32_r32( FPSCR_PR, R_ECX );
50.824 - JNE_rel8(5, doubleprec);
50.825 - pop_fr( R_EDX, FRn );
50.826 - JMP_rel8(3, end);
50.827 + JNE_rel8(doubleprec);
50.828 + pop_fr( FRn );
50.829 + JMP_rel8(end);
50.830 JMP_TARGET(doubleprec);
50.831 - pop_dr( R_EDX, FRn );
50.832 + pop_dr( FRn );
50.833 JMP_TARGET(end);
50.834 sh4_x86.tstate = TSTATE_NONE;
50.835 }
50.836 @@ -3317,29 +3160,28 @@
50.837 uint32_t FRm = ((ir>>8)&0xF);
50.838 check_fpuen();
50.839 load_spreg( R_ECX, R_FPSCR );
50.840 - load_fr_bank( R_EDX );
50.841 TEST_imm32_r32( FPSCR_PR, R_ECX );
50.842 - JNE_rel8(5, doubleprec);
50.843 - push_fr( R_EDX, FRm );
50.844 - JMP_rel8(3, doop);
50.845 + JNE_rel8(doubleprec);
50.846 + push_fr( FRm );
50.847 + JMP_rel8(doop);
50.848 JMP_TARGET(doubleprec);
50.849 - push_dr( R_EDX, FRm );
50.850 + push_dr( FRm );
50.851 JMP_TARGET( doop );
50.852 load_imm32( R_ECX, (uint32_t)&max_int );
50.853 FILD_r32ind( R_ECX );
50.854 FCOMIP_st(1);
50.855 - JNA_rel8( 32, sat );
50.856 + JNA_rel8( sat );
50.857 load_imm32( R_ECX, (uint32_t)&min_int ); // 5
50.858 FILD_r32ind( R_ECX ); // 2
50.859 FCOMIP_st(1); // 2
50.860 - JAE_rel8( 21, sat2 ); // 2
50.861 + JAE_rel8( sat2 ); // 2
50.862 load_imm32( R_EAX, (uint32_t)&save_fcw );
50.863 FNSTCW_r32ind( R_EAX );
50.864 load_imm32( R_EDX, (uint32_t)&trunc_fcw );
50.865 FLDCW_r32ind( R_EDX );
50.866 FISTP_sh4r(R_FPUL); // 3
50.867 FLDCW_r32ind( R_EAX );
50.868 - JMP_rel8( 9, end ); // 2
50.869 + JMP_rel8(end); // 2
50.870
50.871 JMP_TARGET(sat);
50.872 JMP_TARGET(sat2);
50.873 @@ -3356,16 +3198,15 @@
50.874 check_fpuen();
50.875 load_spreg( R_ECX, R_FPSCR );
50.876 TEST_imm32_r32( FPSCR_PR, R_ECX );
50.877 - load_fr_bank( R_EDX );
50.878 - JNE_rel8(10, doubleprec);
50.879 - push_fr(R_EDX, FRn);
50.880 + JNE_rel8(doubleprec);
50.881 + push_fr(FRn);
50.882 FCHS_st0();
50.883 - pop_fr(R_EDX, FRn);
50.884 - JMP_rel8(8, end);
50.885 + pop_fr(FRn);
50.886 + JMP_rel8(end);
50.887 JMP_TARGET(doubleprec);
50.888 - push_dr(R_EDX, FRn);
50.889 + push_dr(FRn);
50.890 FCHS_st0();
50.891 - pop_dr(R_EDX, FRn);
50.892 + pop_dr(FRn);
50.893 JMP_TARGET(end);
50.894 sh4_x86.tstate = TSTATE_NONE;
50.895 }
50.896 @@ -3375,17 +3216,16 @@
50.897 uint32_t FRn = ((ir>>8)&0xF);
50.898 check_fpuen();
50.899 load_spreg( R_ECX, R_FPSCR );
50.900 - load_fr_bank( R_EDX );
50.901 TEST_imm32_r32( FPSCR_PR, R_ECX );
50.902 - JNE_rel8(10, doubleprec);
50.903 - push_fr(R_EDX, FRn); // 3
50.904 + JNE_rel8(doubleprec);
50.905 + push_fr(FRn); // 6
50.906 FABS_st0(); // 2
50.907 - pop_fr( R_EDX, FRn); //3
50.908 - JMP_rel8(8,end); // 2
50.909 + pop_fr(FRn); //6
50.910 + JMP_rel8(end); // 2
50.911 JMP_TARGET(doubleprec);
50.912 - push_dr(R_EDX, FRn);
50.913 + push_dr(FRn);
50.914 FABS_st0();
50.915 - pop_dr(R_EDX, FRn);
50.916 + pop_dr(FRn);
50.917 JMP_TARGET(end);
50.918 sh4_x86.tstate = TSTATE_NONE;
50.919 }
50.920 @@ -3396,16 +3236,15 @@
50.921 check_fpuen();
50.922 load_spreg( R_ECX, R_FPSCR );
50.923 TEST_imm32_r32( FPSCR_PR, R_ECX );
50.924 - load_fr_bank( R_EDX );
50.925 - JNE_rel8(10, doubleprec);
50.926 - push_fr(R_EDX, FRn);
50.927 + JNE_rel8(doubleprec);
50.928 + push_fr(FRn);
50.929 FSQRT_st0();
50.930 - pop_fr(R_EDX, FRn);
50.931 - JMP_rel8(8, end);
50.932 + pop_fr(FRn);
50.933 + JMP_rel8(end);
50.934 JMP_TARGET(doubleprec);
50.935 - push_dr(R_EDX, FRn);
50.936 + push_dr(FRn);
50.937 FSQRT_st0();
50.938 - pop_dr(R_EDX, FRn);
50.939 + pop_dr(FRn);
50.940 JMP_TARGET(end);
50.941 sh4_x86.tstate = TSTATE_NONE;
50.942 }
50.943 @@ -3416,13 +3255,12 @@
50.944 check_fpuen();
50.945 load_spreg( R_ECX, R_FPSCR );
50.946 TEST_imm32_r32( FPSCR_PR, R_ECX );
50.947 - load_fr_bank( R_EDX );
50.948 - JNE_rel8(12, end); // PR=0 only
50.949 + JNE_rel8(end); // PR=0 only
50.950 FLD1_st0();
50.951 - push_fr(R_EDX, FRn);
50.952 + push_fr(FRn);
50.953 FSQRT_st0();
50.954 FDIVP_st(1);
50.955 - pop_fr(R_EDX, FRn);
50.956 + pop_fr(FRn);
50.957 JMP_TARGET(end);
50.958 sh4_x86.tstate = TSTATE_NONE;
50.959 }
50.960 @@ -3434,10 +3272,9 @@
50.961 check_fpuen();
50.962 load_spreg( R_ECX, R_FPSCR );
50.963 TEST_imm32_r32( FPSCR_PR, R_ECX );
50.964 - JNE_rel8(8, end);
50.965 + JNE_rel8(end);
50.966 XOR_r32_r32( R_EAX, R_EAX );
50.967 - load_spreg( R_ECX, REG_OFFSET(fr_bank) );
50.968 - store_fr( R_ECX, R_EAX, FRn );
50.969 + store_fr( R_EAX, FRn );
50.970 JMP_TARGET(end);
50.971 sh4_x86.tstate = TSTATE_NONE;
50.972 }
50.973 @@ -3449,10 +3286,9 @@
50.974 check_fpuen();
50.975 load_spreg( R_ECX, R_FPSCR );
50.976 TEST_imm32_r32( FPSCR_PR, R_ECX );
50.977 - JNE_rel8(11, end);
50.978 + JNE_rel8(end);
50.979 load_imm32(R_EAX, 0x3F800000);
50.980 - load_spreg( R_ECX, REG_OFFSET(fr_bank) );
50.981 - store_fr( R_ECX, R_EAX, FRn );
50.982 + store_fr( R_EAX, FRn );
50.983 JMP_TARGET(end);
50.984 sh4_x86.tstate = TSTATE_NONE;
50.985 }
50.986 @@ -3463,10 +3299,9 @@
50.987 check_fpuen();
50.988 load_spreg( R_ECX, R_FPSCR );
50.989 TEST_imm32_r32( FPSCR_PR, R_ECX );
50.990 - JE_rel8(9, end); // only when PR=1
50.991 - load_fr_bank( R_ECX );
50.992 + JE_rel8(end); // only when PR=1
50.993 push_fpul();
50.994 - pop_dr( R_ECX, FRn );
50.995 + pop_dr( FRn );
50.996 JMP_TARGET(end);
50.997 sh4_x86.tstate = TSTATE_NONE;
50.998 }
50.999 @@ -3477,9 +3312,8 @@
50.1000 check_fpuen();
50.1001 load_spreg( R_ECX, R_FPSCR );
50.1002 TEST_imm32_r32( FPSCR_PR, R_ECX );
50.1003 - JE_rel8(9, end); // only when PR=1
50.1004 - load_fr_bank( R_ECX );
50.1005 - push_dr( R_ECX, FRm );
50.1006 + JE_rel8(end); // only when PR=1
50.1007 + push_dr( FRm );
50.1008 pop_fpul();
50.1009 JMP_TARGET(end);
50.1010 sh4_x86.tstate = TSTATE_NONE;
50.1011 @@ -3491,25 +3325,24 @@
50.1012 check_fpuen();
50.1013 load_spreg( R_ECX, R_FPSCR );
50.1014 TEST_imm32_r32( FPSCR_PR, R_ECX );
50.1015 - JNE_rel8(44, doubleprec);
50.1016 + JNE_rel8( doubleprec);
50.1017
50.1018 - load_fr_bank( R_ECX );
50.1019 - push_fr( R_ECX, FVm<<2 );
50.1020 - push_fr( R_ECX, FVn<<2 );
50.1021 + push_fr( FVm<<2 );
50.1022 + push_fr( FVn<<2 );
50.1023 FMULP_st(1);
50.1024 - push_fr( R_ECX, (FVm<<2)+1);
50.1025 - push_fr( R_ECX, (FVn<<2)+1);
50.1026 + push_fr( (FVm<<2)+1);
50.1027 + push_fr( (FVn<<2)+1);
50.1028 FMULP_st(1);
50.1029 FADDP_st(1);
50.1030 - push_fr( R_ECX, (FVm<<2)+2);
50.1031 - push_fr( R_ECX, (FVn<<2)+2);
50.1032 + push_fr( (FVm<<2)+2);
50.1033 + push_fr( (FVn<<2)+2);
50.1034 FMULP_st(1);
50.1035 FADDP_st(1);
50.1036 - push_fr( R_ECX, (FVm<<2)+3);
50.1037 - push_fr( R_ECX, (FVn<<2)+3);
50.1038 + push_fr( (FVm<<2)+3);
50.1039 + push_fr( (FVn<<2)+3);
50.1040 FMULP_st(1);
50.1041 FADDP_st(1);
50.1042 - pop_fr( R_ECX, (FVn<<2)+3);
50.1043 + pop_fr( (FVn<<2)+3);
50.1044 JMP_TARGET(doubleprec);
50.1045 sh4_x86.tstate = TSTATE_NONE;
50.1046 }
50.1047 @@ -3522,9 +3355,8 @@
50.1048 check_fpuen();
50.1049 load_spreg( R_ECX, R_FPSCR );
50.1050 TEST_imm32_r32( FPSCR_PR, R_ECX );
50.1051 - JNE_rel8( CALL_FUNC2_SIZE + 9, doubleprec );
50.1052 - load_fr_bank( R_ECX );
50.1053 - ADD_imm8s_r32( (FRn&0x0E)<<2, R_ECX );
50.1054 + JNE_rel8(doubleprec );
50.1055 + LEA_sh4r_r32( REG_OFFSET(fr[0][FRn&0x0E]), R_ECX );
50.1056 load_spreg( R_EDX, R_FPUL );
50.1057 call_func2( sh4_fsca, R_EDX, R_ECX );
50.1058 JMP_TARGET(doubleprec);
50.1059 @@ -3539,11 +3371,9 @@
50.1060 check_fpuen();
50.1061 load_spreg( R_ECX, R_FPSCR );
50.1062 TEST_imm32_r32( FPSCR_PR, R_ECX );
50.1063 - JNE_rel8( 18 + CALL_FUNC2_SIZE, doubleprec );
50.1064 - load_fr_bank( R_EDX ); // 3
50.1065 - ADD_imm8s_r32( FVn<<4, R_EDX ); // 3
50.1066 - load_xf_bank( R_ECX ); // 12
50.1067 - call_func2( sh4_ftrv, R_EDX, R_ECX ); // 12
50.1068 + JNE_rel8( doubleprec );
50.1069 + LEA_sh4r_r32( REG_OFFSET(fr[0][FVn<<2]), R_EDX );
50.1070 + call_func1( sh4_ftrv, R_EDX ); // 12
50.1071 JMP_TARGET(doubleprec);
50.1072 sh4_x86.tstate = TSTATE_NONE;
50.1073 }
50.1074 @@ -3565,7 +3395,7 @@
50.1075 load_spreg( R_ECX, R_FPSCR );
50.1076 XOR_imm32_r32( FPSCR_FR, R_ECX );
50.1077 store_spreg( R_ECX, R_FPSCR );
50.1078 - update_fr_bank( R_ECX );
50.1079 + call_func0( sh4_switch_fr_banks );
50.1080 sh4_x86.tstate = TSTATE_NONE;
50.1081 }
50.1082 break;
50.1083 @@ -3598,23 +3428,22 @@
50.1084 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
50.1085 check_fpuen();
50.1086 load_spreg( R_ECX, R_FPSCR );
50.1087 - load_spreg( R_EDX, REG_OFFSET(fr_bank));
50.1088 TEST_imm32_r32( FPSCR_PR, R_ECX );
50.1089 - JNE_rel8(18, doubleprec);
50.1090 - push_fr( R_EDX, 0 );
50.1091 - push_fr( R_EDX, FRm );
50.1092 + JNE_rel8(doubleprec);
50.1093 + push_fr( 0 );
50.1094 + push_fr( FRm );
50.1095 FMULP_st(1);
50.1096 - push_fr( R_EDX, FRn );
50.1097 + push_fr( FRn );
50.1098 FADDP_st(1);
50.1099 - pop_fr( R_EDX, FRn );
50.1100 - JMP_rel8(16, end);
50.1101 + pop_fr( FRn );
50.1102 + JMP_rel8(end);
50.1103 JMP_TARGET(doubleprec);
50.1104 - push_dr( R_EDX, 0 );
50.1105 - push_dr( R_EDX, FRm );
50.1106 + push_dr( 0 );
50.1107 + push_dr( FRm );
50.1108 FMULP_st(1);
50.1109 - push_dr( R_EDX, FRn );
50.1110 + push_dr( FRn );
50.1111 FADDP_st(1);
50.1112 - pop_dr( R_EDX, FRn );
50.1113 + pop_dr( FRn );
50.1114 JMP_TARGET(end);
50.1115 sh4_x86.tstate = TSTATE_NONE;
50.1116 }
51.1 --- a/src/sh4/sh4x86.in Sun Apr 20 05:30:07 2008 +0000
51.2 +++ b/src/sh4/sh4x86.in Mon May 12 10:00:13 2008 +0000
51.3 @@ -80,15 +80,14 @@
51.4 #define TSTATE_AE 3
51.5
51.6 /** Branch if T is set (either in the current cflags, or in sh4r.t) */
51.7 -#define JT_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
51.8 +#define JT_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
51.9 CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
51.10 - OP(0x70+sh4_x86.tstate); OP(rel8); \
51.11 - MARK_JMP(rel8,label)
51.12 + OP(0x70+sh4_x86.tstate); MARK_JMP8(label); OP(-1)
51.13 +
51.14 /** Branch if T is clear (either in the current cflags or in sh4r.t) */
51.15 -#define JF_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
51.16 +#define JF_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
51.17 CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
51.18 - OP(0x70+ (sh4_x86.tstate^1)); OP(rel8); \
51.19 - MARK_JMP(rel8, label)
51.20 + OP(0x70+ (sh4_x86.tstate^1)); MARK_JMP8(label); OP(-1)
51.21
51.22 static struct sh4_x86_state sh4_x86;
51.23
51.24 @@ -97,7 +96,7 @@
51.25 static uint32_t save_fcw; /* save value for fpu control word */
51.26 static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
51.27
51.28 -void sh4_x86_init()
51.29 +void sh4_translate_init(void)
51.30 {
51.31 sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
51.32 sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
51.33 @@ -169,7 +168,6 @@
51.34 OP64(value);
51.35 }
51.36
51.37 -
51.38 /**
51.39 * Emit an instruction to store an SH4 reg (RN)
51.40 */
51.41 @@ -180,97 +178,42 @@
51.42 OP(REG_OFFSET(r[sh4reg]));
51.43 }
51.44
51.45 -#define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
51.46 -
51.47 /**
51.48 * Load an FR register (single-precision floating point) into an integer x86
51.49 * register (eg for register-to-register moves)
51.50 */
51.51 -void static inline load_fr( int bankreg, int x86reg, int frm )
51.52 -{
51.53 - OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
51.54 -}
51.55 +#define load_fr(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[0][(frm)^1]) )
51.56 +#define load_xf(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[1][(frm)^1]) )
51.57
51.58 /**
51.59 - * Store an FR register (single-precision floating point) into an integer x86
51.60 + * Load the low half of a DR register (DR or XD) into an integer x86 register
51.61 + */
51.62 +#define load_dr0(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
51.63 +#define load_dr1(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
51.64 +
51.65 +/**
51.66 + * Store an FR register (single-precision floating point) from an integer x86+
51.67 * register (eg for register-to-register moves)
51.68 */
51.69 -void static inline store_fr( int bankreg, int x86reg, int frn )
51.70 -{
51.71 - OP(0x89); OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
51.72 -}
51.73 +#define store_fr(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[0][(frm)^1]) )
51.74 +#define store_xf(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[1][(frm)^1]) )
51.75
51.76 +#define store_dr0(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
51.77 +#define store_dr1(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
51.78
51.79 -/**
51.80 - * Load a pointer to the back fp back into the specified x86 register. The
51.81 - * bankreg must have been previously loaded with FPSCR.
51.82 - * NB: 12 bytes
51.83 - */
51.84 -static inline void load_xf_bank( int bankreg )
51.85 -{
51.86 - NOT_r32( bankreg );
51.87 - SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
51.88 - AND_imm8s_r32( 0x40, bankreg ); // Complete extraction
51.89 - OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
51.90 -}
51.91
51.92 -/**
51.93 - * Update the fr_bank pointer based on the current fpscr value.
51.94 - */
51.95 -static inline void update_fr_bank( int fpscrreg )
51.96 -{
51.97 - SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
51.98 - AND_imm8s_r32( 0x40, fpscrreg ); // Complete extraction
51.99 - OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
51.100 - store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
51.101 -}
51.102 -/**
51.103 - * Push FPUL (as a 32-bit float) onto the FPU stack
51.104 - */
51.105 -static inline void push_fpul( )
51.106 -{
51.107 - OP(0xD9); OP(0x45); OP(R_FPUL);
51.108 -}
51.109 +#define push_fpul() FLDF_sh4r(R_FPUL)
51.110 +#define pop_fpul() FSTPF_sh4r(R_FPUL)
51.111 +#define push_fr(frm) FLDF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
51.112 +#define pop_fr(frm) FSTPF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
51.113 +#define push_xf(frm) FLDF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
51.114 +#define pop_xf(frm) FSTPF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
51.115 +#define push_dr(frm) FLDD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
51.116 +#define pop_dr(frm) FSTPD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
51.117 +#define push_xdr(frm) FLDD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
51.118 +#define pop_xdr(frm) FSTPD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
51.119
51.120 -/**
51.121 - * Pop FPUL (as a 32-bit float) from the FPU stack
51.122 - */
51.123 -static inline void pop_fpul( )
51.124 -{
51.125 - OP(0xD9); OP(0x5D); OP(R_FPUL);
51.126 -}
51.127
51.128 -/**
51.129 - * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
51.130 - * with the location of the current fp bank.
51.131 - */
51.132 -static inline void push_fr( int bankreg, int frm )
51.133 -{
51.134 - OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2); // FLD.S [bankreg + frm^1*4]
51.135 -}
51.136 -
51.137 -/**
51.138 - * Pop a 32-bit float from the FPU stack and store it back into the fp bank,
51.139 - * with bankreg previously loaded with the location of the current fp bank.
51.140 - */
51.141 -static inline void pop_fr( int bankreg, int frm )
51.142 -{
51.143 - OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
51.144 -}
51.145 -
51.146 -/**
51.147 - * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
51.148 - * with the location of the current fp bank.
51.149 - */
51.150 -static inline void push_dr( int bankreg, int frm )
51.151 -{
51.152 - OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
51.153 -}
51.154 -
51.155 -static inline void pop_dr( int bankreg, int frm )
51.156 -{
51.157 - OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
51.158 -}
51.159
51.160 /* Exception checks - Note that all exception checks will clobber EAX */
51.161
51.162 @@ -555,13 +498,13 @@
51.163 load_reg( R_ECX, Rn );
51.164 XOR_r32_r32( R_ECX, R_EAX );
51.165 TEST_r8_r8( R_AL, R_AL );
51.166 - JE_rel8(13, target1);
51.167 - TEST_r8_r8( R_AH, R_AH ); // 2
51.168 - JE_rel8(9, target2);
51.169 - SHR_imm8_r32( 16, R_EAX ); // 3
51.170 - TEST_r8_r8( R_AL, R_AL ); // 2
51.171 - JE_rel8(2, target3);
51.172 - TEST_r8_r8( R_AH, R_AH ); // 2
51.173 + JE_rel8(target1);
51.174 + TEST_r8_r8( R_AH, R_AH );
51.175 + JE_rel8(target2);
51.176 + SHR_imm8_r32( 16, R_EAX );
51.177 + TEST_r8_r8( R_AL, R_AL );
51.178 + JE_rel8(target3);
51.179 + TEST_r8_r8( R_AH, R_AH );
51.180 JMP_TARGET(target1);
51.181 JMP_TARGET(target2);
51.182 JMP_TARGET(target3);
51.183 @@ -595,9 +538,9 @@
51.184 RCL1_r32( R_EAX );
51.185 SETC_r8( R_DL ); // Q'
51.186 CMP_sh4r_r32( R_Q, R_ECX );
51.187 - JE_rel8(5, mqequal);
51.188 + JE_rel8(mqequal);
51.189 ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
51.190 - JMP_rel8(3, end);
51.191 + JMP_rel8(end);
51.192 JMP_TARGET(mqequal);
51.193 SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
51.194 JMP_TARGET(end);
51.195 @@ -690,7 +633,7 @@
51.196
51.197 load_spreg( R_ECX, R_S );
51.198 TEST_r32_r32(R_ECX, R_ECX);
51.199 - JE_rel8( CALL_FUNC0_SIZE, nosat );
51.200 + JE_rel8( nosat );
51.201 call_func0( signsat48 );
51.202 JMP_TARGET( nosat );
51.203 sh4_x86.tstate = TSTATE_NONE;
51.204 @@ -728,21 +671,21 @@
51.205
51.206 load_spreg( R_ECX, R_S );
51.207 TEST_r32_r32( R_ECX, R_ECX );
51.208 - JE_rel8( 47, nosat );
51.209 + JE_rel8( nosat );
51.210
51.211 ADD_r32_sh4r( R_EAX, R_MACL ); // 6
51.212 - JNO_rel8( 51, end ); // 2
51.213 + JNO_rel8( end ); // 2
51.214 load_imm32( R_EDX, 1 ); // 5
51.215 store_spreg( R_EDX, R_MACH ); // 6
51.216 - JS_rel8( 13, positive ); // 2
51.217 + JS_rel8( positive ); // 2
51.218 load_imm32( R_EAX, 0x80000000 );// 5
51.219 store_spreg( R_EAX, R_MACL ); // 6
51.220 - JMP_rel8( 25, end2 ); // 2
51.221 + JMP_rel8(end2); // 2
51.222
51.223 JMP_TARGET(positive);
51.224 load_imm32( R_EAX, 0x7FFFFFFF );// 5
51.225 store_spreg( R_EAX, R_MACL ); // 6
51.226 - JMP_rel8( 12, end3); // 2
51.227 + JMP_rel8(end3); // 2
51.228
51.229 JMP_TARGET(nosat);
51.230 ADD_r32_sh4r( R_EAX, R_MACL ); // 6
51.231 @@ -862,17 +805,17 @@
51.232 load_reg( R_EAX, Rn );
51.233 load_reg( R_ECX, Rm );
51.234 CMP_imm32_r32( 0, R_ECX );
51.235 - JGE_rel8(16, doshl);
51.236 + JGE_rel8(doshl);
51.237
51.238 NEG_r32( R_ECX ); // 2
51.239 AND_imm8_r8( 0x1F, R_CL ); // 3
51.240 - JE_rel8( 4, emptysar); // 2
51.241 + JE_rel8(emptysar); // 2
51.242 SAR_r32_CL( R_EAX ); // 2
51.243 - JMP_rel8(10, end); // 2
51.244 + JMP_rel8(end); // 2
51.245
51.246 JMP_TARGET(emptysar);
51.247 SAR_imm8_r32(31, R_EAX ); // 3
51.248 - JMP_rel8(5, end2);
51.249 + JMP_rel8(end2);
51.250
51.251 JMP_TARGET(doshl);
51.252 AND_imm8_r8( 0x1F, R_CL ); // 3
51.253 @@ -886,17 +829,17 @@
51.254 load_reg( R_EAX, Rn );
51.255 load_reg( R_ECX, Rm );
51.256 CMP_imm32_r32( 0, R_ECX );
51.257 - JGE_rel8(15, doshl);
51.258 + JGE_rel8(doshl);
51.259
51.260 NEG_r32( R_ECX ); // 2
51.261 AND_imm8_r8( 0x1F, R_CL ); // 3
51.262 - JE_rel8( 4, emptyshr );
51.263 + JE_rel8(emptyshr );
51.264 SHR_r32_CL( R_EAX ); // 2
51.265 - JMP_rel8(9, end); // 2
51.266 + JMP_rel8(end); // 2
51.267
51.268 JMP_TARGET(emptyshr);
51.269 XOR_r32_r32( R_EAX, R_EAX );
51.270 - JMP_rel8(5, end2);
51.271 + JMP_rel8(end2);
51.272
51.273 JMP_TARGET(doshl);
51.274 AND_imm8_r8( 0x1F, R_CL ); // 3
51.275 @@ -1427,7 +1370,7 @@
51.276 SLOTILLEGAL();
51.277 } else {
51.278 sh4vma_t target = disp + pc + 4;
51.279 - JT_rel8( EXIT_BLOCK_REL_SIZE(target), nottaken );
51.280 + JT_rel8( nottaken );
51.281 exit_block_rel(target, pc+2 );
51.282 JMP_TARGET(nottaken);
51.283 return 2;
51.284 @@ -1440,7 +1383,7 @@
51.285 sh4_x86.in_delay_slot = DELAY_PC;
51.286 if( UNTRANSLATABLE(pc+2) ) {
51.287 load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
51.288 - JT_rel8(6,nottaken);
51.289 + JT_rel8(nottaken);
51.290 ADD_imm32_r32( disp, R_EAX );
51.291 JMP_TARGET(nottaken);
51.292 ADD_sh4r_r32( R_PC, R_EAX );
51.293 @@ -1555,7 +1498,7 @@
51.294 SLOTILLEGAL();
51.295 } else {
51.296 sh4vma_t target = disp + pc + 4;
51.297 - JF_rel8( EXIT_BLOCK_REL_SIZE(target), nottaken );
51.298 + JF_rel8( nottaken );
51.299 exit_block_rel(target, pc+2 );
51.300 JMP_TARGET(nottaken);
51.301 return 2;
51.302 @@ -1568,7 +1511,7 @@
51.303 sh4_x86.in_delay_slot = DELAY_PC;
51.304 if( UNTRANSLATABLE(pc+2) ) {
51.305 load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
51.306 - JF_rel8(6,nottaken);
51.307 + JF_rel8(nottaken);
51.308 ADD_imm32_r32( disp, R_EAX );
51.309 JMP_TARGET(nottaken);
51.310 ADD_sh4r_r32( R_PC, R_EAX );
51.311 @@ -1734,44 +1677,17 @@
51.312 */
51.313 check_fpuen();
51.314 load_spreg( R_ECX, R_FPSCR );
51.315 - load_fr_bank( R_EDX );
51.316 TEST_imm32_r32( FPSCR_SZ, R_ECX );
51.317 - JNE_rel8(8, doublesize);
51.318 - load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
51.319 - store_fr( R_EDX, R_EAX, FRn );
51.320 - if( FRm&1 ) {
51.321 - JMP_rel8(24, end);
51.322 - JMP_TARGET(doublesize);
51.323 - load_xf_bank( R_ECX );
51.324 - load_fr( R_ECX, R_EAX, FRm-1 );
51.325 - if( FRn&1 ) {
51.326 - load_fr( R_ECX, R_EDX, FRm );
51.327 - store_fr( R_ECX, R_EAX, FRn-1 );
51.328 - store_fr( R_ECX, R_EDX, FRn );
51.329 - } else /* FRn&1 == 0 */ {
51.330 - load_fr( R_ECX, R_ECX, FRm );
51.331 - store_fr( R_EDX, R_EAX, FRn );
51.332 - store_fr( R_EDX, R_ECX, FRn+1 );
51.333 - }
51.334 - JMP_TARGET(end);
51.335 - } else /* FRm&1 == 0 */ {
51.336 - if( FRn&1 ) {
51.337 - JMP_rel8(24, end);
51.338 - load_xf_bank( R_ECX );
51.339 - load_fr( R_EDX, R_EAX, FRm );
51.340 - load_fr( R_EDX, R_EDX, FRm+1 );
51.341 - store_fr( R_ECX, R_EAX, FRn-1 );
51.342 - store_fr( R_ECX, R_EDX, FRn );
51.343 - JMP_TARGET(end);
51.344 - } else /* FRn&1 == 0 */ {
51.345 - JMP_rel8(12, end);
51.346 - load_fr( R_EDX, R_EAX, FRm );
51.347 - load_fr( R_EDX, R_ECX, FRm+1 );
51.348 - store_fr( R_EDX, R_EAX, FRn );
51.349 - store_fr( R_EDX, R_ECX, FRn+1 );
51.350 - JMP_TARGET(end);
51.351 - }
51.352 - }
51.353 + JNE_rel8(doublesize);
51.354 + load_fr( R_EAX, FRm ); // PR=0 branch
51.355 + store_fr( R_EAX, FRn );
51.356 + JMP_rel8(end);
51.357 + JMP_TARGET(doublesize);
51.358 + load_dr0( R_EAX, FRm );
51.359 + load_dr1( R_ECX, FRm );
51.360 + store_dr0( R_EAX, FRn );
51.361 + store_dr1( R_ECX, FRn );
51.362 + JMP_TARGET(end);
51.363 sh4_x86.tstate = TSTATE_NONE;
51.364 :}
51.365 FMOV FRm, @Rn {:
51.366 @@ -1781,27 +1697,17 @@
51.367 MMU_TRANSLATE_WRITE( R_EAX );
51.368 load_spreg( R_EDX, R_FPSCR );
51.369 TEST_imm32_r32( FPSCR_SZ, R_EDX );
51.370 - JNE_rel8(8 + MEM_WRITE_SIZE, doublesize);
51.371 - load_fr_bank( R_EDX );
51.372 - load_fr( R_EDX, R_ECX, FRm );
51.373 + JNE_rel8(doublesize);
51.374 +
51.375 + load_fr( R_ECX, FRm );
51.376 MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
51.377 - if( FRm&1 ) {
51.378 - JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end );
51.379 - JMP_TARGET(doublesize);
51.380 - load_xf_bank( R_EDX );
51.381 - load_fr( R_EDX, R_ECX, FRm&0x0E );
51.382 - load_fr( R_EDX, R_EDX, FRm|0x01 );
51.383 - MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
51.384 - JMP_TARGET(end);
51.385 - } else {
51.386 - JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end );
51.387 - JMP_TARGET(doublesize);
51.388 - load_fr_bank( R_EDX );
51.389 - load_fr( R_EDX, R_ECX, FRm&0x0E );
51.390 - load_fr( R_EDX, R_EDX, FRm|0x01 );
51.391 - MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
51.392 - JMP_TARGET(end);
51.393 - }
51.394 + JMP_rel8(end);
51.395 +
51.396 + JMP_TARGET(doublesize);
51.397 + load_dr0( R_ECX, FRm );
51.398 + load_dr1( R_EDX, FRm );
51.399 + MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
51.400 + JMP_TARGET(end);
51.401 sh4_x86.tstate = TSTATE_NONE;
51.402 :}
51.403 FMOV @Rm, FRn {:
51.404 @@ -1811,28 +1717,17 @@
51.405 MMU_TRANSLATE_READ( R_EAX );
51.406 load_spreg( R_EDX, R_FPSCR );
51.407 TEST_imm32_r32( FPSCR_SZ, R_EDX );
51.408 - JNE_rel8(8 + MEM_READ_SIZE, doublesize);
51.409 + JNE_rel8(doublesize);
51.410 +
51.411 MEM_READ_LONG( R_EAX, R_EAX );
51.412 - load_fr_bank( R_EDX );
51.413 - store_fr( R_EDX, R_EAX, FRn );
51.414 - if( FRn&1 ) {
51.415 - JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end);
51.416 - JMP_TARGET(doublesize);
51.417 - MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
51.418 - load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
51.419 - load_xf_bank( R_EDX );
51.420 - store_fr( R_EDX, R_ECX, FRn&0x0E );
51.421 - store_fr( R_EDX, R_EAX, FRn|0x01 );
51.422 - JMP_TARGET(end);
51.423 - } else {
51.424 - JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end);
51.425 - JMP_TARGET(doublesize);
51.426 - MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
51.427 - load_fr_bank( R_EDX );
51.428 - store_fr( R_EDX, R_ECX, FRn&0x0E );
51.429 - store_fr( R_EDX, R_EAX, FRn|0x01 );
51.430 - JMP_TARGET(end);
51.431 - }
51.432 + store_fr( R_EAX, FRn );
51.433 + JMP_rel8(end);
51.434 +
51.435 + JMP_TARGET(doublesize);
51.436 + MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
51.437 + store_dr0( R_ECX, FRn );
51.438 + store_dr1( R_EAX, FRn );
51.439 + JMP_TARGET(end);
51.440 sh4_x86.tstate = TSTATE_NONE;
51.441 :}
51.442 FMOV FRm, @-Rn {:
51.443 @@ -1841,36 +1736,24 @@
51.444 check_walign32( R_EAX );
51.445 load_spreg( R_EDX, R_FPSCR );
51.446 TEST_imm32_r32( FPSCR_SZ, R_EDX );
51.447 - JNE_rel8(15 + MEM_WRITE_SIZE + MMU_TRANSLATE_SIZE, doublesize);
51.448 + JNE_rel8(doublesize);
51.449 +
51.450 ADD_imm8s_r32( -4, R_EAX );
51.451 MMU_TRANSLATE_WRITE( R_EAX );
51.452 - load_fr_bank( R_EDX );
51.453 - load_fr( R_EDX, R_ECX, FRm );
51.454 + load_fr( R_ECX, FRm );
51.455 ADD_imm8s_sh4r(-4,REG_OFFSET(r[Rn]));
51.456 - MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
51.457 - if( FRm&1 ) {
51.458 - JMP_rel8( 25 + MEM_WRITE_DOUBLE_SIZE + MMU_TRANSLATE_SIZE, end );
51.459 - JMP_TARGET(doublesize);
51.460 - ADD_imm8s_r32(-8,R_EAX);
51.461 - MMU_TRANSLATE_WRITE( R_EAX );
51.462 - load_xf_bank( R_EDX );
51.463 - load_fr( R_EDX, R_ECX, FRm&0x0E );
51.464 - load_fr( R_EDX, R_EDX, FRm|0x01 );
51.465 - ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
51.466 - MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
51.467 - JMP_TARGET(end);
51.468 - } else {
51.469 - JMP_rel8( 16 + MEM_WRITE_DOUBLE_SIZE + MMU_TRANSLATE_SIZE, end );
51.470 - JMP_TARGET(doublesize);
51.471 - ADD_imm8s_r32(-8,R_EAX);
51.472 - MMU_TRANSLATE_WRITE( R_EAX );
51.473 - load_fr_bank( R_EDX );
51.474 - load_fr( R_EDX, R_ECX, FRm&0x0E );
51.475 - load_fr( R_EDX, R_EDX, FRm|0x01 );
51.476 - ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
51.477 - MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
51.478 - JMP_TARGET(end);
51.479 - }
51.480 + MEM_WRITE_LONG( R_EAX, R_ECX );
51.481 + JMP_rel8(end);
51.482 +
51.483 + JMP_TARGET(doublesize);
51.484 + ADD_imm8s_r32(-8,R_EAX);
51.485 + MMU_TRANSLATE_WRITE( R_EAX );
51.486 + load_dr0( R_ECX, FRm );
51.487 + load_dr1( R_EDX, FRm );
51.488 + ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
51.489 + MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
51.490 + JMP_TARGET(end);
51.491 +
51.492 sh4_x86.tstate = TSTATE_NONE;
51.493 :}
51.494 FMOV @Rm+, FRn {:
51.495 @@ -1880,30 +1763,20 @@
51.496 MMU_TRANSLATE_READ( R_EAX );
51.497 load_spreg( R_EDX, R_FPSCR );
51.498 TEST_imm32_r32( FPSCR_SZ, R_EDX );
51.499 - JNE_rel8(12 + MEM_READ_SIZE, doublesize);
51.500 + JNE_rel8(doublesize);
51.501 +
51.502 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
51.503 MEM_READ_LONG( R_EAX, R_EAX );
51.504 - load_fr_bank( R_EDX );
51.505 - store_fr( R_EDX, R_EAX, FRn );
51.506 - if( FRn&1 ) {
51.507 - JMP_rel8(25 + MEM_READ_DOUBLE_SIZE, end);
51.508 - JMP_TARGET(doublesize);
51.509 - ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
51.510 - MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
51.511 - load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
51.512 - load_xf_bank( R_EDX );
51.513 - store_fr( R_EDX, R_ECX, FRn&0x0E );
51.514 - store_fr( R_EDX, R_EAX, FRn|0x01 );
51.515 - JMP_TARGET(end);
51.516 - } else {
51.517 - JMP_rel8(13 + MEM_READ_DOUBLE_SIZE, end);
51.518 - ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
51.519 - MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
51.520 - load_fr_bank( R_EDX );
51.521 - store_fr( R_EDX, R_ECX, FRn&0x0E );
51.522 - store_fr( R_EDX, R_EAX, FRn|0x01 );
51.523 - JMP_TARGET(end);
51.524 - }
51.525 + store_fr( R_EAX, FRn );
51.526 + JMP_rel8(end);
51.527 +
51.528 + JMP_TARGET(doublesize);
51.529 + ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
51.530 + MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
51.531 + store_dr0( R_ECX, FRn );
51.532 + store_dr1( R_EAX, FRn );
51.533 + JMP_TARGET(end);
51.534 +
51.535 sh4_x86.tstate = TSTATE_NONE;
51.536 :}
51.537 FMOV FRm, @(R0, Rn) {:
51.538 @@ -1914,27 +1787,18 @@
51.539 MMU_TRANSLATE_WRITE( R_EAX );
51.540 load_spreg( R_EDX, R_FPSCR );
51.541 TEST_imm32_r32( FPSCR_SZ, R_EDX );
51.542 - JNE_rel8(8 + MEM_WRITE_SIZE, doublesize);
51.543 - load_fr_bank( R_EDX );
51.544 - load_fr( R_EDX, R_ECX, FRm );
51.545 + JNE_rel8(doublesize);
51.546 +
51.547 + load_fr( R_ECX, FRm );
51.548 MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
51.549 - if( FRm&1 ) {
51.550 - JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end );
51.551 - JMP_TARGET(doublesize);
51.552 - load_xf_bank( R_EDX );
51.553 - load_fr( R_EDX, R_ECX, FRm&0x0E );
51.554 - load_fr( R_EDX, R_EDX, FRm|0x01 );
51.555 - MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
51.556 - JMP_TARGET(end);
51.557 - } else {
51.558 - JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end );
51.559 - JMP_TARGET(doublesize);
51.560 - load_fr_bank( R_EDX );
51.561 - load_fr( R_EDX, R_ECX, FRm&0x0E );
51.562 - load_fr( R_EDX, R_EDX, FRm|0x01 );
51.563 - MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
51.564 - JMP_TARGET(end);
51.565 - }
51.566 + JMP_rel8(end);
51.567 +
51.568 + JMP_TARGET(doublesize);
51.569 + load_dr0( R_ECX, FRm );
51.570 + load_dr1( R_EDX, FRm );
51.571 + MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
51.572 + JMP_TARGET(end);
51.573 +
51.574 sh4_x86.tstate = TSTATE_NONE;
51.575 :}
51.576 FMOV @(R0, Rm), FRn {:
51.577 @@ -1945,38 +1809,27 @@
51.578 MMU_TRANSLATE_READ( R_EAX );
51.579 load_spreg( R_EDX, R_FPSCR );
51.580 TEST_imm32_r32( FPSCR_SZ, R_EDX );
51.581 - JNE_rel8(8 + MEM_READ_SIZE, doublesize);
51.582 + JNE_rel8(doublesize);
51.583 +
51.584 MEM_READ_LONG( R_EAX, R_EAX );
51.585 - load_fr_bank( R_EDX );
51.586 - store_fr( R_EDX, R_EAX, FRn );
51.587 - if( FRn&1 ) {
51.588 - JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end);
51.589 - JMP_TARGET(doublesize);
51.590 - MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
51.591 - load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
51.592 - load_xf_bank( R_EDX );
51.593 - store_fr( R_EDX, R_ECX, FRn&0x0E );
51.594 - store_fr( R_EDX, R_EAX, FRn|0x01 );
51.595 - JMP_TARGET(end);
51.596 - } else {
51.597 - JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end);
51.598 - JMP_TARGET(doublesize);
51.599 - MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
51.600 - load_fr_bank( R_EDX );
51.601 - store_fr( R_EDX, R_ECX, FRn&0x0E );
51.602 - store_fr( R_EDX, R_EAX, FRn|0x01 );
51.603 - JMP_TARGET(end);
51.604 - }
51.605 + store_fr( R_EAX, FRn );
51.606 + JMP_rel8(end);
51.607 +
51.608 + JMP_TARGET(doublesize);
51.609 + MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
51.610 + store_dr0( R_ECX, FRn );
51.611 + store_dr1( R_EAX, FRn );
51.612 + JMP_TARGET(end);
51.613 +
51.614 sh4_x86.tstate = TSTATE_NONE;
51.615 :}
51.616 FLDI0 FRn {: /* IFF PR=0 */
51.617 check_fpuen();
51.618 load_spreg( R_ECX, R_FPSCR );
51.619 TEST_imm32_r32( FPSCR_PR, R_ECX );
51.620 - JNE_rel8(8, end);
51.621 + JNE_rel8(end);
51.622 XOR_r32_r32( R_EAX, R_EAX );
51.623 - load_spreg( R_ECX, REG_OFFSET(fr_bank) );
51.624 - store_fr( R_ECX, R_EAX, FRn );
51.625 + store_fr( R_EAX, FRn );
51.626 JMP_TARGET(end);
51.627 sh4_x86.tstate = TSTATE_NONE;
51.628 :}
51.629 @@ -1984,10 +1837,9 @@
51.630 check_fpuen();
51.631 load_spreg( R_ECX, R_FPSCR );
51.632 TEST_imm32_r32( FPSCR_PR, R_ECX );
51.633 - JNE_rel8(11, end);
51.634 + JNE_rel8(end);
51.635 load_imm32(R_EAX, 0x3F800000);
51.636 - load_spreg( R_ECX, REG_OFFSET(fr_bank) );
51.637 - store_fr( R_ECX, R_EAX, FRn );
51.638 + store_fr( R_EAX, FRn );
51.639 JMP_TARGET(end);
51.640 sh4_x86.tstate = TSTATE_NONE;
51.641 :}
51.642 @@ -1995,43 +1847,41 @@
51.643 FLOAT FPUL, FRn {:
51.644 check_fpuen();
51.645 load_spreg( R_ECX, R_FPSCR );
51.646 - load_spreg(R_EDX, REG_OFFSET(fr_bank));
51.647 FILD_sh4r(R_FPUL);
51.648 TEST_imm32_r32( FPSCR_PR, R_ECX );
51.649 - JNE_rel8(5, doubleprec);
51.650 - pop_fr( R_EDX, FRn );
51.651 - JMP_rel8(3, end);
51.652 + JNE_rel8(doubleprec);
51.653 + pop_fr( FRn );
51.654 + JMP_rel8(end);
51.655 JMP_TARGET(doubleprec);
51.656 - pop_dr( R_EDX, FRn );
51.657 + pop_dr( FRn );
51.658 JMP_TARGET(end);
51.659 sh4_x86.tstate = TSTATE_NONE;
51.660 :}
51.661 FTRC FRm, FPUL {:
51.662 check_fpuen();
51.663 load_spreg( R_ECX, R_FPSCR );
51.664 - load_fr_bank( R_EDX );
51.665 TEST_imm32_r32( FPSCR_PR, R_ECX );
51.666 - JNE_rel8(5, doubleprec);
51.667 - push_fr( R_EDX, FRm );
51.668 - JMP_rel8(3, doop);
51.669 + JNE_rel8(doubleprec);
51.670 + push_fr( FRm );
51.671 + JMP_rel8(doop);
51.672 JMP_TARGET(doubleprec);
51.673 - push_dr( R_EDX, FRm );
51.674 + push_dr( FRm );
51.675 JMP_TARGET( doop );
51.676 load_imm32( R_ECX, (uint32_t)&max_int );
51.677 FILD_r32ind( R_ECX );
51.678 FCOMIP_st(1);
51.679 - JNA_rel8( 32, sat );
51.680 + JNA_rel8( sat );
51.681 load_imm32( R_ECX, (uint32_t)&min_int ); // 5
51.682 FILD_r32ind( R_ECX ); // 2
51.683 FCOMIP_st(1); // 2
51.684 - JAE_rel8( 21, sat2 ); // 2
51.685 + JAE_rel8( sat2 ); // 2
51.686 load_imm32( R_EAX, (uint32_t)&save_fcw );
51.687 FNSTCW_r32ind( R_EAX );
51.688 load_imm32( R_EDX, (uint32_t)&trunc_fcw );
51.689 FLDCW_r32ind( R_EDX );
51.690 FISTP_sh4r(R_FPUL); // 3
51.691 FLDCW_r32ind( R_EAX );
51.692 - JMP_rel8( 9, end ); // 2
51.693 + JMP_rel8(end); // 2
51.694
51.695 JMP_TARGET(sat);
51.696 JMP_TARGET(sat2);
51.697 @@ -2043,25 +1893,22 @@
51.698 :}
51.699 FLDS FRm, FPUL {:
51.700 check_fpuen();
51.701 - load_fr_bank( R_ECX );
51.702 - load_fr( R_ECX, R_EAX, FRm );
51.703 + load_fr( R_EAX, FRm );
51.704 store_spreg( R_EAX, R_FPUL );
51.705 sh4_x86.tstate = TSTATE_NONE;
51.706 :}
51.707 FSTS FPUL, FRn {:
51.708 check_fpuen();
51.709 - load_fr_bank( R_ECX );
51.710 load_spreg( R_EAX, R_FPUL );
51.711 - store_fr( R_ECX, R_EAX, FRn );
51.712 + store_fr( R_EAX, FRn );
51.713 sh4_x86.tstate = TSTATE_NONE;
51.714 :}
51.715 FCNVDS FRm, FPUL {:
51.716 check_fpuen();
51.717 load_spreg( R_ECX, R_FPSCR );
51.718 TEST_imm32_r32( FPSCR_PR, R_ECX );
51.719 - JE_rel8(9, end); // only when PR=1
51.720 - load_fr_bank( R_ECX );
51.721 - push_dr( R_ECX, FRm );
51.722 + JE_rel8(end); // only when PR=1
51.723 + push_dr( FRm );
51.724 pop_fpul();
51.725 JMP_TARGET(end);
51.726 sh4_x86.tstate = TSTATE_NONE;
51.727 @@ -2070,10 +1917,9 @@
51.728 check_fpuen();
51.729 load_spreg( R_ECX, R_FPSCR );
51.730 TEST_imm32_r32( FPSCR_PR, R_ECX );
51.731 - JE_rel8(9, end); // only when PR=1
51.732 - load_fr_bank( R_ECX );
51.733 + JE_rel8(end); // only when PR=1
51.734 push_fpul();
51.735 - pop_dr( R_ECX, FRn );
51.736 + pop_dr( FRn );
51.737 JMP_TARGET(end);
51.738 sh4_x86.tstate = TSTATE_NONE;
51.739 :}
51.740 @@ -2082,17 +1928,16 @@
51.741 FABS FRn {:
51.742 check_fpuen();
51.743 load_spreg( R_ECX, R_FPSCR );
51.744 - load_fr_bank( R_EDX );
51.745 TEST_imm32_r32( FPSCR_PR, R_ECX );
51.746 - JNE_rel8(10, doubleprec);
51.747 - push_fr(R_EDX, FRn); // 3
51.748 + JNE_rel8(doubleprec);
51.749 + push_fr(FRn); // 6
51.750 FABS_st0(); // 2
51.751 - pop_fr( R_EDX, FRn); //3
51.752 - JMP_rel8(8,end); // 2
51.753 + pop_fr(FRn); //6
51.754 + JMP_rel8(end); // 2
51.755 JMP_TARGET(doubleprec);
51.756 - push_dr(R_EDX, FRn);
51.757 + push_dr(FRn);
51.758 FABS_st0();
51.759 - pop_dr(R_EDX, FRn);
51.760 + pop_dr(FRn);
51.761 JMP_TARGET(end);
51.762 sh4_x86.tstate = TSTATE_NONE;
51.763 :}
51.764 @@ -2100,18 +1945,17 @@
51.765 check_fpuen();
51.766 load_spreg( R_ECX, R_FPSCR );
51.767 TEST_imm32_r32( FPSCR_PR, R_ECX );
51.768 - load_fr_bank( R_EDX );
51.769 - JNE_rel8(13,doubleprec);
51.770 - push_fr(R_EDX, FRm);
51.771 - push_fr(R_EDX, FRn);
51.772 + JNE_rel8(doubleprec);
51.773 + push_fr(FRm);
51.774 + push_fr(FRn);
51.775 FADDP_st(1);
51.776 - pop_fr(R_EDX, FRn);
51.777 - JMP_rel8(11,end);
51.778 + pop_fr(FRn);
51.779 + JMP_rel8(end);
51.780 JMP_TARGET(doubleprec);
51.781 - push_dr(R_EDX, FRm);
51.782 - push_dr(R_EDX, FRn);
51.783 + push_dr(FRm);
51.784 + push_dr(FRn);
51.785 FADDP_st(1);
51.786 - pop_dr(R_EDX, FRn);
51.787 + pop_dr(FRn);
51.788 JMP_TARGET(end);
51.789 sh4_x86.tstate = TSTATE_NONE;
51.790 :}
51.791 @@ -2119,41 +1963,39 @@
51.792 check_fpuen();
51.793 load_spreg( R_ECX, R_FPSCR );
51.794 TEST_imm32_r32( FPSCR_PR, R_ECX );
51.795 - load_fr_bank( R_EDX );
51.796 - JNE_rel8(13, doubleprec);
51.797 - push_fr(R_EDX, FRn);
51.798 - push_fr(R_EDX, FRm);
51.799 + JNE_rel8(doubleprec);
51.800 + push_fr(FRn);
51.801 + push_fr(FRm);
51.802 FDIVP_st(1);
51.803 - pop_fr(R_EDX, FRn);
51.804 - JMP_rel8(11, end);
51.805 + pop_fr(FRn);
51.806 + JMP_rel8(end);
51.807 JMP_TARGET(doubleprec);
51.808 - push_dr(R_EDX, FRn);
51.809 - push_dr(R_EDX, FRm);
51.810 + push_dr(FRn);
51.811 + push_dr(FRm);
51.812 FDIVP_st(1);
51.813 - pop_dr(R_EDX, FRn);
51.814 + pop_dr(FRn);
51.815 JMP_TARGET(end);
51.816 sh4_x86.tstate = TSTATE_NONE;
51.817 :}
51.818 FMAC FR0, FRm, FRn {:
51.819 check_fpuen();
51.820 load_spreg( R_ECX, R_FPSCR );
51.821 - load_spreg( R_EDX, REG_OFFSET(fr_bank));
51.822 TEST_imm32_r32( FPSCR_PR, R_ECX );
51.823 - JNE_rel8(18, doubleprec);
51.824 - push_fr( R_EDX, 0 );
51.825 - push_fr( R_EDX, FRm );
51.826 + JNE_rel8(doubleprec);
51.827 + push_fr( 0 );
51.828 + push_fr( FRm );
51.829 FMULP_st(1);
51.830 - push_fr( R_EDX, FRn );
51.831 + push_fr( FRn );
51.832 FADDP_st(1);
51.833 - pop_fr( R_EDX, FRn );
51.834 - JMP_rel8(16, end);
51.835 + pop_fr( FRn );
51.836 + JMP_rel8(end);
51.837 JMP_TARGET(doubleprec);
51.838 - push_dr( R_EDX, 0 );
51.839 - push_dr( R_EDX, FRm );
51.840 + push_dr( 0 );
51.841 + push_dr( FRm );
51.842 FMULP_st(1);
51.843 - push_dr( R_EDX, FRn );
51.844 + push_dr( FRn );
51.845 FADDP_st(1);
51.846 - pop_dr( R_EDX, FRn );
51.847 + pop_dr( FRn );
51.848 JMP_TARGET(end);
51.849 sh4_x86.tstate = TSTATE_NONE;
51.850 :}
51.851 @@ -2162,18 +2004,17 @@
51.852 check_fpuen();
51.853 load_spreg( R_ECX, R_FPSCR );
51.854 TEST_imm32_r32( FPSCR_PR, R_ECX );
51.855 - load_fr_bank( R_EDX );
51.856 - JNE_rel8(13, doubleprec);
51.857 - push_fr(R_EDX, FRm);
51.858 - push_fr(R_EDX, FRn);
51.859 + JNE_rel8(doubleprec);
51.860 + push_fr(FRm);
51.861 + push_fr(FRn);
51.862 FMULP_st(1);
51.863 - pop_fr(R_EDX, FRn);
51.864 - JMP_rel8(11, end);
51.865 + pop_fr(FRn);
51.866 + JMP_rel8(end);
51.867 JMP_TARGET(doubleprec);
51.868 - push_dr(R_EDX, FRm);
51.869 - push_dr(R_EDX, FRn);
51.870 + push_dr(FRm);
51.871 + push_dr(FRn);
51.872 FMULP_st(1);
51.873 - pop_dr(R_EDX, FRn);
51.874 + pop_dr(FRn);
51.875 JMP_TARGET(end);
51.876 sh4_x86.tstate = TSTATE_NONE;
51.877 :}
51.878 @@ -2181,16 +2022,15 @@
51.879 check_fpuen();
51.880 load_spreg( R_ECX, R_FPSCR );
51.881 TEST_imm32_r32( FPSCR_PR, R_ECX );
51.882 - load_fr_bank( R_EDX );
51.883 - JNE_rel8(10, doubleprec);
51.884 - push_fr(R_EDX, FRn);
51.885 + JNE_rel8(doubleprec);
51.886 + push_fr(FRn);
51.887 FCHS_st0();
51.888 - pop_fr(R_EDX, FRn);
51.889 - JMP_rel8(8, end);
51.890 + pop_fr(FRn);
51.891 + JMP_rel8(end);
51.892 JMP_TARGET(doubleprec);
51.893 - push_dr(R_EDX, FRn);
51.894 + push_dr(FRn);
51.895 FCHS_st0();
51.896 - pop_dr(R_EDX, FRn);
51.897 + pop_dr(FRn);
51.898 JMP_TARGET(end);
51.899 sh4_x86.tstate = TSTATE_NONE;
51.900 :}
51.901 @@ -2198,13 +2038,12 @@
51.902 check_fpuen();
51.903 load_spreg( R_ECX, R_FPSCR );
51.904 TEST_imm32_r32( FPSCR_PR, R_ECX );
51.905 - load_fr_bank( R_EDX );
51.906 - JNE_rel8(12, end); // PR=0 only
51.907 + JNE_rel8(end); // PR=0 only
51.908 FLD1_st0();
51.909 - push_fr(R_EDX, FRn);
51.910 + push_fr(FRn);
51.911 FSQRT_st0();
51.912 FDIVP_st(1);
51.913 - pop_fr(R_EDX, FRn);
51.914 + pop_fr(FRn);
51.915 JMP_TARGET(end);
51.916 sh4_x86.tstate = TSTATE_NONE;
51.917 :}
51.918 @@ -2212,16 +2051,15 @@
51.919 check_fpuen();
51.920 load_spreg( R_ECX, R_FPSCR );
51.921 TEST_imm32_r32( FPSCR_PR, R_ECX );
51.922 - load_fr_bank( R_EDX );
51.923 - JNE_rel8(10, doubleprec);
51.924 - push_fr(R_EDX, FRn);
51.925 + JNE_rel8(doubleprec);
51.926 + push_fr(FRn);
51.927 FSQRT_st0();
51.928 - pop_fr(R_EDX, FRn);
51.929 - JMP_rel8(8, end);
51.930 + pop_fr(FRn);
51.931 + JMP_rel8(end);
51.932 JMP_TARGET(doubleprec);
51.933 - push_dr(R_EDX, FRn);
51.934 + push_dr(FRn);
51.935 FSQRT_st0();
51.936 - pop_dr(R_EDX, FRn);
51.937 + pop_dr(FRn);
51.938 JMP_TARGET(end);
51.939 sh4_x86.tstate = TSTATE_NONE;
51.940 :}
51.941 @@ -2229,18 +2067,17 @@
51.942 check_fpuen();
51.943 load_spreg( R_ECX, R_FPSCR );
51.944 TEST_imm32_r32( FPSCR_PR, R_ECX );
51.945 - load_fr_bank( R_EDX );
51.946 - JNE_rel8(13, doubleprec);
51.947 - push_fr(R_EDX, FRn);
51.948 - push_fr(R_EDX, FRm);
51.949 + JNE_rel8(doubleprec);
51.950 + push_fr(FRn);
51.951 + push_fr(FRm);
51.952 FSUBP_st(1);
51.953 - pop_fr(R_EDX, FRn);
51.954 - JMP_rel8(11, end);
51.955 + pop_fr(FRn);
51.956 + JMP_rel8(end);
51.957 JMP_TARGET(doubleprec);
51.958 - push_dr(R_EDX, FRn);
51.959 - push_dr(R_EDX, FRm);
51.960 + push_dr(FRn);
51.961 + push_dr(FRm);
51.962 FSUBP_st(1);
51.963 - pop_dr(R_EDX, FRn);
51.964 + pop_dr(FRn);
51.965 JMP_TARGET(end);
51.966 sh4_x86.tstate = TSTATE_NONE;
51.967 :}
51.968 @@ -2249,14 +2086,13 @@
51.969 check_fpuen();
51.970 load_spreg( R_ECX, R_FPSCR );
51.971 TEST_imm32_r32( FPSCR_PR, R_ECX );
51.972 - load_fr_bank( R_EDX );
51.973 - JNE_rel8(8, doubleprec);
51.974 - push_fr(R_EDX, FRm);
51.975 - push_fr(R_EDX, FRn);
51.976 - JMP_rel8(6, end);
51.977 + JNE_rel8(doubleprec);
51.978 + push_fr(FRm);
51.979 + push_fr(FRn);
51.980 + JMP_rel8(end);
51.981 JMP_TARGET(doubleprec);
51.982 - push_dr(R_EDX, FRm);
51.983 - push_dr(R_EDX, FRn);
51.984 + push_dr(FRm);
51.985 + push_dr(FRn);
51.986 JMP_TARGET(end);
51.987 FCOMIP_st(1);
51.988 SETE_t();
51.989 @@ -2267,14 +2103,13 @@
51.990 check_fpuen();
51.991 load_spreg( R_ECX, R_FPSCR );
51.992 TEST_imm32_r32( FPSCR_PR, R_ECX );
51.993 - load_fr_bank( R_EDX );
51.994 - JNE_rel8(8, doubleprec);
51.995 - push_fr(R_EDX, FRm);
51.996 - push_fr(R_EDX, FRn);
51.997 - JMP_rel8(6, end);
51.998 + JNE_rel8(doubleprec);
51.999 + push_fr(FRm);
51.1000 + push_fr(FRn);
51.1001 + JMP_rel8(end);
51.1002 JMP_TARGET(doubleprec);
51.1003 - push_dr(R_EDX, FRm);
51.1004 - push_dr(R_EDX, FRn);
51.1005 + push_dr(FRm);
51.1006 + push_dr(FRn);
51.1007 JMP_TARGET(end);
51.1008 FCOMIP_st(1);
51.1009 SETA_t();
51.1010 @@ -2286,9 +2121,8 @@
51.1011 check_fpuen();
51.1012 load_spreg( R_ECX, R_FPSCR );
51.1013 TEST_imm32_r32( FPSCR_PR, R_ECX );
51.1014 - JNE_rel8( CALL_FUNC2_SIZE + 9, doubleprec );
51.1015 - load_fr_bank( R_ECX );
51.1016 - ADD_imm8s_r32( (FRn&0x0E)<<2, R_ECX );
51.1017 + JNE_rel8(doubleprec );
51.1018 + LEA_sh4r_r32( REG_OFFSET(fr[0][FRn&0x0E]), R_ECX );
51.1019 load_spreg( R_EDX, R_FPUL );
51.1020 call_func2( sh4_fsca, R_EDX, R_ECX );
51.1021 JMP_TARGET(doubleprec);
51.1022 @@ -2298,25 +2132,24 @@
51.1023 check_fpuen();
51.1024 load_spreg( R_ECX, R_FPSCR );
51.1025 TEST_imm32_r32( FPSCR_PR, R_ECX );
51.1026 - JNE_rel8(44, doubleprec);
51.1027 + JNE_rel8( doubleprec);
51.1028
51.1029 - load_fr_bank( R_ECX );
51.1030 - push_fr( R_ECX, FVm<<2 );
51.1031 - push_fr( R_ECX, FVn<<2 );
51.1032 + push_fr( FVm<<2 );
51.1033 + push_fr( FVn<<2 );
51.1034 FMULP_st(1);
51.1035 - push_fr( R_ECX, (FVm<<2)+1);
51.1036 - push_fr( R_ECX, (FVn<<2)+1);
51.1037 + push_fr( (FVm<<2)+1);
51.1038 + push_fr( (FVn<<2)+1);
51.1039 FMULP_st(1);
51.1040 FADDP_st(1);
51.1041 - push_fr( R_ECX, (FVm<<2)+2);
51.1042 - push_fr( R_ECX, (FVn<<2)+2);
51.1043 + push_fr( (FVm<<2)+2);
51.1044 + push_fr( (FVn<<2)+2);
51.1045 FMULP_st(1);
51.1046 FADDP_st(1);
51.1047 - push_fr( R_ECX, (FVm<<2)+3);
51.1048 - push_fr( R_ECX, (FVn<<2)+3);
51.1049 + push_fr( (FVm<<2)+3);
51.1050 + push_fr( (FVn<<2)+3);
51.1051 FMULP_st(1);
51.1052 FADDP_st(1);
51.1053 - pop_fr( R_ECX, (FVn<<2)+3);
51.1054 + pop_fr( (FVn<<2)+3);
51.1055 JMP_TARGET(doubleprec);
51.1056 sh4_x86.tstate = TSTATE_NONE;
51.1057 :}
51.1058 @@ -2324,11 +2157,9 @@
51.1059 check_fpuen();
51.1060 load_spreg( R_ECX, R_FPSCR );
51.1061 TEST_imm32_r32( FPSCR_PR, R_ECX );
51.1062 - JNE_rel8( 18 + CALL_FUNC2_SIZE, doubleprec );
51.1063 - load_fr_bank( R_EDX ); // 3
51.1064 - ADD_imm8s_r32( FVn<<4, R_EDX ); // 3
51.1065 - load_xf_bank( R_ECX ); // 12
51.1066 - call_func2( sh4_ftrv, R_EDX, R_ECX ); // 12
51.1067 + JNE_rel8( doubleprec );
51.1068 + LEA_sh4r_r32( REG_OFFSET(fr[0][FVn<<2]), R_EDX );
51.1069 + call_func1( sh4_ftrv, R_EDX ); // 12
51.1070 JMP_TARGET(doubleprec);
51.1071 sh4_x86.tstate = TSTATE_NONE;
51.1072 :}
51.1073 @@ -2338,7 +2169,7 @@
51.1074 load_spreg( R_ECX, R_FPSCR );
51.1075 XOR_imm32_r32( FPSCR_FR, R_ECX );
51.1076 store_spreg( R_ECX, R_FPSCR );
51.1077 - update_fr_bank( R_ECX );
51.1078 + call_func0( sh4_switch_fr_banks );
51.1079 sh4_x86.tstate = TSTATE_NONE;
51.1080 :}
51.1081 FSCHG {:
51.1082 @@ -2490,8 +2321,7 @@
51.1083 LDS Rm, FPSCR {:
51.1084 check_fpuen();
51.1085 load_reg( R_EAX, Rm );
51.1086 - store_spreg( R_EAX, R_FPSCR );
51.1087 - update_fr_bank( R_EAX );
51.1088 + call_func1( sh4_write_fpscr, R_EAX );
51.1089 sh4_x86.tstate = TSTATE_NONE;
51.1090 :}
51.1091 LDS.L @Rm+, FPSCR {:
51.1092 @@ -2501,8 +2331,7 @@
51.1093 MMU_TRANSLATE_READ( R_EAX );
51.1094 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
51.1095 MEM_READ_LONG( R_EAX, R_EAX );
51.1096 - store_spreg( R_EAX, R_FPSCR );
51.1097 - update_fr_bank( R_EAX );
51.1098 + call_func1( sh4_write_fpscr, R_EAX );
51.1099 sh4_x86.tstate = TSTATE_NONE;
51.1100 :}
51.1101 LDS Rm, FPUL {:
51.1102 @@ -2570,7 +2399,7 @@
51.1103 MOV_r32_r32( R_EAX, R_ECX );
51.1104 AND_imm32_r32( 0xFC000000, R_EAX );
51.1105 CMP_imm32_r32( 0xE0000000, R_EAX );
51.1106 - JNE_rel8(8+CALL_FUNC1_SIZE, end);
51.1107 + JNE_rel8(end);
51.1108 call_func1( sh4_flush_store_queue, R_ECX );
51.1109 TEST_r32_r32( R_EAX, R_EAX );
51.1110 JE_exc(-1);
52.1 --- a/src/sh4/x86op.h Sun Apr 20 05:30:07 2008 +0000
52.2 +++ b/src/sh4/x86op.h Mon May 12 10:00:13 2008 +0000
52.3 @@ -38,17 +38,9 @@
52.4 #define R_DH 6
52.5 #define R_BH 7
52.6
52.7 -#ifdef DEBUG_JUMPS
52.8 -#define MARK_JMP(n,x) uint8_t *_mark_jmp_##x = xlat_output + n
52.9 -#define JMP_TARGET(x) assert( _mark_jmp_##x == xlat_output )
52.10 -#else
52.11 -#define MARK_JMP(n, x)
52.12 -#define JMP_TARGET(x)
52.13 -#endif
52.14 -
52.15 -
52.16 -
52.17 -
52.18 +#define MARK_JMP8(x) uint8_t *_mark_jmp_##x = xlat_output
52.19 +#define MARK_JMP32(x) uint32_t *_mark_jmp_##x = (uint32_t *)xlat_output
52.20 +#define JMP_TARGET(x) *_mark_jmp_##x += (xlat_output - _mark_jmp_##x)
52.21
52.22 #define OP(x) *xlat_output++ = (x)
52.23 #define OP32(x) *((uint32_t *)xlat_output) = (x); xlat_output+=4
52.24 @@ -90,7 +82,7 @@
52.25
52.26
52.27 /* Offset of a reg relative to the sh4r structure */
52.28 -#define REG_OFFSET(reg) (((char *)&sh4r.reg) - ((char *)&sh4r))
52.29 +#define REG_OFFSET(reg) (((char *)&sh4r.reg) - ((char *)&sh4r) - 128)
52.30
52.31 #define R_T REG_OFFSET(t)
52.32 #define R_Q REG_OFFSET(q)
52.33 @@ -155,7 +147,8 @@
52.34 #define DEC_r32(r1) OP(0x48+r1)
52.35 #define IMUL_r32(r1) OP(0xF7); MODRM_rm32_r32(r1,5)
52.36 #define INC_r32(r1) OP(0x40+r1)
52.37 -#define JMP_rel8(rel, label) OP(0xEB); OP(rel); MARK_JMP(rel,label)
52.38 +#define JMP_rel8(label) OP(0xEB); MARK_JMP8(label); OP(-1);
52.39 +#define LEA_sh4r_r32(disp,r1) OP(0x8D); MODRM_r32_sh4r(r1,disp)
52.40 #define MOV_r32_r32(r1,r2) OP(0x89); MODRM_r32_rm32(r1,r2)
52.41 #define MOV_r32_sh4r(r1,disp) OP(0x89); MODRM_r32_sh4r(r1,disp)
52.42 #define MOV_moff32_EAX(off) OP(0xA1); OPPTR(off)
52.43 @@ -209,35 +202,44 @@
52.44 #define FCHS_st0() OP(0xD9); OP(0xE0)
52.45 #define FCOMIP_st(st) OP(0xDF); OP(0xF0+st)
52.46 #define FDIVP_st(st) OP(0xDE); OP(0xF8+st)
52.47 -#define FILD_sh4r(disp) OP(0xDB); MODRM_r32_sh4r(0, disp)
52.48 #define FILD_r32ind(r32) OP(0xDB); OP(0x00+r32)
52.49 -#define FISTP_sh4r(disp) OP(0xDB); MODRM_r32_sh4r(3, disp)
52.50 #define FLD0_st0() OP(0xD9); OP(0xEE);
52.51 #define FLD1_st0() OP(0xD9); OP(0xE8);
52.52 +#define FLDf_sh4r(disp) OP(0xD9); MODRM_r32_sh4r(0, disp)
52.53 +#define FLDd_sh4r(disp) OP(0xDD); MODRM_r32_sh4r(0, disp)
52.54 #define FLDCW_r32ind(r32) OP(0xD9); OP(0x28+r32)
52.55 #define FMULP_st(st) OP(0xDE); OP(0xC8+st)
52.56 #define FNSTCW_r32ind(r32) OP(0xD9); OP(0x38+r32)
52.57 #define FPOP_st() OP(0xDD); OP(0xC0); OP(0xD9); OP(0xF7)
52.58 +#define FSTPf_sh4r(disp) OP(0xD9); MODRM_r32_sh4r(3, disp)
52.59 +#define FSTPd_sh4r(disp) OP(0xDD); MODRM_r32_sh4r(3, disp)
52.60 #define FSUBP_st(st) OP(0xDE); OP(0xE8+st)
52.61 #define FSQRT_st0() OP(0xD9); OP(0xFA)
52.62
52.63 +#define FILD_sh4r(disp) OP(0xDB); MODRM_r32_sh4r(0, disp)
52.64 +#define FLDF_sh4r(disp) OP(0xD9); MODRM_r32_sh4r(0, disp)
52.65 +#define FLDD_sh4r(disp) OP(0xDD); MODRM_r32_sh4r(0, disp)
52.66 +#define FISTP_sh4r(disp) OP(0xDB); MODRM_r32_sh4r(3, disp)
52.67 +#define FSTPF_sh4r(disp) OP(0xD9); MODRM_r32_sh4r(3,disp)
52.68 +#define FSTPD_sh4r(disp) OP(0xDD); MODRM_r32_sh4r(3,disp)
52.69 +
52.70 /* Conditional branches */
52.71 -#define JE_rel8(rel,label) OP(0x74); OP(rel); MARK_JMP(rel,label)
52.72 -#define JA_rel8(rel,label) OP(0x77); OP(rel); MARK_JMP(rel,label)
52.73 -#define JAE_rel8(rel,label) OP(0x73); OP(rel); MARK_JMP(rel,label)
52.74 -#define JG_rel8(rel,label) OP(0x7F); OP(rel); MARK_JMP(rel,label)
52.75 -#define JGE_rel8(rel,label) OP(0x7D); OP(rel); MARK_JMP(rel,label)
52.76 -#define JC_rel8(rel,label) OP(0x72); OP(rel); MARK_JMP(rel,label)
52.77 -#define JO_rel8(rel,label) OP(0x70); OP(rel); MARK_JMP(rel,label)
52.78 -#define JNE_rel8(rel,label) OP(0x75); OP(rel); MARK_JMP(rel,label)
52.79 -#define JNA_rel8(rel,label) OP(0x76); OP(rel); MARK_JMP(rel,label)
52.80 -#define JNAE_rel8(rel,label) OP(0x72); OP(rel); MARK_JMP(rel,label)
52.81 -#define JNG_rel8(rel,label) OP(0x7E); OP(rel); MARK_JMP(rel,label)
52.82 -#define JNGE_rel8(rel,label) OP(0x7C); OP(rel); MARK_JMP(rel,label)
52.83 -#define JNC_rel8(rel,label) OP(0x73); OP(rel); MARK_JMP(rel,label)
52.84 -#define JNO_rel8(rel,label) OP(0x71); OP(rel); MARK_JMP(rel,label)
52.85 -#define JNS_rel8(rel,label) OP(0x79); OP(rel); MARK_JMP(rel,label)
52.86 -#define JS_rel8(rel,label) OP(0x78); OP(rel); MARK_JMP(rel,label)
52.87 +#define JE_rel8(label) OP(0x74); MARK_JMP8(label); OP(-1)
52.88 +#define JA_rel8(label) OP(0x77); MARK_JMP8(label); OP(-1)
52.89 +#define JAE_rel8(label) OP(0x73); MARK_JMP8(label); OP(-1)
52.90 +#define JG_rel8(label) OP(0x7F); MARK_JMP8(label); OP(-1)
52.91 +#define JGE_rel8(label) OP(0x7D); MARK_JMP8(label); OP(-1)
52.92 +#define JC_rel8(label) OP(0x72); MARK_JMP8(label); OP(-1)
52.93 +#define JO_rel8(label) OP(0x70); MARK_JMP8(label); OP(-1)
52.94 +#define JNE_rel8(label) OP(0x75); MARK_JMP8(label); OP(-1)
52.95 +#define JNA_rel8(label) OP(0x76); MARK_JMP8(label); OP(-1)
52.96 +#define JNAE_rel8(label) OP(0x72); MARK_JMP8(label); OP(-1)
52.97 +#define JNG_rel8(label) OP(0x7E); MARK_JMP8(label); OP(-1)
52.98 +#define JNGE_rel8(label) OP(0x7C); MARK_JMP8(label); OP(-1)
52.99 +#define JNC_rel8(label) OP(0x73); MARK_JMP8(label); OP(-1)
52.100 +#define JNO_rel8(label) OP(0x71); MARK_JMP8(label); OP(-1)
52.101 +#define JNS_rel8(label) OP(0x79); MARK_JMP8(label); OP(-1)
52.102 +#define JS_rel8(label) OP(0x78); MARK_JMP8(label); OP(-1)
52.103
52.104 /** JMP relative 8 or 32 depending on size of rel. rel offset
52.105 * from the start of the instruction (not end)
53.1 --- a/src/syscall.c Sun Apr 20 05:30:07 2008 +0000
53.2 +++ b/src/syscall.c Mon May 12 10:00:13 2008 +0000
53.3 @@ -16,7 +16,7 @@
53.4 * GNU General Public License for more details.
53.5 */
53.6
53.7 -#include "dream.h"
53.8 +#include "lxdream.h"
53.9 #include "mem.h"
53.10 #include "syscall.h"
53.11 #include "sh4/sh4.h"
53.12 @@ -42,7 +42,7 @@
53.13 hook_id &= 0xFF;
53.14 syscall_add_hook( hook_id, hook );
53.15 syscall_hooks[hook_id].vector = vector_addr;
53.16 - sh4_write_long( vector_addr, 0xFFFFFF00 + hook_id );
53.17 + mem_write_long( vector_addr, 0xFFFFFF00 + hook_id );
53.18 }
53.19
53.20 void syscall_invoke( uint32_t hook_id )
53.21 @@ -62,7 +62,7 @@
53.22 for( i=0; i<256; i++ ) {
53.23 if( syscall_hooks[i].hook != NULL &&
53.24 syscall_hooks[i].vector != 0 ) {
53.25 - sh4_write_long( syscall_hooks[i].vector, 0xFFFFFF00 + i );
53.26 + mem_write_long( syscall_hooks[i].vector, 0xFFFFFF00 + i );
53.27 }
53.28 }
53.29 }
54.1 --- a/src/test/testsh4x86.c Sun Apr 20 05:30:07 2008 +0000
54.2 +++ b/src/test/testsh4x86.c Mon May 12 10:00:13 2008 +0000
54.3 @@ -81,6 +81,8 @@
54.4 void sh4_write_byte( uint32_t addr, uint32_t val ) {}
54.5 void sh4_write_word( uint32_t addr, uint32_t val ) {}
54.6 void sh4_write_long( uint32_t addr, uint32_t val ) {}
54.7 +void sh4_write_fpscr( uint32_t val ) { }
54.8 +void sh4_switch_fr_banks() { }
54.9 void mem_copy_to_sh4( sh4addr_t addr, sh4ptr_t src, size_t size ) { }
54.10 void sh4_write_sr( uint32_t val ) { }
54.11 gboolean sh4_has_page( sh4vma_t vma ) { return TRUE; }
.