lxdream 0.9.1revision 750:af3b7e6c85ff
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raw | bz2 | zip | gz | changeset | 750:af3b7e6c85ff |
| parent | 749:f06c5a12903a |
| child | 751:5af50a1c4cf4 |
| author | nkeynes |
| date | Sat Jul 19 02:41:30 2008 +0000 (15 years ago) |
Remove built sources from SVN
| src/drivers/mac_keymap.h | view | annotate | diff | log | |
| src/pvr2/gl_slsrc.c | view | annotate | diff | log | |
| src/sh4/sh4core.c | view | annotate | diff | log | |
| src/sh4/sh4dasm.c | view | annotate | diff | log | |
| src/sh4/sh4stat.c | view | annotate | diff | log | |
| src/sh4/sh4x86.c | view | annotate | diff | log |
1.1 --- a/src/drivers/mac_keymap.h Sat Jul 19 02:34:11 2008 +00001.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +00001.3 @@ -1,16 +0,0 @@1.4 -/**1.5 - * mac keyboard map autogenerated by genkeymap.pl1.6 - */1.7 -1.8 -const gchar *mac_keysyms_by_keycode[128] = { "a", "s", "d", "f", "h", "g", "z", "x", "c", "v", NULL, "b", "q", "w", "e", "r", "y", "t", "1", "2", "3", "4", "6", "5", "equal", "9", "7", "minus", "8", NULL, "bracketright", "o", "u", "bracketleft", "i", "p", "Return", "l", "j", "apostrophe", "k", "semicolon", "backslash", "comma", "slash", "n", "m", "period", "Tab", "space", "grave", "BackSpace", NULL, "Escape", "Meta_R", "Meta_L", "Shift_L", "Caps_Lock", "Alt_L", "Control_L", "Shift_R", "Alt_R", "Control_R", "Function", NULL, "KP_Delete", NULL, "KP_Multiply", NULL, "KP_Add", NULL, "Num_Lock", NULL, NULL, NULL, "KP_Divide", "KP_Enter", NULL, "KP_Subtract", NULL, NULL, "KP_Equal", "KP_Insert", "KP_End", "KP_Down", "KP_Page_Down", "KP_Left", "KP_Begin", "KP_Right", "KP_Home", NULL, "KP_Up", "KP_Page_Up", NULL, NULL, NULL, "F5", "F6", "F7", "F3", "F8", "F9", NULL, "F11", NULL, "F13", NULL, "F14", NULL, "F10", NULL, "F12", NULL, "F15", "Insert", "Home", "Page_Up", "Delete", "F4", "End", "F2", "Page_Down", "F1", "Left", "Right", "Down", "Up", "Power"};1.9 -1.10 -const uint16_t mac_keycode_to_dckeysym[128] = { DCKB_a, DCKB_s, DCKB_d, DCKB_f, DCKB_h, DCKB_g, DCKB_z, DCKB_x, DCKB_c, DCKB_v, DCKB_NONE, DCKB_b, DCKB_q, DCKB_w, DCKB_e, DCKB_r, DCKB_y, DCKB_t, DCKB_1, DCKB_2, DCKB_3, DCKB_4, DCKB_6, DCKB_5, DCKB_equal, DCKB_9, DCKB_7, DCKB_minus, DCKB_8, DCKB_NONE, DCKB_bracketright, DCKB_o, DCKB_u, DCKB_bracketleft, DCKB_i, DCKB_p, DCKB_Return, DCKB_l, DCKB_j, DCKB_apostrophe, DCKB_k, DCKB_semicolon, DCKB_backslash, DCKB_comma, DCKB_slash, DCKB_n, DCKB_m, DCKB_period, DCKB_Tab, DCKB_space, DCKB_grave, DCKB_BackSpace, DCKB_NONE, DCKB_Escape, DCKB_Meta_R, DCKB_Meta_L, DCKB_Shift_L, DCKB_Caps_Lock, DCKB_Alt_L, DCKB_Control_L, DCKB_Shift_R, DCKB_Alt_R, DCKB_Control_R, DCKB_NONE, DCKB_NONE, DCKB_KP_Delete, DCKB_NONE, DCKB_KP_Multiply, DCKB_NONE, DCKB_KP_Add, DCKB_NONE, DCKB_Num_Lock, DCKB_NONE, DCKB_NONE, DCKB_NONE, DCKB_KP_Divide, DCKB_KP_Enter, DCKB_NONE, DCKB_KP_Subtract, DCKB_NONE, DCKB_NONE, DCKB_NONE, DCKB_KP_Insert, DCKB_KP_End, DCKB_KP_Down, DCKB_KP_Page_Down, DCKB_KP_Left, DCKB_KP_Begin, DCKB_KP_Right, DCKB_KP_Home, DCKB_NONE, DCKB_KP_Up, DCKB_KP_Page_Up, DCKB_NONE, DCKB_NONE, DCKB_NONE, DCKB_F5, DCKB_F6, DCKB_F7, DCKB_F3, DCKB_F8, DCKB_F9, DCKB_NONE, DCKB_F11, DCKB_NONE, DCKB_NONE, DCKB_NONE, DCKB_NONE, DCKB_NONE, DCKB_F10, DCKB_NONE, DCKB_F12, DCKB_NONE, DCKB_NONE, DCKB_Insert, DCKB_Home, DCKB_Page_Up, DCKB_Delete, DCKB_F4, DCKB_End, DCKB_F2, DCKB_Page_Down, DCKB_F1, DCKB_Left, DCKB_Right, DCKB_Down, DCKB_Up, DCKB_NONE};1.11 -1.12 -#define mac_keysym_count 1061.13 -struct mac_keymap_struct {1.14 - const gchar *name;1.15 - uint16_t keycode;1.16 -};1.17 -1.18 -struct mac_keymap_struct mac_keysyms[] = { {"0", 29 }, {"1", 18 }, {"2", 19 }, {"3", 20 }, {"4", 21 }, {"5", 23 }, {"6", 22 }, {"7", 26 }, {"8", 28 }, {"9", 25 }, {"a", 0 }, {"Alt_L", 58 }, {"Alt_R", 61 }, {"apostrophe", 39 }, {"b", 11 }, {"backslash", 42 }, {"BackSpace", 51 }, {"bracketleft", 33 }, {"bracketright", 30 }, {"c", 8 }, {"Caps_Lock", 57 }, {"comma", 43 }, {"Control_L", 59 }, {"Control_R", 62 }, {"d", 2 }, {"Delete", 117 }, {"Down", 125 }, {"e", 14 }, {"End", 119 }, {"equal", 24 }, {"Escape", 53 }, {"f", 3 }, {"F1", 122 }, {"F10", 109 }, {"F11", 103 }, {"F12", 111 }, {"F13", 105 }, {"F14", 107 }, {"F15", 113 }, {"F2", 120 }, {"F3", 99 }, {"F4", 118 }, {"F5", 96 }, {"F6", 97 }, {"F7", 98 }, {"F8", 100 }, {"F9", 101 }, {"Function", 63 }, {"g", 5 }, {"grave", 50 }, {"h", 4 }, {"Home", 115 }, {"i", 34 }, {"Insert", 114 }, {"j", 38 }, {"k", 40 }, {"KP_Add", 69 }, {"KP_Begin", 87 }, {"KP_Delete", 65 }, {"KP_Divide", 75 }, {"KP_Down", 84 }, {"KP_End", 83 }, {"KP_Enter", 76 }, {"KP_Equal", 81 }, {"KP_Home", 89 }, {"KP_Insert", 82 }, {"KP_Left", 86 }, {"KP_Multiply", 67 }, {"KP_Page_Down", 85 }, {"KP_Page_Up", 92 }, {"KP_Right", 88 }, {"KP_Subtract", 78 }, {"KP_Up", 91 }, {"l", 37 }, {"Left", 123 }, {"m", 46 }, {"Meta_L", 55 }, {"Meta_R", 54 }, {"minus", 27 }, {"n", 45 }, {"Num_Lock", 71 }, {"o", 31 }, {"p", 35 }, {"Page_Down", 121 }, {"Page_Up", 116 }, {"period", 47 }, {"Power", 127 }, {"q", 12 }, {"r", 15 }, {"Return", 36 }, {"Right", 124 }, {"s", 1 }, {"semicolon", 41 }, {"Shift_L", 56 }, {"Shift_R", 60 }, {"slash", 44 }, {"space", 49 }, {"t", 17 }, {"Tab", 48 }, {"u", 32 }, {"Up", 126 }, {"v", 9 }, {"w", 13 }, {"x", 7 }, {"y", 16 }, {"z", 6 }, {NULL,-1} };1.19 -
2.1 --- a/src/pvr2/gl_slsrc.c Sat Jul 19 02:34:11 2008 +00002.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +00002.3 @@ -1,25 +0,0 @@2.4 -/**2.5 - * This file is automatically generated - do not edit2.6 - */2.7 -2.8 -const char *glsl_vertex_shader_src = "// Standard PVR2 vertex shader\n\2.9 -\n\2.10 -void main()\n\2.11 -{\n\2.12 - vec4 tmp = ftransform();\n\2.13 - float w = gl_Vertex.z;\n\2.14 - gl_Position = tmp * w;\n\2.15 - gl_FrontColor = gl_Color;\n\2.16 - gl_FrontSecondaryColor = gl_SecondaryColor;\n\2.17 - gl_TexCoord[0] = gl_MultiTexCoord0;\n\2.18 -}\n\2.19 -";2.20 -2.21 -const char *glsl_fragment_shader_src = "// Standard PVR2 fragment shader\n\2.22 -\n\2.23 -void main()\n\2.24 -{\n\2.25 - gl_FragColor = gl_Color;\n\2.26 - gl_FragDepth = gl_FragCoord.z;\n\2.27 -}";2.28 -
3.1 --- a/src/sh4/sh4core.c Sat Jul 19 02:34:11 2008 +00003.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +00003.3 @@ -1,2188 +0,0 @@3.4 -/**3.5 - * $Id$3.6 - *3.7 - * SH4 emulation core, and parent module for all the SH4 peripheral3.8 - * modules.3.9 - *3.10 - * Copyright (c) 2005 Nathan Keynes.3.11 - *3.12 - * This program is free software; you can redistribute it and/or modify3.13 - * it under the terms of the GNU General Public License as published by3.14 - * the Free Software Foundation; either version 2 of the License, or3.15 - * (at your option) any later version.3.16 - *3.17 - * This program is distributed in the hope that it will be useful,3.18 - * but WITHOUT ANY WARRANTY; without even the implied warranty of3.19 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the3.20 - * GNU General Public License for more details.3.21 - */3.22 -3.23 -#define MODULE sh4_module3.24 -#include <assert.h>3.25 -#include <math.h>3.26 -#include "dream.h"3.27 -#include "dreamcast.h"3.28 -#include "eventq.h"3.29 -#include "mem.h"3.30 -#include "clock.h"3.31 -#include "syscall.h"3.32 -#include "sh4/sh4core.h"3.33 -#include "sh4/sh4mmio.h"3.34 -#include "sh4/sh4stat.h"3.35 -#include "sh4/intc.h"3.36 -3.37 -#define SH4_CALLTRACE 13.38 -3.39 -#define MAX_INT 0x7FFFFFFF3.40 -#define MIN_INT 0x800000003.41 -#define MAX_INTF 2147483647.03.42 -#define MIN_INTF -2147483648.03.43 -3.44 -/********************** SH4 Module Definition ****************************/3.45 -3.46 -uint32_t sh4_emulate_run_slice( uint32_t nanosecs )3.47 -{3.48 - int i;3.49 -3.50 - if( sh4_breakpoint_count == 0 ) {3.51 - for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {3.52 - if( SH4_EVENT_PENDING() ) {3.53 - if( sh4r.event_types & PENDING_EVENT ) {3.54 - event_execute();3.55 - }3.56 - /* Eventq execute may (quite likely) deliver an immediate IRQ */3.57 - if( sh4r.event_types & PENDING_IRQ ) {3.58 - sh4_accept_interrupt();3.59 - }3.60 - }3.61 - if( !sh4_execute_instruction() ) {3.62 - break;3.63 - }3.64 - }3.65 - } else {3.66 - for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {3.67 - if( SH4_EVENT_PENDING() ) {3.68 - if( sh4r.event_types & PENDING_EVENT ) {3.69 - event_execute();3.70 - }3.71 - /* Eventq execute may (quite likely) deliver an immediate IRQ */3.72 - if( sh4r.event_types & PENDING_IRQ ) {3.73 - sh4_accept_interrupt();3.74 - }3.75 - }3.76 -3.77 - if( !sh4_execute_instruction() )3.78 - break;3.79 -#ifdef ENABLE_DEBUG_MODE3.80 - for( i=0; i<sh4_breakpoint_count; i++ ) {3.81 - if( sh4_breakpoints[i].address == sh4r.pc ) {3.82 - break;3.83 - }3.84 - }3.85 - if( i != sh4_breakpoint_count ) {3.86 - sh4_core_exit( CORE_EXIT_BREAKPOINT );3.87 - }3.88 -#endif3.89 - }3.90 - }3.91 -3.92 - /* If we aborted early, but the cpu is still technically running,3.93 - * we're doing a hard abort - cut the timeslice back to what we3.94 - * actually executed3.95 - */3.96 - if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {3.97 - nanosecs = sh4r.slice_cycle;3.98 - }3.99 - if( sh4r.sh4_state != SH4_STATE_STANDBY ) {3.100 - TMU_run_slice( nanosecs );3.101 - SCIF_run_slice( nanosecs );3.102 - }3.103 - return nanosecs;3.104 -}3.105 -3.106 -/********************** SH4 emulation core ****************************/3.107 -3.108 -#define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)3.109 -#define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); sh4_core_exit(CORE_EXIT_HALT); return FALSE; }while(0)3.110 -3.111 -#if(SH4_CALLTRACE == 1)3.112 -#define MAX_CALLSTACK 323.113 -static struct call_stack {3.114 - sh4addr_t call_addr;3.115 - sh4addr_t target_addr;3.116 - sh4addr_t stack_pointer;3.117 -} call_stack[MAX_CALLSTACK];3.118 -3.119 -static int call_stack_depth = 0;3.120 -int sh4_call_trace_on = 0;3.121 -3.122 -static inline void trace_call( sh4addr_t source, sh4addr_t dest )3.123 -{3.124 - if( call_stack_depth < MAX_CALLSTACK ) {3.125 - call_stack[call_stack_depth].call_addr = source;3.126 - call_stack[call_stack_depth].target_addr = dest;3.127 - call_stack[call_stack_depth].stack_pointer = sh4r.r[15];3.128 - }3.129 - call_stack_depth++;3.130 -}3.131 -3.132 -static inline void trace_return( sh4addr_t source, sh4addr_t dest )3.133 -{3.134 - if( call_stack_depth > 0 ) {3.135 - call_stack_depth--;3.136 - }3.137 -}3.138 -3.139 -void fprint_stack_trace( FILE *f )3.140 -{3.141 - int i = call_stack_depth -1;3.142 - if( i >= MAX_CALLSTACK )3.143 - i = MAX_CALLSTACK - 1;3.144 - for( ; i >= 0; i-- ) {3.145 - fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n",3.146 - (call_stack_depth - i), call_stack[i].call_addr,3.147 - call_stack[i].target_addr, call_stack[i].stack_pointer );3.148 - }3.149 -}3.150 -3.151 -#define TRACE_CALL( source, dest ) trace_call(source, dest)3.152 -#define TRACE_RETURN( source, dest ) trace_return(source, dest)3.153 -#else3.154 -#define TRACE_CALL( dest, rts )3.155 -#define TRACE_RETURN( source, dest )3.156 -#endif3.157 -3.158 -#define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )3.159 -#define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )3.160 -#define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )3.161 -#define CHECKRALIGN64(addr) if( (addr)&0x07 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )3.162 -#define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )3.163 -#define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )3.164 -#define CHECKWALIGN64(addr) if( (addr)&0x07 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )3.165 -3.166 -#define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }3.167 -#define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); sh4_core_exit(CORE_EXIT_HALT); return FALSE; }3.168 -#define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)3.169 -3.170 -#define MEM_READ_BYTE( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_byte(memtmp); }3.171 -#define MEM_READ_WORD( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_word(memtmp); }3.172 -#define MEM_READ_LONG( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_long(memtmp); }3.173 -#define MEM_WRITE_BYTE( addr, val ) memtmp = mmu_vma_to_phys_write(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { sh4_write_byte(memtmp, val); }3.174 -#define MEM_WRITE_WORD( addr, val ) memtmp = mmu_vma_to_phys_write(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { sh4_write_word(memtmp, val); }3.175 -#define MEM_WRITE_LONG( addr, val ) memtmp = mmu_vma_to_phys_write(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { sh4_write_long(memtmp, val); }3.176 -3.177 -#define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)3.178 -3.179 -#define MEM_FP_READ( addr, reg ) \3.180 - if( IS_FPU_DOUBLESIZE() ) { \3.181 - CHECKRALIGN64(addr); \3.182 - memtmp = mmu_vma_to_phys_read(addr); \3.183 - if( memtmp == MMU_VMA_ERROR ) { \3.184 - return TRUE; \3.185 - } else { \3.186 - if( reg & 1 ) { \3.187 - *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(memtmp); \3.188 - *((uint32_t *)&XF(reg)) = sh4_read_long(memtmp+4); \3.189 - } else { \3.190 - *((uint32_t *)&FR(reg)) = sh4_read_long(memtmp); \3.191 - *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(memtmp+4); \3.192 - } \3.193 - } \3.194 - } else { \3.195 - CHECKRALIGN32(addr); \3.196 - memtmp = mmu_vma_to_phys_read(addr); \3.197 - if( memtmp == MMU_VMA_ERROR ) { \3.198 - return TRUE; \3.199 - } else { \3.200 - *((uint32_t *)&FR(reg)) = sh4_read_long(memtmp); \3.201 - } \3.202 - }3.203 -#define MEM_FP_WRITE( addr, reg ) \3.204 - if( IS_FPU_DOUBLESIZE() ) { \3.205 - CHECKWALIGN64(addr); \3.206 - memtmp = mmu_vma_to_phys_write(addr); \3.207 - if( memtmp == MMU_VMA_ERROR ) { \3.208 - return TRUE; \3.209 - } else { \3.210 - if( reg & 1 ) { \3.211 - sh4_write_long( memtmp, *((uint32_t *)&XF((reg)&0x0E)) ); \3.212 - sh4_write_long( memtmp+4, *((uint32_t *)&XF(reg)) ); \3.213 - } else { \3.214 - sh4_write_long( memtmp, *((uint32_t *)&FR(reg)) ); \3.215 - sh4_write_long( memtmp+4, *((uint32_t *)&FR((reg)|0x01)) ); \3.216 - } \3.217 - } \3.218 - } else { \3.219 - CHECKWALIGN32(addr); \3.220 - memtmp = mmu_vma_to_phys_write(addr); \3.221 - if( memtmp == MMU_VMA_ERROR ) { \3.222 - return TRUE; \3.223 - } else { \3.224 - sh4_write_long( memtmp, *((uint32_t *)&FR((reg))) ); \3.225 - } \3.226 - }3.227 -3.228 -gboolean sh4_execute_instruction( void )3.229 -{3.230 - uint32_t pc;3.231 - unsigned short ir;3.232 - uint32_t tmp;3.233 - float ftmp;3.234 - double dtmp;3.235 - int64_t memtmp; // temporary holder for memory reads3.236 -3.237 -#define R0 sh4r.r[0]3.238 - pc = sh4r.pc;3.239 - if( pc > 0xFFFFFF00 ) {3.240 - /* SYSCALL Magic */3.241 - syscall_invoke( pc );3.242 - sh4r.in_delay_slot = 0;3.243 - pc = sh4r.pc = sh4r.pr;3.244 - sh4r.new_pc = sh4r.pc + 2;3.245 - return TRUE;3.246 - }3.247 - CHECKRALIGN16(pc);3.248 -3.249 -#ifdef ENABLE_SH4STATS3.250 - sh4_stats_add_by_pc(sh4r.pc);3.251 -#endif3.252 -3.253 - /* Read instruction */3.254 - if( !IS_IN_ICACHE(pc) ) {3.255 - if( !mmu_update_icache(pc) ) {3.256 - // Fault - look for the fault handler3.257 - if( !mmu_update_icache(sh4r.pc) ) {3.258 - // double fault - halt3.259 - ERROR( "Double fault - halting" );3.260 - sh4_core_exit(CORE_EXIT_HALT);3.261 - return FALSE;3.262 - }3.263 - }3.264 - pc = sh4r.pc;3.265 - }3.266 - assert( IS_IN_ICACHE(pc) );3.267 - ir = *(uint16_t *)GET_ICACHE_PTR(sh4r.pc);3.268 - switch( (ir&0xF000) >> 12 ) {3.269 - case 0x0:3.270 - switch( ir&0xF ) {3.271 - case 0x2:3.272 - switch( (ir&0x80) >> 7 ) {3.273 - case 0x0:3.274 - switch( (ir&0x70) >> 4 ) {3.275 - case 0x0:3.276 - { /* STC SR, Rn */3.277 - uint32_t Rn = ((ir>>8)&0xF);3.278 - CHECKPRIV();3.279 - sh4r.r[Rn] = sh4_read_sr();3.280 - }3.281 - break;3.282 - case 0x1:3.283 - { /* STC GBR, Rn */3.284 - uint32_t Rn = ((ir>>8)&0xF);3.285 - sh4r.r[Rn] = sh4r.gbr;3.286 - }3.287 - break;3.288 - case 0x2:3.289 - { /* STC VBR, Rn */3.290 - uint32_t Rn = ((ir>>8)&0xF);3.291 - CHECKPRIV();3.292 - sh4r.r[Rn] = sh4r.vbr;3.293 - }3.294 - break;3.295 - case 0x3:3.296 - { /* STC SSR, Rn */3.297 - uint32_t Rn = ((ir>>8)&0xF);3.298 - CHECKPRIV();3.299 - sh4r.r[Rn] = sh4r.ssr;3.300 - }3.301 - break;3.302 - case 0x4:3.303 - { /* STC SPC, Rn */3.304 - uint32_t Rn = ((ir>>8)&0xF);3.305 - CHECKPRIV();3.306 - sh4r.r[Rn] = sh4r.spc;3.307 - }3.308 - break;3.309 - default:3.310 - UNDEF();3.311 - break;3.312 - }3.313 - break;3.314 - case 0x1:3.315 - { /* STC Rm_BANK, Rn */3.316 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);3.317 - CHECKPRIV();3.318 - sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];3.319 - }3.320 - break;3.321 - }3.322 - break;3.323 - case 0x3:3.324 - switch( (ir&0xF0) >> 4 ) {3.325 - case 0x0:3.326 - { /* BSRF Rn */3.327 - uint32_t Rn = ((ir>>8)&0xF);3.328 - CHECKSLOTILLEGAL();3.329 - CHECKDEST( pc + 4 + sh4r.r[Rn] );3.330 - sh4r.in_delay_slot = 1;3.331 - sh4r.pr = sh4r.pc + 4;3.332 - sh4r.pc = sh4r.new_pc;3.333 - sh4r.new_pc = pc + 4 + sh4r.r[Rn];3.334 - TRACE_CALL( pc, sh4r.new_pc );3.335 - return TRUE;3.336 - }3.337 - break;3.338 - case 0x2:3.339 - { /* BRAF Rn */3.340 - uint32_t Rn = ((ir>>8)&0xF);3.341 - CHECKSLOTILLEGAL();3.342 - CHECKDEST( pc + 4 + sh4r.r[Rn] );3.343 - sh4r.in_delay_slot = 1;3.344 - sh4r.pc = sh4r.new_pc;3.345 - sh4r.new_pc = pc + 4 + sh4r.r[Rn];3.346 - return TRUE;3.347 - }3.348 - break;3.349 - case 0x8:3.350 - { /* PREF @Rn */3.351 - uint32_t Rn = ((ir>>8)&0xF);3.352 - tmp = sh4r.r[Rn];3.353 - if( (tmp & 0xFC000000) == 0xE0000000 ) {3.354 - sh4_flush_store_queue(tmp);3.355 - }3.356 - }3.357 - break;3.358 - case 0x9:3.359 - { /* OCBI @Rn */3.360 - uint32_t Rn = ((ir>>8)&0xF);3.361 - }3.362 - break;3.363 - case 0xA:3.364 - { /* OCBP @Rn */3.365 - uint32_t Rn = ((ir>>8)&0xF);3.366 - }3.367 - break;3.368 - case 0xB:3.369 - { /* OCBWB @Rn */3.370 - uint32_t Rn = ((ir>>8)&0xF);3.371 - }3.372 - break;3.373 - case 0xC:3.374 - { /* MOVCA.L R0, @Rn */3.375 - uint32_t Rn = ((ir>>8)&0xF);3.376 - tmp = sh4r.r[Rn];3.377 - CHECKWALIGN32(tmp);3.378 - MEM_WRITE_LONG( tmp, R0 );3.379 - }3.380 - break;3.381 - default:3.382 - UNDEF();3.383 - break;3.384 - }3.385 - break;3.386 - case 0x4:3.387 - { /* MOV.B Rm, @(R0, Rn) */3.388 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.389 - MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] );3.390 - }3.391 - break;3.392 - case 0x5:3.393 - { /* MOV.W Rm, @(R0, Rn) */3.394 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.395 - CHECKWALIGN16( R0 + sh4r.r[Rn] );3.396 - MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );3.397 - }3.398 - break;3.399 - case 0x6:3.400 - { /* MOV.L Rm, @(R0, Rn) */3.401 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.402 - CHECKWALIGN32( R0 + sh4r.r[Rn] );3.403 - MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );3.404 - }3.405 - break;3.406 - case 0x7:3.407 - { /* MUL.L Rm, Rn */3.408 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.409 - sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |3.410 - (sh4r.r[Rm] * sh4r.r[Rn]);3.411 - }3.412 - break;3.413 - case 0x8:3.414 - switch( (ir&0xFF0) >> 4 ) {3.415 - case 0x0:3.416 - { /* CLRT */3.417 - sh4r.t = 0;3.418 - }3.419 - break;3.420 - case 0x1:3.421 - { /* SETT */3.422 - sh4r.t = 1;3.423 - }3.424 - break;3.425 - case 0x2:3.426 - { /* CLRMAC */3.427 - sh4r.mac = 0;3.428 - }3.429 - break;3.430 - case 0x3:3.431 - { /* LDTLB */3.432 - MMU_ldtlb();3.433 - }3.434 - break;3.435 - case 0x4:3.436 - { /* CLRS */3.437 - sh4r.s = 0;3.438 - }3.439 - break;3.440 - case 0x5:3.441 - { /* SETS */3.442 - sh4r.s = 1;3.443 - }3.444 - break;3.445 - default:3.446 - UNDEF();3.447 - break;3.448 - }3.449 - break;3.450 - case 0x9:3.451 - switch( (ir&0xF0) >> 4 ) {3.452 - case 0x0:3.453 - { /* NOP */3.454 - /* NOP */3.455 - }3.456 - break;3.457 - case 0x1:3.458 - { /* DIV0U */3.459 - sh4r.m = sh4r.q = sh4r.t = 0;3.460 - }3.461 - break;3.462 - case 0x2:3.463 - { /* MOVT Rn */3.464 - uint32_t Rn = ((ir>>8)&0xF);3.465 - sh4r.r[Rn] = sh4r.t;3.466 - }3.467 - break;3.468 - default:3.469 - UNDEF();3.470 - break;3.471 - }3.472 - break;3.473 - case 0xA:3.474 - switch( (ir&0xF0) >> 4 ) {3.475 - case 0x0:3.476 - { /* STS MACH, Rn */3.477 - uint32_t Rn = ((ir>>8)&0xF);3.478 - sh4r.r[Rn] = (sh4r.mac>>32);3.479 - }3.480 - break;3.481 - case 0x1:3.482 - { /* STS MACL, Rn */3.483 - uint32_t Rn = ((ir>>8)&0xF);3.484 - sh4r.r[Rn] = (uint32_t)sh4r.mac;3.485 - }3.486 - break;3.487 - case 0x2:3.488 - { /* STS PR, Rn */3.489 - uint32_t Rn = ((ir>>8)&0xF);3.490 - sh4r.r[Rn] = sh4r.pr;3.491 - }3.492 - break;3.493 - case 0x3:3.494 - { /* STC SGR, Rn */3.495 - uint32_t Rn = ((ir>>8)&0xF);3.496 - CHECKPRIV();3.497 - sh4r.r[Rn] = sh4r.sgr;3.498 - }3.499 - break;3.500 - case 0x5:3.501 - { /* STS FPUL, Rn */3.502 - uint32_t Rn = ((ir>>8)&0xF);3.503 - CHECKFPUEN();3.504 - sh4r.r[Rn] = FPULi;3.505 - }3.506 - break;3.507 - case 0x6:3.508 - { /* STS FPSCR, Rn */3.509 - uint32_t Rn = ((ir>>8)&0xF);3.510 - CHECKFPUEN();3.511 - sh4r.r[Rn] = sh4r.fpscr;3.512 - }3.513 - break;3.514 - case 0xF:3.515 - { /* STC DBR, Rn */3.516 - uint32_t Rn = ((ir>>8)&0xF);3.517 - CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr;3.518 - }3.519 - break;3.520 - default:3.521 - UNDEF();3.522 - break;3.523 - }3.524 - break;3.525 - case 0xB:3.526 - switch( (ir&0xFF0) >> 4 ) {3.527 - case 0x0:3.528 - { /* RTS */3.529 - CHECKSLOTILLEGAL();3.530 - CHECKDEST( sh4r.pr );3.531 - sh4r.in_delay_slot = 1;3.532 - sh4r.pc = sh4r.new_pc;3.533 - sh4r.new_pc = sh4r.pr;3.534 - TRACE_RETURN( pc, sh4r.new_pc );3.535 - return TRUE;3.536 - }3.537 - break;3.538 - case 0x1:3.539 - { /* SLEEP */3.540 - if( MMIO_READ( CPG, STBCR ) & 0x80 ) {3.541 - sh4r.sh4_state = SH4_STATE_STANDBY;3.542 - } else {3.543 - sh4r.sh4_state = SH4_STATE_SLEEP;3.544 - }3.545 - return FALSE; /* Halt CPU */3.546 - }3.547 - break;3.548 - case 0x2:3.549 - { /* RTE */3.550 - CHECKPRIV();3.551 - CHECKDEST( sh4r.spc );3.552 - CHECKSLOTILLEGAL();3.553 - sh4r.in_delay_slot = 1;3.554 - sh4r.pc = sh4r.new_pc;3.555 - sh4r.new_pc = sh4r.spc;3.556 - sh4_write_sr( sh4r.ssr );3.557 - return TRUE;3.558 - }3.559 - break;3.560 - default:3.561 - UNDEF();3.562 - break;3.563 - }3.564 - break;3.565 - case 0xC:3.566 - { /* MOV.B @(R0, Rm), Rn */3.567 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.568 - MEM_READ_BYTE( R0 + sh4r.r[Rm], sh4r.r[Rn] );3.569 - }3.570 - break;3.571 - case 0xD:3.572 - { /* MOV.W @(R0, Rm), Rn */3.573 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.574 - CHECKRALIGN16( R0 + sh4r.r[Rm] );3.575 - MEM_READ_WORD( R0 + sh4r.r[Rm], sh4r.r[Rn] );3.576 - }3.577 - break;3.578 - case 0xE:3.579 - { /* MOV.L @(R0, Rm), Rn */3.580 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.581 - CHECKRALIGN32( R0 + sh4r.r[Rm] );3.582 - MEM_READ_LONG( R0 + sh4r.r[Rm], sh4r.r[Rn] );3.583 - }3.584 - break;3.585 - case 0xF:3.586 - { /* MAC.L @Rm+, @Rn+ */3.587 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.588 - int64_t tmpl;3.589 - if( Rm == Rn ) {3.590 - CHECKRALIGN32( sh4r.r[Rn] );3.591 - MEM_READ_LONG(sh4r.r[Rn], tmp);3.592 - tmpl = SIGNEXT32(tmp);3.593 - MEM_READ_LONG(sh4r.r[Rn]+4, tmp);3.594 - tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;3.595 - sh4r.r[Rn] += 8;3.596 - } else {3.597 - CHECKRALIGN32( sh4r.r[Rm] );3.598 - CHECKRALIGN32( sh4r.r[Rn] );3.599 - MEM_READ_LONG(sh4r.r[Rn], tmp);3.600 - tmpl = SIGNEXT32(tmp);3.601 - MEM_READ_LONG(sh4r.r[Rm], tmp);3.602 - tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;3.603 - sh4r.r[Rn] += 4;3.604 - sh4r.r[Rm] += 4;3.605 - }3.606 - if( sh4r.s ) {3.607 - /* 48-bit Saturation. Yuch */3.608 - if( tmpl < (int64_t)0xFFFF800000000000LL )3.609 - tmpl = 0xFFFF800000000000LL;3.610 - else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )3.611 - tmpl = 0x00007FFFFFFFFFFFLL;3.612 - }3.613 - sh4r.mac = tmpl;3.614 - }3.615 - break;3.616 - default:3.617 - UNDEF();3.618 - break;3.619 - }3.620 - break;3.621 - case 0x1:3.622 - { /* MOV.L Rm, @(disp, Rn) */3.623 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;3.624 - tmp = sh4r.r[Rn] + disp;3.625 - CHECKWALIGN32( tmp );3.626 - MEM_WRITE_LONG( tmp, sh4r.r[Rm] );3.627 - }3.628 - break;3.629 - case 0x2:3.630 - switch( ir&0xF ) {3.631 - case 0x0:3.632 - { /* MOV.B Rm, @Rn */3.633 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.634 - MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] );3.635 - }3.636 - break;3.637 - case 0x1:3.638 - { /* MOV.W Rm, @Rn */3.639 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.640 - CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] );3.641 - }3.642 - break;3.643 - case 0x2:3.644 - { /* MOV.L Rm, @Rn */3.645 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.646 - CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] );3.647 - }3.648 - break;3.649 - case 0x4:3.650 - { /* MOV.B Rm, @-Rn */3.651 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.652 - MEM_WRITE_BYTE( sh4r.r[Rn]-1, sh4r.r[Rm] ); sh4r.r[Rn]--;3.653 - }3.654 - break;3.655 - case 0x5:3.656 - { /* MOV.W Rm, @-Rn */3.657 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.658 - CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn]-2, sh4r.r[Rm] ); sh4r.r[Rn] -= 2;3.659 - }3.660 - break;3.661 - case 0x6:3.662 - { /* MOV.L Rm, @-Rn */3.663 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.664 - CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.r[Rm] ); sh4r.r[Rn] -= 4;3.665 - }3.666 - break;3.667 - case 0x7:3.668 - { /* DIV0S Rm, Rn */3.669 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.670 - sh4r.q = sh4r.r[Rn]>>31;3.671 - sh4r.m = sh4r.r[Rm]>>31;3.672 - sh4r.t = sh4r.q ^ sh4r.m;3.673 - }3.674 - break;3.675 - case 0x8:3.676 - { /* TST Rm, Rn */3.677 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.678 - sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1);3.679 - }3.680 - break;3.681 - case 0x9:3.682 - { /* AND Rm, Rn */3.683 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.684 - sh4r.r[Rn] &= sh4r.r[Rm];3.685 - }3.686 - break;3.687 - case 0xA:3.688 - { /* XOR Rm, Rn */3.689 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.690 - sh4r.r[Rn] ^= sh4r.r[Rm];3.691 - }3.692 - break;3.693 - case 0xB:3.694 - { /* OR Rm, Rn */3.695 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.696 - sh4r.r[Rn] |= sh4r.r[Rm];3.697 - }3.698 - break;3.699 - case 0xC:3.700 - { /* CMP/STR Rm, Rn */3.701 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.702 - /* set T = 1 if any byte in RM & RN is the same */3.703 - tmp = sh4r.r[Rm] ^ sh4r.r[Rn];3.704 - sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||3.705 - (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;3.706 - }3.707 - break;3.708 - case 0xD:3.709 - { /* XTRCT Rm, Rn */3.710 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.711 - sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16);3.712 - }3.713 - break;3.714 - case 0xE:3.715 - { /* MULU.W Rm, Rn */3.716 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.717 - sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |3.718 - (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));3.719 - }3.720 - break;3.721 - case 0xF:3.722 - { /* MULS.W Rm, Rn */3.723 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.724 - sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |3.725 - (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));3.726 - }3.727 - break;3.728 - default:3.729 - UNDEF();3.730 - break;3.731 - }3.732 - break;3.733 - case 0x3:3.734 - switch( ir&0xF ) {3.735 - case 0x0:3.736 - { /* CMP/EQ Rm, Rn */3.737 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.738 - sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 );3.739 - }3.740 - break;3.741 - case 0x2:3.742 - { /* CMP/HS Rm, Rn */3.743 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.744 - sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 );3.745 - }3.746 - break;3.747 - case 0x3:3.748 - { /* CMP/GE Rm, Rn */3.749 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.750 - sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 );3.751 - }3.752 - break;3.753 - case 0x4:3.754 - { /* DIV1 Rm, Rn */3.755 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.756 - /* This is derived from the sh4 manual with some simplifications */3.757 - uint32_t tmp0, tmp1, tmp2, dir;3.758 -3.759 - dir = sh4r.q ^ sh4r.m;3.760 - sh4r.q = (sh4r.r[Rn] >> 31);3.761 - tmp2 = sh4r.r[Rm];3.762 - sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;3.763 - tmp0 = sh4r.r[Rn];3.764 - if( dir ) {3.765 - sh4r.r[Rn] += tmp2;3.766 - tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );3.767 - } else {3.768 - sh4r.r[Rn] -= tmp2;3.769 - tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );3.770 - }3.771 - sh4r.q ^= sh4r.m ^ tmp1;3.772 - sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );3.773 - }3.774 - break;3.775 - case 0x5:3.776 - { /* DMULU.L Rm, Rn */3.777 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.778 - sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]);3.779 - }3.780 - break;3.781 - case 0x6:3.782 - { /* CMP/HI Rm, Rn */3.783 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.784 - sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 );3.785 - }3.786 - break;3.787 - case 0x7:3.788 - { /* CMP/GT Rm, Rn */3.789 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.790 - sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 );3.791 - }3.792 - break;3.793 - case 0x8:3.794 - { /* SUB Rm, Rn */3.795 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.796 - sh4r.r[Rn] -= sh4r.r[Rm];3.797 - }3.798 - break;3.799 - case 0xA:3.800 - { /* SUBC Rm, Rn */3.801 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.802 - tmp = sh4r.r[Rn];3.803 - sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;3.804 - sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));3.805 - }3.806 - break;3.807 - case 0xB:3.808 - UNIMP(ir); /* SUBV Rm, Rn */3.809 - break;3.810 - case 0xC:3.811 - { /* ADD Rm, Rn */3.812 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.813 - sh4r.r[Rn] += sh4r.r[Rm];3.814 - }3.815 - break;3.816 - case 0xD:3.817 - { /* DMULS.L Rm, Rn */3.818 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.819 - sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]);3.820 - }3.821 - break;3.822 - case 0xE:3.823 - { /* ADDC Rm, Rn */3.824 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.825 - tmp = sh4r.r[Rn];3.826 - sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;3.827 - sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );3.828 - }3.829 - break;3.830 - case 0xF:3.831 - { /* ADDV Rm, Rn */3.832 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.833 - tmp = sh4r.r[Rn] + sh4r.r[Rm];3.834 - sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );3.835 - sh4r.r[Rn] = tmp;3.836 - }3.837 - break;3.838 - default:3.839 - UNDEF();3.840 - break;3.841 - }3.842 - break;3.843 - case 0x4:3.844 - switch( ir&0xF ) {3.845 - case 0x0:3.846 - switch( (ir&0xF0) >> 4 ) {3.847 - case 0x0:3.848 - { /* SHLL Rn */3.849 - uint32_t Rn = ((ir>>8)&0xF);3.850 - sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1;3.851 - }3.852 - break;3.853 - case 0x1:3.854 - { /* DT Rn */3.855 - uint32_t Rn = ((ir>>8)&0xF);3.856 - sh4r.r[Rn] --;3.857 - sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );3.858 - }3.859 - break;3.860 - case 0x2:3.861 - { /* SHAL Rn */3.862 - uint32_t Rn = ((ir>>8)&0xF);3.863 - sh4r.t = sh4r.r[Rn] >> 31;3.864 - sh4r.r[Rn] <<= 1;3.865 - }3.866 - break;3.867 - default:3.868 - UNDEF();3.869 - break;3.870 - }3.871 - break;3.872 - case 0x1:3.873 - switch( (ir&0xF0) >> 4 ) {3.874 - case 0x0:3.875 - { /* SHLR Rn */3.876 - uint32_t Rn = ((ir>>8)&0xF);3.877 - sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1;3.878 - }3.879 - break;3.880 - case 0x1:3.881 - { /* CMP/PZ Rn */3.882 - uint32_t Rn = ((ir>>8)&0xF);3.883 - sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 );3.884 - }3.885 - break;3.886 - case 0x2:3.887 - { /* SHAR Rn */3.888 - uint32_t Rn = ((ir>>8)&0xF);3.889 - sh4r.t = sh4r.r[Rn] & 0x00000001;3.890 - sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;3.891 - }3.892 - break;3.893 - default:3.894 - UNDEF();3.895 - break;3.896 - }3.897 - break;3.898 - case 0x2:3.899 - switch( (ir&0xF0) >> 4 ) {3.900 - case 0x0:3.901 - { /* STS.L MACH, @-Rn */3.902 - uint32_t Rn = ((ir>>8)&0xF);3.903 - CHECKWALIGN32( sh4r.r[Rn] );3.904 - MEM_WRITE_LONG( sh4r.r[Rn]-4, (sh4r.mac>>32) );3.905 - sh4r.r[Rn] -= 4;3.906 - }3.907 - break;3.908 - case 0x1:3.909 - { /* STS.L MACL, @-Rn */3.910 - uint32_t Rn = ((ir>>8)&0xF);3.911 - CHECKWALIGN32( sh4r.r[Rn] );3.912 - MEM_WRITE_LONG( sh4r.r[Rn]-4, (uint32_t)sh4r.mac );3.913 - sh4r.r[Rn] -= 4;3.914 - }3.915 - break;3.916 - case 0x2:3.917 - { /* STS.L PR, @-Rn */3.918 - uint32_t Rn = ((ir>>8)&0xF);3.919 - CHECKWALIGN32( sh4r.r[Rn] );3.920 - MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.pr );3.921 - sh4r.r[Rn] -= 4;3.922 - }3.923 - break;3.924 - case 0x3:3.925 - { /* STC.L SGR, @-Rn */3.926 - uint32_t Rn = ((ir>>8)&0xF);3.927 - CHECKPRIV();3.928 - CHECKWALIGN32( sh4r.r[Rn] );3.929 - MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.sgr );3.930 - sh4r.r[Rn] -= 4;3.931 - }3.932 - break;3.933 - case 0x5:3.934 - { /* STS.L FPUL, @-Rn */3.935 - uint32_t Rn = ((ir>>8)&0xF);3.936 - CHECKFPUEN();3.937 - CHECKWALIGN32( sh4r.r[Rn] );3.938 - MEM_WRITE_LONG( sh4r.r[Rn]-4, FPULi );3.939 - sh4r.r[Rn] -= 4;3.940 - }3.941 - break;3.942 - case 0x6:3.943 - { /* STS.L FPSCR, @-Rn */3.944 - uint32_t Rn = ((ir>>8)&0xF);3.945 - CHECKFPUEN();3.946 - CHECKWALIGN32( sh4r.r[Rn] );3.947 - MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.fpscr );3.948 - sh4r.r[Rn] -= 4;3.949 - }3.950 - break;3.951 - case 0xF:3.952 - { /* STC.L DBR, @-Rn */3.953 - uint32_t Rn = ((ir>>8)&0xF);3.954 - CHECKPRIV();3.955 - CHECKWALIGN32( sh4r.r[Rn] );3.956 - MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.dbr );3.957 - sh4r.r[Rn] -= 4;3.958 - }3.959 - break;3.960 - default:3.961 - UNDEF();3.962 - break;3.963 - }3.964 - break;3.965 - case 0x3:3.966 - switch( (ir&0x80) >> 7 ) {3.967 - case 0x0:3.968 - switch( (ir&0x70) >> 4 ) {3.969 - case 0x0:3.970 - { /* STC.L SR, @-Rn */3.971 - uint32_t Rn = ((ir>>8)&0xF);3.972 - CHECKPRIV();3.973 - CHECKWALIGN32( sh4r.r[Rn] );3.974 - MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4_read_sr() );3.975 - sh4r.r[Rn] -= 4;3.976 - }3.977 - break;3.978 - case 0x1:3.979 - { /* STC.L GBR, @-Rn */3.980 - uint32_t Rn = ((ir>>8)&0xF);3.981 - CHECKWALIGN32( sh4r.r[Rn] );3.982 - MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.gbr );3.983 - sh4r.r[Rn] -= 4;3.984 - }3.985 - break;3.986 - case 0x2:3.987 - { /* STC.L VBR, @-Rn */3.988 - uint32_t Rn = ((ir>>8)&0xF);3.989 - CHECKPRIV();3.990 - CHECKWALIGN32( sh4r.r[Rn] );3.991 - MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.vbr );3.992 - sh4r.r[Rn] -= 4;3.993 - }3.994 - break;3.995 - case 0x3:3.996 - { /* STC.L SSR, @-Rn */3.997 - uint32_t Rn = ((ir>>8)&0xF);3.998 - CHECKPRIV();3.999 - CHECKWALIGN32( sh4r.r[Rn] );3.1000 - MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.ssr );3.1001 - sh4r.r[Rn] -= 4;3.1002 - }3.1003 - break;3.1004 - case 0x4:3.1005 - { /* STC.L SPC, @-Rn */3.1006 - uint32_t Rn = ((ir>>8)&0xF);3.1007 - CHECKPRIV();3.1008 - CHECKWALIGN32( sh4r.r[Rn] );3.1009 - MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.spc );3.1010 - sh4r.r[Rn] -= 4;3.1011 - }3.1012 - break;3.1013 - default:3.1014 - UNDEF();3.1015 - break;3.1016 - }3.1017 - break;3.1018 - case 0x1:3.1019 - { /* STC.L Rm_BANK, @-Rn */3.1020 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);3.1021 - CHECKPRIV();3.1022 - CHECKWALIGN32( sh4r.r[Rn] );3.1023 - MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.r_bank[Rm_BANK] );3.1024 - sh4r.r[Rn] -= 4;3.1025 - }3.1026 - break;3.1027 - }3.1028 - break;3.1029 - case 0x4:3.1030 - switch( (ir&0xF0) >> 4 ) {3.1031 - case 0x0:3.1032 - { /* ROTL Rn */3.1033 - uint32_t Rn = ((ir>>8)&0xF);3.1034 - sh4r.t = sh4r.r[Rn] >> 31;3.1035 - sh4r.r[Rn] <<= 1;3.1036 - sh4r.r[Rn] |= sh4r.t;3.1037 - }3.1038 - break;3.1039 - case 0x2:3.1040 - { /* ROTCL Rn */3.1041 - uint32_t Rn = ((ir>>8)&0xF);3.1042 - tmp = sh4r.r[Rn] >> 31;3.1043 - sh4r.r[Rn] <<= 1;3.1044 - sh4r.r[Rn] |= sh4r.t;3.1045 - sh4r.t = tmp;3.1046 - }3.1047 - break;3.1048 - default:3.1049 - UNDEF();3.1050 - break;3.1051 - }3.1052 - break;3.1053 - case 0x5:3.1054 - switch( (ir&0xF0) >> 4 ) {3.1055 - case 0x0:3.1056 - { /* ROTR Rn */3.1057 - uint32_t Rn = ((ir>>8)&0xF);3.1058 - sh4r.t = sh4r.r[Rn] & 0x00000001;3.1059 - sh4r.r[Rn] >>= 1;3.1060 - sh4r.r[Rn] |= (sh4r.t << 31);3.1061 - }3.1062 - break;3.1063 - case 0x1:3.1064 - { /* CMP/PL Rn */3.1065 - uint32_t Rn = ((ir>>8)&0xF);3.1066 - sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 );3.1067 - }3.1068 - break;3.1069 - case 0x2:3.1070 - { /* ROTCR Rn */3.1071 - uint32_t Rn = ((ir>>8)&0xF);3.1072 - tmp = sh4r.r[Rn] & 0x00000001;3.1073 - sh4r.r[Rn] >>= 1;3.1074 - sh4r.r[Rn] |= (sh4r.t << 31 );3.1075 - sh4r.t = tmp;3.1076 - }3.1077 - break;3.1078 - default:3.1079 - UNDEF();3.1080 - break;3.1081 - }3.1082 - break;3.1083 - case 0x6:3.1084 - switch( (ir&0xF0) >> 4 ) {3.1085 - case 0x0:3.1086 - { /* LDS.L @Rm+, MACH */3.1087 - uint32_t Rm = ((ir>>8)&0xF);3.1088 - CHECKRALIGN32( sh4r.r[Rm] );3.1089 - MEM_READ_LONG(sh4r.r[Rm], tmp);3.1090 - sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |3.1091 - (((uint64_t)tmp)<<32);3.1092 - sh4r.r[Rm] += 4;3.1093 - }3.1094 - break;3.1095 - case 0x1:3.1096 - { /* LDS.L @Rm+, MACL */3.1097 - uint32_t Rm = ((ir>>8)&0xF);3.1098 - CHECKRALIGN32( sh4r.r[Rm] );3.1099 - MEM_READ_LONG(sh4r.r[Rm], tmp);3.1100 - sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |3.1101 - (uint64_t)((uint32_t)tmp);3.1102 - sh4r.r[Rm] += 4;3.1103 - }3.1104 - break;3.1105 - case 0x2:3.1106 - { /* LDS.L @Rm+, PR */3.1107 - uint32_t Rm = ((ir>>8)&0xF);3.1108 - CHECKRALIGN32( sh4r.r[Rm] );3.1109 - MEM_READ_LONG( sh4r.r[Rm], sh4r.pr );3.1110 - sh4r.r[Rm] += 4;3.1111 - }3.1112 - break;3.1113 - case 0x3:3.1114 - { /* LDC.L @Rm+, SGR */3.1115 - uint32_t Rm = ((ir>>8)&0xF);3.1116 - CHECKPRIV();3.1117 - CHECKRALIGN32( sh4r.r[Rm] );3.1118 - MEM_READ_LONG(sh4r.r[Rm], sh4r.sgr);3.1119 - sh4r.r[Rm] +=4;3.1120 - }3.1121 - break;3.1122 - case 0x5:3.1123 - { /* LDS.L @Rm+, FPUL */3.1124 - uint32_t Rm = ((ir>>8)&0xF);3.1125 - CHECKFPUEN();3.1126 - CHECKRALIGN32( sh4r.r[Rm] );3.1127 - MEM_READ_LONG(sh4r.r[Rm], FPULi);3.1128 - sh4r.r[Rm] +=4;3.1129 - }3.1130 - break;3.1131 - case 0x6:3.1132 - { /* LDS.L @Rm+, FPSCR */3.1133 - uint32_t Rm = ((ir>>8)&0xF);3.1134 - CHECKFPUEN();3.1135 - CHECKRALIGN32( sh4r.r[Rm] );3.1136 - MEM_READ_LONG(sh4r.r[Rm], tmp);3.1137 - sh4r.r[Rm] +=4;3.1138 - sh4_write_fpscr( tmp );3.1139 - }3.1140 - break;3.1141 - case 0xF:3.1142 - { /* LDC.L @Rm+, DBR */3.1143 - uint32_t Rm = ((ir>>8)&0xF);3.1144 - CHECKPRIV();3.1145 - CHECKRALIGN32( sh4r.r[Rm] );3.1146 - MEM_READ_LONG(sh4r.r[Rm], sh4r.dbr);3.1147 - sh4r.r[Rm] +=4;3.1148 - }3.1149 - break;3.1150 - default:3.1151 - UNDEF();3.1152 - break;3.1153 - }3.1154 - break;3.1155 - case 0x7:3.1156 - switch( (ir&0x80) >> 7 ) {3.1157 - case 0x0:3.1158 - switch( (ir&0x70) >> 4 ) {3.1159 - case 0x0:3.1160 - { /* LDC.L @Rm+, SR */3.1161 - uint32_t Rm = ((ir>>8)&0xF);3.1162 - CHECKSLOTILLEGAL();3.1163 - CHECKPRIV();3.1164 - CHECKWALIGN32( sh4r.r[Rm] );3.1165 - MEM_READ_LONG(sh4r.r[Rm], tmp);3.1166 - sh4_write_sr( tmp );3.1167 - sh4r.r[Rm] +=4;3.1168 - }3.1169 - break;3.1170 - case 0x1:3.1171 - { /* LDC.L @Rm+, GBR */3.1172 - uint32_t Rm = ((ir>>8)&0xF);3.1173 - CHECKRALIGN32( sh4r.r[Rm] );3.1174 - MEM_READ_LONG(sh4r.r[Rm], sh4r.gbr);3.1175 - sh4r.r[Rm] +=4;3.1176 - }3.1177 - break;3.1178 - case 0x2:3.1179 - { /* LDC.L @Rm+, VBR */3.1180 - uint32_t Rm = ((ir>>8)&0xF);3.1181 - CHECKPRIV();3.1182 - CHECKRALIGN32( sh4r.r[Rm] );3.1183 - MEM_READ_LONG(sh4r.r[Rm], sh4r.vbr);3.1184 - sh4r.r[Rm] +=4;3.1185 - }3.1186 - break;3.1187 - case 0x3:3.1188 - { /* LDC.L @Rm+, SSR */3.1189 - uint32_t Rm = ((ir>>8)&0xF);3.1190 - CHECKPRIV();3.1191 - CHECKRALIGN32( sh4r.r[Rm] );3.1192 - MEM_READ_LONG(sh4r.r[Rm], sh4r.ssr);3.1193 - sh4r.r[Rm] +=4;3.1194 - }3.1195 - break;3.1196 - case 0x4:3.1197 - { /* LDC.L @Rm+, SPC */3.1198 - uint32_t Rm = ((ir>>8)&0xF);3.1199 - CHECKPRIV();3.1200 - CHECKRALIGN32( sh4r.r[Rm] );3.1201 - MEM_READ_LONG(sh4r.r[Rm], sh4r.spc);3.1202 - sh4r.r[Rm] +=4;3.1203 - }3.1204 - break;3.1205 - default:3.1206 - UNDEF();3.1207 - break;3.1208 - }3.1209 - break;3.1210 - case 0x1:3.1211 - { /* LDC.L @Rm+, Rn_BANK */3.1212 - uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);3.1213 - CHECKPRIV();3.1214 - CHECKRALIGN32( sh4r.r[Rm] );3.1215 - MEM_READ_LONG( sh4r.r[Rm], sh4r.r_bank[Rn_BANK] );3.1216 - sh4r.r[Rm] += 4;3.1217 - }3.1218 - break;3.1219 - }3.1220 - break;3.1221 - case 0x8:3.1222 - switch( (ir&0xF0) >> 4 ) {3.1223 - case 0x0:3.1224 - { /* SHLL2 Rn */3.1225 - uint32_t Rn = ((ir>>8)&0xF);3.1226 - sh4r.r[Rn] <<= 2;3.1227 - }3.1228 - break;3.1229 - case 0x1:3.1230 - { /* SHLL8 Rn */3.1231 - uint32_t Rn = ((ir>>8)&0xF);3.1232 - sh4r.r[Rn] <<= 8;3.1233 - }3.1234 - break;3.1235 - case 0x2:3.1236 - { /* SHLL16 Rn */3.1237 - uint32_t Rn = ((ir>>8)&0xF);3.1238 - sh4r.r[Rn] <<= 16;3.1239 - }3.1240 - break;3.1241 - default:3.1242 - UNDEF();3.1243 - break;3.1244 - }3.1245 - break;3.1246 - case 0x9:3.1247 - switch( (ir&0xF0) >> 4 ) {3.1248 - case 0x0:3.1249 - { /* SHLR2 Rn */3.1250 - uint32_t Rn = ((ir>>8)&0xF);3.1251 - sh4r.r[Rn] >>= 2;3.1252 - }3.1253 - break;3.1254 - case 0x1:3.1255 - { /* SHLR8 Rn */3.1256 - uint32_t Rn = ((ir>>8)&0xF);3.1257 - sh4r.r[Rn] >>= 8;3.1258 - }3.1259 - break;3.1260 - case 0x2:3.1261 - { /* SHLR16 Rn */3.1262 - uint32_t Rn = ((ir>>8)&0xF);3.1263 - sh4r.r[Rn] >>= 16;3.1264 - }3.1265 - break;3.1266 - default:3.1267 - UNDEF();3.1268 - break;3.1269 - }3.1270 - break;3.1271 - case 0xA:3.1272 - switch( (ir&0xF0) >> 4 ) {3.1273 - case 0x0:3.1274 - { /* LDS Rm, MACH */3.1275 - uint32_t Rm = ((ir>>8)&0xF);3.1276 - sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |3.1277 - (((uint64_t)sh4r.r[Rm])<<32);3.1278 - }3.1279 - break;3.1280 - case 0x1:3.1281 - { /* LDS Rm, MACL */3.1282 - uint32_t Rm = ((ir>>8)&0xF);3.1283 - sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |3.1284 - (uint64_t)((uint32_t)(sh4r.r[Rm]));3.1285 - }3.1286 - break;3.1287 - case 0x2:3.1288 - { /* LDS Rm, PR */3.1289 - uint32_t Rm = ((ir>>8)&0xF);3.1290 - sh4r.pr = sh4r.r[Rm];3.1291 - }3.1292 - break;3.1293 - case 0x3:3.1294 - { /* LDC Rm, SGR */3.1295 - uint32_t Rm = ((ir>>8)&0xF);3.1296 - CHECKPRIV();3.1297 - sh4r.sgr = sh4r.r[Rm];3.1298 - }3.1299 - break;3.1300 - case 0x5:3.1301 - { /* LDS Rm, FPUL */3.1302 - uint32_t Rm = ((ir>>8)&0xF);3.1303 - CHECKFPUEN();3.1304 - FPULi = sh4r.r[Rm];3.1305 - }3.1306 - break;3.1307 - case 0x6:3.1308 - { /* LDS Rm, FPSCR */3.1309 - uint32_t Rm = ((ir>>8)&0xF);3.1310 - CHECKFPUEN();3.1311 - sh4_write_fpscr( sh4r.r[Rm] );3.1312 - }3.1313 - break;3.1314 - case 0xF:3.1315 - { /* LDC Rm, DBR */3.1316 - uint32_t Rm = ((ir>>8)&0xF);3.1317 - CHECKPRIV();3.1318 - sh4r.dbr = sh4r.r[Rm];3.1319 - }3.1320 - break;3.1321 - default:3.1322 - UNDEF();3.1323 - break;3.1324 - }3.1325 - break;3.1326 - case 0xB:3.1327 - switch( (ir&0xF0) >> 4 ) {3.1328 - case 0x0:3.1329 - { /* JSR @Rn */3.1330 - uint32_t Rn = ((ir>>8)&0xF);3.1331 - CHECKDEST( sh4r.r[Rn] );3.1332 - CHECKSLOTILLEGAL();3.1333 - sh4r.in_delay_slot = 1;3.1334 - sh4r.pc = sh4r.new_pc;3.1335 - sh4r.new_pc = sh4r.r[Rn];3.1336 - sh4r.pr = pc + 4;3.1337 - TRACE_CALL( pc, sh4r.new_pc );3.1338 - return TRUE;3.1339 - }3.1340 - break;3.1341 - case 0x1:3.1342 - { /* TAS.B @Rn */3.1343 - uint32_t Rn = ((ir>>8)&0xF);3.1344 - MEM_READ_BYTE( sh4r.r[Rn], tmp );3.1345 - sh4r.t = ( tmp == 0 ? 1 : 0 );3.1346 - MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );3.1347 - }3.1348 - break;3.1349 - case 0x2:3.1350 - { /* JMP @Rn */3.1351 - uint32_t Rn = ((ir>>8)&0xF);3.1352 - CHECKDEST( sh4r.r[Rn] );3.1353 - CHECKSLOTILLEGAL();3.1354 - sh4r.in_delay_slot = 1;3.1355 - sh4r.pc = sh4r.new_pc;3.1356 - sh4r.new_pc = sh4r.r[Rn];3.1357 - return TRUE;3.1358 - }3.1359 - break;3.1360 - default:3.1361 - UNDEF();3.1362 - break;3.1363 - }3.1364 - break;3.1365 - case 0xC:3.1366 - { /* SHAD Rm, Rn */3.1367 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1368 - tmp = sh4r.r[Rm];3.1369 - if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);3.1370 - else if( (tmp & 0x1F) == 0 )3.1371 - sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;3.1372 - else3.1373 - sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);3.1374 - }3.1375 - break;3.1376 - case 0xD:3.1377 - { /* SHLD Rm, Rn */3.1378 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1379 - tmp = sh4r.r[Rm];3.1380 - if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);3.1381 - else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;3.1382 - else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);3.1383 - }3.1384 - break;3.1385 - case 0xE:3.1386 - switch( (ir&0x80) >> 7 ) {3.1387 - case 0x0:3.1388 - switch( (ir&0x70) >> 4 ) {3.1389 - case 0x0:3.1390 - { /* LDC Rm, SR */3.1391 - uint32_t Rm = ((ir>>8)&0xF);3.1392 - CHECKSLOTILLEGAL();3.1393 - CHECKPRIV();3.1394 - sh4_write_sr( sh4r.r[Rm] );3.1395 - }3.1396 - break;3.1397 - case 0x1:3.1398 - { /* LDC Rm, GBR */3.1399 - uint32_t Rm = ((ir>>8)&0xF);3.1400 - sh4r.gbr = sh4r.r[Rm];3.1401 - }3.1402 - break;3.1403 - case 0x2:3.1404 - { /* LDC Rm, VBR */3.1405 - uint32_t Rm = ((ir>>8)&0xF);3.1406 - CHECKPRIV();3.1407 - sh4r.vbr = sh4r.r[Rm];3.1408 - }3.1409 - break;3.1410 - case 0x3:3.1411 - { /* LDC Rm, SSR */3.1412 - uint32_t Rm = ((ir>>8)&0xF);3.1413 - CHECKPRIV();3.1414 - sh4r.ssr = sh4r.r[Rm];3.1415 - }3.1416 - break;3.1417 - case 0x4:3.1418 - { /* LDC Rm, SPC */3.1419 - uint32_t Rm = ((ir>>8)&0xF);3.1420 - CHECKPRIV();3.1421 - sh4r.spc = sh4r.r[Rm];3.1422 - }3.1423 - break;3.1424 - default:3.1425 - UNDEF();3.1426 - break;3.1427 - }3.1428 - break;3.1429 - case 0x1:3.1430 - { /* LDC Rm, Rn_BANK */3.1431 - uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);3.1432 - CHECKPRIV();3.1433 - sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];3.1434 - }3.1435 - break;3.1436 - }3.1437 - break;3.1438 - case 0xF:3.1439 - { /* MAC.W @Rm+, @Rn+ */3.1440 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1441 - int32_t stmp;3.1442 - if( Rm == Rn ) {3.1443 - CHECKRALIGN16(sh4r.r[Rn]);3.1444 - MEM_READ_WORD( sh4r.r[Rn], tmp );3.1445 - stmp = SIGNEXT16(tmp);3.1446 - MEM_READ_WORD( sh4r.r[Rn]+2, tmp );3.1447 - stmp *= SIGNEXT16(tmp);3.1448 - sh4r.r[Rn] += 4;3.1449 - } else {3.1450 - CHECKRALIGN16( sh4r.r[Rn] );3.1451 - CHECKRALIGN16( sh4r.r[Rm] );3.1452 - MEM_READ_WORD(sh4r.r[Rn], tmp);3.1453 - stmp = SIGNEXT16(tmp);3.1454 - MEM_READ_WORD(sh4r.r[Rm], tmp);3.1455 - stmp = stmp * SIGNEXT16(tmp);3.1456 - sh4r.r[Rn] += 2;3.1457 - sh4r.r[Rm] += 2;3.1458 - }3.1459 - if( sh4r.s ) {3.1460 - int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;3.1461 - if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {3.1462 - sh4r.mac = 0x000000017FFFFFFFLL;3.1463 - } else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {3.1464 - sh4r.mac = 0x0000000180000000LL;3.1465 - } else {3.1466 - sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |3.1467 - ((uint32_t)(sh4r.mac + stmp));3.1468 - }3.1469 - } else {3.1470 - sh4r.mac += SIGNEXT32(stmp);3.1471 - }3.1472 - }3.1473 - break;3.1474 - }3.1475 - break;3.1476 - case 0x5:3.1477 - { /* MOV.L @(disp, Rm), Rn */3.1478 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;3.1479 - tmp = sh4r.r[Rm] + disp;3.1480 - CHECKRALIGN32( tmp );3.1481 - MEM_READ_LONG( tmp, sh4r.r[Rn] );3.1482 - }3.1483 - break;3.1484 - case 0x6:3.1485 - switch( ir&0xF ) {3.1486 - case 0x0:3.1487 - { /* MOV.B @Rm, Rn */3.1488 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1489 - MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] );3.1490 - }3.1491 - break;3.1492 - case 0x1:3.1493 - { /* MOV.W @Rm, Rn */3.1494 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1495 - CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] );3.1496 - }3.1497 - break;3.1498 - case 0x2:3.1499 - { /* MOV.L @Rm, Rn */3.1500 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1501 - CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] );3.1502 - }3.1503 - break;3.1504 - case 0x3:3.1505 - { /* MOV Rm, Rn */3.1506 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1507 - sh4r.r[Rn] = sh4r.r[Rm];3.1508 - }3.1509 - break;3.1510 - case 0x4:3.1511 - { /* MOV.B @Rm+, Rn */3.1512 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1513 - MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] ++;3.1514 - }3.1515 - break;3.1516 - case 0x5:3.1517 - { /* MOV.W @Rm+, Rn */3.1518 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1519 - CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] += 2;3.1520 - }3.1521 - break;3.1522 - case 0x6:3.1523 - { /* MOV.L @Rm+, Rn */3.1524 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1525 - CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] += 4;3.1526 - }3.1527 - break;3.1528 - case 0x7:3.1529 - { /* NOT Rm, Rn */3.1530 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1531 - sh4r.r[Rn] = ~sh4r.r[Rm];3.1532 - }3.1533 - break;3.1534 - case 0x8:3.1535 - { /* SWAP.B Rm, Rn */3.1536 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1537 - sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8);3.1538 - }3.1539 - break;3.1540 - case 0x9:3.1541 - { /* SWAP.W Rm, Rn */3.1542 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1543 - sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16);3.1544 - }3.1545 - break;3.1546 - case 0xA:3.1547 - { /* NEGC Rm, Rn */3.1548 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1549 - tmp = 0 - sh4r.r[Rm];3.1550 - sh4r.r[Rn] = tmp - sh4r.t;3.1551 - sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );3.1552 - }3.1553 - break;3.1554 - case 0xB:3.1555 - { /* NEG Rm, Rn */3.1556 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1557 - sh4r.r[Rn] = 0 - sh4r.r[Rm];3.1558 - }3.1559 - break;3.1560 - case 0xC:3.1561 - { /* EXTU.B Rm, Rn */3.1562 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1563 - sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF;3.1564 - }3.1565 - break;3.1566 - case 0xD:3.1567 - { /* EXTU.W Rm, Rn */3.1568 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1569 - sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF;3.1570 - }3.1571 - break;3.1572 - case 0xE:3.1573 - { /* EXTS.B Rm, Rn */3.1574 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1575 - sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF );3.1576 - }3.1577 - break;3.1578 - case 0xF:3.1579 - { /* EXTS.W Rm, Rn */3.1580 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1581 - sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF );3.1582 - }3.1583 - break;3.1584 - }3.1585 - break;3.1586 - case 0x7:3.1587 - { /* ADD #imm, Rn */3.1588 - uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);3.1589 - sh4r.r[Rn] += imm;3.1590 - }3.1591 - break;3.1592 - case 0x8:3.1593 - switch( (ir&0xF00) >> 8 ) {3.1594 - case 0x0:3.1595 - { /* MOV.B R0, @(disp, Rn) */3.1596 - uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);3.1597 - MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 );3.1598 - }3.1599 - break;3.1600 - case 0x1:3.1601 - { /* MOV.W R0, @(disp, Rn) */3.1602 - uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;3.1603 - tmp = sh4r.r[Rn] + disp;3.1604 - CHECKWALIGN16( tmp );3.1605 - MEM_WRITE_WORD( tmp, R0 );3.1606 - }3.1607 - break;3.1608 - case 0x4:3.1609 - { /* MOV.B @(disp, Rm), R0 */3.1610 - uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);3.1611 - MEM_READ_BYTE( sh4r.r[Rm] + disp, R0 );3.1612 - }3.1613 - break;3.1614 - case 0x5:3.1615 - { /* MOV.W @(disp, Rm), R0 */3.1616 - uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;3.1617 - tmp = sh4r.r[Rm] + disp;3.1618 - CHECKRALIGN16( tmp );3.1619 - MEM_READ_WORD( tmp, R0 );3.1620 - }3.1621 - break;3.1622 - case 0x8:3.1623 - { /* CMP/EQ #imm, R0 */3.1624 - int32_t imm = SIGNEXT8(ir&0xFF);3.1625 - sh4r.t = ( R0 == imm ? 1 : 0 );3.1626 - }3.1627 - break;3.1628 - case 0x9:3.1629 - { /* BT disp */3.1630 - int32_t disp = SIGNEXT8(ir&0xFF)<<1;3.1631 - CHECKSLOTILLEGAL();3.1632 - if( sh4r.t ) {3.1633 - CHECKDEST( sh4r.pc + disp + 4 )3.1634 - sh4r.pc += disp + 4;3.1635 - sh4r.new_pc = sh4r.pc + 2;3.1636 - return TRUE;3.1637 - }3.1638 - }3.1639 - break;3.1640 - case 0xB:3.1641 - { /* BF disp */3.1642 - int32_t disp = SIGNEXT8(ir&0xFF)<<1;3.1643 - CHECKSLOTILLEGAL();3.1644 - if( !sh4r.t ) {3.1645 - CHECKDEST( sh4r.pc + disp + 4 )3.1646 - sh4r.pc += disp + 4;3.1647 - sh4r.new_pc = sh4r.pc + 2;3.1648 - return TRUE;3.1649 - }3.1650 - }3.1651 - break;3.1652 - case 0xD:3.1653 - { /* BT/S disp */3.1654 - int32_t disp = SIGNEXT8(ir&0xFF)<<1;3.1655 - CHECKSLOTILLEGAL();3.1656 - if( sh4r.t ) {3.1657 - CHECKDEST( sh4r.pc + disp + 4 )3.1658 - sh4r.in_delay_slot = 1;3.1659 - sh4r.pc = sh4r.new_pc;3.1660 - sh4r.new_pc = pc + disp + 4;3.1661 - sh4r.in_delay_slot = 1;3.1662 - return TRUE;3.1663 - }3.1664 - }3.1665 - break;3.1666 - case 0xF:3.1667 - { /* BF/S disp */3.1668 - int32_t disp = SIGNEXT8(ir&0xFF)<<1;3.1669 - CHECKSLOTILLEGAL();3.1670 - if( !sh4r.t ) {3.1671 - CHECKDEST( sh4r.pc + disp + 4 )3.1672 - sh4r.in_delay_slot = 1;3.1673 - sh4r.pc = sh4r.new_pc;3.1674 - sh4r.new_pc = pc + disp + 4;3.1675 - return TRUE;3.1676 - }3.1677 - }3.1678 - break;3.1679 - default:3.1680 - UNDEF();3.1681 - break;3.1682 - }3.1683 - break;3.1684 - case 0x9:3.1685 - { /* MOV.W @(disp, PC), Rn */3.1686 - uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1;3.1687 - CHECKSLOTILLEGAL();3.1688 - tmp = pc + 4 + disp;3.1689 - MEM_READ_WORD( tmp, sh4r.r[Rn] );3.1690 - }3.1691 - break;3.1692 - case 0xA:3.1693 - { /* BRA disp */3.1694 - int32_t disp = SIGNEXT12(ir&0xFFF)<<1;3.1695 - CHECKSLOTILLEGAL();3.1696 - CHECKDEST( sh4r.pc + disp + 4 );3.1697 - sh4r.in_delay_slot = 1;3.1698 - sh4r.pc = sh4r.new_pc;3.1699 - sh4r.new_pc = pc + 4 + disp;3.1700 - return TRUE;3.1701 - }3.1702 - break;3.1703 - case 0xB:3.1704 - { /* BSR disp */3.1705 - int32_t disp = SIGNEXT12(ir&0xFFF)<<1;3.1706 - CHECKDEST( sh4r.pc + disp + 4 );3.1707 - CHECKSLOTILLEGAL();3.1708 - sh4r.in_delay_slot = 1;3.1709 - sh4r.pr = pc + 4;3.1710 - sh4r.pc = sh4r.new_pc;3.1711 - sh4r.new_pc = pc + 4 + disp;3.1712 - TRACE_CALL( pc, sh4r.new_pc );3.1713 - return TRUE;3.1714 - }3.1715 - break;3.1716 - case 0xC:3.1717 - switch( (ir&0xF00) >> 8 ) {3.1718 - case 0x0:3.1719 - { /* MOV.B R0, @(disp, GBR) */3.1720 - uint32_t disp = (ir&0xFF);3.1721 - MEM_WRITE_BYTE( sh4r.gbr + disp, R0 );3.1722 - }3.1723 - break;3.1724 - case 0x1:3.1725 - { /* MOV.W R0, @(disp, GBR) */3.1726 - uint32_t disp = (ir&0xFF)<<1;3.1727 - tmp = sh4r.gbr + disp;3.1728 - CHECKWALIGN16( tmp );3.1729 - MEM_WRITE_WORD( tmp, R0 );3.1730 - }3.1731 - break;3.1732 - case 0x2:3.1733 - { /* MOV.L R0, @(disp, GBR) */3.1734 - uint32_t disp = (ir&0xFF)<<2;3.1735 - tmp = sh4r.gbr + disp;3.1736 - CHECKWALIGN32( tmp );3.1737 - MEM_WRITE_LONG( tmp, R0 );3.1738 - }3.1739 - break;3.1740 - case 0x3:3.1741 - { /* TRAPA #imm */3.1742 - uint32_t imm = (ir&0xFF);3.1743 - CHECKSLOTILLEGAL();3.1744 - sh4r.pc += 2;3.1745 - sh4_raise_trap( imm );3.1746 - return TRUE;3.1747 - }3.1748 - break;3.1749 - case 0x4:3.1750 - { /* MOV.B @(disp, GBR), R0 */3.1751 - uint32_t disp = (ir&0xFF);3.1752 - MEM_READ_BYTE( sh4r.gbr + disp, R0 );3.1753 - }3.1754 - break;3.1755 - case 0x5:3.1756 - { /* MOV.W @(disp, GBR), R0 */3.1757 - uint32_t disp = (ir&0xFF)<<1;3.1758 - tmp = sh4r.gbr + disp;3.1759 - CHECKRALIGN16( tmp );3.1760 - MEM_READ_WORD( tmp, R0 );3.1761 - }3.1762 - break;3.1763 - case 0x6:3.1764 - { /* MOV.L @(disp, GBR), R0 */3.1765 - uint32_t disp = (ir&0xFF)<<2;3.1766 - tmp = sh4r.gbr + disp;3.1767 - CHECKRALIGN32( tmp );3.1768 - MEM_READ_LONG( tmp, R0 );3.1769 - }3.1770 - break;3.1771 - case 0x7:3.1772 - { /* MOVA @(disp, PC), R0 */3.1773 - uint32_t disp = (ir&0xFF)<<2;3.1774 - CHECKSLOTILLEGAL();3.1775 - R0 = (pc&0xFFFFFFFC) + disp + 4;3.1776 - }3.1777 - break;3.1778 - case 0x8:3.1779 - { /* TST #imm, R0 */3.1780 - uint32_t imm = (ir&0xFF);3.1781 - sh4r.t = (R0 & imm ? 0 : 1);3.1782 - }3.1783 - break;3.1784 - case 0x9:3.1785 - { /* AND #imm, R0 */3.1786 - uint32_t imm = (ir&0xFF);3.1787 - R0 &= imm;3.1788 - }3.1789 - break;3.1790 - case 0xA:3.1791 - { /* XOR #imm, R0 */3.1792 - uint32_t imm = (ir&0xFF);3.1793 - R0 ^= imm;3.1794 - }3.1795 - break;3.1796 - case 0xB:3.1797 - { /* OR #imm, R0 */3.1798 - uint32_t imm = (ir&0xFF);3.1799 - R0 |= imm;3.1800 - }3.1801 - break;3.1802 - case 0xC:3.1803 - { /* TST.B #imm, @(R0, GBR) */3.1804 - uint32_t imm = (ir&0xFF);3.1805 - MEM_READ_BYTE(R0+sh4r.gbr, tmp); sh4r.t = ( tmp & imm ? 0 : 1 );3.1806 - }3.1807 - break;3.1808 - case 0xD:3.1809 - { /* AND.B #imm, @(R0, GBR) */3.1810 - uint32_t imm = (ir&0xFF);3.1811 - MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & tmp );3.1812 - }3.1813 - break;3.1814 - case 0xE:3.1815 - { /* XOR.B #imm, @(R0, GBR) */3.1816 - uint32_t imm = (ir&0xFF);3.1817 - MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ tmp );3.1818 - }3.1819 - break;3.1820 - case 0xF:3.1821 - { /* OR.B #imm, @(R0, GBR) */3.1822 - uint32_t imm = (ir&0xFF);3.1823 - MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | tmp );3.1824 - }3.1825 - break;3.1826 - }3.1827 - break;3.1828 - case 0xD:3.1829 - { /* MOV.L @(disp, PC), Rn */3.1830 - uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2;3.1831 - CHECKSLOTILLEGAL();3.1832 - tmp = (pc&0xFFFFFFFC) + disp + 4;3.1833 - MEM_READ_LONG( tmp, sh4r.r[Rn] );3.1834 - }3.1835 - break;3.1836 - case 0xE:3.1837 - { /* MOV #imm, Rn */3.1838 - uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);3.1839 - sh4r.r[Rn] = imm;3.1840 - }3.1841 - break;3.1842 - case 0xF:3.1843 - switch( ir&0xF ) {3.1844 - case 0x0:3.1845 - { /* FADD FRm, FRn */3.1846 - uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);3.1847 - CHECKFPUEN();3.1848 - if( IS_FPU_DOUBLEPREC() ) {3.1849 - DR(FRn) += DR(FRm);3.1850 - } else {3.1851 - FR(FRn) += FR(FRm);3.1852 - }3.1853 - }3.1854 - break;3.1855 - case 0x1:3.1856 - { /* FSUB FRm, FRn */3.1857 - uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);3.1858 - CHECKFPUEN();3.1859 - if( IS_FPU_DOUBLEPREC() ) {3.1860 - DR(FRn) -= DR(FRm);3.1861 - } else {3.1862 - FR(FRn) -= FR(FRm);3.1863 - }3.1864 - }3.1865 - break;3.1866 - case 0x2:3.1867 - { /* FMUL FRm, FRn */3.1868 - uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);3.1869 - CHECKFPUEN();3.1870 - if( IS_FPU_DOUBLEPREC() ) {3.1871 - DR(FRn) *= DR(FRm);3.1872 - } else {3.1873 - FR(FRn) *= FR(FRm);3.1874 - }3.1875 - }3.1876 - break;3.1877 - case 0x3:3.1878 - { /* FDIV FRm, FRn */3.1879 - uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);3.1880 - CHECKFPUEN();3.1881 - if( IS_FPU_DOUBLEPREC() ) {3.1882 - DR(FRn) /= DR(FRm);3.1883 - } else {3.1884 - FR(FRn) /= FR(FRm);3.1885 - }3.1886 - }3.1887 - break;3.1888 - case 0x4:3.1889 - { /* FCMP/EQ FRm, FRn */3.1890 - uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);3.1891 - CHECKFPUEN();3.1892 - if( IS_FPU_DOUBLEPREC() ) {3.1893 - sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );3.1894 - } else {3.1895 - sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );3.1896 - }3.1897 - }3.1898 - break;3.1899 - case 0x5:3.1900 - { /* FCMP/GT FRm, FRn */3.1901 - uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);3.1902 - CHECKFPUEN();3.1903 - if( IS_FPU_DOUBLEPREC() ) {3.1904 - sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );3.1905 - } else {3.1906 - sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );3.1907 - }3.1908 - }3.1909 - break;3.1910 - case 0x6:3.1911 - { /* FMOV @(R0, Rm), FRn */3.1912 - uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1913 - MEM_FP_READ( sh4r.r[Rm] + R0, FRn );3.1914 - }3.1915 - break;3.1916 - case 0x7:3.1917 - { /* FMOV FRm, @(R0, Rn) */3.1918 - uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);3.1919 - MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm );3.1920 - }3.1921 - break;3.1922 - case 0x8:3.1923 - { /* FMOV @Rm, FRn */3.1924 - uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1925 - MEM_FP_READ( sh4r.r[Rm], FRn );3.1926 - }3.1927 - break;3.1928 - case 0x9:3.1929 - { /* FMOV @Rm+, FRn */3.1930 - uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1931 - MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH;3.1932 - }3.1933 - break;3.1934 - case 0xA:3.1935 - { /* FMOV FRm, @Rn */3.1936 - uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);3.1937 - MEM_FP_WRITE( sh4r.r[Rn], FRm );3.1938 - }3.1939 - break;3.1940 - case 0xB:3.1941 - { /* FMOV FRm, @-Rn */3.1942 - uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);3.1943 - MEM_FP_WRITE( sh4r.r[Rn] - FP_WIDTH, FRm ); sh4r.r[Rn] -= FP_WIDTH;3.1944 - }3.1945 - break;3.1946 - case 0xC:3.1947 - { /* FMOV FRm, FRn */3.1948 - uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);3.1949 - if( IS_FPU_DOUBLESIZE() )3.1950 - DR(FRn) = DR(FRm);3.1951 - else3.1952 - FR(FRn) = FR(FRm);3.1953 - }3.1954 - break;3.1955 - case 0xD:3.1956 - switch( (ir&0xF0) >> 4 ) {3.1957 - case 0x0:3.1958 - { /* FSTS FPUL, FRn */3.1959 - uint32_t FRn = ((ir>>8)&0xF);3.1960 - CHECKFPUEN(); FR(FRn) = FPULf;3.1961 - }3.1962 - break;3.1963 - case 0x1:3.1964 - { /* FLDS FRm, FPUL */3.1965 - uint32_t FRm = ((ir>>8)&0xF);3.1966 - CHECKFPUEN(); FPULf = FR(FRm);3.1967 - }3.1968 - break;3.1969 - case 0x2:3.1970 - { /* FLOAT FPUL, FRn */3.1971 - uint32_t FRn = ((ir>>8)&0xF);3.1972 - CHECKFPUEN();3.1973 - if( IS_FPU_DOUBLEPREC() ) {3.1974 - if( FRn&1 ) { // No, really...3.1975 - dtmp = (double)FPULi;3.1976 - FR(FRn) = *(((float *)&dtmp)+1);3.1977 - } else {3.1978 - DRF(FRn>>1) = (double)FPULi;3.1979 - }3.1980 - } else {3.1981 - FR(FRn) = (float)FPULi;3.1982 - }3.1983 - }3.1984 - break;3.1985 - case 0x3:3.1986 - { /* FTRC FRm, FPUL */3.1987 - uint32_t FRm = ((ir>>8)&0xF);3.1988 - CHECKFPUEN();3.1989 - if( IS_FPU_DOUBLEPREC() ) {3.1990 - if( FRm&1 ) {3.1991 - dtmp = 0;3.1992 - *(((float *)&dtmp)+1) = FR(FRm);3.1993 - } else {3.1994 - dtmp = DRF(FRm>>1);3.1995 - }3.1996 - if( dtmp >= MAX_INTF )3.1997 - FPULi = MAX_INT;3.1998 - else if( dtmp <= MIN_INTF )3.1999 - FPULi = MIN_INT;3.2000 - else3.2001 - FPULi = (int32_t)dtmp;3.2002 - } else {3.2003 - ftmp = FR(FRm);3.2004 - if( ftmp >= MAX_INTF )3.2005 - FPULi = MAX_INT;3.2006 - else if( ftmp <= MIN_INTF )3.2007 - FPULi = MIN_INT;3.2008 - else3.2009 - FPULi = (int32_t)ftmp;3.2010 - }3.2011 - }3.2012 - break;3.2013 - case 0x4:3.2014 - { /* FNEG FRn */3.2015 - uint32_t FRn = ((ir>>8)&0xF);3.2016 - CHECKFPUEN();3.2017 - if( IS_FPU_DOUBLEPREC() ) {3.2018 - DR(FRn) = -DR(FRn);3.2019 - } else {3.2020 - FR(FRn) = -FR(FRn);3.2021 - }3.2022 - }3.2023 - break;3.2024 - case 0x5:3.2025 - { /* FABS FRn */3.2026 - uint32_t FRn = ((ir>>8)&0xF);3.2027 - CHECKFPUEN();3.2028 - if( IS_FPU_DOUBLEPREC() ) {3.2029 - DR(FRn) = fabs(DR(FRn));3.2030 - } else {3.2031 - FR(FRn) = fabsf(FR(FRn));3.2032 - }3.2033 - }3.2034 - break;3.2035 - case 0x6:3.2036 - { /* FSQRT FRn */3.2037 - uint32_t FRn = ((ir>>8)&0xF);3.2038 - CHECKFPUEN();3.2039 - if( IS_FPU_DOUBLEPREC() ) {3.2040 - DR(FRn) = sqrt(DR(FRn));3.2041 - } else {3.2042 - FR(FRn) = sqrtf(FR(FRn));3.2043 - }3.2044 - }3.2045 - break;3.2046 - case 0x7:3.2047 - { /* FSRRA FRn */3.2048 - uint32_t FRn = ((ir>>8)&0xF);3.2049 - CHECKFPUEN();3.2050 - if( !IS_FPU_DOUBLEPREC() ) {3.2051 - FR(FRn) = 1.0/sqrtf(FR(FRn));3.2052 - }3.2053 - }3.2054 - break;3.2055 - case 0x8:3.2056 - { /* FLDI0 FRn */3.2057 - uint32_t FRn = ((ir>>8)&0xF);3.2058 - CHECKFPUEN();3.2059 - if( IS_FPU_DOUBLEPREC() ) {3.2060 - DR(FRn) = 0.0;3.2061 - } else {3.2062 - FR(FRn) = 0.0;3.2063 - }3.2064 - }3.2065 - break;3.2066 - case 0x9:3.2067 - { /* FLDI1 FRn */3.2068 - uint32_t FRn = ((ir>>8)&0xF);3.2069 - CHECKFPUEN();3.2070 - if( IS_FPU_DOUBLEPREC() ) {3.2071 - DR(FRn) = 1.0;3.2072 - } else {3.2073 - FR(FRn) = 1.0;3.2074 - }3.2075 - }3.2076 - break;3.2077 - case 0xA:3.2078 - { /* FCNVSD FPUL, FRn */3.2079 - uint32_t FRn = ((ir>>8)&0xF);3.2080 - CHECKFPUEN();3.2081 - if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {3.2082 - DR(FRn) = (double)FPULf;3.2083 - }3.2084 - }3.2085 - break;3.2086 - case 0xB:3.2087 - { /* FCNVDS FRm, FPUL */3.2088 - uint32_t FRm = ((ir>>8)&0xF);3.2089 - CHECKFPUEN();3.2090 - if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {3.2091 - FPULf = (float)DR(FRm);3.2092 - }3.2093 - }3.2094 - break;3.2095 - case 0xE:3.2096 - { /* FIPR FVm, FVn */3.2097 - uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3);3.2098 - CHECKFPUEN();3.2099 - if( !IS_FPU_DOUBLEPREC() ) {3.2100 - int tmp2 = FVn<<2;3.2101 - tmp = FVm<<2;3.2102 - FR(tmp2+3) = FR(tmp)*FR(tmp2) +3.2103 - FR(tmp+1)*FR(tmp2+1) +3.2104 - FR(tmp+2)*FR(tmp2+2) +3.2105 - FR(tmp+3)*FR(tmp2+3);3.2106 - }3.2107 - }3.2108 - break;3.2109 - case 0xF:3.2110 - switch( (ir&0x100) >> 8 ) {3.2111 - case 0x0:3.2112 - { /* FSCA FPUL, FRn */3.2113 - uint32_t FRn = ((ir>>9)&0x7)<<1;3.2114 - CHECKFPUEN();3.2115 - if( !IS_FPU_DOUBLEPREC() ) {3.2116 - sh4_fsca( FPULi, &(DRF(FRn>>1)) );3.2117 - /*3.2118 - float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;3.2119 - FR(FRn) = sinf(angle);3.2120 - FR((FRn)+1) = cosf(angle);3.2121 - */3.2122 - }3.2123 - }3.2124 - break;3.2125 - case 0x1:3.2126 - switch( (ir&0x200) >> 9 ) {3.2127 - case 0x0:3.2128 - { /* FTRV XMTRX, FVn */3.2129 - uint32_t FVn = ((ir>>10)&0x3);3.2130 - CHECKFPUEN();3.2131 - if( !IS_FPU_DOUBLEPREC() ) {3.2132 - sh4_ftrv(&(DRF(FVn<<1)) );3.2133 - }3.2134 - }3.2135 - break;3.2136 - case 0x1:3.2137 - switch( (ir&0xC00) >> 10 ) {3.2138 - case 0x0:3.2139 - { /* FSCHG */3.2140 - CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ;3.2141 - }3.2142 - break;3.2143 - case 0x2:3.2144 - { /* FRCHG */3.2145 - CHECKFPUEN();3.2146 - sh4r.fpscr ^= FPSCR_FR;3.2147 - sh4_switch_fr_banks();3.2148 - }3.2149 - break;3.2150 - case 0x3:3.2151 - { /* UNDEF */3.2152 - UNDEF(ir);3.2153 - }3.2154 - break;3.2155 - default:3.2156 - UNDEF();3.2157 - break;3.2158 - }3.2159 - break;3.2160 - }3.2161 - break;3.2162 - }3.2163 - break;3.2164 - default:3.2165 - UNDEF();3.2166 - break;3.2167 - }3.2168 - break;3.2169 - case 0xE:3.2170 - { /* FMAC FR0, FRm, FRn */3.2171 - uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);3.2172 - CHECKFPUEN();3.2173 - if( IS_FPU_DOUBLEPREC() ) {3.2174 - DR(FRn) += DR(FRm)*DR(0);3.2175 - } else {3.2176 - FR(FRn) += FR(FRm)*FR(0);3.2177 - }3.2178 - }3.2179 - break;3.2180 - default:3.2181 - UNDEF();3.2182 - break;3.2183 - }3.2184 - break;3.2185 - }3.2186 -3.2187 - sh4r.pc = sh4r.new_pc;3.2188 - sh4r.new_pc += 2;3.2189 - sh4r.in_delay_slot = 0;3.2190 - return TRUE;3.2191 -}
4.1 --- a/src/sh4/sh4dasm.c Sat Jul 19 02:34:11 2008 +00004.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +00004.3 @@ -1,1571 +0,0 @@4.4 -/**4.5 - * $Id$4.6 - *4.7 - * SH4 CPU definition and disassembly functions4.8 - *4.9 - * Copyright (c) 2005 Nathan Keynes.4.10 - *4.11 - * This program is free software; you can redistribute it and/or modify4.12 - * it under the terms of the GNU General Public License as published by4.13 - * the Free Software Foundation; either version 2 of the License, or4.14 - * (at your option) any later version.4.15 - *4.16 - * This program is distributed in the hope that it will be useful,4.17 - * but WITHOUT ANY WARRANTY; without even the implied warranty of4.18 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the4.19 - * GNU General Public License for more details.4.20 - */4.21 -4.22 -#include "sh4/sh4core.h"4.23 -#include "sh4/sh4dasm.h"4.24 -#include "mem.h"4.25 -4.26 -#define UNIMP(ir) snprintf( buf, len, "??? " )4.27 -4.28 -4.29 -const struct reg_desc_struct sh4_reg_map[] =4.30 - { {"R0", REG_INT, &sh4r.r[0]}, {"R1", REG_INT, &sh4r.r[1]},4.31 - {"R2", REG_INT, &sh4r.r[2]}, {"R3", REG_INT, &sh4r.r[3]},4.32 - {"R4", REG_INT, &sh4r.r[4]}, {"R5", REG_INT, &sh4r.r[5]},4.33 - {"R6", REG_INT, &sh4r.r[6]}, {"R7", REG_INT, &sh4r.r[7]},4.34 - {"R8", REG_INT, &sh4r.r[8]}, {"R9", REG_INT, &sh4r.r[9]},4.35 - {"R10",REG_INT, &sh4r.r[10]}, {"R11",REG_INT, &sh4r.r[11]},4.36 - {"R12",REG_INT, &sh4r.r[12]}, {"R13",REG_INT, &sh4r.r[13]},4.37 - {"R14",REG_INT, &sh4r.r[14]}, {"R15",REG_INT, &sh4r.r[15]},4.38 - {"SR", REG_INT, &sh4r.sr}, {"GBR", REG_INT, &sh4r.gbr},4.39 - {"SSR",REG_INT, &sh4r.ssr}, {"SPC", REG_INT, &sh4r.spc},4.40 - {"SGR",REG_INT, &sh4r.sgr}, {"DBR", REG_INT, &sh4r.dbr},4.41 - {"VBR",REG_INT, &sh4r.vbr},4.42 - {"PC", REG_INT, &sh4r.pc}, {"PR", REG_INT, &sh4r.pr},4.43 - {"MACL",REG_INT, &sh4r.mac},{"MACH",REG_INT, ((uint32_t *)&sh4r.mac)+1},4.44 - {"FPUL", REG_INT, &sh4r.fpul.i}, {"FPSCR", REG_INT, &sh4r.fpscr},4.45 - {NULL, 0, NULL} };4.46 -4.47 -4.48 -const struct cpu_desc_struct sh4_cpu_desc =4.49 - { "SH4", sh4_disasm_instruction, sh4_execute_instruction, sh4_has_page,4.50 - sh4_set_breakpoint, sh4_clear_breakpoint, sh4_get_breakpoint, 2,4.51 - (char *)&sh4r, sizeof(sh4r), sh4_reg_map,4.52 - &sh4r.pc };4.53 -4.54 -uint32_t sh4_disasm_instruction( sh4vma_t pc, char *buf, int len, char *opcode )4.55 -{4.56 - sh4addr_t addr = mmu_vma_to_phys_disasm(pc);4.57 - uint16_t ir = sh4_read_word(addr);4.58 -4.59 -#define UNDEF(ir) snprintf( buf, len, "???? " );4.60 -#define RN(ir) ((ir&0x0F00)>>8)4.61 -#define RN_BANK(ir) ((ir&0x0070)>>4)4.62 -#define RM(ir) ((ir&0x00F0)>>4)4.63 -#define DISP4(ir) (ir&0x000F) /* 4-bit displacements are *not* sign extended */4.64 -#define DISP8(ir) (ir&0x00FF)4.65 -#define PCDISP8(ir) SIGNEXT8(ir&0x00FF)4.66 -#define UIMM8(ir) (ir&0x00FF)4.67 -#define IMM8(ir) SIGNEXT8(ir&0x00FF)4.68 -#define DISP12(ir) SIGNEXT12(ir&0x0FFF)4.69 -#define FVN(ir) ((ir&0x0C00)>>10)4.70 -#define FVM(ir) ((ir&0x0300)>>8)4.71 -4.72 - sprintf( opcode, "%02X %02X", ir&0xFF, ir>>8 );4.73 -4.74 - switch( (ir&0xF000) >> 12 ) {4.75 - case 0x0:4.76 - switch( ir&0xF ) {4.77 - case 0x2:4.78 - switch( (ir&0x80) >> 7 ) {4.79 - case 0x0:4.80 - switch( (ir&0x70) >> 4 ) {4.81 - case 0x0:4.82 - { /* STC SR, Rn */4.83 - uint32_t Rn = ((ir>>8)&0xF);4.84 - snprintf( buf, len, "STC SR, R%d", Rn );4.85 - }4.86 - break;4.87 - case 0x1:4.88 - { /* STC GBR, Rn */4.89 - uint32_t Rn = ((ir>>8)&0xF);4.90 - snprintf( buf, len, "STC GBR, R%d", Rn );4.91 - }4.92 - break;4.93 - case 0x2:4.94 - { /* STC VBR, Rn */4.95 - uint32_t Rn = ((ir>>8)&0xF);4.96 - snprintf( buf, len, "STC VBR, R%d", Rn );4.97 - }4.98 - break;4.99 - case 0x3:4.100 - { /* STC SSR, Rn */4.101 - uint32_t Rn = ((ir>>8)&0xF);4.102 - snprintf( buf, len, "STC SSR, R%d", Rn );4.103 - }4.104 - break;4.105 - case 0x4:4.106 - { /* STC SPC, Rn */4.107 - uint32_t Rn = ((ir>>8)&0xF);4.108 - snprintf( buf, len, "STC SPC, R%d", Rn );4.109 - }4.110 - break;4.111 - default:4.112 - UNDEF();4.113 - break;4.114 - }4.115 - break;4.116 - case 0x1:4.117 - { /* STC Rm_BANK, Rn */4.118 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);4.119 - snprintf( buf, len, "STC R%d_BANK, R%d", Rm_BANK, Rn );4.120 - }4.121 - break;4.122 - }4.123 - break;4.124 - case 0x3:4.125 - switch( (ir&0xF0) >> 4 ) {4.126 - case 0x0:4.127 - { /* BSRF Rn */4.128 - uint32_t Rn = ((ir>>8)&0xF);4.129 - snprintf( buf, len, "BSRF R%d", Rn );4.130 - }4.131 - break;4.132 - case 0x2:4.133 - { /* BRAF Rn */4.134 - uint32_t Rn = ((ir>>8)&0xF);4.135 - snprintf( buf, len, "BRAF R%d", Rn );4.136 - }4.137 - break;4.138 - case 0x8:4.139 - { /* PREF @Rn */4.140 - uint32_t Rn = ((ir>>8)&0xF);4.141 - snprintf( buf, len, "PREF R%d", Rn );4.142 - }4.143 - break;4.144 - case 0x9:4.145 - { /* OCBI @Rn */4.146 - uint32_t Rn = ((ir>>8)&0xF);4.147 - snprintf( buf, len, "OCBI @R%d", Rn );4.148 - }4.149 - break;4.150 - case 0xA:4.151 - { /* OCBP @Rn */4.152 - uint32_t Rn = ((ir>>8)&0xF);4.153 - snprintf( buf, len, "OCBP @R%d", Rn );4.154 - }4.155 - break;4.156 - case 0xB:4.157 - { /* OCBWB @Rn */4.158 - uint32_t Rn = ((ir>>8)&0xF);4.159 - snprintf( buf, len, "OCBWB @R%d", Rn );4.160 - }4.161 - break;4.162 - case 0xC:4.163 - { /* MOVCA.L R0, @Rn */4.164 - uint32_t Rn = ((ir>>8)&0xF);4.165 - snprintf( buf, len, "MOVCA.L R0, @R%d", Rn );4.166 - }4.167 - break;4.168 - default:4.169 - UNDEF();4.170 - break;4.171 - }4.172 - break;4.173 - case 0x4:4.174 - { /* MOV.B Rm, @(R0, Rn) */4.175 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.176 - snprintf( buf, len, "MOV.B R%d, @(R0, R%d)", Rm, Rn );4.177 - }4.178 - break;4.179 - case 0x5:4.180 - { /* MOV.W Rm, @(R0, Rn) */4.181 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.182 - snprintf( buf, len, "MOV.W R%d, @(R0, R%d)", Rm, Rn );4.183 - }4.184 - break;4.185 - case 0x6:4.186 - { /* MOV.L Rm, @(R0, Rn) */4.187 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.188 - snprintf( buf, len, "MOV.L R%d, @(R0, R%d)", Rm, Rn );4.189 - }4.190 - break;4.191 - case 0x7:4.192 - { /* MUL.L Rm, Rn */4.193 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.194 - snprintf( buf, len, "MUL.L R%d, R%d", Rm, Rn );4.195 - }4.196 - break;4.197 - case 0x8:4.198 - switch( (ir&0xFF0) >> 4 ) {4.199 - case 0x0:4.200 - { /* CLRT */4.201 - snprintf( buf, len, "CLRT " );4.202 - }4.203 - break;4.204 - case 0x1:4.205 - { /* SETT */4.206 - snprintf( buf, len, "SETT " );4.207 - }4.208 - break;4.209 - case 0x2:4.210 - { /* CLRMAC */4.211 - snprintf( buf, len, "CLRMAC " );4.212 - }4.213 - break;4.214 - case 0x3:4.215 - { /* LDTLB */4.216 - snprintf( buf, len, "LDTLB " );4.217 - }4.218 - break;4.219 - case 0x4:4.220 - { /* CLRS */4.221 - snprintf( buf, len, "CLRS " );4.222 - }4.223 - break;4.224 - case 0x5:4.225 - { /* SETS */4.226 - snprintf( buf, len, "SETS " );4.227 - }4.228 - break;4.229 - default:4.230 - UNDEF();4.231 - break;4.232 - }4.233 - break;4.234 - case 0x9:4.235 - switch( (ir&0xF0) >> 4 ) {4.236 - case 0x0:4.237 - { /* NOP */4.238 - snprintf( buf, len, "NOP " );4.239 - }4.240 - break;4.241 - case 0x1:4.242 - { /* DIV0U */4.243 - snprintf( buf, len, "DIV0U " );4.244 - }4.245 - break;4.246 - case 0x2:4.247 - { /* MOVT Rn */4.248 - uint32_t Rn = ((ir>>8)&0xF);4.249 - snprintf( buf, len, "MOVT R%d", Rn );4.250 - }4.251 - break;4.252 - default:4.253 - UNDEF();4.254 - break;4.255 - }4.256 - break;4.257 - case 0xA:4.258 - switch( (ir&0xF0) >> 4 ) {4.259 - case 0x0:4.260 - { /* STS MACH, Rn */4.261 - uint32_t Rn = ((ir>>8)&0xF);4.262 - snprintf( buf, len, "STS MACH, R%d", Rn );4.263 - }4.264 - break;4.265 - case 0x1:4.266 - { /* STS MACL, Rn */4.267 - uint32_t Rn = ((ir>>8)&0xF);4.268 - snprintf( buf, len, "STS MACL, R%d", Rn );4.269 - }4.270 - break;4.271 - case 0x2:4.272 - { /* STS PR, Rn */4.273 - uint32_t Rn = ((ir>>8)&0xF);4.274 - snprintf( buf, len, "STS PR, R%d", Rn );4.275 - }4.276 - break;4.277 - case 0x3:4.278 - { /* STC SGR, Rn */4.279 - uint32_t Rn = ((ir>>8)&0xF);4.280 - snprintf( buf, len, "STC SGR, R%d", Rn );4.281 - }4.282 - break;4.283 - case 0x5:4.284 - { /* STS FPUL, Rn */4.285 - uint32_t Rn = ((ir>>8)&0xF);4.286 - snprintf( buf, len, "STS FPUL, R%d", Rn );4.287 - }4.288 - break;4.289 - case 0x6:4.290 - { /* STS FPSCR, Rn */4.291 - uint32_t Rn = ((ir>>8)&0xF);4.292 - snprintf( buf, len, "STS FPSCR, R%d", Rn );4.293 - }4.294 - break;4.295 - case 0xF:4.296 - { /* STC DBR, Rn */4.297 - uint32_t Rn = ((ir>>8)&0xF);4.298 - snprintf( buf, len, "STC DBR, R%d", Rn );4.299 - }4.300 - break;4.301 - default:4.302 - UNDEF();4.303 - break;4.304 - }4.305 - break;4.306 - case 0xB:4.307 - switch( (ir&0xFF0) >> 4 ) {4.308 - case 0x0:4.309 - { /* RTS */4.310 - snprintf( buf, len, "RTS " );4.311 - }4.312 - break;4.313 - case 0x1:4.314 - { /* SLEEP */4.315 - snprintf( buf, len, "SLEEP " );4.316 - }4.317 - break;4.318 - case 0x2:4.319 - { /* RTE */4.320 - snprintf( buf, len, "RTE " );4.321 - }4.322 - break;4.323 - default:4.324 - UNDEF();4.325 - break;4.326 - }4.327 - break;4.328 - case 0xC:4.329 - { /* MOV.B @(R0, Rm), Rn */4.330 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.331 - snprintf( buf, len, "MOV.B @(R0, R%d), R%d", Rm, Rn );4.332 - }4.333 - break;4.334 - case 0xD:4.335 - { /* MOV.W @(R0, Rm), Rn */4.336 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.337 - snprintf( buf, len, "MOV.W @(R0, R%d), R%d", Rm, Rn );4.338 - }4.339 - break;4.340 - case 0xE:4.341 - { /* MOV.L @(R0, Rm), Rn */4.342 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.343 - snprintf( buf, len, "MOV.L @(R0, R%d), R%d", Rm, Rn );4.344 - }4.345 - break;4.346 - case 0xF:4.347 - { /* MAC.L @Rm+, @Rn+ */4.348 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.349 - snprintf( buf, len, "MAC.L @R%d+, @R%d+", Rm, Rn );4.350 - }4.351 - break;4.352 - default:4.353 - UNDEF();4.354 - break;4.355 - }4.356 - break;4.357 - case 0x1:4.358 - { /* MOV.L Rm, @(disp, Rn) */4.359 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;4.360 - snprintf( buf, len, "MOV.L R%d, @(%d, R%d)", Rm, disp, Rn );4.361 - }4.362 - break;4.363 - case 0x2:4.364 - switch( ir&0xF ) {4.365 - case 0x0:4.366 - { /* MOV.B Rm, @Rn */4.367 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.368 - snprintf( buf, len, "MOV.B R%d, @R%d", Rm, Rn );4.369 - }4.370 - break;4.371 - case 0x1:4.372 - { /* MOV.W Rm, @Rn */4.373 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.374 - snprintf( buf, len, "MOV.W R%d, @R%d", Rm, Rn );4.375 - }4.376 - break;4.377 - case 0x2:4.378 - { /* MOV.L Rm, @Rn */4.379 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.380 - snprintf( buf, len, "MOV.L R%d, @R%d", Rm, Rn );4.381 - }4.382 - break;4.383 - case 0x4:4.384 - { /* MOV.B Rm, @-Rn */4.385 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.386 - snprintf( buf, len, "MOV.B R%d, @-R%d", Rm, Rn );4.387 - }4.388 - break;4.389 - case 0x5:4.390 - { /* MOV.W Rm, @-Rn */4.391 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.392 - snprintf( buf, len, "MOV.W R%d, @-R%d", Rm, Rn );4.393 - }4.394 - break;4.395 - case 0x6:4.396 - { /* MOV.L Rm, @-Rn */4.397 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.398 - snprintf( buf, len, "MOV.L R%d, @-R%d", Rm, Rn );4.399 - }4.400 - break;4.401 - case 0x7:4.402 - { /* DIV0S Rm, Rn */4.403 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.404 - snprintf( buf, len, "DIV0S R%d, R%d", Rm, Rn );4.405 - }4.406 - break;4.407 - case 0x8:4.408 - { /* TST Rm, Rn */4.409 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.410 - snprintf( buf, len, "TST R%d, R%d", Rm, Rn );4.411 - }4.412 - break;4.413 - case 0x9:4.414 - { /* AND Rm, Rn */4.415 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.416 - snprintf( buf, len, "AND R%d, R%d", Rm, Rn );4.417 - }4.418 - break;4.419 - case 0xA:4.420 - { /* XOR Rm, Rn */4.421 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.422 - snprintf( buf, len, "XOR R%d, R%d", Rm, Rn );4.423 - }4.424 - break;4.425 - case 0xB:4.426 - { /* OR Rm, Rn */4.427 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.428 - snprintf( buf, len, "OR R%d, R%d", Rm, Rn );4.429 - }4.430 - break;4.431 - case 0xC:4.432 - { /* CMP/STR Rm, Rn */4.433 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.434 - snprintf( buf, len, "CMP/STR R%d, R%d", Rm, Rn );4.435 - }4.436 - break;4.437 - case 0xD:4.438 - { /* XTRCT Rm, Rn */4.439 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.440 - snprintf( buf, len, "XTRCT R%d, R%d", Rm, Rn );4.441 - }4.442 - break;4.443 - case 0xE:4.444 - { /* MULU.W Rm, Rn */4.445 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.446 - snprintf( buf, len, "MULU.W R%d, R%d", Rm, Rn );4.447 - }4.448 - break;4.449 - case 0xF:4.450 - { /* MULS.W Rm, Rn */4.451 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.452 - snprintf( buf, len, "MULS.W R%d, R%d", Rm, Rn );4.453 - }4.454 - break;4.455 - default:4.456 - UNDEF();4.457 - break;4.458 - }4.459 - break;4.460 - case 0x3:4.461 - switch( ir&0xF ) {4.462 - case 0x0:4.463 - { /* CMP/EQ Rm, Rn */4.464 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.465 - snprintf( buf, len, "CMP/EQ R%d, R%d", Rm, Rn );4.466 - }4.467 - break;4.468 - case 0x2:4.469 - { /* CMP/HS Rm, Rn */4.470 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.471 - snprintf( buf, len, "CMP/HS R%d, R%d", Rm, Rn );4.472 - }4.473 - break;4.474 - case 0x3:4.475 - { /* CMP/GE Rm, Rn */4.476 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.477 - snprintf( buf, len, "CMP/GE R%d, R%d", Rm, Rn );4.478 - }4.479 - break;4.480 - case 0x4:4.481 - { /* DIV1 Rm, Rn */4.482 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.483 - snprintf( buf, len, "DIV1 R%d, R%d", Rm, Rn );4.484 - }4.485 - break;4.486 - case 0x5:4.487 - { /* DMULU.L Rm, Rn */4.488 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.489 - snprintf( buf, len, "DMULU.L R%d, R%d", Rm, Rn );4.490 - }4.491 - break;4.492 - case 0x6:4.493 - { /* CMP/HI Rm, Rn */4.494 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.495 - snprintf( buf, len, "CMP/HI R%d, R%d", Rm, Rn );4.496 - }4.497 - break;4.498 - case 0x7:4.499 - { /* CMP/GT Rm, Rn */4.500 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.501 - snprintf( buf, len, "CMP/GT R%d, R%d", Rm, Rn );4.502 - }4.503 - break;4.504 - case 0x8:4.505 - { /* SUB Rm, Rn */4.506 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.507 - snprintf( buf, len, "SUB R%d, R%d", Rm, Rn );4.508 - }4.509 - break;4.510 - case 0xA:4.511 - { /* SUBC Rm, Rn */4.512 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.513 - snprintf( buf, len, "SUBC R%d, R%d", Rm, Rn );4.514 - }4.515 - break;4.516 - case 0xB:4.517 - { /* SUBV Rm, Rn */4.518 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.519 - snprintf( buf, len, "SUBV R%d, R%d", Rm, Rn );4.520 - }4.521 - break;4.522 - case 0xC:4.523 - { /* ADD Rm, Rn */4.524 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.525 - snprintf( buf, len, "ADD R%d, R%d", Rm, Rn );4.526 - }4.527 - break;4.528 - case 0xD:4.529 - { /* DMULS.L Rm, Rn */4.530 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.531 - snprintf( buf, len, "DMULS.L R%d, R%d", Rm, Rn );4.532 - }4.533 - break;4.534 - case 0xE:4.535 - { /* ADDC Rm, Rn */4.536 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.537 - snprintf( buf, len, "ADDC R%d, R%d", Rm, Rn );4.538 - }4.539 - break;4.540 - case 0xF:4.541 - { /* ADDV Rm, Rn */4.542 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.543 - snprintf( buf, len, "ADDV R%d, R%d", Rm, Rn );4.544 - }4.545 - break;4.546 - default:4.547 - UNDEF();4.548 - break;4.549 - }4.550 - break;4.551 - case 0x4:4.552 - switch( ir&0xF ) {4.553 - case 0x0:4.554 - switch( (ir&0xF0) >> 4 ) {4.555 - case 0x0:4.556 - { /* SHLL Rn */4.557 - uint32_t Rn = ((ir>>8)&0xF);4.558 - snprintf( buf, len, "SHLL R%d", Rn );4.559 - }4.560 - break;4.561 - case 0x1:4.562 - { /* DT Rn */4.563 - uint32_t Rn = ((ir>>8)&0xF);4.564 - snprintf( buf, len, "DT R%d", Rn );4.565 - }4.566 - break;4.567 - case 0x2:4.568 - { /* SHAL Rn */4.569 - uint32_t Rn = ((ir>>8)&0xF);4.570 - snprintf( buf, len, "SHAL R%d", Rn );4.571 - }4.572 - break;4.573 - default:4.574 - UNDEF();4.575 - break;4.576 - }4.577 - break;4.578 - case 0x1:4.579 - switch( (ir&0xF0) >> 4 ) {4.580 - case 0x0:4.581 - { /* SHLR Rn */4.582 - uint32_t Rn = ((ir>>8)&0xF);4.583 - snprintf( buf, len, "SHLR R%d", Rn );4.584 - }4.585 - break;4.586 - case 0x1:4.587 - { /* CMP/PZ Rn */4.588 - uint32_t Rn = ((ir>>8)&0xF);4.589 - snprintf( buf, len, "CMP/PZ R%d", Rn );4.590 - }4.591 - break;4.592 - case 0x2:4.593 - { /* SHAR Rn */4.594 - uint32_t Rn = ((ir>>8)&0xF);4.595 - snprintf( buf, len, "SHAR R%d", Rn );4.596 - }4.597 - break;4.598 - default:4.599 - UNDEF();4.600 - break;4.601 - }4.602 - break;4.603 - case 0x2:4.604 - switch( (ir&0xF0) >> 4 ) {4.605 - case 0x0:4.606 - { /* STS.L MACH, @-Rn */4.607 - uint32_t Rn = ((ir>>8)&0xF);4.608 - snprintf( buf, len, "STS.L MACH, @-R%d", Rn );4.609 - }4.610 - break;4.611 - case 0x1:4.612 - { /* STS.L MACL, @-Rn */4.613 - uint32_t Rn = ((ir>>8)&0xF);4.614 - snprintf( buf, len, "STS.L MACL, @-R%d", Rn );4.615 - }4.616 - break;4.617 - case 0x2:4.618 - { /* STS.L PR, @-Rn */4.619 - uint32_t Rn = ((ir>>8)&0xF);4.620 - snprintf( buf, len, "STS.L PR, @-R%d", Rn );4.621 - }4.622 - break;4.623 - case 0x3:4.624 - { /* STC.L SGR, @-Rn */4.625 - uint32_t Rn = ((ir>>8)&0xF);4.626 - snprintf( buf, len, "STC.L SGR, @-R%d", Rn );4.627 - }4.628 - break;4.629 - case 0x5:4.630 - { /* STS.L FPUL, @-Rn */4.631 - uint32_t Rn = ((ir>>8)&0xF);4.632 - snprintf( buf, len, "STS.L FPUL, @-R%d", Rn );4.633 - }4.634 - break;4.635 - case 0x6:4.636 - { /* STS.L FPSCR, @-Rn */4.637 - uint32_t Rn = ((ir>>8)&0xF);4.638 - snprintf( buf, len, "STS.L FPSCR, @-R%d", Rn );4.639 - }4.640 - break;4.641 - case 0xF:4.642 - { /* STC.L DBR, @-Rn */4.643 - uint32_t Rn = ((ir>>8)&0xF);4.644 - snprintf( buf, len, "STC.L DBR, @-R%d", Rn );4.645 - }4.646 - break;4.647 - default:4.648 - UNDEF();4.649 - break;4.650 - }4.651 - break;4.652 - case 0x3:4.653 - switch( (ir&0x80) >> 7 ) {4.654 - case 0x0:4.655 - switch( (ir&0x70) >> 4 ) {4.656 - case 0x0:4.657 - { /* STC.L SR, @-Rn */4.658 - uint32_t Rn = ((ir>>8)&0xF);4.659 - snprintf( buf, len, "STC.L SR, @-R%d", Rn );4.660 - }4.661 - break;4.662 - case 0x1:4.663 - { /* STC.L GBR, @-Rn */4.664 - uint32_t Rn = ((ir>>8)&0xF);4.665 - snprintf( buf, len, "STC.L GBR, @-R%d", Rn );4.666 - }4.667 - break;4.668 - case 0x2:4.669 - { /* STC.L VBR, @-Rn */4.670 - uint32_t Rn = ((ir>>8)&0xF);4.671 - snprintf( buf, len, "STC.L VBR, @-R%d", Rn );4.672 - }4.673 - break;4.674 - case 0x3:4.675 - { /* STC.L SSR, @-Rn */4.676 - uint32_t Rn = ((ir>>8)&0xF);4.677 - snprintf( buf, len, "STC.L SSR, @-R%d", Rn );4.678 - }4.679 - break;4.680 - case 0x4:4.681 - { /* STC.L SPC, @-Rn */4.682 - uint32_t Rn = ((ir>>8)&0xF);4.683 - snprintf( buf, len, "STC.L SPC, @-R%d", Rn );4.684 - }4.685 - break;4.686 - default:4.687 - UNDEF();4.688 - break;4.689 - }4.690 - break;4.691 - case 0x1:4.692 - { /* STC.L Rm_BANK, @-Rn */4.693 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);4.694 - snprintf( buf, len, "STC.L @-R%d_BANK, @-R%d", Rm_BANK, Rn );4.695 - }4.696 - break;4.697 - }4.698 - break;4.699 - case 0x4:4.700 - switch( (ir&0xF0) >> 4 ) {4.701 - case 0x0:4.702 - { /* ROTL Rn */4.703 - uint32_t Rn = ((ir>>8)&0xF);4.704 - snprintf( buf, len, "ROTL R%d", Rn );4.705 - }4.706 - break;4.707 - case 0x2:4.708 - { /* ROTCL Rn */4.709 - uint32_t Rn = ((ir>>8)&0xF);4.710 - snprintf( buf, len, "ROTCL R%d", Rn );4.711 - }4.712 - break;4.713 - default:4.714 - UNDEF();4.715 - break;4.716 - }4.717 - break;4.718 - case 0x5:4.719 - switch( (ir&0xF0) >> 4 ) {4.720 - case 0x0:4.721 - { /* ROTR Rn */4.722 - uint32_t Rn = ((ir>>8)&0xF);4.723 - snprintf( buf, len, "ROTR R%d", Rn );4.724 - }4.725 - break;4.726 - case 0x1:4.727 - { /* CMP/PL Rn */4.728 - uint32_t Rn = ((ir>>8)&0xF);4.729 - snprintf( buf, len, "CMP/PL R%d", Rn );4.730 - }4.731 - break;4.732 - case 0x2:4.733 - { /* ROTCR Rn */4.734 - uint32_t Rn = ((ir>>8)&0xF);4.735 - snprintf( buf, len, "ROTCR R%d", Rn );4.736 - }4.737 - break;4.738 - default:4.739 - UNDEF();4.740 - break;4.741 - }4.742 - break;4.743 - case 0x6:4.744 - switch( (ir&0xF0) >> 4 ) {4.745 - case 0x0:4.746 - { /* LDS.L @Rm+, MACH */4.747 - uint32_t Rm = ((ir>>8)&0xF);4.748 - snprintf( buf, len, "LDS.L @R%d+, MACH", Rm );4.749 - }4.750 - break;4.751 - case 0x1:4.752 - { /* LDS.L @Rm+, MACL */4.753 - uint32_t Rm = ((ir>>8)&0xF);4.754 - snprintf( buf, len, "LDS.L @R%d+, MACL", Rm );4.755 - }4.756 - break;4.757 - case 0x2:4.758 - { /* LDS.L @Rm+, PR */4.759 - uint32_t Rm = ((ir>>8)&0xF);4.760 - snprintf( buf, len, "LDS.L @R%d+, PR", Rm );4.761 - }4.762 - break;4.763 - case 0x3:4.764 - { /* LDC.L @Rm+, SGR */4.765 - uint32_t Rm = ((ir>>8)&0xF);4.766 - snprintf( buf, len, "LDC.L @R%d+, SGR", Rm );4.767 - }4.768 - break;4.769 - case 0x5:4.770 - { /* LDS.L @Rm+, FPUL */4.771 - uint32_t Rm = ((ir>>8)&0xF);4.772 - snprintf( buf, len, "LDS.L @R%d+, FPUL", Rm );4.773 - }4.774 - break;4.775 - case 0x6:4.776 - { /* LDS.L @Rm+, FPSCR */4.777 - uint32_t Rm = ((ir>>8)&0xF);4.778 - snprintf( buf, len, "LDS.L @R%d+, FPSCR", Rm );4.779 - }4.780 - break;4.781 - case 0xF:4.782 - { /* LDC.L @Rm+, DBR */4.783 - uint32_t Rm = ((ir>>8)&0xF);4.784 - snprintf( buf, len, "LDC.L @R%d+, DBR", Rm );4.785 - }4.786 - break;4.787 - default:4.788 - UNDEF();4.789 - break;4.790 - }4.791 - break;4.792 - case 0x7:4.793 - switch( (ir&0x80) >> 7 ) {4.794 - case 0x0:4.795 - switch( (ir&0x70) >> 4 ) {4.796 - case 0x0:4.797 - { /* LDC.L @Rm+, SR */4.798 - uint32_t Rm = ((ir>>8)&0xF);4.799 - snprintf( buf, len, "LDC.L @R%d+, SR", Rm );4.800 - }4.801 - break;4.802 - case 0x1:4.803 - { /* LDC.L @Rm+, GBR */4.804 - uint32_t Rm = ((ir>>8)&0xF);4.805 - snprintf( buf, len, "LDC.L @R%d+, GBR", Rm );4.806 - }4.807 - break;4.808 - case 0x2:4.809 - { /* LDC.L @Rm+, VBR */4.810 - uint32_t Rm = ((ir>>8)&0xF);4.811 - snprintf( buf, len, "LDC.L @R%d+, VBR", Rm );4.812 - }4.813 - break;4.814 - case 0x3:4.815 - { /* LDC.L @Rm+, SSR */4.816 - uint32_t Rm = ((ir>>8)&0xF);4.817 - snprintf( buf, len, "LDC.L @R%d+, SSR", Rm );4.818 - }4.819 - break;4.820 - case 0x4:4.821 - { /* LDC.L @Rm+, SPC */4.822 - uint32_t Rm = ((ir>>8)&0xF);4.823 - snprintf( buf, len, "LDC.L @R%d+, SPC", Rm );4.824 - }4.825 - break;4.826 - default:4.827 - UNDEF();4.828 - break;4.829 - }4.830 - break;4.831 - case 0x1:4.832 - { /* LDC.L @Rm+, Rn_BANK */4.833 - uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);4.834 - snprintf( buf, len, "LDC.L @R%d+, @R%d+_BANK", Rm, Rn_BANK );4.835 - }4.836 - break;4.837 - }4.838 - break;4.839 - case 0x8:4.840 - switch( (ir&0xF0) >> 4 ) {4.841 - case 0x0:4.842 - { /* SHLL2 Rn */4.843 - uint32_t Rn = ((ir>>8)&0xF);4.844 - snprintf( buf, len, "SHLL2 R%d", Rn );4.845 - }4.846 - break;4.847 - case 0x1:4.848 - { /* SHLL8 Rn */4.849 - uint32_t Rn = ((ir>>8)&0xF);4.850 - snprintf( buf, len, "SHLL8 R%d", Rn );4.851 - }4.852 - break;4.853 - case 0x2:4.854 - { /* SHLL16 Rn */4.855 - uint32_t Rn = ((ir>>8)&0xF);4.856 - snprintf( buf, len, "SHLL16 R%d", Rn );4.857 - }4.858 - break;4.859 - default:4.860 - UNDEF();4.861 - break;4.862 - }4.863 - break;4.864 - case 0x9:4.865 - switch( (ir&0xF0) >> 4 ) {4.866 - case 0x0:4.867 - { /* SHLR2 Rn */4.868 - uint32_t Rn = ((ir>>8)&0xF);4.869 - snprintf( buf, len, "SHLR2 R%d", Rn );4.870 - }4.871 - break;4.872 - case 0x1:4.873 - { /* SHLR8 Rn */4.874 - uint32_t Rn = ((ir>>8)&0xF);4.875 - snprintf( buf, len, "SHLR8 R%d", Rn );4.876 - }4.877 - break;4.878 - case 0x2:4.879 - { /* SHLR16 Rn */4.880 - uint32_t Rn = ((ir>>8)&0xF);4.881 - snprintf( buf, len, "SHLR16 R%d", Rn );4.882 - }4.883 - break;4.884 - default:4.885 - UNDEF();4.886 - break;4.887 - }4.888 - break;4.889 - case 0xA:4.890 - switch( (ir&0xF0) >> 4 ) {4.891 - case 0x0:4.892 - { /* LDS Rm, MACH */4.893 - uint32_t Rm = ((ir>>8)&0xF);4.894 - snprintf( buf, len, "LDS R%d, MACH", Rm );4.895 - }4.896 - break;4.897 - case 0x1:4.898 - { /* LDS Rm, MACL */4.899 - uint32_t Rm = ((ir>>8)&0xF);4.900 - snprintf( buf, len, "LDS R%d, MACL", Rm );4.901 - }4.902 - break;4.903 - case 0x2:4.904 - { /* LDS Rm, PR */4.905 - uint32_t Rm = ((ir>>8)&0xF);4.906 - snprintf( buf, len, "LDS R%d, PR", Rm );4.907 - }4.908 - break;4.909 - case 0x3:4.910 - { /* LDC Rm, SGR */4.911 - uint32_t Rm = ((ir>>8)&0xF);4.912 - snprintf( buf, len, "LDC R%d, SGR", Rm );4.913 - }4.914 - break;4.915 - case 0x5:4.916 - { /* LDS Rm, FPUL */4.917 - uint32_t Rm = ((ir>>8)&0xF);4.918 - snprintf( buf, len, "LDS R%d, FPUL", Rm );4.919 - }4.920 - break;4.921 - case 0x6:4.922 - { /* LDS Rm, FPSCR */4.923 - uint32_t Rm = ((ir>>8)&0xF);4.924 - snprintf( buf, len, "LDS R%d, FPSCR", Rm );4.925 - }4.926 - break;4.927 - case 0xF:4.928 - { /* LDC Rm, DBR */4.929 - uint32_t Rm = ((ir>>8)&0xF);4.930 - snprintf( buf, len, "LDC R%d, DBR", Rm );4.931 - }4.932 - break;4.933 - default:4.934 - UNDEF();4.935 - break;4.936 - }4.937 - break;4.938 - case 0xB:4.939 - switch( (ir&0xF0) >> 4 ) {4.940 - case 0x0:4.941 - { /* JSR @Rn */4.942 - uint32_t Rn = ((ir>>8)&0xF);4.943 - snprintf( buf, len, "JSR @R%d", Rn );4.944 - }4.945 - break;4.946 - case 0x1:4.947 - { /* TAS.B @Rn */4.948 - uint32_t Rn = ((ir>>8)&0xF);4.949 - snprintf( buf, len, "TAS.B R%d", Rn );4.950 - }4.951 - break;4.952 - case 0x2:4.953 - { /* JMP @Rn */4.954 - uint32_t Rn = ((ir>>8)&0xF);4.955 - snprintf( buf, len, "JMP @R%d", Rn );4.956 - }4.957 - break;4.958 - default:4.959 - UNDEF();4.960 - break;4.961 - }4.962 - break;4.963 - case 0xC:4.964 - { /* SHAD Rm, Rn */4.965 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.966 - snprintf( buf, len, "SHAD R%d, R%d", Rm, Rn );4.967 - }4.968 - break;4.969 - case 0xD:4.970 - { /* SHLD Rm, Rn */4.971 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.972 - snprintf( buf, len, "SHLD R%d, R%d", Rm, Rn );4.973 - }4.974 - break;4.975 - case 0xE:4.976 - switch( (ir&0x80) >> 7 ) {4.977 - case 0x0:4.978 - switch( (ir&0x70) >> 4 ) {4.979 - case 0x0:4.980 - { /* LDC Rm, SR */4.981 - uint32_t Rm = ((ir>>8)&0xF);4.982 - snprintf( buf, len, "LDC R%d, SR", Rm );4.983 - }4.984 - break;4.985 - case 0x1:4.986 - { /* LDC Rm, GBR */4.987 - uint32_t Rm = ((ir>>8)&0xF);4.988 - snprintf( buf, len, "LDC R%d, GBR", Rm );4.989 - }4.990 - break;4.991 - case 0x2:4.992 - { /* LDC Rm, VBR */4.993 - uint32_t Rm = ((ir>>8)&0xF);4.994 - snprintf( buf, len, "LDC R%d, VBR", Rm );4.995 - }4.996 - break;4.997 - case 0x3:4.998 - { /* LDC Rm, SSR */4.999 - uint32_t Rm = ((ir>>8)&0xF);4.1000 - snprintf( buf, len, "LDC R%d, SSR", Rm );4.1001 - }4.1002 - break;4.1003 - case 0x4:4.1004 - { /* LDC Rm, SPC */4.1005 - uint32_t Rm = ((ir>>8)&0xF);4.1006 - snprintf( buf, len, "LDC R%d, SPC", Rm );4.1007 - }4.1008 - break;4.1009 - default:4.1010 - UNDEF();4.1011 - break;4.1012 - }4.1013 - break;4.1014 - case 0x1:4.1015 - { /* LDC Rm, Rn_BANK */4.1016 - uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);4.1017 - snprintf( buf, len, "LDC R%d, R%d_BANK", Rm, Rn_BANK );4.1018 - }4.1019 - break;4.1020 - }4.1021 - break;4.1022 - case 0xF:4.1023 - { /* MAC.W @Rm+, @Rn+ */4.1024 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.1025 - snprintf( buf, len, "MAC.W @R%d+, @R%d+", Rm, Rn );4.1026 - }4.1027 - break;4.1028 - }4.1029 - break;4.1030 - case 0x5:4.1031 - { /* MOV.L @(disp, Rm), Rn */4.1032 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;4.1033 - snprintf( buf, len, "MOV.L @(%d, R%d), R%d", disp, Rm, Rn );4.1034 - }4.1035 - break;4.1036 - case 0x6:4.1037 - switch( ir&0xF ) {4.1038 - case 0x0:4.1039 - { /* MOV.B @Rm, Rn */4.1040 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.1041 - snprintf( buf, len, "MOV.B @R%d, R%d", Rm, Rn );4.1042 - }4.1043 - break;4.1044 - case 0x1:4.1045 - { /* MOV.W @Rm, Rn */4.1046 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.1047 - snprintf( buf, len, "MOV.W @R%d, R%d", Rm, Rn );4.1048 - }4.1049 - break;4.1050 - case 0x2:4.1051 - { /* MOV.L @Rm, Rn */4.1052 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.1053 - snprintf( buf, len, "MOV.L @R%d, R%d", Rm, Rn );4.1054 - }4.1055 - break;4.1056 - case 0x3:4.1057 - { /* MOV Rm, Rn */4.1058 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.1059 - snprintf( buf, len, "MOV R%d, R%d", Rm, Rn );4.1060 - }4.1061 - break;4.1062 - case 0x4:4.1063 - { /* MOV.B @Rm+, Rn */4.1064 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.1065 - snprintf( buf, len, "MOV.B @R%d+, R%d", Rm, Rn );4.1066 - }4.1067 - break;4.1068 - case 0x5:4.1069 - { /* MOV.W @Rm+, Rn */4.1070 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.1071 - snprintf( buf, len, "MOV.W @R%d+, R%d", Rm, Rn );4.1072 - }4.1073 - break;4.1074 - case 0x6:4.1075 - { /* MOV.L @Rm+, Rn */4.1076 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.1077 - snprintf( buf, len, "MOV.L @R%d+, R%d", Rm, Rn );4.1078 - }4.1079 - break;4.1080 - case 0x7:4.1081 - { /* NOT Rm, Rn */4.1082 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.1083 - snprintf( buf, len, "NOT R%d, R%d", Rm, Rn );4.1084 - }4.1085 - break;4.1086 - case 0x8:4.1087 - { /* SWAP.B Rm, Rn */4.1088 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.1089 - snprintf( buf, len, "SWAP.B R%d, R%d", Rm, Rn );4.1090 - }4.1091 - break;4.1092 - case 0x9:4.1093 - { /* SWAP.W Rm, Rn */4.1094 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.1095 - snprintf( buf, len, "SWAP.W R%d, R%d", Rm, Rn );4.1096 - }4.1097 - break;4.1098 - case 0xA:4.1099 - { /* NEGC Rm, Rn */4.1100 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.1101 - snprintf( buf, len, "NEGC R%d, R%d", Rm, Rn );4.1102 - }4.1103 - break;4.1104 - case 0xB:4.1105 - { /* NEG Rm, Rn */4.1106 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.1107 - snprintf( buf, len, "NEG R%d, R%d", Rm, Rn );4.1108 - }4.1109 - break;4.1110 - case 0xC:4.1111 - { /* EXTU.B Rm, Rn */4.1112 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.1113 - snprintf( buf, len, "EXTU.B R%d, R%d", Rm, Rn );4.1114 - }4.1115 - break;4.1116 - case 0xD:4.1117 - { /* EXTU.W Rm, Rn */4.1118 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.1119 - snprintf( buf, len, "EXTU.W R%d, R%d", Rm, Rn );4.1120 - }4.1121 - break;4.1122 - case 0xE:4.1123 - { /* EXTS.B Rm, Rn */4.1124 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.1125 - snprintf( buf, len, "EXTS.B R%d, R%d", Rm, Rn );4.1126 - }4.1127 - break;4.1128 - case 0xF:4.1129 - { /* EXTS.W Rm, Rn */4.1130 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.1131 - snprintf( buf, len, "EXTS.W R%d, R%d", Rm, Rn );4.1132 - }4.1133 - break;4.1134 - }4.1135 - break;4.1136 - case 0x7:4.1137 - { /* ADD #imm, Rn */4.1138 - uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);4.1139 - snprintf( buf, len, "ADD #%d, R%d", imm, Rn );4.1140 - }4.1141 - break;4.1142 - case 0x8:4.1143 - switch( (ir&0xF00) >> 8 ) {4.1144 - case 0x0:4.1145 - { /* MOV.B R0, @(disp, Rn) */4.1146 - uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);4.1147 - snprintf( buf, len, "MOV.B R0, @(%d, R%d)", disp, Rn );4.1148 - }4.1149 - break;4.1150 - case 0x1:4.1151 - { /* MOV.W R0, @(disp, Rn) */4.1152 - uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;4.1153 - snprintf( buf, len, "MOV.W R0, @(%d, R%d)", disp, Rn );4.1154 - }4.1155 - break;4.1156 - case 0x4:4.1157 - { /* MOV.B @(disp, Rm), R0 */4.1158 - uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);4.1159 - snprintf( buf, len, "MOV.B @(%d, R%d), R0", disp, Rm );4.1160 - }4.1161 - break;4.1162 - case 0x5:4.1163 - { /* MOV.W @(disp, Rm), R0 */4.1164 - uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;4.1165 - snprintf( buf, len, "MOV.W @(%d, R%d), R0", disp, Rm );4.1166 - }4.1167 - break;4.1168 - case 0x8:4.1169 - { /* CMP/EQ #imm, R0 */4.1170 - int32_t imm = SIGNEXT8(ir&0xFF);4.1171 - snprintf( buf, len, "CMP/EQ #%d, R0", imm );4.1172 - }4.1173 - break;4.1174 - case 0x9:4.1175 - { /* BT disp */4.1176 - int32_t disp = SIGNEXT8(ir&0xFF)<<1;4.1177 - snprintf( buf, len, "BT $%xh", disp+pc+4 );4.1178 - }4.1179 - break;4.1180 - case 0xB:4.1181 - { /* BF disp */4.1182 - int32_t disp = SIGNEXT8(ir&0xFF)<<1;4.1183 - snprintf( buf, len, "BF $%xh", disp+pc+4 );4.1184 - }4.1185 - break;4.1186 - case 0xD:4.1187 - { /* BT/S disp */4.1188 - int32_t disp = SIGNEXT8(ir&0xFF)<<1;4.1189 - snprintf( buf, len, "BT/S $%xh", disp+pc+4 );4.1190 - }4.1191 - break;4.1192 - case 0xF:4.1193 - { /* BF/S disp */4.1194 - int32_t disp = SIGNEXT8(ir&0xFF)<<1;4.1195 - snprintf( buf, len, "BF/S $%xh", disp+pc+4 );4.1196 - }4.1197 - break;4.1198 - default:4.1199 - UNDEF();4.1200 - break;4.1201 - }4.1202 - break;4.1203 - case 0x9:4.1204 - { /* MOV.W @(disp, PC), Rn */4.1205 - uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1;4.1206 - snprintf( buf, len, "MOV.W @($%xh), R%d ; <- #%08x", disp + pc + 4, Rn, sh4_read_word(disp+addr+4) );4.1207 - }4.1208 - break;4.1209 - case 0xA:4.1210 - { /* BRA disp */4.1211 - int32_t disp = SIGNEXT12(ir&0xFFF)<<1;4.1212 - snprintf( buf, len, "BRA $%xh", disp+pc+4 );4.1213 - }4.1214 - break;4.1215 - case 0xB:4.1216 - { /* BSR disp */4.1217 - int32_t disp = SIGNEXT12(ir&0xFFF)<<1;4.1218 - snprintf( buf, len, "BSR $%xh", disp+pc+4 );4.1219 - }4.1220 - break;4.1221 - case 0xC:4.1222 - switch( (ir&0xF00) >> 8 ) {4.1223 - case 0x0:4.1224 - { /* MOV.B R0, @(disp, GBR) */4.1225 - uint32_t disp = (ir&0xFF);4.1226 - snprintf( buf, len, "MOV.B R0, @(%d, GBR)", disp );4.1227 - }4.1228 - break;4.1229 - case 0x1:4.1230 - { /* MOV.W R0, @(disp, GBR) */4.1231 - uint32_t disp = (ir&0xFF)<<1;4.1232 - snprintf( buf, len, "MOV.W R0, @(%d, GBR)", disp);4.1233 - }4.1234 - break;4.1235 - case 0x2:4.1236 - { /* MOV.L R0, @(disp, GBR) */4.1237 - uint32_t disp = (ir&0xFF)<<2;4.1238 - snprintf( buf, len, "MOV.L R0, @(%d, GBR)", disp );4.1239 - }4.1240 - break;4.1241 - case 0x3:4.1242 - { /* TRAPA #imm */4.1243 - uint32_t imm = (ir&0xFF);4.1244 - snprintf( buf, len, "TRAPA #%d", imm );4.1245 - }4.1246 - break;4.1247 - case 0x4:4.1248 - { /* MOV.B @(disp, GBR), R0 */4.1249 - uint32_t disp = (ir&0xFF);4.1250 - snprintf( buf, len, "MOV.B @(%d, GBR), R0", disp );4.1251 - }4.1252 - break;4.1253 - case 0x5:4.1254 - { /* MOV.W @(disp, GBR), R0 */4.1255 - uint32_t disp = (ir&0xFF)<<1;4.1256 - snprintf( buf, len, "MOV.W @(%d, GBR), R0", disp );4.1257 - }4.1258 - break;4.1259 - case 0x6:4.1260 - { /* MOV.L @(disp, GBR), R0 */4.1261 - uint32_t disp = (ir&0xFF)<<2;4.1262 - snprintf( buf, len, "MOV.L @(%d, GBR), R0",disp );4.1263 - }4.1264 - break;4.1265 - case 0x7:4.1266 - { /* MOVA @(disp, PC), R0 */4.1267 - uint32_t disp = (ir&0xFF)<<2;4.1268 - snprintf( buf, len, "MOVA @($%xh), R0", disp + (pc&0xFFFFFFFC) + 4 );4.1269 - }4.1270 - break;4.1271 - case 0x8:4.1272 - { /* TST #imm, R0 */4.1273 - uint32_t imm = (ir&0xFF);4.1274 - snprintf( buf, len, "TST #%d, R0", imm );4.1275 - }4.1276 - break;4.1277 - case 0x9:4.1278 - { /* AND #imm, R0 */4.1279 - uint32_t imm = (ir&0xFF);4.1280 - snprintf( buf, len, "AND #%d, R0", imm );4.1281 - }4.1282 - break;4.1283 - case 0xA:4.1284 - { /* XOR #imm, R0 */4.1285 - uint32_t imm = (ir&0xFF);4.1286 - snprintf( buf, len, "XOR #%d, R0", imm );4.1287 - }4.1288 - break;4.1289 - case 0xB:4.1290 - { /* OR #imm, R0 */4.1291 - uint32_t imm = (ir&0xFF);4.1292 - snprintf( buf, len, "OR #%d, R0", imm );4.1293 - }4.1294 - break;4.1295 - case 0xC:4.1296 - { /* TST.B #imm, @(R0, GBR) */4.1297 - uint32_t imm = (ir&0xFF);4.1298 - snprintf( buf, len, "TST.B #%d, @(R0, GBR)", imm );4.1299 - }4.1300 - break;4.1301 - case 0xD:4.1302 - { /* AND.B #imm, @(R0, GBR) */4.1303 - uint32_t imm = (ir&0xFF);4.1304 - snprintf( buf, len, "AND.B #%d, @(R0, GBR)", imm );4.1305 - }4.1306 - break;4.1307 - case 0xE:4.1308 - { /* XOR.B #imm, @(R0, GBR) */4.1309 - uint32_t imm = (ir&0xFF);4.1310 - snprintf( buf, len, "XOR.B #%d, @(R0, GBR)", imm );4.1311 - }4.1312 - break;4.1313 - case 0xF:4.1314 - { /* OR.B #imm, @(R0, GBR) */4.1315 - uint32_t imm = (ir&0xFF);4.1316 - snprintf( buf, len, "OR.B #%d, @(R0, GBR)", imm );4.1317 - }4.1318 - break;4.1319 - }4.1320 - break;4.1321 - case 0xD:4.1322 - { /* MOV.L @(disp, PC), Rn */4.1323 - uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2;4.1324 - snprintf( buf, len, "MOV.L @($%xh), R%d ; <- #%08x", disp + (pc & 0xFFFFFFFC) + 4, Rn, sh4_read_long(disp+(addr&0xFFFFFFFC)+4) );4.1325 - }4.1326 - break;4.1327 - case 0xE:4.1328 - { /* MOV #imm, Rn */4.1329 - uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);4.1330 - snprintf( buf, len, "MOV #%d, R%d", imm, Rn );4.1331 - }4.1332 - break;4.1333 - case 0xF:4.1334 - switch( ir&0xF ) {4.1335 - case 0x0:4.1336 - { /* FADD FRm, FRn */4.1337 - uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);4.1338 - snprintf( buf, len, "FADD FR%d, FR%d", FRm, FRn );4.1339 - }4.1340 - break;4.1341 - case 0x1:4.1342 - { /* FSUB FRm, FRn */4.1343 - uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);4.1344 - snprintf( buf, len, "FSUB FR%d, FR%d", FRm, FRn );4.1345 - }4.1346 - break;4.1347 - case 0x2:4.1348 - { /* FMUL FRm, FRn */4.1349 - uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);4.1350 - snprintf( buf, len, "FMUL FR%d, FR%d", FRm, FRn );4.1351 - }4.1352 - break;4.1353 - case 0x3:4.1354 - { /* FDIV FRm, FRn */4.1355 - uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);4.1356 - snprintf( buf, len, "FDIV FR%d, FR%d", FRm, FRn );4.1357 - }4.1358 - break;4.1359 - case 0x4:4.1360 - { /* FCMP/EQ FRm, FRn */4.1361 - uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);4.1362 - snprintf( buf, len, "FCMP/EQ FR%d, FR%d", FRm, FRn );4.1363 - }4.1364 - break;4.1365 - case 0x5:4.1366 - { /* FCMP/GT FRm, FRn */4.1367 - uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);4.1368 - snprintf( buf, len, "FCMP/QT FR%d, FR%d", FRm, FRn );4.1369 - }4.1370 - break;4.1371 - case 0x6:4.1372 - { /* FMOV @(R0, Rm), FRn */4.1373 - uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.1374 - snprintf( buf, len, "FMOV @(R0, R%d), FR%d", Rm, FRn );4.1375 - }4.1376 - break;4.1377 - case 0x7:4.1378 - { /* FMOV FRm, @(R0, Rn) */4.1379 - uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);4.1380 - snprintf( buf, len, "FMOV FR%d, @(R0, R%d)", FRm, Rn );4.1381 - }4.1382 - break;4.1383 - case 0x8:4.1384 - { /* FMOV @Rm, FRn */4.1385 - uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.1386 - snprintf( buf, len, "FMOV @R%d, FR%d", Rm, FRn );4.1387 - }4.1388 - break;4.1389 - case 0x9:4.1390 - { /* FMOV @Rm+, FRn */4.1391 - uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);4.1392 - snprintf( buf, len, "FMOV @R%d+, FR%d", Rm, FRn );4.1393 - }4.1394 - break;4.1395 - case 0xA:4.1396 - { /* FMOV FRm, @Rn */4.1397 - uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);4.1398 - snprintf( buf, len, "FMOV FR%d, @R%d", FRm, Rn );4.1399 - }4.1400 - break;4.1401 - case 0xB:4.1402 - { /* FMOV FRm, @-Rn */4.1403 - uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);4.1404 - snprintf( buf, len, "FMOV FR%d, @-R%d", FRm, Rn );4.1405 - }4.1406 - break;4.1407 - case 0xC:4.1408 - { /* FMOV FRm, FRn */4.1409 - uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);4.1410 - snprintf( buf, len, "FMOV FR%d, FR%d", FRm, FRn );4.1411 - }4.1412 - break;4.1413 - case 0xD:4.1414 - switch( (ir&0xF0) >> 4 ) {4.1415 - case 0x0:4.1416 - { /* FSTS FPUL, FRn */4.1417 - uint32_t FRn = ((ir>>8)&0xF);4.1418 - snprintf( buf, len, "FSTS FPUL, FR%d", FRn );4.1419 - }4.1420 - break;4.1421 - case 0x1:4.1422 - { /* FLDS FRm, FPUL */4.1423 - uint32_t FRm = ((ir>>8)&0xF);4.1424 - snprintf( buf, len, "FLDS FR%d, FPUL", FRm );4.1425 - }4.1426 - break;4.1427 - case 0x2:4.1428 - { /* FLOAT FPUL, FRn */4.1429 - uint32_t FRn = ((ir>>8)&0xF);4.1430 - snprintf( buf, len, "FLOAT FPUL, FR%d", FRn );4.1431 - }4.1432 - break;4.1433 - case 0x3:4.1434 - { /* FTRC FRm, FPUL */4.1435 - uint32_t FRm = ((ir>>8)&0xF);4.1436 - snprintf( buf, len, "FTRC FR%d, FPUL", FRm );4.1437 - }4.1438 - break;4.1439 - case 0x4:4.1440 - { /* FNEG FRn */4.1441 - uint32_t FRn = ((ir>>8)&0xF);4.1442 - snprintf( buf, len, "FNEG FR%d", FRn );4.1443 - }4.1444 - break;4.1445 - case 0x5:4.1446 - { /* FABS FRn */4.1447 - uint32_t FRn = ((ir>>8)&0xF);4.1448 - snprintf( buf, len, "FABS FR%d", FRn );4.1449 - }4.1450 - break;4.1451 - case 0x6:4.1452 - { /* FSQRT FRn */4.1453 - uint32_t FRn = ((ir>>8)&0xF);4.1454 - snprintf( buf, len, "FSQRT FR%d", FRn );4.1455 - }4.1456 - break;4.1457 - case 0x7:4.1458 - { /* FSRRA FRn */4.1459 - uint32_t FRn = ((ir>>8)&0xF);4.1460 - snprintf( buf, len, "FSRRA FR%d", FRn );4.1461 - }4.1462 - break;4.1463 - case 0x8:4.1464 - { /* FLDI0 FRn */4.1465 - uint32_t FRn = ((ir>>8)&0xF);4.1466 - snprintf( buf, len, "FLDI0 FR%d", FRn );4.1467 - }4.1468 - break;4.1469 - case 0x9:4.1470 - { /* FLDI1 FRn */4.1471 - uint32_t FRn = ((ir>>8)&0xF);4.1472 - snprintf( buf, len, "FLDI1 FR%d", FRn );4.1473 - }4.1474 - break;4.1475 - case 0xA:4.1476 - { /* FCNVSD FPUL, FRn */4.1477 - uint32_t FRn = ((ir>>8)&0xF);4.1478 - snprintf( buf, len, "FCNVSD FPUL, FR%d", FRn );4.1479 - }4.1480 - break;4.1481 - case 0xB:4.1482 - { /* FCNVDS FRm, FPUL */4.1483 - uint32_t FRm = ((ir>>8)&0xF);4.1484 - snprintf( buf, len, "FCNVDS FR%d, FPUL", FRm );4.1485 - }4.1486 - break;4.1487 - case 0xE:4.1488 - { /* FIPR FVm, FVn */4.1489 - uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3);4.1490 - snprintf( buf, len, "FIPR FV%d, FV%d", FVm, FVn );4.1491 - }4.1492 - break;4.1493 - case 0xF:4.1494 - switch( (ir&0x100) >> 8 ) {4.1495 - case 0x0:4.1496 - { /* FSCA FPUL, FRn */4.1497 - uint32_t FRn = ((ir>>9)&0x7)<<1;4.1498 - snprintf( buf, len, "FSCA FPUL, FR%d", FRn );4.1499 - }4.1500 - break;4.1501 - case 0x1:4.1502 - switch( (ir&0x200) >> 9 ) {4.1503 - case 0x0:4.1504 - { /* FTRV XMTRX, FVn */4.1505 - uint32_t FVn = ((ir>>10)&0x3);4.1506 - snprintf( buf, len, "FTRV XMTRX, FV%d", FVn );4.1507 - }4.1508 - break;4.1509 - case 0x1:4.1510 - switch( (ir&0xC00) >> 10 ) {4.1511 - case 0x0:4.1512 - { /* FSCHG */4.1513 - snprintf( buf, len, "FSCHG " );4.1514 - }4.1515 - break;4.1516 - case 0x2:4.1517 - { /* FRCHG */4.1518 - snprintf( buf, len, "FRCHG " );4.1519 - }4.1520 - break;4.1521 - case 0x3:4.1522 - { /* UNDEF */4.1523 - snprintf( buf, len, "UNDEF " );4.1524 - }4.1525 - break;4.1526 - default:4.1527 - UNDEF();4.1528 - break;4.1529 - }4.1530 - break;4.1531 - }4.1532 - break;4.1533 - }4.1534 - break;4.1535 - default:4.1536 - UNDEF();4.1537 - break;4.1538 - }4.1539 - break;4.1540 - case 0xE:4.1541 - { /* FMAC FR0, FRm, FRn */4.1542 - uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);4.1543 - snprintf( buf, len, "FMAC FR0, FR%d, FR%d", FRm, FRn );4.1544 - }4.1545 - break;4.1546 - default:4.1547 - UNDEF();4.1548 - break;4.1549 - }4.1550 - break;4.1551 - }4.1552 -4.1553 - return pc+2;4.1554 -}4.1555 -4.1556 -4.1557 -void sh4_disasm_region( FILE *f, int from, int to )4.1558 -{4.1559 - int pc;4.1560 - char buf[80];4.1561 - char opcode[16];4.1562 -4.1563 - for( pc = from; pc < to; pc+=2 ) {4.1564 - buf[0] = '\0';4.1565 - sh4_disasm_instruction( pc,4.1566 - buf, sizeof(buf), opcode );4.1567 - fprintf( f, " %08x: %s %s\n", pc, opcode, buf );4.1568 - }4.1569 -}4.1570 -4.1571 -void sh4_dump_region( int from, int to )4.1572 -{4.1573 - sh4_disasm_region( stdout, from, to );4.1574 -}
5.1 --- a/src/sh4/sh4stat.c Sat Jul 19 02:34:11 2008 +00005.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +00005.3 @@ -1,1680 +0,0 @@5.4 -/**5.5 - * $Id$5.6 - *5.7 - * Support module for collecting instruction stats5.8 - *5.9 - * Copyright (c) 2005 Nathan Keynes.5.10 - *5.11 - * This program is free software; you can redistribute it and/or modify5.12 - * it under the terms of the GNU General Public License as published by5.13 - * the Free Software Foundation; either version 2 of the License, or5.14 - * (at your option) any later version.5.15 - *5.16 - * This program is distributed in the hope that it will be useful,5.17 - * but WITHOUT ANY WARRANTY; without even the implied warranty of5.18 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the5.19 - * GNU General Public License for more details.5.20 - */5.21 -5.22 -#include "dream.h"5.23 -#include "sh4/sh4stat.h"5.24 -#include "sh4/sh4core.h"5.25 -5.26 -static uint64_t sh4_stats[SH4_INSTRUCTION_COUNT+1];5.27 -static uint64_t sh4_stats_total;5.28 -static const char *sh4_stats_names[] = {5.29 - "???",5.30 -"ADD Rm, Rn",5.31 -"ADD #imm, Rn",5.32 -"ADDC Rm, Rn",5.33 -"ADDV Rm, Rn",5.34 -"AND Rm, Rn",5.35 -"AND #imm, R0",5.36 -"AND.B #imm, @(R0, GBR)",5.37 -"BF disp",5.38 -"BF/S disp",5.39 -"BRA disp",5.40 -"BRAF Rn",5.41 -"BSR disp",5.42 -"BSRF Rn",5.43 -"BT disp",5.44 -"BT/S disp",5.45 -"CLRMAC",5.46 -"CLRS",5.47 -"CLRT",5.48 -"CMP/EQ Rm, Rn",5.49 -"CMP/EQ #imm, R0",5.50 -"CMP/GE Rm, Rn",5.51 -"CMP/GT Rm, Rn",5.52 -"CMP/HI Rm, Rn",5.53 -"CMP/HS Rm, Rn",5.54 -"CMP/PL Rn",5.55 -"CMP/PZ Rn",5.56 -"CMP/STR Rm, Rn",5.57 -"DIV0S Rm, Rn",5.58 -"DIV0U",5.59 -"DIV1 Rm, Rn",5.60 -"DMULS.L Rm, Rn",5.61 -"DMULU.L Rm, Rn",5.62 -"DT Rn",5.63 -"EXTS.B Rm, Rn",5.64 -"EXTS.W Rm, Rn",5.65 -"EXTU.B Rm, Rn",5.66 -"EXTU.W Rm, Rn",5.67 -"FABS FRn",5.68 -"FADD FRm, FRn",5.69 -"FCMP/EQ FRm, FRn",5.70 -"FCMP/GT FRm, FRn",5.71 -"FCNVDS FRm, FPUL",5.72 -"FCNVSD FPUL, FRn",5.73 -"FDIV FRm, FRn",5.74 -"FIPR FVm, FVn",5.75 -"FLDS FRm, FPUL",5.76 -"FLDI0 FRn",5.77 -"FLDI1 FRn",5.78 -"FLOAT FPUL, FRn",5.79 -"FMAC FR0, FRm, FRn",5.80 -"FMOV FRm, FRn",5.81 -"FMOV FRm, @Rn",5.82 -"FMOV FRm, @-Rn",5.83 -"FMOV FRm, @(R0, Rn)",5.84 -"FMOV @Rm, FRn",5.85 -"FMOV @Rm+, FRn",5.86 -"FMOV @(R0, Rm), FRn",5.87 -"FMUL FRm, FRn",5.88 -"FNEG FRn",5.89 -"FRCHG",5.90 -"FSCA FPUL, FRn",5.91 -"FSCHG",5.92 -"FSQRT FRn",5.93 -"FSRRA FRn",5.94 -"FSTS FPUL, FRn",5.95 -"FSUB FRm, FRn",5.96 -"FTRC FRm, FPUL",5.97 -"FTRV XMTRX, FVn",5.98 -"JMP @Rn",5.99 -"JSR @Rn",5.100 -"LDC Rm, SR",5.101 -"LDC Rm, *",5.102 -"LDC.L @Rm+, SR",5.103 -"LDC.L @Rm+, *",5.104 -"LDS Rm, FPSCR",5.105 -"LDS Rm, *",5.106 -"LDS.L @Rm+, FPSCR",5.107 -"LDS.L @Rm+, *",5.108 -"LDTLB",5.109 -"MAC.L @Rm+, @Rn+",5.110 -"MAC.W @Rm+, @Rn+",5.111 -"MOV Rm, Rn",5.112 -"MOV #imm, Rn",5.113 -"MOV.B ...",5.114 -"MOV.L ...",5.115 -"MOV.L @(disp, PC)",5.116 -"MOV.W ...",5.117 -"MOVA @(disp, PC), R0",5.118 -"MOVCA.L R0, @Rn",5.119 -"MOVT Rn",5.120 -"MUL.L Rm, Rn",5.121 -"MULS.W Rm, Rn",5.122 -"MULU.W Rm, Rn",5.123 -"NEG Rm, Rn",5.124 -"NEGC Rm, Rn",5.125 -"NOP",5.126 -"NOT Rm, Rn",5.127 -"OCBI @Rn",5.128 -"OCBP @Rn",5.129 -"OCBWB @Rn",5.130 -"OR Rm, Rn",5.131 -"OR #imm, R0",5.132 -"OR.B #imm, @(R0, GBR)",5.133 -"PREF @Rn",5.134 -"ROTCL Rn",5.135 -"ROTCR Rn",5.136 -"ROTL Rn",5.137 -"ROTR Rn",5.138 -"RTE",5.139 -"RTS",5.140 -"SETS",5.141 -"SETT",5.142 -"SHAD Rm, Rn",5.143 -"SHAL Rn",5.144 -"SHAR Rn",5.145 -"SHLD Rm, Rn",5.146 -"SHLL* Rn",5.147 -"SHLR* Rn",5.148 -"SLEEP",5.149 -"STC SR, Rn",5.150 -"STC *, Rn",5.151 -"STC.L SR, @-Rn",5.152 -"STC.L *, @-Rn",5.153 -"STS FPSCR, Rn",5.154 -"STS *, Rn",5.155 -"STS.L FPSCR, @-Rn",5.156 -"STS.L *, @-Rn",5.157 -"SUB Rm, Rn",5.158 -"SUBC Rm, Rn",5.159 -"SUBV Rm, Rn",5.160 -"SWAP.B Rm, Rn",5.161 -"SWAP.W Rm, Rn",5.162 -"TAS.B @Rn",5.163 -"TRAPA #imm",5.164 -"TST Rm, Rn",5.165 -"TST #imm, R0",5.166 -"TST.B #imm, @(R0, GBR)",5.167 -"XOR Rm, Rn",5.168 -"XOR #imm, R0",5.169 -"XOR.B #imm, @(R0, GBR)",5.170 -"XTRCT Rm, Rn",5.171 -"UNDEF"5.172 -};5.173 -5.174 -void sh4_stats_reset( void )5.175 -{5.176 - int i;5.177 - for( i=0; i<= I_UNDEF; i++ ) {5.178 - sh4_stats[i] = 0;5.179 - }5.180 - sh4_stats_total = 0;5.181 -}5.182 -5.183 -void sh4_stats_print( FILE *out )5.184 -{5.185 - int i;5.186 - for( i=0; i<= I_UNDEF; i++ ) {5.187 - fprintf( out, "%-20s\t%d\t%.2f%%\n", sh4_stats_names[i], (uint32_t)sh4_stats[i], ((double)sh4_stats[i])*100.0/(double)sh4_stats_total );5.188 - }5.189 - fprintf( out, "Total: %lld\n", sh4_stats_total );5.190 -}5.191 -5.192 -void sh4_stats_add( sh4_inst_id item )5.193 -{5.194 - sh4_stats[item]++;5.195 - sh4_stats_total++;5.196 -}5.197 -5.198 -void sh4_stats_add_by_pc( uint32_t pc )5.199 -{5.200 - uint16_t ir = sh4_read_word(pc);5.201 -#define UNDEF() sh4_stats[0]++5.202 - switch( (ir&0xF000) >> 12 ) {5.203 - case 0x0:5.204 - switch( ir&0xF ) {5.205 - case 0x2:5.206 - switch( (ir&0x80) >> 7 ) {5.207 - case 0x0:5.208 - switch( (ir&0x70) >> 4 ) {5.209 - case 0x0:5.210 - { /* STC SR, Rn */5.211 - uint32_t Rn = ((ir>>8)&0xF);5.212 - sh4_stats[I_STCSR]++;5.213 - }5.214 - break;5.215 - case 0x1:5.216 - { /* STC GBR, Rn */5.217 - uint32_t Rn = ((ir>>8)&0xF);5.218 - sh4_stats[I_STC]++;5.219 - }5.220 - break;5.221 - case 0x2:5.222 - { /* STC VBR, Rn */5.223 - uint32_t Rn = ((ir>>8)&0xF);5.224 - sh4_stats[I_STC]++;5.225 - }5.226 - break;5.227 - case 0x3:5.228 - { /* STC SSR, Rn */5.229 - uint32_t Rn = ((ir>>8)&0xF);5.230 - sh4_stats[I_STC]++;5.231 - }5.232 - break;5.233 - case 0x4:5.234 - { /* STC SPC, Rn */5.235 - uint32_t Rn = ((ir>>8)&0xF);5.236 - sh4_stats[I_STC]++;5.237 - }5.238 - break;5.239 - default:5.240 - UNDEF();5.241 - break;5.242 - }5.243 - break;5.244 - case 0x1:5.245 - { /* STC Rm_BANK, Rn */5.246 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);5.247 - sh4_stats[I_STC]++;5.248 - }5.249 - break;5.250 - }5.251 - break;5.252 - case 0x3:5.253 - switch( (ir&0xF0) >> 4 ) {5.254 - case 0x0:5.255 - { /* BSRF Rn */5.256 - uint32_t Rn = ((ir>>8)&0xF);5.257 - sh4_stats[I_BSRF]++;5.258 - }5.259 - break;5.260 - case 0x2:5.261 - { /* BRAF Rn */5.262 - uint32_t Rn = ((ir>>8)&0xF);5.263 - sh4_stats[I_BRAF]++;5.264 - }5.265 - break;5.266 - case 0x8:5.267 - { /* PREF @Rn */5.268 - uint32_t Rn = ((ir>>8)&0xF);5.269 - sh4_stats[I_PREF]++;5.270 - }5.271 - break;5.272 - case 0x9:5.273 - { /* OCBI @Rn */5.274 - uint32_t Rn = ((ir>>8)&0xF);5.275 - sh4_stats[I_OCBI]++;5.276 - }5.277 - break;5.278 - case 0xA:5.279 - { /* OCBP @Rn */5.280 - uint32_t Rn = ((ir>>8)&0xF);5.281 - sh4_stats[I_OCBP]++;5.282 - }5.283 - break;5.284 - case 0xB:5.285 - { /* OCBWB @Rn */5.286 - uint32_t Rn = ((ir>>8)&0xF);5.287 - sh4_stats[I_OCBWB]++;5.288 - }5.289 - break;5.290 - case 0xC:5.291 - { /* MOVCA.L R0, @Rn */5.292 - uint32_t Rn = ((ir>>8)&0xF);5.293 - sh4_stats[I_MOVCA]++;5.294 - }5.295 - break;5.296 - default:5.297 - UNDEF();5.298 - break;5.299 - }5.300 - break;5.301 - case 0x4:5.302 - { /* MOV.B Rm, @(R0, Rn) */5.303 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.304 - sh4_stats[I_MOVB]++;5.305 - }5.306 - break;5.307 - case 0x5:5.308 - { /* MOV.W Rm, @(R0, Rn) */5.309 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.310 - sh4_stats[I_MOVW]++;5.311 - }5.312 - break;5.313 - case 0x6:5.314 - { /* MOV.L Rm, @(R0, Rn) */5.315 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.316 - sh4_stats[I_MOVL]++;5.317 - }5.318 - break;5.319 - case 0x7:5.320 - { /* MUL.L Rm, Rn */5.321 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.322 - sh4_stats[I_MULL]++;5.323 - }5.324 - break;5.325 - case 0x8:5.326 - switch( (ir&0xFF0) >> 4 ) {5.327 - case 0x0:5.328 - { /* CLRT */5.329 - sh4_stats[I_CLRT]++;5.330 - }5.331 - break;5.332 - case 0x1:5.333 - { /* SETT */5.334 - sh4_stats[I_SETT]++;5.335 - }5.336 - break;5.337 - case 0x2:5.338 - { /* CLRMAC */5.339 - sh4_stats[I_CLRMAC]++;5.340 - }5.341 - break;5.342 - case 0x3:5.343 - { /* LDTLB */5.344 - sh4_stats[I_LDTLB]++;5.345 - }5.346 - break;5.347 - case 0x4:5.348 - { /* CLRS */5.349 - sh4_stats[I_CLRS]++;5.350 - }5.351 - break;5.352 - case 0x5:5.353 - { /* SETS */5.354 - sh4_stats[I_SETS]++;5.355 - }5.356 - break;5.357 - default:5.358 - UNDEF();5.359 - break;5.360 - }5.361 - break;5.362 - case 0x9:5.363 - switch( (ir&0xF0) >> 4 ) {5.364 - case 0x0:5.365 - { /* NOP */5.366 - sh4_stats[I_NOP]++;5.367 - }5.368 - break;5.369 - case 0x1:5.370 - { /* DIV0U */5.371 - sh4_stats[I_DIV0U]++;5.372 - }5.373 - break;5.374 - case 0x2:5.375 - { /* MOVT Rn */5.376 - uint32_t Rn = ((ir>>8)&0xF);5.377 - sh4_stats[I_MOVT]++;5.378 - }5.379 - break;5.380 - default:5.381 - UNDEF();5.382 - break;5.383 - }5.384 - break;5.385 - case 0xA:5.386 - switch( (ir&0xF0) >> 4 ) {5.387 - case 0x0:5.388 - { /* STS MACH, Rn */5.389 - uint32_t Rn = ((ir>>8)&0xF);5.390 - sh4_stats[I_STS]++;5.391 - }5.392 - break;5.393 - case 0x1:5.394 - { /* STS MACL, Rn */5.395 - uint32_t Rn = ((ir>>8)&0xF);5.396 - sh4_stats[I_STS]++;5.397 - }5.398 - break;5.399 - case 0x2:5.400 - { /* STS PR, Rn */5.401 - uint32_t Rn = ((ir>>8)&0xF);5.402 - sh4_stats[I_STS]++;5.403 - }5.404 - break;5.405 - case 0x3:5.406 - { /* STC SGR, Rn */5.407 - uint32_t Rn = ((ir>>8)&0xF);5.408 - sh4_stats[I_STC]++;5.409 - }5.410 - break;5.411 - case 0x5:5.412 - { /* STS FPUL, Rn */5.413 - uint32_t Rn = ((ir>>8)&0xF);5.414 - sh4_stats[I_STS]++;5.415 - }5.416 - break;5.417 - case 0x6:5.418 - { /* STS FPSCR, Rn */5.419 - uint32_t Rn = ((ir>>8)&0xF);5.420 - sh4_stats[I_STSFPSCR]++;5.421 - }5.422 - break;5.423 - case 0xF:5.424 - { /* STC DBR, Rn */5.425 - uint32_t Rn = ((ir>>8)&0xF);5.426 - sh4_stats[I_STC]++;5.427 - }5.428 - break;5.429 - default:5.430 - UNDEF();5.431 - break;5.432 - }5.433 - break;5.434 - case 0xB:5.435 - switch( (ir&0xFF0) >> 4 ) {5.436 - case 0x0:5.437 - { /* RTS */5.438 - sh4_stats[I_RTS]++;5.439 - }5.440 - break;5.441 - case 0x1:5.442 - { /* SLEEP */5.443 - sh4_stats[I_SLEEP]++;5.444 - }5.445 - break;5.446 - case 0x2:5.447 - { /* RTE */5.448 - sh4_stats[I_RTE]++;5.449 - }5.450 - break;5.451 - default:5.452 - UNDEF();5.453 - break;5.454 - }5.455 - break;5.456 - case 0xC:5.457 - { /* MOV.B @(R0, Rm), Rn */5.458 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.459 - sh4_stats[I_MOVB]++;5.460 - }5.461 - break;5.462 - case 0xD:5.463 - { /* MOV.W @(R0, Rm), Rn */5.464 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.465 - sh4_stats[I_MOVW]++;5.466 - }5.467 - break;5.468 - case 0xE:5.469 - { /* MOV.L @(R0, Rm), Rn */5.470 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.471 - sh4_stats[I_MOVL]++;5.472 - }5.473 - break;5.474 - case 0xF:5.475 - { /* MAC.L @Rm+, @Rn+ */5.476 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.477 - sh4_stats[I_MACL]++;5.478 - }5.479 - break;5.480 - default:5.481 - UNDEF();5.482 - break;5.483 - }5.484 - break;5.485 - case 0x1:5.486 - { /* MOV.L Rm, @(disp, Rn) */5.487 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;5.488 - sh4_stats[I_MOVL]++;5.489 - }5.490 - break;5.491 - case 0x2:5.492 - switch( ir&0xF ) {5.493 - case 0x0:5.494 - { /* MOV.B Rm, @Rn */5.495 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.496 - sh4_stats[I_MOVB]++;5.497 - }5.498 - break;5.499 - case 0x1:5.500 - { /* MOV.W Rm, @Rn */5.501 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.502 - sh4_stats[I_MOVW]++;5.503 - }5.504 - break;5.505 - case 0x2:5.506 - { /* MOV.L Rm, @Rn */5.507 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.508 - sh4_stats[I_MOVL]++;5.509 - }5.510 - break;5.511 - case 0x4:5.512 - { /* MOV.B Rm, @-Rn */5.513 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.514 - sh4_stats[I_MOVB]++;5.515 - }5.516 - break;5.517 - case 0x5:5.518 - { /* MOV.W Rm, @-Rn */5.519 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.520 - sh4_stats[I_MOVW]++;5.521 - }5.522 - break;5.523 - case 0x6:5.524 - { /* MOV.L Rm, @-Rn */5.525 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.526 - sh4_stats[I_MOVL]++;5.527 - }5.528 - break;5.529 - case 0x7:5.530 - { /* DIV0S Rm, Rn */5.531 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.532 - sh4_stats[I_DIV0S]++;5.533 - }5.534 - break;5.535 - case 0x8:5.536 - { /* TST Rm, Rn */5.537 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.538 - sh4_stats[I_TST]++;5.539 - }5.540 - break;5.541 - case 0x9:5.542 - { /* AND Rm, Rn */5.543 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.544 - sh4_stats[I_AND]++;5.545 - }5.546 - break;5.547 - case 0xA:5.548 - { /* XOR Rm, Rn */5.549 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.550 - sh4_stats[I_XOR]++;5.551 - }5.552 - break;5.553 - case 0xB:5.554 - { /* OR Rm, Rn */5.555 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.556 - sh4_stats[I_OR]++;5.557 - }5.558 - break;5.559 - case 0xC:5.560 - { /* CMP/STR Rm, Rn */5.561 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.562 - sh4_stats[I_CMPSTR]++;5.563 - }5.564 - break;5.565 - case 0xD:5.566 - { /* XTRCT Rm, Rn */5.567 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.568 - sh4_stats[I_XTRCT]++;5.569 - }5.570 - break;5.571 - case 0xE:5.572 - { /* MULU.W Rm, Rn */5.573 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.574 - sh4_stats[I_MULUW]++;5.575 - }5.576 - break;5.577 - case 0xF:5.578 - { /* MULS.W Rm, Rn */5.579 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.580 - sh4_stats[I_MULSW]++;5.581 - }5.582 - break;5.583 - default:5.584 - UNDEF();5.585 - break;5.586 - }5.587 - break;5.588 - case 0x3:5.589 - switch( ir&0xF ) {5.590 - case 0x0:5.591 - { /* CMP/EQ Rm, Rn */5.592 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.593 - sh4_stats[I_CMPEQ]++;5.594 - }5.595 - break;5.596 - case 0x2:5.597 - { /* CMP/HS Rm, Rn */5.598 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.599 - sh4_stats[I_CMPHS]++;5.600 - }5.601 - break;5.602 - case 0x3:5.603 - { /* CMP/GE Rm, Rn */5.604 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.605 - sh4_stats[I_CMPGE]++;5.606 - }5.607 - break;5.608 - case 0x4:5.609 - { /* DIV1 Rm, Rn */5.610 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.611 - sh4_stats[I_DIV1]++;5.612 - }5.613 - break;5.614 - case 0x5:5.615 - { /* DMULU.L Rm, Rn */5.616 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.617 - sh4_stats[I_DMULU]++;5.618 - }5.619 - break;5.620 - case 0x6:5.621 - { /* CMP/HI Rm, Rn */5.622 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.623 - sh4_stats[I_CMPHI]++;5.624 - }5.625 - break;5.626 - case 0x7:5.627 - { /* CMP/GT Rm, Rn */5.628 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.629 - sh4_stats[I_CMPGT]++;5.630 - }5.631 - break;5.632 - case 0x8:5.633 - { /* SUB Rm, Rn */5.634 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.635 - sh4_stats[I_SUB]++;5.636 - }5.637 - break;5.638 - case 0xA:5.639 - { /* SUBC Rm, Rn */5.640 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.641 - sh4_stats[I_SUBC]++;5.642 - }5.643 - break;5.644 - case 0xB:5.645 - { /* SUBV Rm, Rn */5.646 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.647 - sh4_stats[I_SUBV]++;5.648 - }5.649 - break;5.650 - case 0xC:5.651 - { /* ADD Rm, Rn */5.652 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.653 - sh4_stats[I_ADD]++;5.654 - }5.655 - break;5.656 - case 0xD:5.657 - { /* DMULS.L Rm, Rn */5.658 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.659 - sh4_stats[I_DMULS]++;5.660 - }5.661 - break;5.662 - case 0xE:5.663 - { /* ADDC Rm, Rn */5.664 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.665 - sh4_stats[I_ADDC]++;5.666 - }5.667 - break;5.668 - case 0xF:5.669 - { /* ADDV Rm, Rn */5.670 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.671 - sh4_stats[I_ADDV]++;5.672 - }5.673 - break;5.674 - default:5.675 - UNDEF();5.676 - break;5.677 - }5.678 - break;5.679 - case 0x4:5.680 - switch( ir&0xF ) {5.681 - case 0x0:5.682 - switch( (ir&0xF0) >> 4 ) {5.683 - case 0x0:5.684 - { /* SHLL Rn */5.685 - uint32_t Rn = ((ir>>8)&0xF);5.686 - sh4_stats[I_SHLL]++;5.687 - }5.688 - break;5.689 - case 0x1:5.690 - { /* DT Rn */5.691 - uint32_t Rn = ((ir>>8)&0xF);5.692 - sh4_stats[I_DT]++;5.693 - }5.694 - break;5.695 - case 0x2:5.696 - { /* SHAL Rn */5.697 - uint32_t Rn = ((ir>>8)&0xF);5.698 - sh4_stats[I_SHAL]++;5.699 - }5.700 - break;5.701 - default:5.702 - UNDEF();5.703 - break;5.704 - }5.705 - break;5.706 - case 0x1:5.707 - switch( (ir&0xF0) >> 4 ) {5.708 - case 0x0:5.709 - { /* SHLR Rn */5.710 - uint32_t Rn = ((ir>>8)&0xF);5.711 - sh4_stats[I_SHLR]++;5.712 - }5.713 - break;5.714 - case 0x1:5.715 - { /* CMP/PZ Rn */5.716 - uint32_t Rn = ((ir>>8)&0xF);5.717 - sh4_stats[I_CMPPZ]++;5.718 - }5.719 - break;5.720 - case 0x2:5.721 - { /* SHAR Rn */5.722 - uint32_t Rn = ((ir>>8)&0xF);5.723 - sh4_stats[I_SHAR]++;5.724 - }5.725 - break;5.726 - default:5.727 - UNDEF();5.728 - break;5.729 - }5.730 - break;5.731 - case 0x2:5.732 - switch( (ir&0xF0) >> 4 ) {5.733 - case 0x0:5.734 - { /* STS.L MACH, @-Rn */5.735 - uint32_t Rn = ((ir>>8)&0xF);5.736 - sh4_stats[I_STSM]++;5.737 - }5.738 - break;5.739 - case 0x1:5.740 - { /* STS.L MACL, @-Rn */5.741 - uint32_t Rn = ((ir>>8)&0xF);5.742 - sh4_stats[I_STSM]++;5.743 - }5.744 - break;5.745 - case 0x2:5.746 - { /* STS.L PR, @-Rn */5.747 - uint32_t Rn = ((ir>>8)&0xF);5.748 - sh4_stats[I_STSM]++;5.749 - }5.750 - break;5.751 - case 0x3:5.752 - { /* STC.L SGR, @-Rn */5.753 - uint32_t Rn = ((ir>>8)&0xF);5.754 - sh4_stats[I_STCM]++;5.755 - }5.756 - break;5.757 - case 0x5:5.758 - { /* STS.L FPUL, @-Rn */5.759 - uint32_t Rn = ((ir>>8)&0xF);5.760 - sh4_stats[I_STSM]++;5.761 - }5.762 - break;5.763 - case 0x6:5.764 - { /* STS.L FPSCR, @-Rn */5.765 - uint32_t Rn = ((ir>>8)&0xF);5.766 - sh4_stats[I_STSFPSCRM]++;5.767 - }5.768 - break;5.769 - case 0xF:5.770 - { /* STC.L DBR, @-Rn */5.771 - uint32_t Rn = ((ir>>8)&0xF);5.772 - sh4_stats[I_STCM]++;5.773 - }5.774 - break;5.775 - default:5.776 - UNDEF();5.777 - break;5.778 - }5.779 - break;5.780 - case 0x3:5.781 - switch( (ir&0x80) >> 7 ) {5.782 - case 0x0:5.783 - switch( (ir&0x70) >> 4 ) {5.784 - case 0x0:5.785 - { /* STC.L SR, @-Rn */5.786 - uint32_t Rn = ((ir>>8)&0xF);5.787 - sh4_stats[I_STCSRM]++;5.788 - }5.789 - break;5.790 - case 0x1:5.791 - { /* STC.L GBR, @-Rn */5.792 - uint32_t Rn = ((ir>>8)&0xF);5.793 - sh4_stats[I_STCM]++;5.794 - }5.795 - break;5.796 - case 0x2:5.797 - { /* STC.L VBR, @-Rn */5.798 - uint32_t Rn = ((ir>>8)&0xF);5.799 - sh4_stats[I_STCM]++;5.800 - }5.801 - break;5.802 - case 0x3:5.803 - { /* STC.L SSR, @-Rn */5.804 - uint32_t Rn = ((ir>>8)&0xF);5.805 - sh4_stats[I_STCM]++;5.806 - }5.807 - break;5.808 - case 0x4:5.809 - { /* STC.L SPC, @-Rn */5.810 - uint32_t Rn = ((ir>>8)&0xF);5.811 - sh4_stats[I_STCM]++;5.812 - }5.813 - break;5.814 - default:5.815 - UNDEF();5.816 - break;5.817 - }5.818 - break;5.819 - case 0x1:5.820 - { /* STC.L Rm_BANK, @-Rn */5.821 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);5.822 - sh4_stats[I_STCM]++;5.823 - }5.824 - break;5.825 - }5.826 - break;5.827 - case 0x4:5.828 - switch( (ir&0xF0) >> 4 ) {5.829 - case 0x0:5.830 - { /* ROTL Rn */5.831 - uint32_t Rn = ((ir>>8)&0xF);5.832 - sh4_stats[I_ROTL]++;5.833 - }5.834 - break;5.835 - case 0x2:5.836 - { /* ROTCL Rn */5.837 - uint32_t Rn = ((ir>>8)&0xF);5.838 - sh4_stats[I_ROTCL]++;5.839 - }5.840 - break;5.841 - default:5.842 - UNDEF();5.843 - break;5.844 - }5.845 - break;5.846 - case 0x5:5.847 - switch( (ir&0xF0) >> 4 ) {5.848 - case 0x0:5.849 - { /* ROTR Rn */5.850 - uint32_t Rn = ((ir>>8)&0xF);5.851 - sh4_stats[I_ROTR]++;5.852 - }5.853 - break;5.854 - case 0x1:5.855 - { /* CMP/PL Rn */5.856 - uint32_t Rn = ((ir>>8)&0xF);5.857 - sh4_stats[I_CMPPL]++;5.858 - }5.859 - break;5.860 - case 0x2:5.861 - { /* ROTCR Rn */5.862 - uint32_t Rn = ((ir>>8)&0xF);5.863 - sh4_stats[I_ROTCR]++;5.864 - }5.865 - break;5.866 - default:5.867 - UNDEF();5.868 - break;5.869 - }5.870 - break;5.871 - case 0x6:5.872 - switch( (ir&0xF0) >> 4 ) {5.873 - case 0x0:5.874 - { /* LDS.L @Rm+, MACH */5.875 - uint32_t Rm = ((ir>>8)&0xF);5.876 - sh4_stats[I_LDSM]++;5.877 - }5.878 - break;5.879 - case 0x1:5.880 - { /* LDS.L @Rm+, MACL */5.881 - uint32_t Rm = ((ir>>8)&0xF);5.882 - sh4_stats[I_LDSM]++;5.883 - }5.884 - break;5.885 - case 0x2:5.886 - { /* LDS.L @Rm+, PR */5.887 - uint32_t Rm = ((ir>>8)&0xF);5.888 - sh4_stats[I_LDSM]++;5.889 - }5.890 - break;5.891 - case 0x3:5.892 - { /* LDC.L @Rm+, SGR */5.893 - uint32_t Rm = ((ir>>8)&0xF);5.894 - sh4_stats[I_LDCM]++;5.895 - }5.896 - break;5.897 - case 0x5:5.898 - { /* LDS.L @Rm+, FPUL */5.899 - uint32_t Rm = ((ir>>8)&0xF);5.900 - sh4_stats[I_LDSM]++;5.901 - }5.902 - break;5.903 - case 0x6:5.904 - { /* LDS.L @Rm+, FPSCR */5.905 - uint32_t Rm = ((ir>>8)&0xF);5.906 - sh4_stats[I_LDSFPSCRM]++;5.907 - }5.908 - break;5.909 - case 0xF:5.910 - { /* LDC.L @Rm+, DBR */5.911 - uint32_t Rm = ((ir>>8)&0xF);5.912 - sh4_stats[I_LDCM]++;5.913 - }5.914 - break;5.915 - default:5.916 - UNDEF();5.917 - break;5.918 - }5.919 - break;5.920 - case 0x7:5.921 - switch( (ir&0x80) >> 7 ) {5.922 - case 0x0:5.923 - switch( (ir&0x70) >> 4 ) {5.924 - case 0x0:5.925 - { /* LDC.L @Rm+, SR */5.926 - uint32_t Rm = ((ir>>8)&0xF);5.927 - sh4_stats[I_LDCSRM]++;5.928 - }5.929 - break;5.930 - case 0x1:5.931 - { /* LDC.L @Rm+, GBR */5.932 - uint32_t Rm = ((ir>>8)&0xF);5.933 - sh4_stats[I_LDCM]++;5.934 - }5.935 - break;5.936 - case 0x2:5.937 - { /* LDC.L @Rm+, VBR */5.938 - uint32_t Rm = ((ir>>8)&0xF);5.939 - sh4_stats[I_LDCM]++;5.940 - }5.941 - break;5.942 - case 0x3:5.943 - { /* LDC.L @Rm+, SSR */5.944 - uint32_t Rm = ((ir>>8)&0xF);5.945 - sh4_stats[I_LDCM]++;5.946 - }5.947 - break;5.948 - case 0x4:5.949 - { /* LDC.L @Rm+, SPC */5.950 - uint32_t Rm = ((ir>>8)&0xF);5.951 - sh4_stats[I_LDCM]++;5.952 - }5.953 - break;5.954 - default:5.955 - UNDEF();5.956 - break;5.957 - }5.958 - break;5.959 - case 0x1:5.960 - { /* LDC.L @Rm+, Rn_BANK */5.961 - uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);5.962 - sh4_stats[I_LDCM]++;5.963 - }5.964 - break;5.965 - }5.966 - break;5.967 - case 0x8:5.968 - switch( (ir&0xF0) >> 4 ) {5.969 - case 0x0:5.970 - { /* SHLL2 Rn */5.971 - uint32_t Rn = ((ir>>8)&0xF);5.972 - sh4_stats[I_SHLL]++;5.973 - }5.974 - break;5.975 - case 0x1:5.976 - { /* SHLL8 Rn */5.977 - uint32_t Rn = ((ir>>8)&0xF);5.978 - sh4_stats[I_SHLL]++;5.979 - }5.980 - break;5.981 - case 0x2:5.982 - { /* SHLL16 Rn */5.983 - uint32_t Rn = ((ir>>8)&0xF);5.984 - sh4_stats[I_SHLL]++;5.985 - }5.986 - break;5.987 - default:5.988 - UNDEF();5.989 - break;5.990 - }5.991 - break;5.992 - case 0x9:5.993 - switch( (ir&0xF0) >> 4 ) {5.994 - case 0x0:5.995 - { /* SHLR2 Rn */5.996 - uint32_t Rn = ((ir>>8)&0xF);5.997 - sh4_stats[I_SHLR]++;5.998 - }5.999 - break;5.1000 - case 0x1:5.1001 - { /* SHLR8 Rn */5.1002 - uint32_t Rn = ((ir>>8)&0xF);5.1003 - sh4_stats[I_SHLR]++;5.1004 - }5.1005 - break;5.1006 - case 0x2:5.1007 - { /* SHLR16 Rn */5.1008 - uint32_t Rn = ((ir>>8)&0xF);5.1009 - sh4_stats[I_SHLR]++;5.1010 - }5.1011 - break;5.1012 - default:5.1013 - UNDEF();5.1014 - break;5.1015 - }5.1016 - break;5.1017 - case 0xA:5.1018 - switch( (ir&0xF0) >> 4 ) {5.1019 - case 0x0:5.1020 - { /* LDS Rm, MACH */5.1021 - uint32_t Rm = ((ir>>8)&0xF);5.1022 - sh4_stats[I_LDS]++;5.1023 - }5.1024 - break;5.1025 - case 0x1:5.1026 - { /* LDS Rm, MACL */5.1027 - uint32_t Rm = ((ir>>8)&0xF);5.1028 - sh4_stats[I_LDS]++;5.1029 - }5.1030 - break;5.1031 - case 0x2:5.1032 - { /* LDS Rm, PR */5.1033 - uint32_t Rm = ((ir>>8)&0xF);5.1034 - sh4_stats[I_LDS]++;5.1035 - }5.1036 - break;5.1037 - case 0x3:5.1038 - { /* LDC Rm, SGR */5.1039 - uint32_t Rm = ((ir>>8)&0xF);5.1040 - sh4_stats[I_LDC]++;5.1041 - }5.1042 - break;5.1043 - case 0x5:5.1044 - { /* LDS Rm, FPUL */5.1045 - uint32_t Rm = ((ir>>8)&0xF);5.1046 - sh4_stats[I_LDS]++;5.1047 - }5.1048 - break;5.1049 - case 0x6:5.1050 - { /* LDS Rm, FPSCR */5.1051 - uint32_t Rm = ((ir>>8)&0xF);5.1052 - sh4_stats[I_LDSFPSCR]++;5.1053 - }5.1054 - break;5.1055 - case 0xF:5.1056 - { /* LDC Rm, DBR */5.1057 - uint32_t Rm = ((ir>>8)&0xF);5.1058 - sh4_stats[I_LDC]++;5.1059 - }5.1060 - break;5.1061 - default:5.1062 - UNDEF();5.1063 - break;5.1064 - }5.1065 - break;5.1066 - case 0xB:5.1067 - switch( (ir&0xF0) >> 4 ) {5.1068 - case 0x0:5.1069 - { /* JSR @Rn */5.1070 - uint32_t Rn = ((ir>>8)&0xF);5.1071 - sh4_stats[I_JSR]++;5.1072 - }5.1073 - break;5.1074 - case 0x1:5.1075 - { /* TAS.B @Rn */5.1076 - uint32_t Rn = ((ir>>8)&0xF);5.1077 - sh4_stats[I_TASB]++;5.1078 - }5.1079 - break;5.1080 - case 0x2:5.1081 - { /* JMP @Rn */5.1082 - uint32_t Rn = ((ir>>8)&0xF);5.1083 - sh4_stats[I_JMP]++;5.1084 - }5.1085 - break;5.1086 - default:5.1087 - UNDEF();5.1088 - break;5.1089 - }5.1090 - break;5.1091 - case 0xC:5.1092 - { /* SHAD Rm, Rn */5.1093 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.1094 - sh4_stats[I_SHAD]++;5.1095 - }5.1096 - break;5.1097 - case 0xD:5.1098 - { /* SHLD Rm, Rn */5.1099 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.1100 - sh4_stats[I_SHLD]++;5.1101 - }5.1102 - break;5.1103 - case 0xE:5.1104 - switch( (ir&0x80) >> 7 ) {5.1105 - case 0x0:5.1106 - switch( (ir&0x70) >> 4 ) {5.1107 - case 0x0:5.1108 - { /* LDC Rm, SR */5.1109 - uint32_t Rm = ((ir>>8)&0xF);5.1110 - sh4_stats[I_LDCSR]++;5.1111 - }5.1112 - break;5.1113 - case 0x1:5.1114 - { /* LDC Rm, GBR */5.1115 - uint32_t Rm = ((ir>>8)&0xF);5.1116 - sh4_stats[I_LDC]++;5.1117 - }5.1118 - break;5.1119 - case 0x2:5.1120 - { /* LDC Rm, VBR */5.1121 - uint32_t Rm = ((ir>>8)&0xF);5.1122 - sh4_stats[I_LDC]++;5.1123 - }5.1124 - break;5.1125 - case 0x3:5.1126 - { /* LDC Rm, SSR */5.1127 - uint32_t Rm = ((ir>>8)&0xF);5.1128 - sh4_stats[I_LDC]++;5.1129 - }5.1130 - break;5.1131 - case 0x4:5.1132 - { /* LDC Rm, SPC */5.1133 - uint32_t Rm = ((ir>>8)&0xF);5.1134 - sh4_stats[I_LDC]++;5.1135 - }5.1136 - break;5.1137 - default:5.1138 - UNDEF();5.1139 - break;5.1140 - }5.1141 - break;5.1142 - case 0x1:5.1143 - { /* LDC Rm, Rn_BANK */5.1144 - uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);5.1145 - sh4_stats[I_LDC]++;5.1146 - }5.1147 - break;5.1148 - }5.1149 - break;5.1150 - case 0xF:5.1151 - { /* MAC.W @Rm+, @Rn+ */5.1152 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.1153 - sh4_stats[I_MACW]++;5.1154 - }5.1155 - break;5.1156 - }5.1157 - break;5.1158 - case 0x5:5.1159 - { /* MOV.L @(disp, Rm), Rn */5.1160 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;5.1161 - sh4_stats[I_MOVL]++;5.1162 - }5.1163 - break;5.1164 - case 0x6:5.1165 - switch( ir&0xF ) {5.1166 - case 0x0:5.1167 - { /* MOV.B @Rm, Rn */5.1168 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.1169 - sh4_stats[I_MOVB]++;5.1170 - }5.1171 - break;5.1172 - case 0x1:5.1173 - { /* MOV.W @Rm, Rn */5.1174 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.1175 - sh4_stats[I_MOVW]++;5.1176 - }5.1177 - break;5.1178 - case 0x2:5.1179 - { /* MOV.L @Rm, Rn */5.1180 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.1181 - sh4_stats[I_MOVL]++;5.1182 - }5.1183 - break;5.1184 - case 0x3:5.1185 - { /* MOV Rm, Rn */5.1186 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.1187 - sh4_stats[I_MOV]++;5.1188 - }5.1189 - break;5.1190 - case 0x4:5.1191 - { /* MOV.B @Rm+, Rn */5.1192 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.1193 - sh4_stats[I_MOVB]++;5.1194 - }5.1195 - break;5.1196 - case 0x5:5.1197 - { /* MOV.W @Rm+, Rn */5.1198 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.1199 - sh4_stats[I_MOVW]++;5.1200 - }5.1201 - break;5.1202 - case 0x6:5.1203 - { /* MOV.L @Rm+, Rn */5.1204 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.1205 - sh4_stats[I_MOVL]++;5.1206 - }5.1207 - break;5.1208 - case 0x7:5.1209 - { /* NOT Rm, Rn */5.1210 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.1211 - sh4_stats[I_NOT]++;5.1212 - }5.1213 - break;5.1214 - case 0x8:5.1215 - { /* SWAP.B Rm, Rn */5.1216 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.1217 - sh4_stats[I_SWAPB]++;5.1218 - }5.1219 - break;5.1220 - case 0x9:5.1221 - { /* SWAP.W Rm, Rn */5.1222 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.1223 - sh4_stats[I_SWAPW]++;5.1224 - }5.1225 - break;5.1226 - case 0xA:5.1227 - { /* NEGC Rm, Rn */5.1228 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.1229 - sh4_stats[I_NEGC]++;5.1230 - }5.1231 - break;5.1232 - case 0xB:5.1233 - { /* NEG Rm, Rn */5.1234 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.1235 - sh4_stats[I_NEG]++;5.1236 - }5.1237 - break;5.1238 - case 0xC:5.1239 - { /* EXTU.B Rm, Rn */5.1240 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.1241 - sh4_stats[I_EXTUB]++;5.1242 - }5.1243 - break;5.1244 - case 0xD:5.1245 - { /* EXTU.W Rm, Rn */5.1246 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.1247 - sh4_stats[I_EXTUW]++;5.1248 - }5.1249 - break;5.1250 - case 0xE:5.1251 - { /* EXTS.B Rm, Rn */5.1252 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.1253 - sh4_stats[I_EXTSB]++;5.1254 - }5.1255 - break;5.1256 - case 0xF:5.1257 - { /* EXTS.W Rm, Rn */5.1258 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.1259 - sh4_stats[I_EXTSW]++;5.1260 - }5.1261 - break;5.1262 - }5.1263 - break;5.1264 - case 0x7:5.1265 - { /* ADD #imm, Rn */5.1266 - uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);5.1267 - sh4_stats[I_ADDI]++;5.1268 - }5.1269 - break;5.1270 - case 0x8:5.1271 - switch( (ir&0xF00) >> 8 ) {5.1272 - case 0x0:5.1273 - { /* MOV.B R0, @(disp, Rn) */5.1274 - uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);5.1275 - sh4_stats[I_MOVB]++;5.1276 - }5.1277 - break;5.1278 - case 0x1:5.1279 - { /* MOV.W R0, @(disp, Rn) */5.1280 - uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;5.1281 - sh4_stats[I_MOVW]++;5.1282 - }5.1283 - break;5.1284 - case 0x4:5.1285 - { /* MOV.B @(disp, Rm), R0 */5.1286 - uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);5.1287 - sh4_stats[I_MOVB]++;5.1288 - }5.1289 - break;5.1290 - case 0x5:5.1291 - { /* MOV.W @(disp, Rm), R0 */5.1292 - uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;5.1293 - sh4_stats[I_MOVW]++;5.1294 - }5.1295 - break;5.1296 - case 0x8:5.1297 - { /* CMP/EQ #imm, R0 */5.1298 - int32_t imm = SIGNEXT8(ir&0xFF);5.1299 - sh4_stats[I_CMPEQI]++;5.1300 - }5.1301 - break;5.1302 - case 0x9:5.1303 - { /* BT disp */5.1304 - int32_t disp = SIGNEXT8(ir&0xFF)<<1;5.1305 - sh4_stats[I_BT]++;5.1306 - }5.1307 - break;5.1308 - case 0xB:5.1309 - { /* BF disp */5.1310 - int32_t disp = SIGNEXT8(ir&0xFF)<<1;5.1311 - sh4_stats[I_BF]++;5.1312 - }5.1313 - break;5.1314 - case 0xD:5.1315 - { /* BT/S disp */5.1316 - int32_t disp = SIGNEXT8(ir&0xFF)<<1;5.1317 - sh4_stats[I_BTS]++;5.1318 - }5.1319 - break;5.1320 - case 0xF:5.1321 - { /* BF/S disp */5.1322 - int32_t disp = SIGNEXT8(ir&0xFF)<<1;5.1323 - sh4_stats[I_BFS]++;5.1324 - }5.1325 - break;5.1326 - default:5.1327 - UNDEF();5.1328 - break;5.1329 - }5.1330 - break;5.1331 - case 0x9:5.1332 - { /* MOV.W @(disp, PC), Rn */5.1333 - uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1;5.1334 - sh4_stats[I_MOVW]++;5.1335 - }5.1336 - break;5.1337 - case 0xA:5.1338 - { /* BRA disp */5.1339 - int32_t disp = SIGNEXT12(ir&0xFFF)<<1;5.1340 - sh4_stats[I_BRA]++;5.1341 - }5.1342 - break;5.1343 - case 0xB:5.1344 - { /* BSR disp */5.1345 - int32_t disp = SIGNEXT12(ir&0xFFF)<<1;5.1346 - sh4_stats[I_BSR]++;5.1347 - }5.1348 - break;5.1349 - case 0xC:5.1350 - switch( (ir&0xF00) >> 8 ) {5.1351 - case 0x0:5.1352 - { /* MOV.B R0, @(disp, GBR) */5.1353 - uint32_t disp = (ir&0xFF);5.1354 - sh4_stats[I_MOVB]++;5.1355 - }5.1356 - break;5.1357 - case 0x1:5.1358 - { /* MOV.W R0, @(disp, GBR) */5.1359 - uint32_t disp = (ir&0xFF)<<1;5.1360 - sh4_stats[I_MOVW]++;5.1361 - }5.1362 - break;5.1363 - case 0x2:5.1364 - { /* MOV.L R0, @(disp, GBR) */5.1365 - uint32_t disp = (ir&0xFF)<<2;5.1366 - sh4_stats[I_MOVL]++;5.1367 - }5.1368 - break;5.1369 - case 0x3:5.1370 - { /* TRAPA #imm */5.1371 - uint32_t imm = (ir&0xFF);5.1372 - sh4_stats[I_TRAPA]++;5.1373 - }5.1374 - break;5.1375 - case 0x4:5.1376 - { /* MOV.B @(disp, GBR), R0 */5.1377 - uint32_t disp = (ir&0xFF);5.1378 - sh4_stats[I_MOVB]++;5.1379 - }5.1380 - break;5.1381 - case 0x5:5.1382 - { /* MOV.W @(disp, GBR), R0 */5.1383 - uint32_t disp = (ir&0xFF)<<1;5.1384 - sh4_stats[I_MOVW]++;5.1385 - }5.1386 - break;5.1387 - case 0x6:5.1388 - { /* MOV.L @(disp, GBR), R0 */5.1389 - uint32_t disp = (ir&0xFF)<<2;5.1390 - sh4_stats[I_MOVL]++;5.1391 - }5.1392 - break;5.1393 - case 0x7:5.1394 - { /* MOVA @(disp, PC), R0 */5.1395 - uint32_t disp = (ir&0xFF)<<2;5.1396 - sh4_stats[I_MOVA]++;5.1397 - }5.1398 - break;5.1399 - case 0x8:5.1400 - { /* TST #imm, R0 */5.1401 - uint32_t imm = (ir&0xFF);5.1402 - sh4_stats[I_TSTI]++;5.1403 - }5.1404 - break;5.1405 - case 0x9:5.1406 - { /* AND #imm, R0 */5.1407 - uint32_t imm = (ir&0xFF);5.1408 - sh4_stats[I_ANDI]++;5.1409 - }5.1410 - break;5.1411 - case 0xA:5.1412 - { /* XOR #imm, R0 */5.1413 - uint32_t imm = (ir&0xFF);5.1414 - sh4_stats[I_XORI]++;5.1415 - }5.1416 - break;5.1417 - case 0xB:5.1418 - { /* OR #imm, R0 */5.1419 - uint32_t imm = (ir&0xFF);5.1420 - sh4_stats[I_ORI]++;5.1421 - }5.1422 - break;5.1423 - case 0xC:5.1424 - { /* TST.B #imm, @(R0, GBR) */5.1425 - uint32_t imm = (ir&0xFF);5.1426 - sh4_stats[I_TSTB]++;5.1427 - }5.1428 - break;5.1429 - case 0xD:5.1430 - { /* AND.B #imm, @(R0, GBR) */5.1431 - uint32_t imm = (ir&0xFF);5.1432 - sh4_stats[I_ANDB]++;5.1433 - }5.1434 - break;5.1435 - case 0xE:5.1436 - { /* XOR.B #imm, @(R0, GBR) */5.1437 - uint32_t imm = (ir&0xFF);5.1438 - sh4_stats[I_XORB]++;5.1439 - }5.1440 - break;5.1441 - case 0xF:5.1442 - { /* OR.B #imm, @(R0, GBR) */5.1443 - uint32_t imm = (ir&0xFF);5.1444 - sh4_stats[I_ORB]++;5.1445 - }5.1446 - break;5.1447 - }5.1448 - break;5.1449 - case 0xD:5.1450 - { /* MOV.L @(disp, PC), Rn */5.1451 - uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2;5.1452 - sh4_stats[I_MOVLPC]++;5.1453 - }5.1454 - break;5.1455 - case 0xE:5.1456 - { /* MOV #imm, Rn */5.1457 - uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);5.1458 - sh4_stats[I_MOVI]++;5.1459 - }5.1460 - break;5.1461 - case 0xF:5.1462 - switch( ir&0xF ) {5.1463 - case 0x0:5.1464 - { /* FADD FRm, FRn */5.1465 - uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);5.1466 - sh4_stats[I_FADD]++;5.1467 - }5.1468 - break;5.1469 - case 0x1:5.1470 - { /* FSUB FRm, FRn */5.1471 - uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);5.1472 - sh4_stats[I_FSUB]++;5.1473 - }5.1474 - break;5.1475 - case 0x2:5.1476 - { /* FMUL FRm, FRn */5.1477 - uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);5.1478 - sh4_stats[I_FMUL]++;5.1479 - }5.1480 - break;5.1481 - case 0x3:5.1482 - { /* FDIV FRm, FRn */5.1483 - uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);5.1484 - sh4_stats[I_FDIV]++;5.1485 - }5.1486 - break;5.1487 - case 0x4:5.1488 - { /* FCMP/EQ FRm, FRn */5.1489 - uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);5.1490 - sh4_stats[I_FCMPEQ]++;5.1491 - }5.1492 - break;5.1493 - case 0x5:5.1494 - { /* FCMP/GT FRm, FRn */5.1495 - uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);5.1496 - sh4_stats[I_FCMPGT]++;5.1497 - }5.1498 - break;5.1499 - case 0x6:5.1500 - { /* FMOV @(R0, Rm), FRn */5.1501 - uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.1502 - sh4_stats[I_FMOV7]++;5.1503 - }5.1504 - break;5.1505 - case 0x7:5.1506 - { /* FMOV FRm, @(R0, Rn) */5.1507 - uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);5.1508 - sh4_stats[I_FMOV4]++;5.1509 - }5.1510 - break;5.1511 - case 0x8:5.1512 - { /* FMOV @Rm, FRn */5.1513 - uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.1514 - sh4_stats[I_FMOV5]++;5.1515 - }5.1516 - break;5.1517 - case 0x9:5.1518 - { /* FMOV @Rm+, FRn */5.1519 - uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);5.1520 - sh4_stats[I_FMOV6]++;5.1521 - }5.1522 - break;5.1523 - case 0xA:5.1524 - { /* FMOV FRm, @Rn */5.1525 - uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);5.1526 - sh4_stats[I_FMOV2]++;5.1527 - }5.1528 - break;5.1529 - case 0xB:5.1530 - { /* FMOV FRm, @-Rn */5.1531 - uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);5.1532 - sh4_stats[I_FMOV3]++;5.1533 - }5.1534 - break;5.1535 - case 0xC:5.1536 - { /* FMOV FRm, FRn */5.1537 - uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);5.1538 - sh4_stats[I_FMOV1]++;5.1539 - }5.1540 - break;5.1541 - case 0xD:5.1542 - switch( (ir&0xF0) >> 4 ) {5.1543 - case 0x0:5.1544 - { /* FSTS FPUL, FRn */5.1545 - uint32_t FRn = ((ir>>8)&0xF);5.1546 - sh4_stats[I_FSTS]++;5.1547 - }5.1548 - break;5.1549 - case 0x1:5.1550 - { /* FLDS FRm, FPUL */5.1551 - uint32_t FRm = ((ir>>8)&0xF);5.1552 - sh4_stats[I_FLDS]++;5.1553 - }5.1554 - break;5.1555 - case 0x2:5.1556 - { /* FLOAT FPUL, FRn */5.1557 - uint32_t FRn = ((ir>>8)&0xF);5.1558 - sh4_stats[I_FLOAT]++;5.1559 - }5.1560 - break;5.1561 - case 0x3:5.1562 - { /* FTRC FRm, FPUL */5.1563 - uint32_t FRm = ((ir>>8)&0xF);5.1564 - sh4_stats[I_FTRC]++;5.1565 - }5.1566 - break;5.1567 - case 0x4:5.1568 - { /* FNEG FRn */5.1569 - uint32_t FRn = ((ir>>8)&0xF);5.1570 - sh4_stats[I_FNEG]++;5.1571 - }5.1572 - break;5.1573 - case 0x5:5.1574 - { /* FABS FRn */5.1575 - uint32_t FRn = ((ir>>8)&0xF);5.1576 - sh4_stats[I_FABS]++;5.1577 - }5.1578 - break;5.1579 - case 0x6:5.1580 - { /* FSQRT FRn */5.1581 - uint32_t FRn = ((ir>>8)&0xF);5.1582 - sh4_stats[I_FSQRT]++;5.1583 - }5.1584 - break;5.1585 - case 0x7:5.1586 - { /* FSRRA FRn */5.1587 - uint32_t FRn = ((ir>>8)&0xF);5.1588 - sh4_stats[I_FSRRA]++;5.1589 - }5.1590 - break;5.1591 - case 0x8:5.1592 - { /* FLDI0 FRn */5.1593 - uint32_t FRn = ((ir>>8)&0xF);5.1594 - sh4_stats[I_FLDI0]++;5.1595 - }5.1596 - break;5.1597 - case 0x9:5.1598 - { /* FLDI1 FRn */5.1599 - uint32_t FRn = ((ir>>8)&0xF);5.1600 - sh4_stats[I_FLDI1]++;5.1601 - }5.1602 - break;5.1603 - case 0xA:5.1604 - { /* FCNVSD FPUL, FRn */5.1605 - uint32_t FRn = ((ir>>8)&0xF);5.1606 - sh4_stats[I_FCNVSD]++;5.1607 - }5.1608 - break;5.1609 - case 0xB:5.1610 - { /* FCNVDS FRm, FPUL */5.1611 - uint32_t FRm = ((ir>>8)&0xF);5.1612 - sh4_stats[I_FCNVDS]++;5.1613 - }5.1614 - break;5.1615 - case 0xE:5.1616 - { /* FIPR FVm, FVn */5.1617 - uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3);5.1618 - sh4_stats[I_FIPR]++;5.1619 - }5.1620 - break;5.1621 - case 0xF:5.1622 - switch( (ir&0x100) >> 8 ) {5.1623 - case 0x0:5.1624 - { /* FSCA FPUL, FRn */5.1625 - uint32_t FRn = ((ir>>9)&0x7)<<1;5.1626 - sh4_stats[I_FSCA]++;5.1627 - }5.1628 - break;5.1629 - case 0x1:5.1630 - switch( (ir&0x200) >> 9 ) {5.1631 - case 0x0:5.1632 - { /* FTRV XMTRX, FVn */5.1633 - uint32_t FVn = ((ir>>10)&0x3);5.1634 - sh4_stats[I_FTRV]++;5.1635 - }5.1636 - break;5.1637 - case 0x1:5.1638 - switch( (ir&0xC00) >> 10 ) {5.1639 - case 0x0:5.1640 - { /* FSCHG */5.1641 - sh4_stats[I_FSCHG]++;5.1642 - }5.1643 - break;5.1644 - case 0x2:5.1645 - { /* FRCHG */5.1646 - sh4_stats[I_FRCHG]++;5.1647 - }5.1648 - break;5.1649 - case 0x3:5.1650 - { /* UNDEF */5.1651 - sh4_stats[I_UNDEF]++;5.1652 - }5.1653 - break;5.1654 - default:5.1655 - UNDEF();5.1656 - break;5.1657 - }5.1658 - break;5.1659 - }5.1660 - break;5.1661 - }5.1662 - break;5.1663 - default:5.1664 - UNDEF();5.1665 - break;5.1666 - }5.1667 - break;5.1668 - case 0xE:5.1669 - { /* FMAC FR0, FRm, FRn */5.1670 - uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);5.1671 - sh4_stats[I_FMAC]++;5.1672 - }5.1673 - break;5.1674 - default:5.1675 - UNDEF();5.1676 - break;5.1677 - }5.1678 - break;5.1679 - }5.1680 -5.1681 -5.1682 -sh4_stats_total++;5.1683 -}
6.1 --- a/src/sh4/sh4x86.c Sat Jul 19 02:34:11 2008 +00006.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +00006.3 @@ -1,3689 +0,0 @@6.4 -/**6.5 - * $Id$6.6 - *6.7 - * SH4 => x86 translation. This version does no real optimization, it just6.8 - * outputs straight-line x86 code - it mainly exists to provide a baseline6.9 - * to test the optimizing versions against.6.10 - *6.11 - * Copyright (c) 2007 Nathan Keynes.6.12 - *6.13 - * This program is free software; you can redistribute it and/or modify6.14 - * it under the terms of the GNU General Public License as published by6.15 - * the Free Software Foundation; either version 2 of the License, or6.16 - * (at your option) any later version.6.17 - *6.18 - * This program is distributed in the hope that it will be useful,6.19 - * but WITHOUT ANY WARRANTY; without even the implied warranty of6.20 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the6.21 - * GNU General Public License for more details.6.22 - */6.23 -6.24 -#include <assert.h>6.25 -#include <math.h>6.26 -6.27 -#ifndef NDEBUG6.28 -#define DEBUG_JUMPS 16.29 -#endif6.30 -6.31 -#include "sh4/xltcache.h"6.32 -#include "sh4/sh4core.h"6.33 -#include "sh4/sh4trans.h"6.34 -#include "sh4/sh4stat.h"6.35 -#include "sh4/sh4mmio.h"6.36 -#include "sh4/x86op.h"6.37 -#include "clock.h"6.38 -6.39 -#define DEFAULT_BACKPATCH_SIZE 40966.40 -6.41 -struct backpatch_record {6.42 - uint32_t fixup_offset;6.43 - uint32_t fixup_icount;6.44 - int32_t exc_code;6.45 -};6.46 -6.47 -#define DELAY_NONE 06.48 -#define DELAY_PC 16.49 -#define DELAY_PC_PR 26.50 -6.51 -/**6.52 - * Struct to manage internal translation state. This state is not saved -6.53 - * it is only valid between calls to sh4_translate_begin_block() and6.54 - * sh4_translate_end_block()6.55 - */6.56 -struct sh4_x86_state {6.57 - int in_delay_slot;6.58 - gboolean priv_checked; /* true if we've already checked the cpu mode. */6.59 - gboolean fpuen_checked; /* true if we've already checked fpu enabled. */6.60 - gboolean branch_taken; /* true if we branched unconditionally */6.61 - uint32_t block_start_pc;6.62 - uint32_t stack_posn; /* Trace stack height for alignment purposes */6.63 - int tstate;6.64 -6.65 - /* mode flags */6.66 - gboolean tlb_on; /* True if tlb translation is active */6.67 -6.68 - /* Allocated memory for the (block-wide) back-patch list */6.69 - struct backpatch_record *backpatch_list;6.70 - uint32_t backpatch_posn;6.71 - uint32_t backpatch_size;6.72 -};6.73 -6.74 -#define TSTATE_NONE -16.75 -#define TSTATE_O 06.76 -#define TSTATE_C 26.77 -#define TSTATE_E 46.78 -#define TSTATE_NE 56.79 -#define TSTATE_G 0xF6.80 -#define TSTATE_GE 0xD6.81 -#define TSTATE_A 76.82 -#define TSTATE_AE 36.83 -6.84 -#ifdef ENABLE_SH4STATS6.85 -#define COUNT_INST(id) load_imm32(R_EAX,id); call_func1(sh4_stats_add, R_EAX); sh4_x86.tstate = TSTATE_NONE6.86 -#else6.87 -#define COUNT_INST(id)6.88 -#endif6.89 -6.90 -/** Branch if T is set (either in the current cflags, or in sh4r.t) */6.91 -#define JT_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \6.92 - CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \6.93 - OP(0x70+sh4_x86.tstate); MARK_JMP8(label); OP(-1)6.94 -6.95 -/** Branch if T is clear (either in the current cflags or in sh4r.t) */6.96 -#define JF_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \6.97 - CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \6.98 - OP(0x70+ (sh4_x86.tstate^1)); MARK_JMP8(label); OP(-1)6.99 -6.100 -static struct sh4_x86_state sh4_x86;6.101 -6.102 -static uint32_t max_int = 0x7FFFFFFF;6.103 -static uint32_t min_int = 0x80000000;6.104 -static uint32_t save_fcw; /* save value for fpu control word */6.105 -static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */6.106 -6.107 -void sh4_translate_init(void)6.108 -{6.109 - sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);6.110 - sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);6.111 -}6.112 -6.113 -6.114 -static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )6.115 -{6.116 - if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {6.117 - sh4_x86.backpatch_size <<= 1;6.118 - sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list,6.119 - sh4_x86.backpatch_size * sizeof(struct backpatch_record));6.120 - assert( sh4_x86.backpatch_list != NULL );6.121 - }6.122 - if( sh4_x86.in_delay_slot ) {6.123 - fixup_pc -= 2;6.124 - }6.125 - sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_offset =6.126 - ((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code);6.127 - sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;6.128 - sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;6.129 - sh4_x86.backpatch_posn++;6.130 -}6.131 -6.132 -/**6.133 - * Emit an instruction to load an SH4 reg into a real register6.134 - */6.135 -static inline void load_reg( int x86reg, int sh4reg )6.136 -{6.137 - /* mov [bp+n], reg */6.138 - OP(0x8B);6.139 - OP(0x45 + (x86reg<<3));6.140 - OP(REG_OFFSET(r[sh4reg]));6.141 -}6.142 -6.143 -static inline void load_reg16s( int x86reg, int sh4reg )6.144 -{6.145 - OP(0x0F);6.146 - OP(0xBF);6.147 - MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));6.148 -}6.149 -6.150 -static inline void load_reg16u( int x86reg, int sh4reg )6.151 -{6.152 - OP(0x0F);6.153 - OP(0xB7);6.154 - MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));6.155 -6.156 -}6.157 -6.158 -#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )6.159 -#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )6.160 -/**6.161 - * Emit an instruction to load an immediate value into a register6.162 - */6.163 -static inline void load_imm32( int x86reg, uint32_t value ) {6.164 - /* mov #value, reg */6.165 - OP(0xB8 + x86reg);6.166 - OP32(value);6.167 -}6.168 -6.169 -/**6.170 - * Load an immediate 64-bit quantity (note: x86-64 only)6.171 - */6.172 -static inline void load_imm64( int x86reg, uint32_t value ) {6.173 - /* mov #value, reg */6.174 - REXW();6.175 - OP(0xB8 + x86reg);6.176 - OP64(value);6.177 -}6.178 -6.179 -/**6.180 - * Emit an instruction to store an SH4 reg (RN)6.181 - */6.182 -void static inline store_reg( int x86reg, int sh4reg ) {6.183 - /* mov reg, [bp+n] */6.184 - OP(0x89);6.185 - OP(0x45 + (x86reg<<3));6.186 - OP(REG_OFFSET(r[sh4reg]));6.187 -}6.188 -6.189 -/**6.190 - * Load an FR register (single-precision floating point) into an integer x866.191 - * register (eg for register-to-register moves)6.192 - */6.193 -#define load_fr(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[0][(frm)^1]) )6.194 -#define load_xf(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[1][(frm)^1]) )6.195 -6.196 -/**6.197 - * Load the low half of a DR register (DR or XD) into an integer x86 register6.198 - */6.199 -#define load_dr0(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm|0x01]) )6.200 -#define load_dr1(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )6.201 -6.202 -/**6.203 - * Store an FR register (single-precision floating point) from an integer x86+6.204 - * register (eg for register-to-register moves)6.205 - */6.206 -#define store_fr(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[0][(frm)^1]) )6.207 -#define store_xf(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[1][(frm)^1]) )6.208 -6.209 -#define store_dr0(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm|0x01]) )6.210 -#define store_dr1(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )6.211 -6.212 -6.213 -#define push_fpul() FLDF_sh4r(R_FPUL)6.214 -#define pop_fpul() FSTPF_sh4r(R_FPUL)6.215 -#define push_fr(frm) FLDF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )6.216 -#define pop_fr(frm) FSTPF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )6.217 -#define push_xf(frm) FLDF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )6.218 -#define pop_xf(frm) FSTPF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )6.219 -#define push_dr(frm) FLDD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )6.220 -#define pop_dr(frm) FSTPD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )6.221 -#define push_xdr(frm) FLDD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )6.222 -#define pop_xdr(frm) FSTPD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )6.223 -6.224 -6.225 -6.226 -/* Exception checks - Note that all exception checks will clobber EAX */6.227 -6.228 -#define check_priv( ) \6.229 - if( !sh4_x86.priv_checked ) { \6.230 - sh4_x86.priv_checked = TRUE;\6.231 - load_spreg( R_EAX, R_SR );\6.232 - AND_imm32_r32( SR_MD, R_EAX );\6.233 - if( sh4_x86.in_delay_slot ) {\6.234 - JE_exc( EXC_SLOT_ILLEGAL );\6.235 - } else {\6.236 - JE_exc( EXC_ILLEGAL );\6.237 - }\6.238 - }\6.239 -6.240 -#define check_fpuen( ) \6.241 - if( !sh4_x86.fpuen_checked ) {\6.242 - sh4_x86.fpuen_checked = TRUE;\6.243 - load_spreg( R_EAX, R_SR );\6.244 - AND_imm32_r32( SR_FD, R_EAX );\6.245 - if( sh4_x86.in_delay_slot ) {\6.246 - JNE_exc(EXC_SLOT_FPU_DISABLED);\6.247 - } else {\6.248 - JNE_exc(EXC_FPU_DISABLED);\6.249 - }\6.250 - }6.251 -6.252 -#define check_ralign16( x86reg ) \6.253 - TEST_imm32_r32( 0x00000001, x86reg ); \6.254 - JNE_exc(EXC_DATA_ADDR_READ)6.255 -6.256 -#define check_walign16( x86reg ) \6.257 - TEST_imm32_r32( 0x00000001, x86reg ); \6.258 - JNE_exc(EXC_DATA_ADDR_WRITE);6.259 -6.260 -#define check_ralign32( x86reg ) \6.261 - TEST_imm32_r32( 0x00000003, x86reg ); \6.262 - JNE_exc(EXC_DATA_ADDR_READ)6.263 -6.264 -#define check_walign32( x86reg ) \6.265 - TEST_imm32_r32( 0x00000003, x86reg ); \6.266 - JNE_exc(EXC_DATA_ADDR_WRITE);6.267 -6.268 -#define check_ralign64( x86reg ) \6.269 - TEST_imm32_r32( 0x00000007, x86reg ); \6.270 - JNE_exc(EXC_DATA_ADDR_READ)6.271 -6.272 -#define check_walign64( x86reg ) \6.273 - TEST_imm32_r32( 0x00000007, x86reg ); \6.274 - JNE_exc(EXC_DATA_ADDR_WRITE);6.275 -6.276 -#define UNDEF()6.277 -#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }6.278 -#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)6.279 -#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)6.280 -#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)6.281 -#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)6.282 -#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)6.283 -#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)6.284 -6.285 -/**6.286 - * Perform MMU translation on the address in addr_reg for a read operation, iff the TLB is turned6.287 - * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.6.288 - */6.289 -#define MMU_TRANSLATE_READ( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }6.290 -6.291 -#define MMU_TRANSLATE_READ_EXC( addr_reg, exc_code ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(exc_code); MEM_RESULT(addr_reg) }6.292 -/**6.293 - * Perform MMU translation on the address in addr_reg for a write operation, iff the TLB is turned6.294 - * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.6.295 - */6.296 -#define MMU_TRANSLATE_WRITE( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }6.297 -6.298 -#define MEM_READ_SIZE (CALL_FUNC1_SIZE)6.299 -#define MEM_WRITE_SIZE (CALL_FUNC2_SIZE)6.300 -#define MMU_TRANSLATE_SIZE (sh4_x86.tlb_on ? (CALL_FUNC1_SIZE + 12) : 0 )6.301 -6.302 -#define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = DELAY_NONE; return 1;6.303 -6.304 -/****** Import appropriate calling conventions ******/6.305 -#if SIZEOF_VOID_P == 86.306 -#include "sh4/ia64abi.h"6.307 -#else /* 32-bit system */6.308 -#ifdef APPLE_BUILD6.309 -#include "sh4/ia32mac.h"6.310 -#else6.311 -#include "sh4/ia32abi.h"6.312 -#endif6.313 -#endif6.314 -6.315 -uint32_t sh4_translate_end_block_size()6.316 -{6.317 - if( sh4_x86.backpatch_posn <= 3 ) {6.318 - return EPILOGUE_SIZE + (sh4_x86.backpatch_posn*12);6.319 - } else {6.320 - return EPILOGUE_SIZE + 48 + (sh4_x86.backpatch_posn-3)*15;6.321 - }6.322 -}6.323 -6.324 -6.325 -/**6.326 - * Embed a breakpoint into the generated code6.327 - */6.328 -void sh4_translate_emit_breakpoint( sh4vma_t pc )6.329 -{6.330 - load_imm32( R_EAX, pc );6.331 - call_func1( sh4_translate_breakpoint_hit, R_EAX );6.332 -}6.333 -6.334 -6.335 -#define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc)6.336 -6.337 -/**6.338 - * Embed a call to sh4_execute_instruction for situations that we6.339 - * can't translate (just page-crossing delay slots at the moment).6.340 - * Caller is responsible for setting new_pc before calling this function.6.341 - *6.342 - * Performs:6.343 - * Set PC = endpc6.344 - * Set sh4r.in_delay_slot = sh4_x86.in_delay_slot6.345 - * Update slice_cycle for endpc+2 (single step doesn't update slice_cycle)6.346 - * Call sh4_execute_instruction6.347 - * Call xlat_get_code_by_vma / xlat_get_code as for normal exit6.348 - */6.349 -void exit_block_emu( sh4vma_t endpc )6.350 -{6.351 - load_imm32( R_ECX, endpc - sh4_x86.block_start_pc ); // 56.352 - ADD_r32_sh4r( R_ECX, R_PC );6.353 -6.354 - load_imm32( R_ECX, (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period ); // 56.355 - ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) ); // 66.356 - load_imm32( R_ECX, sh4_x86.in_delay_slot ? 1 : 0 );6.357 - store_spreg( R_ECX, REG_OFFSET(in_delay_slot) );6.358 -6.359 - call_func0( sh4_execute_instruction );6.360 - load_spreg( R_EAX, R_PC );6.361 - if( sh4_x86.tlb_on ) {6.362 - call_func1(xlat_get_code_by_vma,R_EAX);6.363 - } else {6.364 - call_func1(xlat_get_code,R_EAX);6.365 - }6.366 - AND_imm8s_rptr( 0xFC, R_EAX );6.367 - POP_r32(R_EBP);6.368 - RET();6.369 -}6.370 -6.371 -/**6.372 - * Translate a single instruction. Delayed branches are handled specially6.373 - * by translating both branch and delayed instruction as a single unit (as6.374 - *6.375 - * The instruction MUST be in the icache (assert check)6.376 - *6.377 - * @return true if the instruction marks the end of a basic block6.378 - * (eg a branch or6.379 - */6.380 -uint32_t sh4_translate_instruction( sh4vma_t pc )6.381 -{6.382 - uint32_t ir;6.383 - /* Read instruction from icache */6.384 - assert( IS_IN_ICACHE(pc) );6.385 - ir = *(uint16_t *)GET_ICACHE_PTR(pc);6.386 -6.387 - /* PC is not in the current icache - this usually means we're running6.388 - * with MMU on, and we've gone past the end of the page. And since6.389 - * sh4_translate_block is pretty careful about this, it means we're6.390 - * almost certainly in a delay slot.6.391 - *6.392 - * Since we can't assume the page is present (and we can't fault it in6.393 - * at this point, inline a call to sh4_execute_instruction (with a few6.394 - * small repairs to cope with the different environment).6.395 - */6.396 -6.397 - if( !sh4_x86.in_delay_slot ) {6.398 - sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 );6.399 - }6.400 - switch( (ir&0xF000) >> 12 ) {6.401 - case 0x0:6.402 - switch( ir&0xF ) {6.403 - case 0x2:6.404 - switch( (ir&0x80) >> 7 ) {6.405 - case 0x0:6.406 - switch( (ir&0x70) >> 4 ) {6.407 - case 0x0:6.408 - { /* STC SR, Rn */6.409 - uint32_t Rn = ((ir>>8)&0xF);6.410 - COUNT_INST(I_STCSR);6.411 - check_priv();6.412 - call_func0(sh4_read_sr);6.413 - store_reg( R_EAX, Rn );6.414 - sh4_x86.tstate = TSTATE_NONE;6.415 - }6.416 - break;6.417 - case 0x1:6.418 - { /* STC GBR, Rn */6.419 - uint32_t Rn = ((ir>>8)&0xF);6.420 - COUNT_INST(I_STC);6.421 - load_spreg( R_EAX, R_GBR );6.422 - store_reg( R_EAX, Rn );6.423 - }6.424 - break;6.425 - case 0x2:6.426 - { /* STC VBR, Rn */6.427 - uint32_t Rn = ((ir>>8)&0xF);6.428 - COUNT_INST(I_STC);6.429 - check_priv();6.430 - load_spreg( R_EAX, R_VBR );6.431 - store_reg( R_EAX, Rn );6.432 - sh4_x86.tstate = TSTATE_NONE;6.433 - }6.434 - break;6.435 - case 0x3:6.436 - { /* STC SSR, Rn */6.437 - uint32_t Rn = ((ir>>8)&0xF);6.438 - COUNT_INST(I_STC);6.439 - check_priv();6.440 - load_spreg( R_EAX, R_SSR );6.441 - store_reg( R_EAX, Rn );6.442 - sh4_x86.tstate = TSTATE_NONE;6.443 - }6.444 - break;6.445 - case 0x4:6.446 - { /* STC SPC, Rn */6.447 - uint32_t Rn = ((ir>>8)&0xF);6.448 - COUNT_INST(I_STC);6.449 - check_priv();6.450 - load_spreg( R_EAX, R_SPC );6.451 - store_reg( R_EAX, Rn );6.452 - sh4_x86.tstate = TSTATE_NONE;6.453 - }6.454 - break;6.455 - default:6.456 - UNDEF();6.457 - break;6.458 - }6.459 - break;6.460 - case 0x1:6.461 - { /* STC Rm_BANK, Rn */6.462 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);6.463 - COUNT_INST(I_STC);6.464 - check_priv();6.465 - load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );6.466 - store_reg( R_EAX, Rn );6.467 - sh4_x86.tstate = TSTATE_NONE;6.468 - }6.469 - break;6.470 - }6.471 - break;6.472 - case 0x3:6.473 - switch( (ir&0xF0) >> 4 ) {6.474 - case 0x0:6.475 - { /* BSRF Rn */6.476 - uint32_t Rn = ((ir>>8)&0xF);6.477 - COUNT_INST(I_BSRF);6.478 - if( sh4_x86.in_delay_slot ) {6.479 - SLOTILLEGAL();6.480 - } else {6.481 - load_spreg( R_EAX, R_PC );6.482 - ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );6.483 - store_spreg( R_EAX, R_PR );6.484 - ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );6.485 - store_spreg( R_EAX, R_NEW_PC );6.486 -6.487 - sh4_x86.in_delay_slot = DELAY_PC;6.488 - sh4_x86.tstate = TSTATE_NONE;6.489 - sh4_x86.branch_taken = TRUE;6.490 - if( UNTRANSLATABLE(pc+2) ) {6.491 - exit_block_emu(pc+2);6.492 - return 2;6.493 - } else {6.494 - sh4_translate_instruction( pc + 2 );6.495 - exit_block_newpcset(pc+2);6.496 - return 4;6.497 - }6.498 - }6.499 - }6.500 - break;6.501 - case 0x2:6.502 - { /* BRAF Rn */6.503 - uint32_t Rn = ((ir>>8)&0xF);6.504 - COUNT_INST(I_BRAF);6.505 - if( sh4_x86.in_delay_slot ) {6.506 - SLOTILLEGAL();6.507 - } else {6.508 - load_spreg( R_EAX, R_PC );6.509 - ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );6.510 - ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );6.511 - store_spreg( R_EAX, R_NEW_PC );6.512 - sh4_x86.in_delay_slot = DELAY_PC;6.513 - sh4_x86.tstate = TSTATE_NONE;6.514 - sh4_x86.branch_taken = TRUE;6.515 - if( UNTRANSLATABLE(pc+2) ) {6.516 - exit_block_emu(pc+2);6.517 - return 2;6.518 - } else {6.519 - sh4_translate_instruction( pc + 2 );6.520 - exit_block_newpcset(pc+2);6.521 - return 4;6.522 - }6.523 - }6.524 - }6.525 - break;6.526 - case 0x8:6.527 - { /* PREF @Rn */6.528 - uint32_t Rn = ((ir>>8)&0xF);6.529 - COUNT_INST(I_PREF);6.530 - load_reg( R_EAX, Rn );6.531 - MOV_r32_r32( R_EAX, R_ECX );6.532 - AND_imm32_r32( 0xFC000000, R_EAX );6.533 - CMP_imm32_r32( 0xE0000000, R_EAX );6.534 - JNE_rel8(end);6.535 - call_func1( sh4_flush_store_queue, R_ECX );6.536 - TEST_r32_r32( R_EAX, R_EAX );6.537 - JE_exc(-1);6.538 - JMP_TARGET(end);6.539 - sh4_x86.tstate = TSTATE_NONE;6.540 - }6.541 - break;6.542 - case 0x9:6.543 - { /* OCBI @Rn */6.544 - uint32_t Rn = ((ir>>8)&0xF);6.545 - COUNT_INST(I_OCBI);6.546 - }6.547 - break;6.548 - case 0xA:6.549 - { /* OCBP @Rn */6.550 - uint32_t Rn = ((ir>>8)&0xF);6.551 - COUNT_INST(I_OCBP);6.552 - }6.553 - break;6.554 - case 0xB:6.555 - { /* OCBWB @Rn */6.556 - uint32_t Rn = ((ir>>8)&0xF);6.557 - COUNT_INST(I_OCBWB);6.558 - }6.559 - break;6.560 - case 0xC:6.561 - { /* MOVCA.L R0, @Rn */6.562 - uint32_t Rn = ((ir>>8)&0xF);6.563 - COUNT_INST(I_MOVCA);6.564 - load_reg( R_EAX, Rn );6.565 - check_walign32( R_EAX );6.566 - MMU_TRANSLATE_WRITE( R_EAX );6.567 - load_reg( R_EDX, 0 );6.568 - MEM_WRITE_LONG( R_EAX, R_EDX );6.569 - sh4_x86.tstate = TSTATE_NONE;6.570 - }6.571 - break;6.572 - default:6.573 - UNDEF();6.574 - break;6.575 - }6.576 - break;6.577 - case 0x4:6.578 - { /* MOV.B Rm, @(R0, Rn) */6.579 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);6.580 - COUNT_INST(I_MOVB);6.581 - load_reg( R_EAX, 0 );6.582 - load_reg( R_ECX, Rn );6.583 - ADD_r32_r32( R_ECX, R_EAX );6.584 - MMU_TRANSLATE_WRITE( R_EAX );6.585 - load_reg( R_EDX, Rm );6.586 - MEM_WRITE_BYTE( R_EAX, R_EDX );6.587 - sh4_x86.tstate = TSTATE_NONE;6.588 - }6.589 - break;6.590 - case 0x5:6.591 - { /* MOV.W Rm, @(R0, Rn) */6.592 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);6.593 - COUNT_INST(I_MOVW);6.594 - load_reg( R_EAX, 0 );6.595 - load_reg( R_ECX, Rn );6.596 - ADD_r32_r32( R_ECX, R_EAX );6.597 - check_walign16( R_EAX );6.598 - MMU_TRANSLATE_WRITE( R_EAX );6.599 - load_reg( R_EDX, Rm );6.600 - MEM_WRITE_WORD( R_EAX, R_EDX );6.601 - sh4_x86.tstate = TSTATE_NONE;6.602 - }6.603 - break;6.604 - case 0x6:6.605 - { /* MOV.L Rm, @(R0, Rn) */6.606 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);6.607 - COUNT_INST(I_MOVL);6.608 - load_reg( R_EAX, 0 );6.609 - load_reg( R_ECX, Rn );6.610 - ADD_r32_r32( R_ECX, R_EAX );6.611 - check_walign32( R_EAX );6.612 - MMU_TRANSLATE_WRITE( R_EAX );6.613 - load_reg( R_EDX, Rm );6.614 - MEM_WRITE_LONG( R_EAX, R_EDX );6.615 - sh4_x86.tstate = TSTATE_NONE;6.616 - }6.617 - break;6.618 - case 0x7:6.619 - { /* MUL.L Rm, Rn */6.620 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);6.621 - COUNT_INST(I_MULL);6.622 - load_reg( R_EAX, Rm );6.623 - load_reg( R_ECX, Rn );6.624 - MUL_r32( R_ECX );6.625 - store_spreg( R_EAX, R_MACL );6.626 - sh4_x86.tstate = TSTATE_NONE;6.627 - }6.628 - break;6.629 - case 0x8:6.630 - switch( (ir&0xFF0) >> 4 ) {6.631 - case 0x0:6.632 - { /* CLRT */6.633 - COUNT_INST(I_CLRT);6.634 - CLC();6.635 - SETC_t();6.636 - sh4_x86.tstate = TSTATE_C;6.637 - }6.638 - break;6.639 - case 0x1:6.640 - { /* SETT */6.641 - COUNT_INST(I_SETT);6.642 - STC();6.643 - SETC_t();6.644 - sh4_x86.tstate = TSTATE_C;6.645 - }6.646 - break;6.647 - case 0x2:6.648 - { /* CLRMAC */6.649 - COUNT_INST(I_CLRMAC);6.650 - XOR_r32_r32(R_EAX, R_EAX);6.651 - store_spreg( R_EAX, R_MACL );6.652 - store_spreg( R_EAX, R_MACH );6.653 - sh4_x86.tstate = TSTATE_NONE;6.654 - }6.655 - break;6.656 - case 0x3:6.657 - { /* LDTLB */6.658 - COUNT_INST(I_LDTLB);6.659 - call_func0( MMU_ldtlb );6.660 - }6.661 - break;6.662 - case 0x4:6.663 - { /* CLRS */6.664 - COUNT_INST(I_CLRS);6.665 - CLC();6.666 - SETC_sh4r(R_S);6.667 - sh4_x86.tstate = TSTATE_C;6.668 - }6.669 - break;6.670 - case 0x5:6.671 - { /* SETS */6.672 - COUNT_INST(I_SETS);6.673 - STC();6.674 - SETC_sh4r(R_S);6.675 - sh4_x86.tstate = TSTATE_C;6.676 - }6.677 - break;6.678 - default:6.679 - UNDEF();6.680 - break;6.681 - }6.682 - break;6.683 - case 0x9:6.684 - switch( (ir&0xF0) >> 4 ) {6.685 - case 0x0:6.686 - { /* NOP */6.687 - COUNT_INST(I_NOP);6.688 - /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */6.689 - }6.690 - break;6.691 - case 0x1:6.692 - { /* DIV0U */6.693 - COUNT_INST(I_DIV0U);6.694 - XOR_r32_r32( R_EAX, R_EAX );6.695 - store_spreg( R_EAX, R_Q );6.696 - store_spreg( R_EAX, R_M );6.697 - store_spreg( R_EAX, R_T );6.698 - sh4_x86.tstate = TSTATE_C; // works for DIV16.699 - }6.700 - break;6.701 - case 0x2:6.702 - { /* MOVT Rn */6.703 - uint32_t Rn = ((ir>>8)&0xF);6.704 - COUNT_INST(I_MOVT);6.705 - load_spreg( R_EAX, R_T );6.706 - store_reg( R_EAX, Rn );6.707 - }6.708 - break;6.709 - default:6.710 - UNDEF();6.711 - break;6.712 - }6.713 - break;6.714 - case 0xA:6.715 - switch( (ir&0xF0) >> 4 ) {6.716 - case 0x0:6.717 - { /* STS MACH, Rn */6.718 - uint32_t Rn = ((ir>>8)&0xF);6.719 - COUNT_INST(I_STS);6.720 - load_spreg( R_EAX, R_MACH );6.721 - store_reg( R_EAX, Rn );6.722 - }6.723 - break;6.724 - case 0x1:6.725 - { /* STS MACL, Rn */6.726 - uint32_t Rn = ((ir>>8)&0xF);6.727 - COUNT_INST(I_STS);6.728 - load_spreg( R_EAX, R_MACL );6.729 - store_reg( R_EAX, Rn );6.730 - }6.731 - break;6.732 - case 0x2:6.733 - { /* STS PR, Rn */6.734 - uint32_t Rn = ((ir>>8)&0xF);6.735 - COUNT_INST(I_STS);6.736 - load_spreg( R_EAX, R_PR );6.737 - store_reg( R_EAX, Rn );6.738 - }6.739 - break;6.740 - case 0x3:6.741 - { /* STC SGR, Rn */6.742 - uint32_t Rn = ((ir>>8)&0xF);6.743 - COUNT_INST(I_STC);6.744 - check_priv();6.745 - load_spreg( R_EAX, R_SGR );6.746 - store_reg( R_EAX, Rn );6.747 - sh4_x86.tstate = TSTATE_NONE;6.748 - }6.749 - break;6.750 - case 0x5:6.751 - { /* STS FPUL, Rn */6.752 - uint32_t Rn = ((ir>>8)&0xF);6.753 - COUNT_INST(I_STS);6.754 - check_fpuen();6.755 - load_spreg( R_EAX, R_FPUL );6.756 - store_reg( R_EAX, Rn );6.757 - }6.758 - break;6.759 - case 0x6:6.760 - { /* STS FPSCR, Rn */6.761 - uint32_t Rn = ((ir>>8)&0xF);6.762 - COUNT_INST(I_STSFPSCR);6.763 - check_fpuen();6.764 - load_spreg( R_EAX, R_FPSCR );6.765 - store_reg( R_EAX, Rn );6.766 - }6.767 - break;6.768 - case 0xF:6.769 - { /* STC DBR, Rn */6.770 - uint32_t Rn = ((ir>>8)&0xF);6.771 - COUNT_INST(I_STC);6.772 - check_priv();6.773 - load_spreg( R_EAX, R_DBR );6.774 - store_reg( R_EAX, Rn );6.775 - sh4_x86.tstate = TSTATE_NONE;6.776 - }6.777 - break;6.778 - default:6.779 - UNDEF();6.780 - break;6.781 - }6.782 - break;6.783 - case 0xB:6.784 - switch( (ir&0xFF0) >> 4 ) {6.785 - case 0x0:6.786 - { /* RTS */6.787 - COUNT_INST(I_RTS);6.788 - if( sh4_x86.in_delay_slot ) {6.789 - SLOTILLEGAL();6.790 - } else {6.791 - load_spreg( R_ECX, R_PR );6.792 - store_spreg( R_ECX, R_NEW_PC );6.793 - sh4_x86.in_delay_slot = DELAY_PC;6.794 - sh4_x86.branch_taken = TRUE;6.795 - if( UNTRANSLATABLE(pc+2) ) {6.796 - exit_block_emu(pc+2);6.797 - return 2;6.798 - } else {6.799 - sh4_translate_instruction(pc+2);6.800 - exit_block_newpcset(pc+2);6.801 - return 4;6.802 - }6.803 - }6.804 - }6.805 - break;6.806 - case 0x1:6.807 - { /* SLEEP */6.808 - COUNT_INST(I_SLEEP);6.809 - check_priv();6.810 - call_func0( sh4_sleep );6.811 - sh4_x86.tstate = TSTATE_NONE;6.812 - sh4_x86.in_delay_slot = DELAY_NONE;6.813 - return 2;6.814 - }6.815 - break;6.816 - case 0x2:6.817 - { /* RTE */6.818 - COUNT_INST(I_RTE);6.819 - if( sh4_x86.in_delay_slot ) {6.820 - SLOTILLEGAL();6.821 - } else {6.822 - check_priv();6.823 - load_spreg( R_ECX, R_SPC );6.824 - store_spreg( R_ECX, R_NEW_PC );6.825 - load_spreg( R_EAX, R_SSR );6.826 - call_func1( sh4_write_sr, R_EAX );6.827 - sh4_x86.in_delay_slot = DELAY_PC;6.828 - sh4_x86.priv_checked = FALSE;6.829 - sh4_x86.fpuen_checked = FALSE;6.830 - sh4_x86.tstate = TSTATE_NONE;6.831 - sh4_x86.branch_taken = TRUE;6.832 - if( UNTRANSLATABLE(pc+2) ) {6.833 - exit_block_emu(pc+2);6.834 - return 2;6.835 - } else {6.836 - sh4_translate_instruction(pc+2);6.837 - exit_block_newpcset(pc+2);6.838 - return 4;6.839 - }6.840 - }6.841 - }6.842 - break;6.843 - default:6.844 - UNDEF();6.845 - break;6.846 - }6.847 - break;6.848 - case 0xC:6.849 - { /* MOV.B @(R0, Rm), Rn */6.850 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);6.851 - COUNT_INST(I_MOVB);6.852 - load_reg( R_EAX, 0 );6.853 - load_reg( R_ECX, Rm );6.854 - ADD_r32_r32( R_ECX, R_EAX );6.855 - MMU_TRANSLATE_READ( R_EAX )6.856 - MEM_READ_BYTE( R_EAX, R_EAX );6.857 - store_reg( R_EAX, Rn );6.858 - sh4_x86.tstate = TSTATE_NONE;6.859 - }6.860 - break;6.861 - case 0xD:6.862 - { /* MOV.W @(R0, Rm), Rn */6.863 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);6.864 - COUNT_INST(I_MOVW);6.865 - load_reg( R_EAX, 0 );6.866 - load_reg( R_ECX, Rm );6.867 - ADD_r32_r32( R_ECX, R_EAX );6.868 - check_ralign16( R_EAX );6.869 - MMU_TRANSLATE_READ( R_EAX );6.870 - MEM_READ_WORD( R_EAX, R_EAX );6.871 - store_reg( R_EAX, Rn );6.872 - sh4_x86.tstate = TSTATE_NONE;6.873 - }6.874 - break;6.875 - case 0xE:6.876 - { /* MOV.L @(R0, Rm), Rn */6.877 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);6.878 - COUNT_INST(I_MOVL);6.879 - load_reg( R_EAX, 0 );6.880 - load_reg( R_ECX, Rm );6.881 - ADD_r32_r32( R_ECX, R_EAX );6.882 - check_ralign32( R_EAX );6.883 - MMU_TRANSLATE_READ( R_EAX );6.884 - MEM_READ_LONG( R_EAX, R_EAX );6.885 - store_reg( R_EAX, Rn );6.886 - sh4_x86.tstate = TSTATE_NONE;6.887 - }6.888 - break;6.889 - case 0xF:6.890 - { /* MAC.L @Rm+, @Rn+ */6.891 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);6.892 - COUNT_INST(I_MACL);6.893 - if( Rm == Rn ) {6.894 - load_reg( R_EAX, Rm );6.895 - check_ralign32( R_EAX );6.896 - MMU_TRANSLATE_READ( R_EAX );6.897 - PUSH_realigned_r32( R_EAX );6.898 - load_reg( R_EAX, Rn );6.899 - ADD_imm8s_r32( 4, R_EAX );6.900 - MMU_TRANSLATE_READ_EXC( R_EAX, -5 );6.901 - ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );6.902 - // Note translate twice in case of page boundaries. Maybe worth6.903 - // adding a page-boundary check to skip the second translation6.904 - } else {6.905 - load_reg( R_EAX, Rm );6.906 - check_ralign32( R_EAX );6.907 - MMU_TRANSLATE_READ( R_EAX );6.908 - load_reg( R_ECX, Rn );6.909 - check_ralign32( R_ECX );6.910 - PUSH_realigned_r32( R_EAX );6.911 - MMU_TRANSLATE_READ_EXC( R_ECX, -5 );6.912 - MOV_r32_r32( R_ECX, R_EAX );6.913 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );6.914 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );6.915 - }6.916 - MEM_READ_LONG( R_EAX, R_EAX );6.917 - POP_r32( R_ECX );6.918 - PUSH_r32( R_EAX );6.919 - MEM_READ_LONG( R_ECX, R_EAX );6.920 - POP_realigned_r32( R_ECX );6.921 -6.922 - IMUL_r32( R_ECX );6.923 - ADD_r32_sh4r( R_EAX, R_MACL );6.924 - ADC_r32_sh4r( R_EDX, R_MACH );6.925 -6.926 - load_spreg( R_ECX, R_S );6.927 - TEST_r32_r32(R_ECX, R_ECX);6.928 - JE_rel8( nosat );6.929 - call_func0( signsat48 );6.930 - JMP_TARGET( nosat );6.931 - sh4_x86.tstate = TSTATE_NONE;6.932 - }6.933 - break;6.934 - default:6.935 - UNDEF();6.936 - break;6.937 - }6.938 - break;6.939 - case 0x1:6.940 - { /* MOV.L Rm, @(disp, Rn) */6.941 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;6.942 - COUNT_INST(I_MOVL);6.943 - load_reg( R_EAX, Rn );6.944 - ADD_imm32_r32( disp, R_EAX );6.945 - check_walign32( R_EAX );6.946 - MMU_TRANSLATE_WRITE( R_EAX );6.947 - load_reg( R_EDX, Rm );6.948 - MEM_WRITE_LONG( R_EAX, R_EDX );6.949 - sh4_x86.tstate = TSTATE_NONE;6.950 - }6.951 - break;6.952 - case 0x2:6.953 - switch( ir&0xF ) {6.954 - case 0x0:6.955 - { /* MOV.B Rm, @Rn */6.956 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);6.957 - COUNT_INST(I_MOVB);6.958 - load_reg( R_EAX, Rn );6.959 - MMU_TRANSLATE_WRITE( R_EAX );6.960 - load_reg( R_EDX, Rm );6.961 - MEM_WRITE_BYTE( R_EAX, R_EDX );6.962 - sh4_x86.tstate = TSTATE_NONE;6.963 - }6.964 - break;6.965 - case 0x1:6.966 - { /* MOV.W Rm, @Rn */6.967 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);6.968 - COUNT_INST(I_MOVW);6.969 - load_reg( R_EAX, Rn );6.970 - check_walign16( R_EAX );6.971 - MMU_TRANSLATE_WRITE( R_EAX )6.972 - load_reg( R_EDX, Rm );6.973 - MEM_WRITE_WORD( R_EAX, R_EDX );6.974 - sh4_x86.tstate = TSTATE_NONE;6.975 - }6.976 - break;6.977 - case 0x2:6.978 - { /* MOV.L Rm, @Rn */6.979 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);6.980 - COUNT_INST(I_MOVL);6.981 - load_reg( R_EAX, Rn );6.982 - check_walign32(R_EAX);6.983 - MMU_TRANSLATE_WRITE( R_EAX );6.984 - load_reg( R_EDX, Rm );6.985 - MEM_WRITE_LONG( R_EAX, R_EDX );6.986 - sh4_x86.tstate = TSTATE_NONE;6.987 - }6.988 - break;6.989 - case 0x4:6.990 - { /* MOV.B Rm, @-Rn */6.991 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);6.992 - COUNT_INST(I_MOVB);6.993 - load_reg( R_EAX, Rn );6.994 - ADD_imm8s_r32( -1, R_EAX );6.995 - MMU_TRANSLATE_WRITE( R_EAX );6.996 - load_reg( R_EDX, Rm );6.997 - ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );6.998 - MEM_WRITE_BYTE( R_EAX, R_EDX );6.999 - sh4_x86.tstate = TSTATE_NONE;6.1000 - }6.1001 - break;6.1002 - case 0x5:6.1003 - { /* MOV.W Rm, @-Rn */6.1004 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);6.1005 - COUNT_INST(I_MOVW);6.1006 - load_reg( R_EAX, Rn );6.1007 - ADD_imm8s_r32( -2, R_EAX );6.1008 - check_walign16( R_EAX );6.1009 - MMU_TRANSLATE_WRITE( R_EAX );6.1010 - load_reg( R_EDX, Rm );6.1011 - ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );6.1012 - MEM_WRITE_WORD( R_EAX, R_EDX );6.1013 - sh4_x86.tstate = TSTATE_NONE;6.1014 - }6.1015 - break;6.1016 - case 0x6:6.1017 - { /* MOV.L Rm, @-Rn */6.1018 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);6.1019 - COUNT_INST(I_MOVL);6.1020 - load_reg( R_EAX, Rn );6.1021 - ADD_imm8s_r32( -4, R_EAX );6.1022 - check_walign32( R_EAX );6.1023 - MMU_TRANSLATE_WRITE( R_EAX );6.1024 - load_reg( R_EDX, Rm );6.1025 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );6.1026 - MEM_WRITE_LONG( R_EAX, R_EDX );6.1027 - sh4_x86.tstate = TSTATE_NONE;6.1028 - }6.1029 - break;6.1030 - case 0x7:6.1031 - { /* DIV0S Rm, Rn */6.1032 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);6.1033 - COUNT_INST(I_DIV0S);6.1034 - load_reg( R_EAX, Rm );6.1035 - load_reg( R_ECX, Rn );6.1036 - SHR_imm8_r32( 31, R_EAX );6.1037 - SHR_imm8_r32( 31, R_ECX );6.1038 - store_spreg( R_EAX, R_M );6.1039 - store_spreg( R_ECX, R_Q );6.1040 - CMP_r32_r32( R_EAX, R_ECX );6.1041 - SETNE_t();6.1042 - sh4_x86.tstate = TSTATE_NE;6.1043 - }6.1044 - break;6.1045 - case 0x8:6.1046 - { /* TST Rm, Rn */6.1047 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);6.1048 - COUNT_INST(I_TST);6.1049 - load_reg( R_EAX, Rm );6.1050 - load_reg( R_ECX, Rn );6.1051 - TEST_r32_r32( R_EAX, R_ECX );6.1052 - SETE_t();6.1053 - sh4_x86.tstate = TSTATE_E;6.1054 - }6.1055 - break;6.1056 - case 0x9:6.1057 - { /* AND Rm, Rn */6.1058 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);6.1059 - COUNT_INST(I_AND);6.1060 - load_reg( R_EAX, Rm );6.1061 - load_reg( R_ECX, Rn );6.1062 - AND_r32_r32( R_EAX, R_ECX );6.1063 - store_reg( R_ECX, Rn );6.1064 - sh4_x86.tstate = TSTATE_NONE;6.1065 - }6.1066 - break;6.1067 - case 0xA:6.1068 - { /* XOR Rm, Rn */6.1069 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);6.1070 - COUNT_INST(I_XOR);6.1071 - load_reg( R_EAX, Rm );6.1072 - load_reg( R_ECX, Rn );6.1073 - XOR_r32_r32( R_EAX, R_ECX );6.1074 - store_reg( R_ECX, Rn );6.1075 - sh4_x86.tstate = TSTATE_NONE;6.1076 - }6.1077 - break;6.1078 - case 0xB:6.1079 - { /* OR Rm, Rn */6.1080 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);6.1081 - COUNT_INST(I_OR);6.1082 - load_reg( R_EAX, Rm );6.1083 - load_reg( R_ECX, Rn );6.1084 - OR_r32_r32( R_EAX, R_ECX );6.1085 - store_reg( R_ECX, Rn );6.1086 - sh4_x86.tstate = TSTATE_NONE;6.1087 - }6.1088 - break;6.1089 - case 0xC:6.1090 - { /* CMP/STR Rm, Rn */6.1091 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);6.1092 - COUNT_INST(I_CMPSTR);6.1093 - load_reg( R_EAX, Rm );6.1094 - load_reg( R_ECX, Rn );6.1095 - XOR_r32_r32( R_ECX, R_EAX );6.1096 - TEST_r8_r8( R_AL, R_AL );6.1097 - JE_rel8(target1);6.1098 - TEST_r8_r8( R_AH, R_AH );6.1099 - JE_rel8(target2);6.1100 - SHR_imm8_r32( 16, R_EAX );6.1101 - TEST_r8_r8( R_AL, R_AL );6.1102 - JE_rel8(target3);6.1103 - TEST_r8_r8( R_AH, R_AH );6.1104 - JMP_TARGET(target1);6.1105 - JMP_TARGET(target2);6.1106 - JMP_TARGET(target3);6.1107 - SETE_t();6.1108 - sh4_x86.tstate = TSTATE_E;6.1109 - }6.1110 - break;6.1111 - case 0xD:6.1112 - { /* XTRCT Rm, Rn */6.1113 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);6.1114 - COUNT_INST(I_XTRCT);6.1115 - load_reg( R_EAX, Rm );6.1116 - load_reg( R_ECX, Rn );6.1117 - SHL_imm8_r32( 16, R_EAX );6.1118 - SHR_imm8_r32( 16, R_ECX );6.1119 - OR_r32_r32( R_EAX, R_ECX );6.1120 - store_reg( R_ECX, Rn );6.1121 - sh4_x86.tstate = TSTATE_NONE;6.1122 - }6.1123 - break;6.1124 - case 0xE:6.1125 - { /* MULU.W Rm, Rn */6.1126 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);6.1127 - COUNT_INST(I_MULUW);6.1128 - load_reg16u( R_EAX, Rm );6.1129 - load_reg16u( R_ECX, Rn );6.1130 - MUL_r32( R_ECX );6.1131 - store_spreg( R_EAX, R_MACL );6.1132 - sh4_x86.tstate = TSTATE_NONE;6.1133 - }6.1134 - break;6.1135 - case 0xF:6.1136 - { /* MULS.W Rm, Rn */6.1137 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);6.1138 - COUNT_INST(I_MULSW);6.1139 - load_reg16s( R_EAX, Rm );6.1140 - load_reg16s( R_ECX, Rn );6.1141 - MUL_r32( R_ECX );6.1142 - store_spreg( R_EAX, R_MACL );6.1143 - sh4_x86.tstate = TSTATE_NONE;6.1144 - }6.1145 - break;6.1146 - default:6.1147 - UNDEF();6.1148 - break;6.1149 - }6.1150 - break;6.1151 - case 0x3:6.1152 - switch( ir&0xF ) {6.1153 - case 0x0:6.1154 - { /* CMP/EQ Rm, Rn */6.1155 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);6.1156 - COUNT_INST(I_CMPEQ);6.1157 - load_reg( R_EAX, Rm );6.1158 - load_reg( R_ECX, Rn );6.1159 - CMP_r32_r32( R_EAX, R_ECX );6.1160 - SETE_t();6.1161 - sh4_x86.tstate = TSTATE_E;6.1162 - }6.1163 - break;6.1164 - case 0x2:6.1165 - { /* CMP/HS Rm, Rn */6.1166 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);6.1167 - COUNT_INST(I_CMPHS);6.1168 - load_reg( R_EAX, Rm );6.1169 - load_reg( R_ECX, Rn );6.1170 - CMP_r32_r32( R_EAX, R_ECX );6.1171 - SETAE_t();6.1172 - sh4_x86.tstate = TSTATE_AE;6.1173 - }6.1174 - break;6.1175 - case 0x3:6.1176 - { /* CMP/GE Rm, Rn */6.1177 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);6.1178 - COUNT_INST(I_CMPGE);6.1179 - load_reg( R_EAX, Rm );6.1180 - load_reg( R_ECX, Rn );6.1181 - CMP_r32_r32( R_EAX, R_ECX );6.1182 - SETGE_t();6.1183 - sh4_x86.tstate = TSTATE_GE;6.1184 - }6.1185 - break;6.1186 - case 0x4:6.1187 - { /* DIV1 Rm, Rn */6.1188 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);6.1189 - COUNT_INST(I_DIV1);6.1190 - load_spreg( R_ECX, R_M );6.1191 - load_reg( R_EAX, Rn );6.1192 - if( sh4_x86.tstate != TSTATE_C ) {6.1193 - LDC_t();6.1194 - }6.1195 - RCL1_r32( R_EAX );6.1196 - SETC_r8( R_DL ); // Q'6.1197 - CMP_sh4r_r32( R_Q, R_ECX );6.1198 - JE_rel8(mqequal);6.1199 - ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );6.1200 - JMP_rel8(end);6.1201 - JMP_TARGET(mqequal);6.1202 - SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );6.1203 - JMP_TARGET(end);6.1204 - store_reg( R_EAX, Rn ); // Done with Rn now6.1205 - SETC_r8(R_AL); // tmp16.1206 - XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp16.1207 - XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M6.1208 - store_spreg( R_ECX, R_Q );6.1209 - XOR_imm8s_r32( 1, R_AL ); // T = !Q'6.1210 - MOVZX_r8_r32( R_AL, R_EAX );6.1211 - store_spreg( R_EAX, R_T );6.1212 - sh4_x86.tstate = TSTATE_NONE;6.1213 - }6.1214 - break;6.1215 - case 0x5:6.1216 - { /* DMULU.L Rm, Rn */6.1217 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);6.1218 - COUNT_INST(I_DMULU);6.1219 - load_reg( R_EAX, Rm );6.1220 - load_reg( R_ECX, Rn );6.1221 - MUL_r32(R_ECX);6.1222 - store_spreg( R_EDX, R_MACH );6.1223 - store_spreg( R_EAX, R_MACL );6.1224 - sh4_x86.tstate = TSTATE_NONE;6.1225 - }6.1226 - break;6.1227 - case 0x6:6.1228 - { /* CMP/HI Rm, Rn */6.1229 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);6.1230 - COUNT_INST(I_CMPHI);6.1231 - load_reg( R_EAX, Rm );6.1232 - load_reg( R_ECX, Rn );6.1233 - CMP_r32_r32( R_EAX, R_ECX );6.1234 - SETA_t();6.1235 - sh4_x86.tstate = TSTATE_A;6.1236 - }6.1237 - break;6.1238 - case 0x7:6.1239 - { /* CMP/GT Rm, Rn */6.1240 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);6.1241 - COUNT_INST(I_CMPGT);6.1242 - load_reg( R_EAX, Rm );6.1243 - load_reg( R_ECX, Rn );6.1244 - CMP_r32_r32( R_EAX, R_ECX );6.1245 - SETG_t();6.1246 - sh4_x86.tstate = TSTATE_G;6.1247 - }6.1248 - break;6.1249 - case 0x8:6.1250 - { /* SUB Rm, Rn */6.1251 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);6.1252 - COUNT_INST(I_SUB);6.1253 - load_reg( R_EAX, Rm );6.1254 - load_reg( R_ECX, Rn );6.1255 - SUB_r32_r32( R_EAX, R_ECX );6.1256 - store_reg( R_ECX, Rn );6.1257 - sh4_x86.tstate = TSTATE_NONE;6.1258 - }6.1259 - break;6.1260 - case 0xA:6.1261 - { /* SUBC Rm, Rn */6.1262 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);6.1263 - COUNT_INST(I_SUBC);6.1264 - load_reg( R_EAX, Rm );6.1265 - load_reg( R_ECX, Rn );6.1266 - if( sh4_x86.tstate != TSTATE_C ) {6.1267 - LDC_t();6.1268 - }6.1269 - SBB_r32_r32( R_EAX, R_ECX );6.1270 - store_reg( R_ECX, Rn );6.1271 - SETC_t();6.1272 - sh4_x86.tstate = TSTATE_C;6.1273 - }6.1274 - break;6.1275 - case 0xB:6.1276 - { /* SUBV Rm, Rn */6.1277 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);6.1278 - COUNT_INST(I_SUBV);6.1279 - load_reg( R_EAX, Rm );6.1280 - load_reg( R_ECX, Rn );6.1281 - SUB_r32_r32( R_EAX, R_ECX );6.1282 - store_reg( R_ECX, Rn );6.1283 - SETO_t();6.1284 - sh4_x86.tstate = TSTATE_O;6.1285 - }6.1286 - break;6.1287 - case 0xC:6.1288 - { /* ADD Rm, Rn */6.1289 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);6.1290 - COUNT_INST(I_ADD);6.1291 - load_reg( R_EAX, Rm );6.1292 - load_reg( R_ECX, Rn );6.1293 - ADD_r32_r32( R_EAX, R_ECX );6.1294 - store_reg( R_ECX, Rn );6.1295 - sh4_x86.tstate = TSTATE_NONE;6.1296 - }6.1297 - break;6.1298 - case 0xD:6.1299 - { /* DMULS.L Rm, Rn */6.1300 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);6.1301 - COUNT_INST(I_DMULS);6.1302 - load_reg( R_EAX, Rm );6.1303 - load_reg( R_ECX, Rn );6.1304 - IMUL_r32(R_ECX);6.1305 - store_spreg( R_EDX, R_MACH );6.1306 - store_spreg( R_EAX, R_MACL );6.1307 - sh4_x86.tstate = TSTATE_NONE;6.1308 - }6.1309 - break;6.1310 - case 0xE:6.1311 - { /* ADDC Rm, Rn */6.1312 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);6.1313 - COUNT_INST(I_ADDC);6.1314 - if( sh4_x86.tstate != TSTATE_C ) {6.1315 - LDC_t();6.1316 - }6.1317 - load_reg( R_EAX, Rm );6.1318 - load_reg( R_ECX, Rn );6.1319 - ADC_r32_r32( R_EAX, R_ECX );6.1320 - store_reg( R_ECX, Rn );6.1321 - SETC_t();6.1322 - sh4_x86.tstate = TSTATE_C;6.1323 - }6.1324 - break;6.1325 - case 0xF:6.1326 - { /* ADDV Rm, Rn */6.1327 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);6.1328 - COUNT_INST(I_ADDV);6.1329 - load_reg( R_EAX, Rm );6.1330 - load_reg( R_ECX, Rn );6.1331 - ADD_r32_r32( R_EAX, R_ECX );6.1332 - store_reg( R_ECX, Rn );6.1333 - SETO_t();6.1334 - sh4_x86.tstate = TSTATE_O;6.1335 - }6.1336 - break;6.1337 - default:6.1338 - UNDEF();6.1339 - break;6.1340 - }6.1341 - break;6.1342 - case 0x4:6.1343 - switch( ir&0xF ) {6.1344 - case 0x0:6.1345 - switch( (ir&0xF0) >> 4 ) {6.1346 - case 0x0:6.1347 - { /* SHLL Rn */6.1348 - uint32_t Rn = ((ir>>8)&0xF);6.1349 - COUNT_INST(I_SHLL);6.1350 - load_reg( R_EAX, Rn );6.1351 - SHL1_r32( R_EAX );6.1352 - SETC_t();6.1353 - store_reg( R_EAX, Rn );6.1354 - sh4_x86.tstate = TSTATE_C;6.1355 - }6.1356 - break;6.1357 - case 0x1:6.1358 - { /* DT Rn */6.1359 - uint32_t Rn = ((ir>>8)&0xF);6.1360 - COUNT_INST(I_DT);6.1361 - load_reg( R_EAX, Rn );6.1362 - ADD_imm8s_r32( -1, R_EAX );6.1363 - store_reg( R_EAX, Rn );6.1364 - SETE_t();6.1365 - sh4_x86.tstate = TSTATE_E;6.1366 - }6.1367 - break;6.1368 - case 0x2:6.1369 - { /* SHAL Rn */6.1370 - uint32_t Rn = ((ir>>8)&0xF);6.1371 - COUNT_INST(I_SHAL);6.1372 - load_reg( R_EAX, Rn );6.1373 - SHL1_r32( R_EAX );6.1374 - SETC_t();6.1375 - store_reg( R_EAX, Rn );6.1376 - sh4_x86.tstate = TSTATE_C;6.1377 - }6.1378 - break;6.1379 - default:6.1380 - UNDEF();6.1381 - break;6.1382 - }6.1383 - break;6.1384 - case 0x1:6.1385 - switch( (ir&0xF0) >> 4 ) {6.1386 - case 0x0:6.1387 - { /* SHLR Rn */6.1388 - uint32_t Rn = ((ir>>8)&0xF);6.1389 - COUNT_INST(I_SHLR);6.1390 - load_reg( R_EAX, Rn );6.1391 - SHR1_r32( R_EAX );6.1392 - SETC_t();6.1393 - store_reg( R_EAX, Rn );6.1394 - sh4_x86.tstate = TSTATE_C;6.1395 - }6.1396 - break;6.1397 - case 0x1:6.1398 - { /* CMP/PZ Rn */6.1399 - uint32_t Rn = ((ir>>8)&0xF);6.1400 - COUNT_INST(I_CMPPZ);6.1401 - load_reg( R_EAX, Rn );6.1402 - CMP_imm8s_r32( 0, R_EAX );6.1403 - SETGE_t();6.1404 - sh4_x86.tstate = TSTATE_GE;6.1405 - }6.1406 - break;6.1407 - case 0x2:6.1408 - { /* SHAR Rn */6.1409 - uint32_t Rn = ((ir>>8)&0xF);6.1410 - COUNT_INST(I_SHAR);6.1411 - load_reg( R_EAX, Rn );6.1412 - SAR1_r32( R_EAX );6.1413 - SETC_t();6.1414 - store_reg( R_EAX, Rn );6.1415 - sh4_x86.tstate = TSTATE_C;6.1416 - }6.1417 - break;6.1418 - default:6.1419 - UNDEF();6.1420 - break;6.1421 - }6.1422 - break;6.1423 - case 0x2:6.1424 - switch( (ir&0xF0) >> 4 ) {6.1425 - case 0x0:6.1426 - { /* STS.L MACH, @-Rn */6.1427 - uint32_t Rn = ((ir>>8)&0xF);6.1428 - COUNT_INST(I_STSM);6.1429 - load_reg( R_EAX, Rn );6.1430 - check_walign32( R_EAX );6.1431 - ADD_imm8s_r32( -4, R_EAX );6.1432 - MMU_TRANSLATE_WRITE( R_EAX );6.1433 - load_spreg( R_EDX, R_MACH );6.1434 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );6.1435 - MEM_WRITE_LONG( R_EAX, R_EDX );6.1436 - sh4_x86.tstate = TSTATE_NONE;6.1437 - }6.1438 - break;6.1439 - case 0x1:6.1440 - { /* STS.L MACL, @-Rn */6.1441 - uint32_t Rn = ((ir>>8)&0xF);6.1442 - COUNT_INST(I_STSM);6.1443 - load_reg( R_EAX, Rn );6.1444 - check_walign32( R_EAX );6.1445 - ADD_imm8s_r32( -4, R_EAX );6.1446 - MMU_TRANSLATE_WRITE( R_EAX );6.1447 - load_spreg( R_EDX, R_MACL );6.1448 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );6.1449 - MEM_WRITE_LONG( R_EAX, R_EDX );6.1450 - sh4_x86.tstate = TSTATE_NONE;6.1451 - }6.1452 - break;6.1453 - case 0x2:6.1454 - { /* STS.L PR, @-Rn */6.1455 - uint32_t Rn = ((ir>>8)&0xF);6.1456 - COUNT_INST(I_STSM);6.1457 - load_reg( R_EAX, Rn );6.1458 - check_walign32( R_EAX );6.1459 - ADD_imm8s_r32( -4, R_EAX );6.1460 - MMU_TRANSLATE_WRITE( R_EAX );6.1461 - load_spreg( R_EDX, R_PR );6.1462 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );6.1463 - MEM_WRITE_LONG( R_EAX, R_EDX );6.1464 - sh4_x86.tstate = TSTATE_NONE;6.1465 - }6.1466 - break;6.1467 - case 0x3:6.1468 - { /* STC.L SGR, @-Rn */6.1469 - uint32_t Rn = ((ir>>8)&0xF);6.1470 - COUNT_INST(I_STCM);6.1471 - check_priv();6.1472 - load_reg( R_EAX, Rn );6.1473 - check_walign32( R_EAX );6.1474 - ADD_imm8s_r32( -4, R_EAX );6.1475 - MMU_TRANSLATE_WRITE( R_EAX );6.1476 - load_spreg( R_EDX, R_SGR );6.1477 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );6.1478 - MEM_WRITE_LONG( R_EAX, R_EDX );6.1479 - sh4_x86.tstate = TSTATE_NONE;6.1480 - }6.1481 - break;6.1482 - case 0x5:6.1483 - { /* STS.L FPUL, @-Rn */6.1484 - uint32_t Rn = ((ir>>8)&0xF);6.1485 - COUNT_INST(I_STSM);6.1486 - check_fpuen();6.1487 - load_reg( R_EAX, Rn );6.1488 - check_walign32( R_EAX );6.1489 - ADD_imm8s_r32( -4, R_EAX );6.1490 - MMU_TRANSLATE_WRITE( R_EAX );6.1491 - load_spreg( R_EDX, R_FPUL );6.1492 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );6.1493 - MEM_WRITE_LONG( R_EAX, R_EDX );6.1494 - sh4_x86.tstate = TSTATE_NONE;6.1495 - }6.1496 - break;6.1497 - case 0x6:6.1498 - { /* STS.L FPSCR, @-Rn */6.1499 - uint32_t Rn = ((ir>>8)&0xF);6.1500 - COUNT_INST(I_STSFPSCRM);6.1501 - check_fpuen();6.1502 - load_reg( R_EAX, Rn );6.1503 - check_walign32( R_EAX );6.1504 - ADD_imm8s_r32( -4, R_EAX );6.1505 - MMU_TRANSLATE_WRITE( R_EAX );6.1506 - load_spreg( R_EDX, R_FPSCR );6.1507 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );6.1508 - MEM_WRITE_LONG( R_EAX, R_EDX );6.1509 - sh4_x86.tstate = TSTATE_NONE;6.1510 - }6.1511 - break;6.1512 - case 0xF:6.1513 - { /* STC.L DBR, @-Rn */6.1514 - uint32_t Rn = ((ir>>8)&0xF);6.1515 - COUNT_INST(I_STCM);6.1516 - check_priv();6.1517 - load_reg( R_EAX, Rn );6.1518 - check_walign32( R_EAX );6.1519 - ADD_imm8s_r32( -4, R_EAX );6.1520 - MMU_TRANSLATE_WRITE( R_EAX );6.1521 - load_spreg( R_EDX, R_DBR );6.1522 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );6.1523 - MEM_WRITE_LONG( R_EAX, R_EDX );6.1524 - sh4_x86.tstate = TSTATE_NONE;6.1525 - }6.1526 - break;6.1527 - default:6.1528 - UNDEF();6.1529 - break;6.1530 - }6.1531 - break;6.1532 - case 0x3:6.1533 - switch( (ir&0x80) >> 7 ) {6.1534 - case 0x0:6.1535 - switch( (ir&0x70) >> 4 ) {6.1536 - case 0x0:6.1537 - { /* STC.L SR, @-Rn */6.1538 - uint32_t Rn = ((ir>>8)&0xF);6.1539 - COUNT_INST(I_STCSRM);6.1540 - check_priv();6.1541 - load_reg( R_EAX, Rn );6.1542 - check_walign32( R_EAX );6.1543 - ADD_imm8s_r32( -4, R_EAX );6.1544 - MMU_TRANSLATE_WRITE( R_EAX );6.1545 - PUSH_realigned_r32( R_EAX );6.1546 - call_func0( sh4_read_sr );6.1547 - POP_realigned_r32( R_ECX );6.1548 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );6.1549 - MEM_WRITE_LONG( R_ECX, R_EAX );6.1550 - sh4_x86.tstate = TSTATE_NONE;6.1551 - }6.1552 - break;6.1553 - case 0x1:6.1554 - { /* STC.L GBR, @-Rn */6.1555 - uint32_t Rn = ((ir>>8)&0xF);6.1556 - COUNT_INST(I_STCM);6.1557 - load_reg( R_EAX, Rn );6.1558 - check_walign32( R_EAX );6.1559 - ADD_imm8s_r32( -4, R_EAX );6.1560 - MMU_TRANSLATE_WRITE( R_EAX );6.1561 - load_spreg( R_EDX, R_GBR );6.1562 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );6.1563 - MEM_WRITE_LONG( R_EAX, R_EDX );6.1564 - sh4_x86.tstate = TSTATE_NONE;6.1565 - }6.1566 - break;6.1567 - case 0x2:6.1568 - { /* STC.L VBR, @-Rn */6.1569 - uint32_t Rn = ((ir>>8)&0xF);6.1570 - COUNT_INST(I_STCM);6.1571 - check_priv();6.1572 - load_reg( R_EAX, Rn );6.1573 - check_walign32( R_EAX );6.1574 - ADD_imm8s_r32( -4, R_EAX );6.1575 - MMU_TRANSLATE_WRITE( R_EAX );6.1576 - load_spreg( R_EDX, R_VBR );6.1577 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );6.1578 - MEM_WRITE_LONG( R_EAX, R_EDX );6.1579 - sh4_x86.tstate = TSTATE_NONE;6.1580 - }6.1581 - break;6.1582 - case 0x3:6.1583 - { /* STC.L SSR, @-Rn */6.1584 - uint32_t Rn = ((ir>>8)&0xF);6.1585 - COUNT_INST(I_STCM);6.1586 - check_priv();6.1587 - load_reg( R_EAX, Rn );6.1588 - check_walign32( R_EAX );6.1589 - ADD_imm8s_r32( -4, R_EAX );6.1590 - MMU_TRANSLATE_WRITE( R_EAX );6.1591 - load_spreg( R_EDX, R_SSR );6.1592 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );6.1593 - MEM_WRITE_LONG( R_EAX, R_EDX );6.1594 - sh4_x86.tstate = TSTATE_NONE;6.1595 - }6.1596 - break;6.1597 - case 0x4:6.1598 - { /* STC.L SPC, @-Rn */6.1599 - uint32_t Rn = ((ir>>8)&0xF);6.1600 - COUNT_INST(I_STCM);6.1601 - check_priv();6.1602 - load_reg( R_EAX, Rn );6.1603 - check_walign32( R_EAX );6.1604 - ADD_imm8s_r32( -4, R_EAX );6.1605 - MMU_TRANSLATE_WRITE( R_EAX );6.1606 - load_spreg( R_EDX, R_SPC );6.1607 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );6.1608 - MEM_WRITE_LONG( R_EAX, R_EDX );6.1609 - sh4_x86.tstate = TSTATE_NONE;6.1610 - }6.1611 - break;6.1612 - default:6.1613 - UNDEF();6.1614 - break;6.1615 - }6.1616 - break;6.1617 - case 0x1:6.1618 - { /* STC.L Rm_BANK, @-Rn */6.1619 - uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);6.1620 - COUNT_INST(I_STCM);6.1621 - check_priv();6.1622 - load_reg( R_EAX, Rn );6.1623 - check_walign32( R_EAX );6.1624 - ADD_imm8s_r32( -4, R_EAX );6.1625 - MMU_TRANSLATE_WRITE( R_EAX );6.1626 - load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) );6.1627 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );6.1628 - MEM_WRITE_LONG( R_EAX, R_EDX );6.1629 - sh4_x86.tstate = TSTATE_NONE;6.1630 - }6.1631 - break;6.1632 - }6.1633 - break;6.1634 - case 0x4:6.1635 - switch( (ir&0xF0) >> 4 ) {6.1636 - case 0x0:6.1637 - { /* ROTL Rn */6.1638 - uint32_t Rn = ((ir>>8)&0xF);6.1639 - COUNT_INST(I_ROTL);6.1640 - load_reg( R_EAX, Rn );6.1641 - ROL1_r32( R_EAX );6.1642 - store_reg( R_EAX, Rn );6.1643 - SETC_t();6.1644 - sh4_x86.tstate = TSTATE_C;6.1645 - }6.1646 - break;6.1647 - case 0x2:6.1648 - { /* ROTCL Rn */6.1649 - uint32_t Rn = ((ir>>8)&0xF);6.1650 - COUNT_INST(I_ROTCL);6.1651 - load_reg( R_EAX, Rn );6.1652 - if( sh4_x86.tstate != TSTATE_C ) {6.1653 - LDC_t();6.1654 - }6.1655 - RCL1_r32( R_EAX );6.1656 - store_reg( R_EAX, Rn );6.1657 - SETC_t();6.1658 - sh4_x86.tstate = TSTATE_C;6.1659 - }6.1660 - break;6.1661 - default:6.1662 - UNDEF();6.1663 - break;6.1664 - }6.1665 - break;6.1666 - case 0x5:6.1667 - switch( (ir&0xF0) >> 4 ) {6.1668 - case 0x0:6.1669 - { /* ROTR Rn */6.1670 - uint32_t Rn = ((ir>>8)&0xF);6.1671 - COUNT_INST(I_ROTR);6.1672 - load_reg( R_EAX, Rn );6.1673 - ROR1_r32( R_EAX );6.1674 - store_reg( R_EAX, Rn );6.1675 - SETC_t();6.1676 - sh4_x86.tstate = TSTATE_C;6.1677 - }6.1678 - break;6.1679 - case 0x1:6.1680 - { /* CMP/PL Rn */6.1681 - uint32_t Rn = ((ir>>8)&0xF);6.1682 - COUNT_INST(I_CMPPL);6.1683 - load_reg( R_EAX, Rn );6.1684 - CMP_imm8s_r32( 0, R_EAX );6.1685 - SETG_t();6.1686 - sh4_x86.tstate = TSTATE_G;6.1687 - }6.1688 - break;6.1689 - case 0x2:6.1690 - { /* ROTCR Rn */6.1691 - uint32_t Rn = ((ir>>8)&0xF);6.1692 - COUNT_INST(I_ROTCR);6.1693 - load_reg( R_EAX, Rn );6.1694 - if( sh4_x86.tstate != TSTATE_C ) {6.1695 - LDC_t();6.1696 - }6.1697 - RCR1_r32( R_EAX );6.1698 - store_reg( R_EAX, Rn );6.1699 - SETC_t();6.1700 - sh4_x86.tstate = TSTATE_C;6.1701 - }6.1702 - break;6.1703 - default:6.1704 - UNDEF();6.1705 - break;6.1706 - }6.1707 - break;6.1708 - case 0x6:6.1709 - switch( (ir&0xF0) >> 4 ) {6.1710 - case 0x0:6.1711 - { /* LDS.L @Rm+, MACH */6.1712 - uint32_t Rm = ((ir>>8)&0xF);6.1713 - COUNT_INST(I_LDSM);6.1714 - load_reg( R_EAX, Rm );6.1715 - check_ralign32( R_EAX );6.1716 - MMU_TRANSLATE_READ( R_EAX );6.1717 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );6.1718 - MEM_READ_LONG( R_EAX, R_EAX );6.1719 - store_spreg( R_EAX, R_MACH );6.1720 - sh4_x86.tstate = TSTATE_NONE;6.1721 - }6.1722 - break;6.1723 - case 0x1:6.1724 - { /* LDS.L @Rm+, MACL */6.1725 - uint32_t Rm = ((ir>>8)&0xF);6.1726 - COUNT_INST(I_LDSM);6.1727 - load_reg( R_EAX, Rm );6.1728 - check_ralign32( R_EAX );6.1729 - MMU_TRANSLATE_READ( R_EAX );6.1730 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );6.1731 - MEM_READ_LONG( R_EAX, R_EAX );6.1732 - store_spreg( R_EAX, R_MACL );6.1733 - sh4_x86.tstate = TSTATE_NONE;6.1734 - }6.1735 - break;6.1736 - case 0x2:6.1737 - { /* LDS.L @Rm+, PR */6.1738 - uint32_t Rm = ((ir>>8)&0xF);6.1739 - COUNT_INST(I_LDSM);6.1740 - load_reg( R_EAX, Rm );6.1741 - check_ralign32( R_EAX );6.1742 - MMU_TRANSLATE_READ( R_EAX );6.1743 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );6.1744 - MEM_READ_LONG( R_EAX, R_EAX );6.1745 - store_spreg( R_EAX, R_PR );6.1746 - sh4_x86.tstate = TSTATE_NONE;6.1747 - }6.1748 - break;6.1749 - case 0x3:6.1750 - { /* LDC.L @Rm+, SGR */6.1751 - uint32_t Rm = ((ir>>8)&0xF);6.1752 - COUNT_INST(I_LDCM);6.1753 - check_priv();6.1754 - load_reg( R_EAX, Rm );6.1755 - check_ralign32( R_EAX );6.1756 - MMU_TRANSLATE_READ( R_EAX );6.1757 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );6.1758 - MEM_READ_LONG( R_EAX, R_EAX );6.1759 - store_spreg( R_EAX, R_SGR );6.1760 - sh4_x86.tstate = TSTATE_NONE;6.1761 - }6.1762 - break;6.1763 - case 0x5:6.1764 - { /* LDS.L @Rm+, FPUL */6.1765 - uint32_t Rm = ((ir>>8)&0xF);6.1766 - COUNT_INST(I_LDSM);6.1767 - check_fpuen();6.1768 - load_reg( R_EAX, Rm );6.1769 - check_ralign32( R_EAX );6.1770 - MMU_TRANSLATE_READ( R_EAX );6.1771 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );6.1772 - MEM_READ_LONG( R_EAX, R_EAX );6.1773 - store_spreg( R_EAX, R_FPUL );6.1774 - sh4_x86.tstate = TSTATE_NONE;6.1775 - }6.1776 - break;6.1777 - case 0x6:6.1778 - { /* LDS.L @Rm+, FPSCR */6.1779 - uint32_t Rm = ((ir>>8)&0xF);6.1780 - COUNT_INST(I_LDSFPSCRM);6.1781 - check_fpuen();6.1782 - load_reg( R_EAX, Rm );6.1783 - check_ralign32( R_EAX );6.1784 - MMU_TRANSLATE_READ( R_EAX );6.1785 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );6.1786 - MEM_READ_LONG( R_EAX, R_EAX );6.1787 - call_func1( sh4_write_fpscr, R_EAX );6.1788 - sh4_x86.tstate = TSTATE_NONE;6.1789 - }6.1790 - break;6.1791 - case 0xF:6.1792 - { /* LDC.L @Rm+, DBR */6.1793 - uint32_t Rm = ((ir>>8)&0xF);6.1794 - COUNT_INST(I_LDCM);6.1795 - check_priv();6.1796 - load_reg( R_EAX, Rm );6.1797 - check_ralign32( R_EAX );6.1798 - MMU_TRANSLATE_READ( R_EAX );6.1799 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );6.1800 - MEM_READ_LONG( R_EAX, R_EAX );6.1801 - store_spreg( R_EAX, R_DBR );6.1802 - sh4_x86.tstate = TSTATE_NONE;6.1803 - }6.1804 - break;6.1805 - default:6.1806 - UNDEF();6.1807 - break;6.1808 - }6.1809 - break;6.1810 - case 0x7:6.1811 - switch( (ir&0x80) >> 7 ) {6.1812 - case 0x0:6.1813 - switch( (ir&0x70) >> 4 ) {6.1814 - case 0x0:6.1815 - { /* LDC.L @Rm+, SR */6.1816 - uint32_t Rm = ((ir>>8)&0xF);6.1817 - COUNT_INST(I_LDCSRM);6.1818 - if( sh4_x86.in_delay_slot ) {6.1819 - SLOTILLEGAL();6.1820 - } else {6.1821 - check_priv();6.1822 - load_reg( R_EAX, Rm );6.1823 - check_ralign32( R_EAX );6.1824 - MMU_TRANSLATE_READ( R_EAX );6.1825 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );6.1826 - MEM_READ_LONG( R_EAX, R_EAX );6.1827 - call_func1( sh4_write_sr, R_EAX );6.1828 - sh4_x86.priv_checked = FALSE;6.1829 - sh4_x86.fpuen_checked = FALSE;6.1830 - sh4_x86.tstate = TSTATE_NONE;6.1831 - }6.1832 - }6.1833 - break;6.1834 - case 0x1:6.1835 - { /* LDC.L @Rm+, GBR */6.1836 - uint32_t Rm = ((ir>>8)&0xF);6.1837 - COUNT_INST(I_LDCM);6.1838 - load_reg( R_EAX, Rm );6.1839 - check_ralign32( R_EAX );6.1840 - MMU_TRANSLATE_READ( R_EAX );6.1841 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );6.1842 - MEM_READ_LONG( R_EAX, R_EAX );6.1843 - store_spreg( R_EAX, R_GBR );6.1844 - sh4_x86.tstate = TSTATE_NONE;6.1845 - }6.1846 - break;6.1847 - case 0x2:6.1848 - { /* LDC.L @Rm+, VBR */6.1849 - uint32_t Rm = ((ir>>8)&0xF);6.1850 - COUNT_INST(I_LDCM);6.1851 - check_priv();6.1852 - load_reg( R_EAX, Rm );6.1853 - check_ralign32( R_EAX );6.1854 - MMU_TRANSLATE_READ( R_EAX );6.1855 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );6.1856 - MEM_READ_LONG( R_EAX, R_EAX );6.1857 - store_spreg( R_EAX, R_VBR );6.1858 - sh4_x86.tstate = TSTATE_NONE;6.1859 - }6.1860 - break;6.1861 - case 0x3:6.1862 - { /* LDC.L @Rm+, SSR */6.1863 - uint32_t Rm = ((ir>>8)&0xF);6.1864 - COUNT_INST(I_LDCM);6.1865 - check_priv();6.1866 - load_reg( R_EAX, Rm );6.1867 - check_ralign32( R_EAX );6.1868 - MMU_TRANSLATE_READ( R_EAX );6.1869 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );6.1870 - MEM_READ_LONG( R_EAX, R_EAX );6.1871 - store_spreg( R_EAX, R_SSR );