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lxdream.org :: lxdream :: r855:b937948d79d9
lxdream 0.9.1
released Jun 29
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changeset855:b937948d79d9
parent854:130928a3cdcb
child856:02ac5f37bfc9
authornkeynes
dateWed Sep 10 02:03:20 2008 +0000 (11 years ago)
Initial impl of the alternate PVR DMA channel
src/asic.c
src/asic.h
1.1 --- a/src/asic.c Tue Sep 09 00:51:43 2008 +0000
1.2 +++ b/src/asic.c Wed Sep 10 02:03:20 2008 +0000
1.3 @@ -351,6 +351,28 @@
1.4 asic_event( EVENT_PVR_DMA );
1.5 }
1.6
1.7 +void pvr_dma2_transfer()
1.8 +{
1.9 + if( MMIO_READ( EXTDMA, PVRDMA2CTL2 ) == 1 ) {
1.10 + if( MMIO_READ( EXTDMA, PVRDMA2CTL1 ) == 1 ) {
1.11 + sh4addr_t extaddr = MMIO_READ( EXTDMA, PVRDMA2EXT );
1.12 + sh4addr_t sh4addr = MMIO_READ( EXTDMA, PVRDMA2SH4 );
1.13 + int dir = MMIO_READ( EXTDMA, PVRDMA2DIR );
1.14 + uint32_t length = MMIO_READ( EXTDMA, PVRDMA2SIZ );
1.15 + unsigned char buf[length];
1.16 + if( dir == 0 ) { /* SH4 to PVR */
1.17 + mem_copy_from_sh4( buf, sh4addr, length );
1.18 + mem_copy_to_sh4( extaddr, buf, length );
1.19 + } else { /* PVR to SH4 */
1.20 + mem_copy_from_sh4( buf, extaddr, length );
1.21 + mem_copy_to_sh4( sh4addr, buf, length );
1.22 + }
1.23 + MMIO_WRITE( EXTDMA, PVRDMA2CTL2, 0 );
1.24 + asic_event( EVENT_PVR_DMA2 );
1.25 + }
1.26 + }
1.27 +}
1.28 +
1.29 void sort_dma_transfer( )
1.30 {
1.31 sh4addr_t table_addr = MMIO_READ( ASIC, SORTDMATBL );
1.32 @@ -615,9 +637,8 @@
1.33 break;
1.34 case PVRDMA2CTL1:
1.35 case PVRDMA2CTL2:
1.36 - if( val != 0 ) {
1.37 - ERROR( "Write to unimplemented DMA control register %08X", reg );
1.38 - }
1.39 + MMIO_WRITE( EXTDMA, reg, val & 1 );
1.40 + pvr_dma2_transfer();
1.41 break;
1.42 default:
1.43 MMIO_WRITE( EXTDMA, reg, val );
2.1 --- a/src/asic.h Tue Sep 09 00:51:43 2008 +0000
2.2 +++ b/src/asic.h Wed Sep 10 02:03:20 2008 +0000
2.3 @@ -182,6 +182,7 @@
2.4 #define EVENT_PVR_OPAQUEMOD_DONE 8
2.5 #define EVENT_PVR_TRANS_DONE 9
2.6 #define EVENT_PVR_TRANSMOD_DONE 10
2.7 +#define EVENT_PVR_DMA2 11
2.8 #define EVENT_MAPLE_DMA 12
2.9 #define EVENT_MAPLE_ERR 13 /* ??? */
2.10 #define EVENT_IDE_DMA 14
.