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lxdream.org :: lxdream :: r417:bd927df302a9
lxdream 0.9.1
released Jun 29
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changeset417:bd927df302a9
parent416:714df603c869
child418:b9b14afa0959
authornkeynes
dateThu Oct 04 08:47:27 2007 +0000 (12 years ago)
Suppress redundant T flag loads
Tweak run_slice for performance
src/sh4/sh4trans.c
src/sh4/sh4x86.c
src/sh4/sh4x86.in
1.1 --- a/src/sh4/sh4trans.c Wed Oct 03 12:19:03 2007 +0000
1.2 +++ b/src/sh4/sh4trans.c Thu Oct 04 08:47:27 2007 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: sh4trans.c,v 1.6 2007-09-29 11:06:40 nkeynes Exp $
1.6 + * $Id: sh4trans.c,v 1.7 2007-10-04 08:47:27 nkeynes Exp $
1.7 *
1.8 * SH4 translation core module. This part handles the non-target-specific
1.9 * section of the translation.
1.10 @@ -50,9 +50,7 @@
1.11 }
1.12 }
1.13
1.14 - if( code ) { // fast path
1.15 - code = code();
1.16 - } else {
1.17 + if( code == NULL ) {
1.18 if( sh4r.pc > 0xFFFFFF00 ) {
1.19 syscall_invoke( sh4r.pc );
1.20 sh4r.in_delay_slot = 0;
1.21 @@ -63,8 +61,8 @@
1.22 if( code == NULL ) {
1.23 code = sh4_translate_basic_block( sh4r.pc );
1.24 }
1.25 - code = code();
1.26 }
1.27 + code = code();
1.28 }
1.29
1.30 if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
2.1 --- a/src/sh4/sh4x86.c Wed Oct 03 12:19:03 2007 +0000
2.2 +++ b/src/sh4/sh4x86.c Thu Oct 04 08:47:27 2007 +0000
2.3 @@ -1,5 +1,5 @@
2.4 /**
2.5 - * $Id: sh4x86.c,v 1.17 2007-10-03 12:19:03 nkeynes Exp $
2.6 + * $Id: sh4x86.c,v 1.18 2007-10-04 08:47:27 nkeynes Exp $
2.7 *
2.8 * SH4 => x86 translation. This version does no real optimization, it just
2.9 * outputs straight-line x86 code - it mainly exists to provide a baseline
2.10 @@ -25,6 +25,7 @@
2.11 #define DEBUG_JUMPS 1
2.12 #endif
2.13
2.14 +#include "sh4/xltcache.h"
2.15 #include "sh4/sh4core.h"
2.16 #include "sh4/sh4trans.h"
2.17 #include "sh4/sh4mmio.h"
2.18 @@ -44,6 +45,7 @@
2.19 gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
2.20 gboolean branch_taken; /* true if we branched unconditionally */
2.21 uint32_t block_start_pc;
2.22 + int tstate;
2.23
2.24 /* Allocated memory for the (block-wide) back-patch list */
2.25 uint32_t **backpatch_list;
2.26 @@ -51,6 +53,28 @@
2.27 uint32_t backpatch_size;
2.28 };
2.29
2.30 +#define TSTATE_NONE -1
2.31 +#define TSTATE_O 0
2.32 +#define TSTATE_C 2
2.33 +#define TSTATE_E 4
2.34 +#define TSTATE_NE 5
2.35 +#define TSTATE_G 0xF
2.36 +#define TSTATE_GE 0xD
2.37 +#define TSTATE_A 7
2.38 +#define TSTATE_AE 3
2.39 +
2.40 +/** Branch if T is set (either in the current cflags, or in sh4r.t) */
2.41 +#define JT_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
2.42 + CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
2.43 + OP(0x70+sh4_x86.tstate); OP(rel8); \
2.44 + MARK_JMP(rel8,label)
2.45 +/** Branch if T is clear (either in the current cflags or in sh4r.t) */
2.46 +#define JF_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
2.47 + CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
2.48 + OP(0x70+ (sh4_x86.tstate^1)); OP(rel8); \
2.49 + MARK_JMP(rel8, label)
2.50 +
2.51 +
2.52 #define EXIT_DATA_ADDR_READ 0
2.53 #define EXIT_DATA_ADDR_WRITE 7
2.54 #define EXIT_ILLEGAL 14
2.55 @@ -403,6 +427,7 @@
2.56 sh4_x86.branch_taken = FALSE;
2.57 sh4_x86.backpatch_posn = 0;
2.58 sh4_x86.block_start_pc = pc;
2.59 + sh4_x86.tstate = TSTATE_NONE;
2.60 }
2.61
2.62 /**
2.63 @@ -427,9 +452,10 @@
2.64 */
2.65 void exit_block_pcset( pc )
2.66 {
2.67 - XOR_r32_r32( R_EAX, R_EAX ); // 2
2.68 load_imm32( R_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
2.69 ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) ); // 6
2.70 + load_spreg( R_EAX, REG_OFFSET(pc) );
2.71 + call_func1(xlat_get_code,R_EAX);
2.72 POP_r32(R_EBP);
2.73 RET();
2.74 }
2.75 @@ -462,20 +488,20 @@
2.76 JMP_TARGET(target3);
2.77 JMP_TARGET(target4);
2.78 JMP_TARGET(target5);
2.79 + // Raise exception
2.80 load_spreg( R_ECX, REG_OFFSET(pc) );
2.81 ADD_r32_r32( R_EDX, R_ECX );
2.82 ADD_r32_r32( R_EDX, R_ECX );
2.83 store_spreg( R_ECX, REG_OFFSET(pc) );
2.84 MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
2.85 - load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
2.86 MUL_r32( R_EDX );
2.87 - ADD_r32_r32( R_EAX, R_ECX );
2.88 - store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
2.89 + ADD_r32_sh4r( R_EAX, REG_OFFSET(slice_cycle) );
2.90
2.91 load_imm32( R_EAX, (uint32_t)sh4_raise_exception ); // 6
2.92 CALL_r32( R_EAX ); // 2
2.93 ADD_imm8s_r32( 4, R_ESP );
2.94 - XOR_r32_r32( R_EAX, R_EAX );
2.95 + load_spreg( R_EAX, REG_OFFSET(pc) );
2.96 + call_func1(xlat_get_code,R_EAX);
2.97 POP_r32(R_EBP);
2.98 RET();
2.99
2.100 @@ -530,6 +556,7 @@
2.101 check_priv();
2.102 call_func0(sh4_read_sr);
2.103 store_reg( R_EAX, Rn );
2.104 + sh4_x86.tstate = TSTATE_NONE;
2.105 }
2.106 break;
2.107 case 0x1:
2.108 @@ -545,6 +572,7 @@
2.109 check_priv();
2.110 load_spreg( R_EAX, R_VBR );
2.111 store_reg( R_EAX, Rn );
2.112 + sh4_x86.tstate = TSTATE_NONE;
2.113 }
2.114 break;
2.115 case 0x3:
2.116 @@ -553,6 +581,7 @@
2.117 check_priv();
2.118 load_spreg( R_EAX, R_SSR );
2.119 store_reg( R_EAX, Rn );
2.120 + sh4_x86.tstate = TSTATE_NONE;
2.121 }
2.122 break;
2.123 case 0x4:
2.124 @@ -561,6 +590,7 @@
2.125 check_priv();
2.126 load_spreg( R_EAX, R_SPC );
2.127 store_reg( R_EAX, Rn );
2.128 + sh4_x86.tstate = TSTATE_NONE;
2.129 }
2.130 break;
2.131 default:
2.132 @@ -574,6 +604,7 @@
2.133 check_priv();
2.134 load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
2.135 store_reg( R_EAX, Rn );
2.136 + sh4_x86.tstate = TSTATE_NONE;
2.137 }
2.138 break;
2.139 }
2.140 @@ -591,6 +622,7 @@
2.141 ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_ECX );
2.142 store_spreg( R_ECX, REG_OFFSET(pc) );
2.143 sh4_x86.in_delay_slot = TRUE;
2.144 + sh4_x86.tstate = TSTATE_NONE;
2.145 sh4_x86_translate_instruction( pc + 2 );
2.146 exit_block_pcset(pc+2);
2.147 sh4_x86.branch_taken = TRUE;
2.148 @@ -608,6 +640,7 @@
2.149 ADD_imm32_r32( pc + 4, R_EAX );
2.150 store_spreg( R_EAX, REG_OFFSET(pc) );
2.151 sh4_x86.in_delay_slot = TRUE;
2.152 + sh4_x86.tstate = TSTATE_NONE;
2.153 sh4_x86_translate_instruction( pc + 2 );
2.154 exit_block_pcset(pc+2);
2.155 sh4_x86.branch_taken = TRUE;
2.156 @@ -626,6 +659,7 @@
2.157 call_func0( sh4_flush_store_queue );
2.158 JMP_TARGET(end);
2.159 ADD_imm8s_r32( 4, R_ESP );
2.160 + sh4_x86.tstate = TSTATE_NONE;
2.161 }
2.162 break;
2.163 case 0x9:
2.164 @@ -651,6 +685,7 @@
2.165 precheck();
2.166 check_walign32( R_ECX );
2.167 MEM_WRITE_LONG( R_ECX, R_EAX );
2.168 + sh4_x86.tstate = TSTATE_NONE;
2.169 }
2.170 break;
2.171 default:
2.172 @@ -666,6 +701,7 @@
2.173 ADD_r32_r32( R_EAX, R_ECX );
2.174 load_reg( R_EAX, Rm );
2.175 MEM_WRITE_BYTE( R_ECX, R_EAX );
2.176 + sh4_x86.tstate = TSTATE_NONE;
2.177 }
2.178 break;
2.179 case 0x5:
2.180 @@ -678,6 +714,7 @@
2.181 check_walign16( R_ECX );
2.182 load_reg( R_EAX, Rm );
2.183 MEM_WRITE_WORD( R_ECX, R_EAX );
2.184 + sh4_x86.tstate = TSTATE_NONE;
2.185 }
2.186 break;
2.187 case 0x6:
2.188 @@ -690,6 +727,7 @@
2.189 check_walign32( R_ECX );
2.190 load_reg( R_EAX, Rm );
2.191 MEM_WRITE_LONG( R_ECX, R_EAX );
2.192 + sh4_x86.tstate = TSTATE_NONE;
2.193 }
2.194 break;
2.195 case 0x7:
2.196 @@ -699,6 +737,7 @@
2.197 load_reg( R_ECX, Rn );
2.198 MUL_r32( R_ECX );
2.199 store_spreg( R_EAX, R_MACL );
2.200 + sh4_x86.tstate = TSTATE_NONE;
2.201 }
2.202 break;
2.203 case 0x8:
2.204 @@ -707,12 +746,14 @@
2.205 { /* CLRT */
2.206 CLC();
2.207 SETC_t();
2.208 + sh4_x86.tstate = TSTATE_C;
2.209 }
2.210 break;
2.211 case 0x1:
2.212 { /* SETT */
2.213 STC();
2.214 SETC_t();
2.215 + sh4_x86.tstate = TSTATE_C;
2.216 }
2.217 break;
2.218 case 0x2:
2.219 @@ -720,6 +761,7 @@
2.220 XOR_r32_r32(R_EAX, R_EAX);
2.221 store_spreg( R_EAX, R_MACL );
2.222 store_spreg( R_EAX, R_MACH );
2.223 + sh4_x86.tstate = TSTATE_NONE;
2.224 }
2.225 break;
2.226 case 0x3:
2.227 @@ -730,12 +772,14 @@
2.228 { /* CLRS */
2.229 CLC();
2.230 SETC_sh4r(R_S);
2.231 + sh4_x86.tstate = TSTATE_C;
2.232 }
2.233 break;
2.234 case 0x5:
2.235 { /* SETS */
2.236 STC();
2.237 SETC_sh4r(R_S);
2.238 + sh4_x86.tstate = TSTATE_C;
2.239 }
2.240 break;
2.241 default:
2.242 @@ -756,6 +800,7 @@
2.243 store_spreg( R_EAX, R_Q );
2.244 store_spreg( R_EAX, R_M );
2.245 store_spreg( R_EAX, R_T );
2.246 + sh4_x86.tstate = TSTATE_C; // works for DIV1
2.247 }
2.248 break;
2.249 case 0x2:
2.250 @@ -799,6 +844,7 @@
2.251 check_priv();
2.252 load_spreg( R_EAX, R_SGR );
2.253 store_reg( R_EAX, Rn );
2.254 + sh4_x86.tstate = TSTATE_NONE;
2.255 }
2.256 break;
2.257 case 0x5:
2.258 @@ -821,6 +867,7 @@
2.259 check_priv();
2.260 load_spreg( R_EAX, R_DBR );
2.261 store_reg( R_EAX, Rn );
2.262 + sh4_x86.tstate = TSTATE_NONE;
2.263 }
2.264 break;
2.265 default:
2.266 @@ -849,6 +896,7 @@
2.267 { /* SLEEP */
2.268 check_priv();
2.269 call_func0( sh4_sleep );
2.270 + sh4_x86.tstate = TSTATE_NONE;
2.271 sh4_x86.in_delay_slot = FALSE;
2.272 return 2;
2.273 }
2.274 @@ -866,6 +914,7 @@
2.275 sh4_x86.in_delay_slot = TRUE;
2.276 sh4_x86.priv_checked = FALSE;
2.277 sh4_x86.fpuen_checked = FALSE;
2.278 + sh4_x86.tstate = TSTATE_NONE;
2.279 sh4_x86_translate_instruction(pc+2);
2.280 exit_block_pcset(pc+2);
2.281 sh4_x86.branch_taken = TRUE;
2.282 @@ -886,6 +935,7 @@
2.283 ADD_r32_r32( R_EAX, R_ECX );
2.284 MEM_READ_BYTE( R_ECX, R_EAX );
2.285 store_reg( R_EAX, Rn );
2.286 + sh4_x86.tstate = TSTATE_NONE;
2.287 }
2.288 break;
2.289 case 0xD:
2.290 @@ -898,6 +948,7 @@
2.291 check_ralign16( R_ECX );
2.292 MEM_READ_WORD( R_ECX, R_EAX );
2.293 store_reg( R_EAX, Rn );
2.294 + sh4_x86.tstate = TSTATE_NONE;
2.295 }
2.296 break;
2.297 case 0xE:
2.298 @@ -910,6 +961,7 @@
2.299 check_ralign32( R_ECX );
2.300 MEM_READ_LONG( R_ECX, R_EAX );
2.301 store_reg( R_EAX, Rn );
2.302 + sh4_x86.tstate = TSTATE_NONE;
2.303 }
2.304 break;
2.305 case 0xF:
2.306 @@ -936,6 +988,7 @@
2.307 JE_rel8( 7, nosat );
2.308 call_func0( signsat48 );
2.309 JMP_TARGET( nosat );
2.310 + sh4_x86.tstate = TSTATE_NONE;
2.311 }
2.312 break;
2.313 default:
2.314 @@ -952,6 +1005,7 @@
2.315 precheck();
2.316 check_walign32( R_ECX );
2.317 MEM_WRITE_LONG( R_ECX, R_EAX );
2.318 + sh4_x86.tstate = TSTATE_NONE;
2.319 }
2.320 break;
2.321 case 0x2:
2.322 @@ -962,6 +1016,7 @@
2.323 load_reg( R_EAX, Rm );
2.324 load_reg( R_ECX, Rn );
2.325 MEM_WRITE_BYTE( R_ECX, R_EAX );
2.326 + sh4_x86.tstate = TSTATE_NONE;
2.327 }
2.328 break;
2.329 case 0x1:
2.330 @@ -972,6 +1027,7 @@
2.331 check_walign16( R_ECX );
2.332 load_reg( R_EAX, Rm );
2.333 MEM_WRITE_WORD( R_ECX, R_EAX );
2.334 + sh4_x86.tstate = TSTATE_NONE;
2.335 }
2.336 break;
2.337 case 0x2:
2.338 @@ -982,6 +1038,7 @@
2.339 precheck();
2.340 check_walign32(R_ECX);
2.341 MEM_WRITE_LONG( R_ECX, R_EAX );
2.342 + sh4_x86.tstate = TSTATE_NONE;
2.343 }
2.344 break;
2.345 case 0x4:
2.346 @@ -992,6 +1049,7 @@
2.347 ADD_imm8s_r32( -1, R_ECX );
2.348 store_reg( R_ECX, Rn );
2.349 MEM_WRITE_BYTE( R_ECX, R_EAX );
2.350 + sh4_x86.tstate = TSTATE_NONE;
2.351 }
2.352 break;
2.353 case 0x5:
2.354 @@ -1004,6 +1062,7 @@
2.355 ADD_imm8s_r32( -2, R_ECX );
2.356 store_reg( R_ECX, Rn );
2.357 MEM_WRITE_WORD( R_ECX, R_EAX );
2.358 + sh4_x86.tstate = TSTATE_NONE;
2.359 }
2.360 break;
2.361 case 0x6:
2.362 @@ -1016,6 +1075,7 @@
2.363 ADD_imm8s_r32( -4, R_ECX );
2.364 store_reg( R_ECX, Rn );
2.365 MEM_WRITE_LONG( R_ECX, R_EAX );
2.366 + sh4_x86.tstate = TSTATE_NONE;
2.367 }
2.368 break;
2.369 case 0x7:
2.370 @@ -1029,6 +1089,7 @@
2.371 store_spreg( R_ECX, R_Q );
2.372 CMP_r32_r32( R_EAX, R_ECX );
2.373 SETNE_t();
2.374 + sh4_x86.tstate = TSTATE_NE;
2.375 }
2.376 break;
2.377 case 0x8:
2.378 @@ -1038,6 +1099,7 @@
2.379 load_reg( R_ECX, Rn );
2.380 TEST_r32_r32( R_EAX, R_ECX );
2.381 SETE_t();
2.382 + sh4_x86.tstate = TSTATE_E;
2.383 }
2.384 break;
2.385 case 0x9:
2.386 @@ -1047,6 +1109,7 @@
2.387 load_reg( R_ECX, Rn );
2.388 AND_r32_r32( R_EAX, R_ECX );
2.389 store_reg( R_ECX, Rn );
2.390 + sh4_x86.tstate = TSTATE_NONE;
2.391 }
2.392 break;
2.393 case 0xA:
2.394 @@ -1056,6 +1119,7 @@
2.395 load_reg( R_ECX, Rn );
2.396 XOR_r32_r32( R_EAX, R_ECX );
2.397 store_reg( R_ECX, Rn );
2.398 + sh4_x86.tstate = TSTATE_NONE;
2.399 }
2.400 break;
2.401 case 0xB:
2.402 @@ -1065,6 +1129,7 @@
2.403 load_reg( R_ECX, Rn );
2.404 OR_r32_r32( R_EAX, R_ECX );
2.405 store_reg( R_ECX, Rn );
2.406 + sh4_x86.tstate = TSTATE_NONE;
2.407 }
2.408 break;
2.409 case 0xC:
2.410 @@ -1085,6 +1150,7 @@
2.411 JMP_TARGET(target2);
2.412 JMP_TARGET(target3);
2.413 SETE_t();
2.414 + sh4_x86.tstate = TSTATE_E;
2.415 }
2.416 break;
2.417 case 0xD:
2.418 @@ -1096,6 +1162,7 @@
2.419 SHR_imm8_r32( 16, R_ECX );
2.420 OR_r32_r32( R_EAX, R_ECX );
2.421 store_reg( R_ECX, Rn );
2.422 + sh4_x86.tstate = TSTATE_NONE;
2.423 }
2.424 break;
2.425 case 0xE:
2.426 @@ -1105,6 +1172,7 @@
2.427 load_reg16u( R_ECX, Rn );
2.428 MUL_r32( R_ECX );
2.429 store_spreg( R_EAX, R_MACL );
2.430 + sh4_x86.tstate = TSTATE_NONE;
2.431 }
2.432 break;
2.433 case 0xF:
2.434 @@ -1114,6 +1182,7 @@
2.435 load_reg16s( R_ECX, Rn );
2.436 MUL_r32( R_ECX );
2.437 store_spreg( R_EAX, R_MACL );
2.438 + sh4_x86.tstate = TSTATE_NONE;
2.439 }
2.440 break;
2.441 default:
2.442 @@ -1130,6 +1199,7 @@
2.443 load_reg( R_ECX, Rn );
2.444 CMP_r32_r32( R_EAX, R_ECX );
2.445 SETE_t();
2.446 + sh4_x86.tstate = TSTATE_E;
2.447 }
2.448 break;
2.449 case 0x2:
2.450 @@ -1139,6 +1209,7 @@
2.451 load_reg( R_ECX, Rn );
2.452 CMP_r32_r32( R_EAX, R_ECX );
2.453 SETAE_t();
2.454 + sh4_x86.tstate = TSTATE_AE;
2.455 }
2.456 break;
2.457 case 0x3:
2.458 @@ -1148,6 +1219,7 @@
2.459 load_reg( R_ECX, Rn );
2.460 CMP_r32_r32( R_EAX, R_ECX );
2.461 SETGE_t();
2.462 + sh4_x86.tstate = TSTATE_GE;
2.463 }
2.464 break;
2.465 case 0x4:
2.466 @@ -1155,7 +1227,9 @@
2.467 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
2.468 load_spreg( R_ECX, R_M );
2.469 load_reg( R_EAX, Rn );
2.470 - LDC_t();
2.471 + if( sh4_x86.tstate != TSTATE_C ) {
2.472 + LDC_t();
2.473 + }
2.474 RCL1_r32( R_EAX );
2.475 SETC_r8( R_DL ); // Q'
2.476 CMP_sh4r_r32( R_Q, R_ECX );
2.477 @@ -1173,6 +1247,7 @@
2.478 XOR_imm8s_r32( 1, R_AL ); // T = !Q'
2.479 MOVZX_r8_r32( R_AL, R_EAX );
2.480 store_spreg( R_EAX, R_T );
2.481 + sh4_x86.tstate = TSTATE_NONE;
2.482 }
2.483 break;
2.484 case 0x5:
2.485 @@ -1182,7 +1257,8 @@
2.486 load_reg( R_ECX, Rn );
2.487 MUL_r32(R_ECX);
2.488 store_spreg( R_EDX, R_MACH );
2.489 - store_spreg( R_EAX, R_MACL );
2.490 + store_spreg( R_EAX, R_MACL );
2.491 + sh4_x86.tstate = TSTATE_NONE;
2.492 }
2.493 break;
2.494 case 0x6:
2.495 @@ -1192,6 +1268,7 @@
2.496 load_reg( R_ECX, Rn );
2.497 CMP_r32_r32( R_EAX, R_ECX );
2.498 SETA_t();
2.499 + sh4_x86.tstate = TSTATE_A;
2.500 }
2.501 break;
2.502 case 0x7:
2.503 @@ -1201,6 +1278,7 @@
2.504 load_reg( R_ECX, Rn );
2.505 CMP_r32_r32( R_EAX, R_ECX );
2.506 SETG_t();
2.507 + sh4_x86.tstate = TSTATE_G;
2.508 }
2.509 break;
2.510 case 0x8:
2.511 @@ -1210,6 +1288,7 @@
2.512 load_reg( R_ECX, Rn );
2.513 SUB_r32_r32( R_EAX, R_ECX );
2.514 store_reg( R_ECX, Rn );
2.515 + sh4_x86.tstate = TSTATE_NONE;
2.516 }
2.517 break;
2.518 case 0xA:
2.519 @@ -1217,10 +1296,13 @@
2.520 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
2.521 load_reg( R_EAX, Rm );
2.522 load_reg( R_ECX, Rn );
2.523 - LDC_t();
2.524 + if( sh4_x86.tstate != TSTATE_C ) {
2.525 + LDC_t();
2.526 + }
2.527 SBB_r32_r32( R_EAX, R_ECX );
2.528 store_reg( R_ECX, Rn );
2.529 SETC_t();
2.530 + sh4_x86.tstate = TSTATE_C;
2.531 }
2.532 break;
2.533 case 0xB:
2.534 @@ -1231,6 +1313,7 @@
2.535 SUB_r32_r32( R_EAX, R_ECX );
2.536 store_reg( R_ECX, Rn );
2.537 SETO_t();
2.538 + sh4_x86.tstate = TSTATE_O;
2.539 }
2.540 break;
2.541 case 0xC:
2.542 @@ -1240,6 +1323,7 @@
2.543 load_reg( R_ECX, Rn );
2.544 ADD_r32_r32( R_EAX, R_ECX );
2.545 store_reg( R_ECX, Rn );
2.546 + sh4_x86.tstate = TSTATE_NONE;
2.547 }
2.548 break;
2.549 case 0xD:
2.550 @@ -1250,17 +1334,21 @@
2.551 IMUL_r32(R_ECX);
2.552 store_spreg( R_EDX, R_MACH );
2.553 store_spreg( R_EAX, R_MACL );
2.554 + sh4_x86.tstate = TSTATE_NONE;
2.555 }
2.556 break;
2.557 case 0xE:
2.558 { /* ADDC Rm, Rn */
2.559 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
2.560 + if( sh4_x86.tstate != TSTATE_C ) {
2.561 + LDC_t();
2.562 + }
2.563 load_reg( R_EAX, Rm );
2.564 load_reg( R_ECX, Rn );
2.565 - LDC_t();
2.566 ADC_r32_r32( R_EAX, R_ECX );
2.567 store_reg( R_ECX, Rn );
2.568 SETC_t();
2.569 + sh4_x86.tstate = TSTATE_C;
2.570 }
2.571 break;
2.572 case 0xF:
2.573 @@ -1271,6 +1359,7 @@
2.574 ADD_r32_r32( R_EAX, R_ECX );
2.575 store_reg( R_ECX, Rn );
2.576 SETO_t();
2.577 + sh4_x86.tstate = TSTATE_O;
2.578 }
2.579 break;
2.580 default:
2.581 @@ -1289,6 +1378,7 @@
2.582 SHL1_r32( R_EAX );
2.583 SETC_t();
2.584 store_reg( R_EAX, Rn );
2.585 + sh4_x86.tstate = TSTATE_C;
2.586 }
2.587 break;
2.588 case 0x1:
2.589 @@ -1298,6 +1388,7 @@
2.590 ADD_imm8s_r32( -1, R_EAX );
2.591 store_reg( R_EAX, Rn );
2.592 SETE_t();
2.593 + sh4_x86.tstate = TSTATE_E;
2.594 }
2.595 break;
2.596 case 0x2:
2.597 @@ -1307,6 +1398,7 @@
2.598 SHL1_r32( R_EAX );
2.599 SETC_t();
2.600 store_reg( R_EAX, Rn );
2.601 + sh4_x86.tstate = TSTATE_C;
2.602 }
2.603 break;
2.604 default:
2.605 @@ -1323,6 +1415,7 @@
2.606 SHR1_r32( R_EAX );
2.607 SETC_t();
2.608 store_reg( R_EAX, Rn );
2.609 + sh4_x86.tstate = TSTATE_C;
2.610 }
2.611 break;
2.612 case 0x1:
2.613 @@ -1331,6 +1424,7 @@
2.614 load_reg( R_EAX, Rn );
2.615 CMP_imm8s_r32( 0, R_EAX );
2.616 SETGE_t();
2.617 + sh4_x86.tstate = TSTATE_GE;
2.618 }
2.619 break;
2.620 case 0x2:
2.621 @@ -1340,6 +1434,7 @@
2.622 SAR1_r32( R_EAX );
2.623 SETC_t();
2.624 store_reg( R_EAX, Rn );
2.625 + sh4_x86.tstate = TSTATE_C;
2.626 }
2.627 break;
2.628 default:
2.629 @@ -1359,6 +1454,7 @@
2.630 store_reg( R_ECX, Rn );
2.631 load_spreg( R_EAX, R_MACH );
2.632 MEM_WRITE_LONG( R_ECX, R_EAX );
2.633 + sh4_x86.tstate = TSTATE_NONE;
2.634 }
2.635 break;
2.636 case 0x1:
2.637 @@ -1371,6 +1467,7 @@
2.638 store_reg( R_ECX, Rn );
2.639 load_spreg( R_EAX, R_MACL );
2.640 MEM_WRITE_LONG( R_ECX, R_EAX );
2.641 + sh4_x86.tstate = TSTATE_NONE;
2.642 }
2.643 break;
2.644 case 0x2:
2.645 @@ -1383,6 +1480,7 @@
2.646 store_reg( R_ECX, Rn );
2.647 load_spreg( R_EAX, R_PR );
2.648 MEM_WRITE_LONG( R_ECX, R_EAX );
2.649 + sh4_x86.tstate = TSTATE_NONE;
2.650 }
2.651 break;
2.652 case 0x3:
2.653 @@ -1396,6 +1494,7 @@
2.654 store_reg( R_ECX, Rn );
2.655 load_spreg( R_EAX, R_SGR );
2.656 MEM_WRITE_LONG( R_ECX, R_EAX );
2.657 + sh4_x86.tstate = TSTATE_NONE;
2.658 }
2.659 break;
2.660 case 0x5:
2.661 @@ -1408,6 +1507,7 @@
2.662 store_reg( R_ECX, Rn );
2.663 load_spreg( R_EAX, R_FPUL );
2.664 MEM_WRITE_LONG( R_ECX, R_EAX );
2.665 + sh4_x86.tstate = TSTATE_NONE;
2.666 }
2.667 break;
2.668 case 0x6:
2.669 @@ -1420,6 +1520,7 @@
2.670 store_reg( R_ECX, Rn );
2.671 load_spreg( R_EAX, R_FPSCR );
2.672 MEM_WRITE_LONG( R_ECX, R_EAX );
2.673 + sh4_x86.tstate = TSTATE_NONE;
2.674 }
2.675 break;
2.676 case 0xF:
2.677 @@ -1433,6 +1534,7 @@
2.678 store_reg( R_ECX, Rn );
2.679 load_spreg( R_EAX, R_DBR );
2.680 MEM_WRITE_LONG( R_ECX, R_EAX );
2.681 + sh4_x86.tstate = TSTATE_NONE;
2.682 }
2.683 break;
2.684 default:
2.685 @@ -1455,6 +1557,7 @@
2.686 ADD_imm8s_r32( -4, R_ECX );
2.687 store_reg( R_ECX, Rn );
2.688 MEM_WRITE_LONG( R_ECX, R_EAX );
2.689 + sh4_x86.tstate = TSTATE_NONE;
2.690 }
2.691 break;
2.692 case 0x1:
2.693 @@ -1467,6 +1570,7 @@
2.694 store_reg( R_ECX, Rn );
2.695 load_spreg( R_EAX, R_GBR );
2.696 MEM_WRITE_LONG( R_ECX, R_EAX );
2.697 + sh4_x86.tstate = TSTATE_NONE;
2.698 }
2.699 break;
2.700 case 0x2:
2.701 @@ -1480,6 +1584,7 @@
2.702 store_reg( R_ECX, Rn );
2.703 load_spreg( R_EAX, R_VBR );
2.704 MEM_WRITE_LONG( R_ECX, R_EAX );
2.705 + sh4_x86.tstate = TSTATE_NONE;
2.706 }
2.707 break;
2.708 case 0x3:
2.709 @@ -1493,6 +1598,7 @@
2.710 store_reg( R_ECX, Rn );
2.711 load_spreg( R_EAX, R_SSR );
2.712 MEM_WRITE_LONG( R_ECX, R_EAX );
2.713 + sh4_x86.tstate = TSTATE_NONE;
2.714 }
2.715 break;
2.716 case 0x4:
2.717 @@ -1506,6 +1612,7 @@
2.718 store_reg( R_ECX, Rn );
2.719 load_spreg( R_EAX, R_SPC );
2.720 MEM_WRITE_LONG( R_ECX, R_EAX );
2.721 + sh4_x86.tstate = TSTATE_NONE;
2.722 }
2.723 break;
2.724 default:
2.725 @@ -1524,6 +1631,7 @@
2.726 store_reg( R_ECX, Rn );
2.727 load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
2.728 MEM_WRITE_LONG( R_ECX, R_EAX );
2.729 + sh4_x86.tstate = TSTATE_NONE;
2.730 }
2.731 break;
2.732 }
2.733 @@ -1537,16 +1645,20 @@
2.734 ROL1_r32( R_EAX );
2.735 store_reg( R_EAX, Rn );
2.736 SETC_t();
2.737 + sh4_x86.tstate = TSTATE_C;
2.738 }
2.739 break;
2.740 case 0x2:
2.741 { /* ROTCL Rn */
2.742 uint32_t Rn = ((ir>>8)&0xF);
2.743 load_reg( R_EAX, Rn );
2.744 - LDC_t();
2.745 + if( sh4_x86.tstate != TSTATE_C ) {
2.746 + LDC_t();
2.747 + }
2.748 RCL1_r32( R_EAX );
2.749 store_reg( R_EAX, Rn );
2.750 SETC_t();
2.751 + sh4_x86.tstate = TSTATE_C;
2.752 }
2.753 break;
2.754 default:
2.755 @@ -1563,6 +1675,7 @@
2.756 ROR1_r32( R_EAX );
2.757 store_reg( R_EAX, Rn );
2.758 SETC_t();
2.759 + sh4_x86.tstate = TSTATE_C;
2.760 }
2.761 break;
2.762 case 0x1:
2.763 @@ -1571,16 +1684,20 @@
2.764 load_reg( R_EAX, Rn );
2.765 CMP_imm8s_r32( 0, R_EAX );
2.766 SETG_t();
2.767 + sh4_x86.tstate = TSTATE_G;
2.768 }
2.769 break;
2.770 case 0x2:
2.771 { /* ROTCR Rn */
2.772 uint32_t Rn = ((ir>>8)&0xF);
2.773 load_reg( R_EAX, Rn );
2.774 - LDC_t();
2.775 + if( sh4_x86.tstate != TSTATE_C ) {
2.776 + LDC_t();
2.777 + }
2.778 RCR1_r32( R_EAX );
2.779 store_reg( R_EAX, Rn );
2.780 SETC_t();
2.781 + sh4_x86.tstate = TSTATE_C;
2.782 }
2.783 break;
2.784 default:
2.785 @@ -1601,6 +1718,7 @@
2.786 store_reg( R_EAX, Rm );
2.787 MEM_READ_LONG( R_ECX, R_EAX );
2.788 store_spreg( R_EAX, R_MACH );
2.789 + sh4_x86.tstate = TSTATE_NONE;
2.790 }
2.791 break;
2.792 case 0x1:
2.793 @@ -1614,6 +1732,7 @@
2.794 store_reg( R_EAX, Rm );
2.795 MEM_READ_LONG( R_ECX, R_EAX );
2.796 store_spreg( R_EAX, R_MACL );
2.797 + sh4_x86.tstate = TSTATE_NONE;
2.798 }
2.799 break;
2.800 case 0x2:
2.801 @@ -1627,6 +1746,7 @@
2.802 store_reg( R_EAX, Rm );
2.803 MEM_READ_LONG( R_ECX, R_EAX );
2.804 store_spreg( R_EAX, R_PR );
2.805 + sh4_x86.tstate = TSTATE_NONE;
2.806 }
2.807 break;
2.808 case 0x3:
2.809 @@ -1641,6 +1761,7 @@
2.810 store_reg( R_EAX, Rm );
2.811 MEM_READ_LONG( R_ECX, R_EAX );
2.812 store_spreg( R_EAX, R_SGR );
2.813 + sh4_x86.tstate = TSTATE_NONE;
2.814 }
2.815 break;
2.816 case 0x5:
2.817 @@ -1654,6 +1775,7 @@
2.818 store_reg( R_EAX, Rm );
2.819 MEM_READ_LONG( R_ECX, R_EAX );
2.820 store_spreg( R_EAX, R_FPUL );
2.821 + sh4_x86.tstate = TSTATE_NONE;
2.822 }
2.823 break;
2.824 case 0x6:
2.825 @@ -1668,6 +1790,7 @@
2.826 MEM_READ_LONG( R_ECX, R_EAX );
2.827 store_spreg( R_EAX, R_FPSCR );
2.828 update_fr_bank( R_EAX );
2.829 + sh4_x86.tstate = TSTATE_NONE;
2.830 }
2.831 break;
2.832 case 0xF:
2.833 @@ -1682,6 +1805,7 @@
2.834 store_reg( R_EAX, Rm );
2.835 MEM_READ_LONG( R_ECX, R_EAX );
2.836 store_spreg( R_EAX, R_DBR );
2.837 + sh4_x86.tstate = TSTATE_NONE;
2.838 }
2.839 break;
2.840 default:
2.841 @@ -1710,6 +1834,7 @@
2.842 call_func1( sh4_write_sr, R_EAX );
2.843 sh4_x86.priv_checked = FALSE;
2.844 sh4_x86.fpuen_checked = FALSE;
2.845 + sh4_x86.tstate = TSTATE_NONE;
2.846 }
2.847 }
2.848 break;
2.849 @@ -1724,6 +1849,7 @@
2.850 store_reg( R_EAX, Rm );
2.851 MEM_READ_LONG( R_ECX, R_EAX );
2.852 store_spreg( R_EAX, R_GBR );
2.853 + sh4_x86.tstate = TSTATE_NONE;
2.854 }
2.855 break;
2.856 case 0x2:
2.857 @@ -1738,6 +1864,7 @@
2.858 store_reg( R_EAX, Rm );
2.859 MEM_READ_LONG( R_ECX, R_EAX );
2.860 store_spreg( R_EAX, R_VBR );
2.861 + sh4_x86.tstate = TSTATE_NONE;
2.862 }
2.863 break;
2.864 case 0x3:
2.865 @@ -1752,6 +1879,7 @@
2.866 store_reg( R_EAX, Rm );
2.867 MEM_READ_LONG( R_ECX, R_EAX );
2.868 store_spreg( R_EAX, R_SSR );
2.869 + sh4_x86.tstate = TSTATE_NONE;
2.870 }
2.871 break;
2.872 case 0x4:
2.873 @@ -1766,6 +1894,7 @@
2.874 store_reg( R_EAX, Rm );
2.875 MEM_READ_LONG( R_ECX, R_EAX );
2.876 store_spreg( R_EAX, R_SPC );
2.877 + sh4_x86.tstate = TSTATE_NONE;
2.878 }
2.879 break;
2.880 default:
2.881 @@ -1785,6 +1914,7 @@
2.882 store_reg( R_EAX, Rm );
2.883 MEM_READ_LONG( R_ECX, R_EAX );
2.884 store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
2.885 + sh4_x86.tstate = TSTATE_NONE;
2.886 }
2.887 break;
2.888 }
2.889 @@ -1797,6 +1927,7 @@
2.890 load_reg( R_EAX, Rn );
2.891 SHL_imm8_r32( 2, R_EAX );
2.892 store_reg( R_EAX, Rn );
2.893 + sh4_x86.tstate = TSTATE_NONE;
2.894 }
2.895 break;
2.896 case 0x1:
2.897 @@ -1805,6 +1936,7 @@
2.898 load_reg( R_EAX, Rn );
2.899 SHL_imm8_r32( 8, R_EAX );
2.900 store_reg( R_EAX, Rn );
2.901 + sh4_x86.tstate = TSTATE_NONE;
2.902 }
2.903 break;
2.904 case 0x2:
2.905 @@ -1813,6 +1945,7 @@
2.906 load_reg( R_EAX, Rn );
2.907 SHL_imm8_r32( 16, R_EAX );
2.908 store_reg( R_EAX, Rn );
2.909 + sh4_x86.tstate = TSTATE_NONE;
2.910 }
2.911 break;
2.912 default:
2.913 @@ -1828,6 +1961,7 @@
2.914 load_reg( R_EAX, Rn );
2.915 SHR_imm8_r32( 2, R_EAX );
2.916 store_reg( R_EAX, Rn );
2.917 + sh4_x86.tstate = TSTATE_NONE;
2.918 }
2.919 break;
2.920 case 0x1:
2.921 @@ -1836,6 +1970,7 @@
2.922 load_reg( R_EAX, Rn );
2.923 SHR_imm8_r32( 8, R_EAX );
2.924 store_reg( R_EAX, Rn );
2.925 + sh4_x86.tstate = TSTATE_NONE;
2.926 }
2.927 break;
2.928 case 0x2:
2.929 @@ -1844,6 +1979,7 @@
2.930 load_reg( R_EAX, Rn );
2.931 SHR_imm8_r32( 16, R_EAX );
2.932 store_reg( R_EAX, Rn );
2.933 + sh4_x86.tstate = TSTATE_NONE;
2.934 }
2.935 break;
2.936 default:
2.937 @@ -1880,6 +2016,7 @@
2.938 check_priv();
2.939 load_reg( R_EAX, Rm );
2.940 store_spreg( R_EAX, R_SGR );
2.941 + sh4_x86.tstate = TSTATE_NONE;
2.942 }
2.943 break;
2.944 case 0x5:
2.945 @@ -1895,6 +2032,7 @@
2.946 load_reg( R_EAX, Rm );
2.947 store_spreg( R_EAX, R_FPSCR );
2.948 update_fr_bank( R_EAX );
2.949 + sh4_x86.tstate = TSTATE_NONE;
2.950 }
2.951 break;
2.952 case 0xF:
2.953 @@ -1903,6 +2041,7 @@
2.954 check_priv();
2.955 load_reg( R_EAX, Rm );
2.956 store_spreg( R_EAX, R_DBR );
2.957 + sh4_x86.tstate = TSTATE_NONE;
2.958 }
2.959 break;
2.960 default:
2.961 @@ -1940,6 +2079,7 @@
2.962 OR_imm8_r8( 0x80, R_AL );
2.963 load_reg( R_ECX, Rn );
2.964 MEM_WRITE_BYTE( R_ECX, R_EAX );
2.965 + sh4_x86.tstate = TSTATE_NONE;
2.966 }
2.967 break;
2.968 case 0x2:
2.969 @@ -1988,6 +2128,7 @@
2.970 JMP_TARGET(end);
2.971 JMP_TARGET(end2);
2.972 store_reg( R_EAX, Rn );
2.973 + sh4_x86.tstate = TSTATE_NONE;
2.974 }
2.975 break;
2.976 case 0xD:
2.977 @@ -2014,6 +2155,7 @@
2.978 JMP_TARGET(end);
2.979 JMP_TARGET(end2);
2.980 store_reg( R_EAX, Rn );
2.981 + sh4_x86.tstate = TSTATE_NONE;
2.982 }
2.983 break;
2.984 case 0xE:
2.985 @@ -2031,6 +2173,7 @@
2.986 call_func1( sh4_write_sr, R_EAX );
2.987 sh4_x86.priv_checked = FALSE;
2.988 sh4_x86.fpuen_checked = FALSE;
2.989 + sh4_x86.tstate = TSTATE_NONE;
2.990 }
2.991 }
2.992 break;
2.993 @@ -2047,6 +2190,7 @@
2.994 check_priv();
2.995 load_reg( R_EAX, Rm );
2.996 store_spreg( R_EAX, R_VBR );
2.997 + sh4_x86.tstate = TSTATE_NONE;
2.998 }
2.999 break;
2.1000 case 0x3:
2.1001 @@ -2055,6 +2199,7 @@
2.1002 check_priv();
2.1003 load_reg( R_EAX, Rm );
2.1004 store_spreg( R_EAX, R_SSR );
2.1005 + sh4_x86.tstate = TSTATE_NONE;
2.1006 }
2.1007 break;
2.1008 case 0x4:
2.1009 @@ -2063,6 +2208,7 @@
2.1010 check_priv();
2.1011 load_reg( R_EAX, Rm );
2.1012 store_spreg( R_EAX, R_SPC );
2.1013 + sh4_x86.tstate = TSTATE_NONE;
2.1014 }
2.1015 break;
2.1016 default:
2.1017 @@ -2076,6 +2222,7 @@
2.1018 check_priv();
2.1019 load_reg( R_EAX, Rm );
2.1020 store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
2.1021 + sh4_x86.tstate = TSTATE_NONE;
2.1022 }
2.1023 break;
2.1024 }
2.1025 @@ -2121,6 +2268,7 @@
2.1026 JMP_TARGET(end);
2.1027 JMP_TARGET(end2);
2.1028 JMP_TARGET(end3);
2.1029 + sh4_x86.tstate = TSTATE_NONE;
2.1030 }
2.1031 break;
2.1032 }
2.1033 @@ -2134,6 +2282,7 @@
2.1034 check_ralign32( R_ECX );
2.1035 MEM_READ_LONG( R_ECX, R_EAX );
2.1036 store_reg( R_EAX, Rn );
2.1037 + sh4_x86.tstate = TSTATE_NONE;
2.1038 }
2.1039 break;
2.1040 case 0x6:
2.1041 @@ -2144,6 +2293,7 @@
2.1042 load_reg( R_ECX, Rm );
2.1043 MEM_READ_BYTE( R_ECX, R_EAX );
2.1044 store_reg( R_EAX, Rn );
2.1045 + sh4_x86.tstate = TSTATE_NONE;
2.1046 }
2.1047 break;
2.1048 case 0x1:
2.1049 @@ -2154,6 +2304,7 @@
2.1050 check_ralign16( R_ECX );
2.1051 MEM_READ_WORD( R_ECX, R_EAX );
2.1052 store_reg( R_EAX, Rn );
2.1053 + sh4_x86.tstate = TSTATE_NONE;
2.1054 }
2.1055 break;
2.1056 case 0x2:
2.1057 @@ -2164,6 +2315,7 @@
2.1058 check_ralign32( R_ECX );
2.1059 MEM_READ_LONG( R_ECX, R_EAX );
2.1060 store_reg( R_EAX, Rn );
2.1061 + sh4_x86.tstate = TSTATE_NONE;
2.1062 }
2.1063 break;
2.1064 case 0x3:
2.1065 @@ -2182,6 +2334,7 @@
2.1066 store_reg( R_EAX, Rm );
2.1067 MEM_READ_BYTE( R_ECX, R_EAX );
2.1068 store_reg( R_EAX, Rn );
2.1069 + sh4_x86.tstate = TSTATE_NONE;
2.1070 }
2.1071 break;
2.1072 case 0x5:
2.1073 @@ -2195,6 +2348,7 @@
2.1074 store_reg( R_EAX, Rm );
2.1075 MEM_READ_WORD( R_ECX, R_EAX );
2.1076 store_reg( R_EAX, Rn );
2.1077 + sh4_x86.tstate = TSTATE_NONE;
2.1078 }
2.1079 break;
2.1080 case 0x6:
2.1081 @@ -2208,6 +2362,7 @@
2.1082 store_reg( R_EAX, Rm );
2.1083 MEM_READ_LONG( R_ECX, R_EAX );
2.1084 store_reg( R_EAX, Rn );
2.1085 + sh4_x86.tstate = TSTATE_NONE;
2.1086 }
2.1087 break;
2.1088 case 0x7:
2.1089 @@ -2216,6 +2371,7 @@
2.1090 load_reg( R_EAX, Rm );
2.1091 NOT_r32( R_EAX );
2.1092 store_reg( R_EAX, Rn );
2.1093 + sh4_x86.tstate = TSTATE_NONE;
2.1094 }
2.1095 break;
2.1096 case 0x8:
2.1097 @@ -2235,6 +2391,7 @@
2.1098 SHR_imm8_r32( 16, R_EAX );
2.1099 OR_r32_r32( R_EAX, R_ECX );
2.1100 store_reg( R_ECX, Rn );
2.1101 + sh4_x86.tstate = TSTATE_NONE;
2.1102 }
2.1103 break;
2.1104 case 0xA:
2.1105 @@ -2246,6 +2403,7 @@
2.1106 SBB_r32_r32( R_EAX, R_ECX );
2.1107 store_reg( R_ECX, Rn );
2.1108 SETC_t();
2.1109 + sh4_x86.tstate = TSTATE_C;
2.1110 }
2.1111 break;
2.1112 case 0xB:
2.1113 @@ -2254,6 +2412,7 @@
2.1114 load_reg( R_EAX, Rm );
2.1115 NEG_r32( R_EAX );
2.1116 store_reg( R_EAX, Rn );
2.1117 + sh4_x86.tstate = TSTATE_NONE;
2.1118 }
2.1119 break;
2.1120 case 0xC:
2.1121 @@ -2296,6 +2455,7 @@
2.1122 load_reg( R_EAX, Rn );
2.1123 ADD_imm8s_r32( imm, R_EAX );
2.1124 store_reg( R_EAX, Rn );
2.1125 + sh4_x86.tstate = TSTATE_NONE;
2.1126 }
2.1127 break;
2.1128 case 0x8:
2.1129 @@ -2307,6 +2467,7 @@
2.1130 load_reg( R_ECX, Rn );
2.1131 ADD_imm32_r32( disp, R_ECX );
2.1132 MEM_WRITE_BYTE( R_ECX, R_EAX );
2.1133 + sh4_x86.tstate = TSTATE_NONE;
2.1134 }
2.1135 break;
2.1136 case 0x1:
2.1137 @@ -2318,6 +2479,7 @@
2.1138 precheck();
2.1139 check_walign16( R_ECX );
2.1140 MEM_WRITE_WORD( R_ECX, R_EAX );
2.1141 + sh4_x86.tstate = TSTATE_NONE;
2.1142 }
2.1143 break;
2.1144 case 0x4:
2.1145 @@ -2327,6 +2489,7 @@
2.1146 ADD_imm32_r32( disp, R_ECX );
2.1147 MEM_READ_BYTE( R_ECX, R_EAX );
2.1148 store_reg( R_EAX, 0 );
2.1149 + sh4_x86.tstate = TSTATE_NONE;
2.1150 }
2.1151 break;
2.1152 case 0x5:
2.1153 @@ -2338,6 +2501,7 @@
2.1154 check_ralign16( R_ECX );
2.1155 MEM_READ_WORD( R_ECX, R_EAX );
2.1156 store_reg( R_EAX, 0 );
2.1157 + sh4_x86.tstate = TSTATE_NONE;
2.1158 }
2.1159 break;
2.1160 case 0x8:
2.1161 @@ -2346,6 +2510,7 @@
2.1162 load_reg( R_EAX, 0 );
2.1163 CMP_imm8s_r32(imm, R_EAX);
2.1164 SETE_t();
2.1165 + sh4_x86.tstate = TSTATE_E;
2.1166 }
2.1167 break;
2.1168 case 0x9:
2.1169 @@ -2354,8 +2519,7 @@
2.1170 if( sh4_x86.in_delay_slot ) {
2.1171 SLOTILLEGAL();
2.1172 } else {
2.1173 - CMP_imm8s_sh4r( 0, R_T );
2.1174 - JE_rel8( 29, nottaken );
2.1175 + JF_rel8( 29, nottaken );
2.1176 exit_block( disp + pc + 4, pc+2 );
2.1177 JMP_TARGET(nottaken);
2.1178 return 2;
2.1179 @@ -2368,8 +2532,7 @@
2.1180 if( sh4_x86.in_delay_slot ) {
2.1181 SLOTILLEGAL();
2.1182 } else {
2.1183 - CMP_imm8s_sh4r( 0, R_T );
2.1184 - JNE_rel8( 29, nottaken );
2.1185 + JT_rel8( 29, nottaken );
2.1186 exit_block( disp + pc + 4, pc+2 );
2.1187 JMP_TARGET(nottaken);
2.1188 return 2;
2.1189 @@ -2383,8 +2546,11 @@
2.1190 SLOTILLEGAL();
2.1191 } else {
2.1192 sh4_x86.in_delay_slot = TRUE;
2.1193 - CMP_imm8s_sh4r( 0, R_T );
2.1194 - OP(0x0F); OP(0x84); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
2.1195 + if( sh4_x86.tstate == TSTATE_NONE ) {
2.1196 + CMP_imm8s_sh4r( 1, R_T );
2.1197 + sh4_x86.tstate = TSTATE_E;
2.1198 + }
2.1199 + OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
2.1200 sh4_x86_translate_instruction(pc+2);
2.1201 exit_block( disp + pc + 4, pc+4 );
2.1202 // not taken
2.1203 @@ -2401,8 +2567,11 @@
2.1204 SLOTILLEGAL();
2.1205 } else {
2.1206 sh4_x86.in_delay_slot = TRUE;
2.1207 - CMP_imm8s_sh4r( 0, R_T );
2.1208 - OP(0x0F); OP(0x85); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32
2.1209 + if( sh4_x86.tstate == TSTATE_NONE ) {
2.1210 + CMP_imm8s_sh4r( 1, R_T );
2.1211 + sh4_x86.tstate = TSTATE_E;
2.1212 + }
2.1213 + OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32
2.1214 sh4_x86_translate_instruction(pc+2);
2.1215 exit_block( disp + pc + 4, pc+4 );
2.1216 // not taken
2.1217 @@ -2426,6 +2595,7 @@
2.1218 load_imm32( R_ECX, pc + disp + 4 );
2.1219 MEM_READ_WORD( R_ECX, R_EAX );
2.1220 store_reg( R_EAX, Rn );
2.1221 + sh4_x86.tstate = TSTATE_NONE;
2.1222 }
2.1223 }
2.1224 break;
2.1225 @@ -2468,6 +2638,7 @@
2.1226 load_spreg( R_ECX, R_GBR );
2.1227 ADD_imm32_r32( disp, R_ECX );
2.1228 MEM_WRITE_BYTE( R_ECX, R_EAX );
2.1229 + sh4_x86.tstate = TSTATE_NONE;
2.1230 }
2.1231 break;
2.1232 case 0x1:
2.1233 @@ -2479,6 +2650,7 @@
2.1234 precheck();
2.1235 check_walign16( R_ECX );
2.1236 MEM_WRITE_WORD( R_ECX, R_EAX );
2.1237 + sh4_x86.tstate = TSTATE_NONE;
2.1238 }
2.1239 break;
2.1240 case 0x2:
2.1241 @@ -2490,6 +2662,7 @@
2.1242 precheck();
2.1243 check_walign32( R_ECX );
2.1244 MEM_WRITE_LONG( R_ECX, R_EAX );
2.1245 + sh4_x86.tstate = TSTATE_NONE;
2.1246 }
2.1247 break;
2.1248 case 0x3:
2.1249 @@ -2501,6 +2674,7 @@
2.1250 PUSH_imm32( imm );
2.1251 call_func0( sh4_raise_trap );
2.1252 ADD_imm8s_r32( 4, R_ESP );
2.1253 + sh4_x86.tstate = TSTATE_NONE;
2.1254 exit_block_pcset(pc);
2.1255 sh4_x86.branch_taken = TRUE;
2.1256 return 2;
2.1257 @@ -2514,6 +2688,7 @@
2.1258 ADD_imm32_r32( disp, R_ECX );
2.1259 MEM_READ_BYTE( R_ECX, R_EAX );
2.1260 store_reg( R_EAX, 0 );
2.1261 + sh4_x86.tstate = TSTATE_NONE;
2.1262 }
2.1263 break;
2.1264 case 0x5:
2.1265 @@ -2525,6 +2700,7 @@
2.1266 check_ralign16( R_ECX );
2.1267 MEM_READ_WORD( R_ECX, R_EAX );
2.1268 store_reg( R_EAX, 0 );
2.1269 + sh4_x86.tstate = TSTATE_NONE;
2.1270 }
2.1271 break;
2.1272 case 0x6:
2.1273 @@ -2536,6 +2712,7 @@
2.1274 check_ralign32( R_ECX );
2.1275 MEM_READ_LONG( R_ECX, R_EAX );
2.1276 store_reg( R_EAX, 0 );
2.1277 + sh4_x86.tstate = TSTATE_NONE;
2.1278 }
2.1279 break;
2.1280 case 0x7:
2.1281 @@ -2555,6 +2732,7 @@
2.1282 load_reg( R_EAX, 0 );
2.1283 TEST_imm32_r32( imm, R_EAX );
2.1284 SETE_t();
2.1285 + sh4_x86.tstate = TSTATE_E;
2.1286 }
2.1287 break;
2.1288 case 0x9:
2.1289 @@ -2563,6 +2741,7 @@
2.1290 load_reg( R_EAX, 0 );
2.1291 AND_imm32_r32(imm, R_EAX);
2.1292 store_reg( R_EAX, 0 );
2.1293 + sh4_x86.tstate = TSTATE_NONE;
2.1294 }
2.1295 break;
2.1296 case 0xA:
2.1297 @@ -2571,6 +2750,7 @@
2.1298 load_reg( R_EAX, 0 );
2.1299 XOR_imm32_r32( imm, R_EAX );
2.1300 store_reg( R_EAX, 0 );
2.1301 + sh4_x86.tstate = TSTATE_NONE;
2.1302 }
2.1303 break;
2.1304 case 0xB:
2.1305 @@ -2579,6 +2759,7 @@
2.1306 load_reg( R_EAX, 0 );
2.1307 OR_imm32_r32(imm, R_EAX);
2.1308 store_reg( R_EAX, 0 );
2.1309 + sh4_x86.tstate = TSTATE_NONE;
2.1310 }
2.1311 break;
2.1312 case 0xC:
2.1313 @@ -2590,6 +2771,7 @@
2.1314 MEM_READ_BYTE( R_ECX, R_EAX );
2.1315 TEST_imm8_r8( imm, R_AL );
2.1316 SETE_t();
2.1317 + sh4_x86.tstate = TSTATE_E;
2.1318 }
2.1319 break;
2.1320 case 0xD:
2.1321 @@ -2603,6 +2785,7 @@
2.1322 POP_r32(R_ECX);
2.1323 AND_imm32_r32(imm, R_EAX );
2.1324 MEM_WRITE_BYTE( R_ECX, R_EAX );
2.1325 + sh4_x86.tstate = TSTATE_NONE;
2.1326 }
2.1327 break;
2.1328 case 0xE:
2.1329 @@ -2616,6 +2799,7 @@
2.1330 POP_r32(R_ECX);
2.1331 XOR_imm32_r32( imm, R_EAX );
2.1332 MEM_WRITE_BYTE( R_ECX, R_EAX );
2.1333 + sh4_x86.tstate = TSTATE_NONE;
2.1334 }
2.1335 break;
2.1336 case 0xF:
2.1337 @@ -2629,6 +2813,7 @@
2.1338 POP_r32(R_ECX);
2.1339 OR_imm32_r32(imm, R_EAX );
2.1340 MEM_WRITE_BYTE( R_ECX, R_EAX );
2.1341 + sh4_x86.tstate = TSTATE_NONE;
2.1342 }
2.1343 break;
2.1344 }
2.1345 @@ -2648,6 +2833,7 @@
2.1346 MEM_READ_LONG( R_ECX, R_EAX );
2.1347 }
2.1348 store_reg( R_EAX, Rn );
2.1349 + sh4_x86.tstate = TSTATE_NONE;
2.1350 }
2.1351 }
2.1352 break;
2.1353 @@ -2679,6 +2865,7 @@
2.1354 FADDP_st(1);
2.1355 pop_dr(R_EDX, FRn);
2.1356 JMP_TARGET(end);
2.1357 + sh4_x86.tstate = TSTATE_NONE;
2.1358 }
2.1359 break;
2.1360 case 0x1:
2.1361 @@ -2700,6 +2887,7 @@
2.1362 FSUBP_st(1);
2.1363 pop_dr(R_EDX, FRn);
2.1364 JMP_TARGET(end);
2.1365 + sh4_x86.tstate = TSTATE_NONE;
2.1366 }
2.1367 break;
2.1368 case 0x2:
2.1369 @@ -2721,6 +2909,7 @@
2.1370 FMULP_st(1);
2.1371 pop_dr(R_EDX, FRn);
2.1372 JMP_TARGET(end);
2.1373 + sh4_x86.tstate = TSTATE_NONE;
2.1374 }
2.1375 break;
2.1376 case 0x3:
2.1377 @@ -2742,6 +2931,7 @@
2.1378 FDIVP_st(1);
2.1379 pop_dr(R_EDX, FRn);
2.1380 JMP_TARGET(end);
2.1381 + sh4_x86.tstate = TSTATE_NONE;
2.1382 }
2.1383 break;
2.1384 case 0x4:
2.1385 @@ -2762,6 +2952,7 @@
2.1386 FCOMIP_st(1);
2.1387 SETE_t();
2.1388 FPOP_st();
2.1389 + sh4_x86.tstate = TSTATE_NONE;
2.1390 }
2.1391 break;
2.1392 case 0x5:
2.1393 @@ -2782,6 +2973,7 @@
2.1394 FCOMIP_st(1);
2.1395 SETA_t();
2.1396 FPOP_st();
2.1397 + sh4_x86.tstate = TSTATE_NONE;
2.1398 }
2.1399 break;
2.1400 case 0x6:
2.1401 @@ -2816,6 +3008,7 @@
2.1402 store_fr( R_EDX, R_ECX, FRn|0x01 );
2.1403 JMP_TARGET(end);
2.1404 }
2.1405 + sh4_x86.tstate = TSTATE_NONE;
2.1406 }
2.1407 break;
2.1408 case 0x7:
2.1409 @@ -2849,6 +3042,7 @@
2.1410 MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
2.1411 JMP_TARGET(end);
2.1412 }
2.1413 + sh4_x86.tstate = TSTATE_NONE;
2.1414 }
2.1415 break;
2.1416 case 0x8:
2.1417 @@ -2882,6 +3076,7 @@
2.1418 store_fr( R_EDX, R_ECX, FRn|0x01 );
2.1419 JMP_TARGET(end);
2.1420 }
2.1421 + sh4_x86.tstate = TSTATE_NONE;
2.1422 }
2.1423 break;
2.1424 case 0x9:
2.1425 @@ -2921,6 +3116,7 @@
2.1426 store_fr( R_EDX, R_ECX, FRn|0x01 );
2.1427 JMP_TARGET(end);
2.1428 }
2.1429 + sh4_x86.tstate = TSTATE_NONE;
2.1430 }
2.1431 break;
2.1432 case 0xA:
2.1433 @@ -2953,6 +3149,7 @@
2.1434 MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
2.1435 JMP_TARGET(end);
2.1436 }
2.1437 + sh4_x86.tstate = TSTATE_NONE;
2.1438 }
2.1439 break;
2.1440 case 0xB:
2.1441 @@ -2991,6 +3188,7 @@
2.1442 MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
2.1443 JMP_TARGET(end);
2.1444 }
2.1445 + sh4_x86.tstate = TSTATE_NONE;
2.1446 }
2.1447 break;
2.1448 case 0xC:
2.1449 @@ -3043,6 +3241,7 @@
2.1450 JMP_TARGET(end);
2.1451 }
2.1452 }
2.1453 + sh4_x86.tstate = TSTATE_NONE;
2.1454 }
2.1455 break;
2.1456 case 0xD:
2.1457 @@ -3054,6 +3253,7 @@
2.1458 load_fr_bank( R_ECX );
2.1459 load_spreg( R_EAX, R_FPUL );
2.1460 store_fr( R_ECX, R_EAX, FRn );
2.1461 + sh4_x86.tstate = TSTATE_NONE;
2.1462 }
2.1463 break;
2.1464 case 0x1:
2.1465 @@ -3063,6 +3263,7 @@
2.1466 load_fr_bank( R_ECX );
2.1467 load_fr( R_ECX, R_EAX, FRm );
2.1468 store_spreg( R_EAX, R_FPUL );
2.1469 + sh4_x86.tstate = TSTATE_NONE;
2.1470 }
2.1471 break;
2.1472 case 0x2:
2.1473 @@ -3079,6 +3280,7 @@
2.1474 JMP_TARGET(doubleprec);
2.1475 pop_dr( R_EDX, FRn );
2.1476 JMP_TARGET(end);
2.1477 + sh4_x86.tstate = TSTATE_NONE;
2.1478 }
2.1479 break;
2.1480 case 0x3:
2.1481 @@ -3116,6 +3318,7 @@
2.1482 store_spreg( R_ECX, R_FPUL );
2.1483 FPOP_st();
2.1484 JMP_TARGET(end);
2.1485 + sh4_x86.tstate = TSTATE_NONE;
2.1486 }
2.1487 break;
2.1488 case 0x4:
2.1489 @@ -3135,6 +3338,7 @@
2.1490 FCHS_st0();
2.1491 pop_dr(R_EDX, FRn);
2.1492 JMP_TARGET(end);
2.1493 + sh4_x86.tstate = TSTATE_NONE;
2.1494 }
2.1495 break;
2.1496 case 0x5:
2.1497 @@ -3154,6 +3358,7 @@
2.1498 FABS_st0();
2.1499 pop_dr(R_EDX, FRn);
2.1500 JMP_TARGET(end);
2.1501 + sh4_x86.tstate = TSTATE_NONE;
2.1502 }
2.1503 break;
2.1504 case 0x6:
2.1505 @@ -3173,6 +3378,7 @@
2.1506 FSQRT_st0();
2.1507 pop_dr(R_EDX, FRn);
2.1508 JMP_TARGET(end);
2.1509 + sh4_x86.tstate = TSTATE_NONE;
2.1510 }
2.1511 break;
2.1512 case 0x7:
2.1513 @@ -3189,6 +3395,7 @@
2.1514 FDIVP_st(1);
2.1515 pop_fr(R_EDX, FRn);
2.1516 JMP_TARGET(end);
2.1517 + sh4_x86.tstate = TSTATE_NONE;
2.1518 }
2.1519 break;
2.1520 case 0x8:
2.1521 @@ -3203,6 +3410,7 @@
2.1522 load_spreg( R_ECX, REG_OFFSET(fr_bank) );
2.1523 store_fr( R_ECX, R_EAX, FRn );
2.1524 JMP_TARGET(end);
2.1525 + sh4_x86.tstate = TSTATE_NONE;
2.1526 }
2.1527 break;
2.1528 case 0x9:
2.1529 @@ -3217,6 +3425,7 @@
2.1530 load_spreg( R_ECX, REG_OFFSET(fr_bank) );
2.1531 store_fr( R_ECX, R_EAX, FRn );
2.1532 JMP_TARGET(end);
2.1533 + sh4_x86.tstate = TSTATE_NONE;
2.1534 }
2.1535 break;
2.1536 case 0xA:
2.1537 @@ -3230,6 +3439,7 @@
2.1538 push_fpul();
2.1539 pop_dr( R_ECX, FRn );
2.1540 JMP_TARGET(end);
2.1541 + sh4_x86.tstate = TSTATE_NONE;
2.1542 }
2.1543 break;
2.1544 case 0xB:
2.1545 @@ -3243,6 +3453,7 @@
2.1546 push_dr( R_ECX, FRm );
2.1547 pop_fpul();
2.1548 JMP_TARGET(end);
2.1549 + sh4_x86.tstate = TSTATE_NONE;
2.1550 }
2.1551 break;
2.1552 case 0xE:
2.1553 @@ -3271,6 +3482,7 @@
2.1554 FADDP_st(1);
2.1555 pop_fr( R_ECX, (FVn<<2)+3);
2.1556 JMP_TARGET(doubleprec);
2.1557 + sh4_x86.tstate = TSTATE_NONE;
2.1558 }
2.1559 break;
2.1560 case 0xF:
2.1561 @@ -3287,6 +3499,7 @@
2.1562 load_spreg( R_EDX, R_FPUL );
2.1563 call_func2( sh4_fsca, R_EDX, R_ECX );
2.1564 JMP_TARGET(doubleprec);
2.1565 + sh4_x86.tstate = TSTATE_NONE;
2.1566 }
2.1567 break;
2.1568 case 0x1:
2.1569 @@ -3303,6 +3516,7 @@
2.1570 load_xf_bank( R_ECX ); // 12
2.1571 call_func2( sh4_ftrv, R_EDX, R_ECX ); // 12
2.1572 JMP_TARGET(doubleprec);
2.1573 + sh4_x86.tstate = TSTATE_NONE;
2.1574 }
2.1575 break;
2.1576 case 0x1:
2.1577 @@ -3313,6 +3527,7 @@
2.1578 load_spreg( R_ECX, R_FPSCR );
2.1579 XOR_imm32_r32( FPSCR_SZ, R_ECX );
2.1580 store_spreg( R_ECX, R_FPSCR );
2.1581 + sh4_x86.tstate = TSTATE_NONE;
2.1582 }
2.1583 break;
2.1584 case 0x2:
2.1585 @@ -3322,6 +3537,7 @@
2.1586 XOR_imm32_r32( FPSCR_FR, R_ECX );
2.1587 store_spreg( R_ECX, R_FPSCR );
2.1588 update_fr_bank( R_ECX );
2.1589 + sh4_x86.tstate = TSTATE_NONE;
2.1590 }
2.1591 break;
2.1592 case 0x3:
2.1593 @@ -3372,6 +3588,7 @@
2.1594 FADDP_st(1);
2.1595 pop_dr( R_EDX, FRn );
2.1596 JMP_TARGET(end);
2.1597 + sh4_x86.tstate = TSTATE_NONE;
2.1598 }
2.1599 break;
2.1600 default:
3.1 --- a/src/sh4/sh4x86.in Wed Oct 03 12:19:03 2007 +0000
3.2 +++ b/src/sh4/sh4x86.in Thu Oct 04 08:47:27 2007 +0000
3.3 @@ -1,5 +1,5 @@
3.4 /**
3.5 - * $Id: sh4x86.in,v 1.18 2007-10-03 12:19:03 nkeynes Exp $
3.6 + * $Id: sh4x86.in,v 1.19 2007-10-04 08:47:27 nkeynes Exp $
3.7 *
3.8 * SH4 => x86 translation. This version does no real optimization, it just
3.9 * outputs straight-line x86 code - it mainly exists to provide a baseline
3.10 @@ -25,6 +25,7 @@
3.11 #define DEBUG_JUMPS 1
3.12 #endif
3.13
3.14 +#include "sh4/xltcache.h"
3.15 #include "sh4/sh4core.h"
3.16 #include "sh4/sh4trans.h"
3.17 #include "sh4/sh4mmio.h"
3.18 @@ -44,6 +45,7 @@
3.19 gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
3.20 gboolean branch_taken; /* true if we branched unconditionally */
3.21 uint32_t block_start_pc;
3.22 + int tstate;
3.23
3.24 /* Allocated memory for the (block-wide) back-patch list */
3.25 uint32_t **backpatch_list;
3.26 @@ -51,6 +53,28 @@
3.27 uint32_t backpatch_size;
3.28 };
3.29
3.30 +#define TSTATE_NONE -1
3.31 +#define TSTATE_O 0
3.32 +#define TSTATE_C 2
3.33 +#define TSTATE_E 4
3.34 +#define TSTATE_NE 5
3.35 +#define TSTATE_G 0xF
3.36 +#define TSTATE_GE 0xD
3.37 +#define TSTATE_A 7
3.38 +#define TSTATE_AE 3
3.39 +
3.40 +/** Branch if T is set (either in the current cflags, or in sh4r.t) */
3.41 +#define JT_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
3.42 + CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
3.43 + OP(0x70+sh4_x86.tstate); OP(rel8); \
3.44 + MARK_JMP(rel8,label)
3.45 +/** Branch if T is clear (either in the current cflags or in sh4r.t) */
3.46 +#define JF_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
3.47 + CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
3.48 + OP(0x70+ (sh4_x86.tstate^1)); OP(rel8); \
3.49 + MARK_JMP(rel8, label)
3.50 +
3.51 +
3.52 #define EXIT_DATA_ADDR_READ 0
3.53 #define EXIT_DATA_ADDR_WRITE 7
3.54 #define EXIT_ILLEGAL 14
3.55 @@ -403,6 +427,7 @@
3.56 sh4_x86.branch_taken = FALSE;
3.57 sh4_x86.backpatch_posn = 0;
3.58 sh4_x86.block_start_pc = pc;
3.59 + sh4_x86.tstate = TSTATE_NONE;
3.60 }
3.61
3.62 /**
3.63 @@ -427,9 +452,10 @@
3.64 */
3.65 void exit_block_pcset( pc )
3.66 {
3.67 - XOR_r32_r32( R_EAX, R_EAX ); // 2
3.68 load_imm32( R_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
3.69 ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) ); // 6
3.70 + load_spreg( R_EAX, REG_OFFSET(pc) );
3.71 + call_func1(xlat_get_code,R_EAX);
3.72 POP_r32(R_EBP);
3.73 RET();
3.74 }
3.75 @@ -462,20 +488,20 @@
3.76 JMP_TARGET(target3);
3.77 JMP_TARGET(target4);
3.78 JMP_TARGET(target5);
3.79 + // Raise exception
3.80 load_spreg( R_ECX, REG_OFFSET(pc) );
3.81 ADD_r32_r32( R_EDX, R_ECX );
3.82 ADD_r32_r32( R_EDX, R_ECX );
3.83 store_spreg( R_ECX, REG_OFFSET(pc) );
3.84 MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
3.85 - load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
3.86 MUL_r32( R_EDX );
3.87 - ADD_r32_r32( R_EAX, R_ECX );
3.88 - store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
3.89 + ADD_r32_sh4r( R_EAX, REG_OFFSET(slice_cycle) );
3.90
3.91 load_imm32( R_EAX, (uint32_t)sh4_raise_exception ); // 6
3.92 CALL_r32( R_EAX ); // 2
3.93 ADD_imm8s_r32( 4, R_ESP );
3.94 - XOR_r32_r32( R_EAX, R_EAX );
3.95 + load_spreg( R_EAX, REG_OFFSET(pc) );
3.96 + call_func1(xlat_get_code,R_EAX);
3.97 POP_r32(R_EBP);
3.98 RET();
3.99
3.100 @@ -524,19 +550,24 @@
3.101 load_reg( R_ECX, Rn );
3.102 ADD_r32_r32( R_EAX, R_ECX );
3.103 store_reg( R_ECX, Rn );
3.104 + sh4_x86.tstate = TSTATE_NONE;
3.105 :}
3.106 ADD #imm, Rn {:
3.107 load_reg( R_EAX, Rn );
3.108 ADD_imm8s_r32( imm, R_EAX );
3.109 store_reg( R_EAX, Rn );
3.110 + sh4_x86.tstate = TSTATE_NONE;
3.111 :}
3.112 ADDC Rm, Rn {:
3.113 + if( sh4_x86.tstate != TSTATE_C ) {
3.114 + LDC_t();
3.115 + }
3.116 load_reg( R_EAX, Rm );
3.117 load_reg( R_ECX, Rn );
3.118 - LDC_t();
3.119 ADC_r32_r32( R_EAX, R_ECX );
3.120 store_reg( R_ECX, Rn );
3.121 SETC_t();
3.122 + sh4_x86.tstate = TSTATE_C;
3.123 :}
3.124 ADDV Rm, Rn {:
3.125 load_reg( R_EAX, Rm );
3.126 @@ -544,17 +575,20 @@
3.127 ADD_r32_r32( R_EAX, R_ECX );
3.128 store_reg( R_ECX, Rn );
3.129 SETO_t();
3.130 + sh4_x86.tstate = TSTATE_O;
3.131 :}
3.132 AND Rm, Rn {:
3.133 load_reg( R_EAX, Rm );
3.134 load_reg( R_ECX, Rn );
3.135 AND_r32_r32( R_EAX, R_ECX );
3.136 store_reg( R_ECX, Rn );
3.137 + sh4_x86.tstate = TSTATE_NONE;
3.138 :}
3.139 AND #imm, R0 {:
3.140 load_reg( R_EAX, 0 );
3.141 AND_imm32_r32(imm, R_EAX);
3.142 store_reg( R_EAX, 0 );
3.143 + sh4_x86.tstate = TSTATE_NONE;
3.144 :}
3.145 AND.B #imm, @(R0, GBR) {:
3.146 load_reg( R_EAX, 0 );
3.147 @@ -565,51 +599,60 @@
3.148 POP_r32(R_ECX);
3.149 AND_imm32_r32(imm, R_EAX );
3.150 MEM_WRITE_BYTE( R_ECX, R_EAX );
3.151 + sh4_x86.tstate = TSTATE_NONE;
3.152 :}
3.153 CMP/EQ Rm, Rn {:
3.154 load_reg( R_EAX, Rm );
3.155 load_reg( R_ECX, Rn );
3.156 CMP_r32_r32( R_EAX, R_ECX );
3.157 SETE_t();
3.158 + sh4_x86.tstate = TSTATE_E;
3.159 :}
3.160 CMP/EQ #imm, R0 {:
3.161 load_reg( R_EAX, 0 );
3.162 CMP_imm8s_r32(imm, R_EAX);
3.163 SETE_t();
3.164 + sh4_x86.tstate = TSTATE_E;
3.165 :}
3.166 CMP/GE Rm, Rn {:
3.167 load_reg( R_EAX, Rm );
3.168 load_reg( R_ECX, Rn );
3.169 CMP_r32_r32( R_EAX, R_ECX );
3.170 SETGE_t();
3.171 + sh4_x86.tstate = TSTATE_GE;
3.172 :}
3.173 CMP/GT Rm, Rn {:
3.174 load_reg( R_EAX, Rm );
3.175 load_reg( R_ECX, Rn );
3.176 CMP_r32_r32( R_EAX, R_ECX );
3.177 SETG_t();
3.178 + sh4_x86.tstate = TSTATE_G;
3.179 :}
3.180 CMP/HI Rm, Rn {:
3.181 load_reg( R_EAX, Rm );
3.182 load_reg( R_ECX, Rn );
3.183 CMP_r32_r32( R_EAX, R_ECX );
3.184 SETA_t();
3.185 + sh4_x86.tstate = TSTATE_A;
3.186 :}
3.187 CMP/HS Rm, Rn {:
3.188 load_reg( R_EAX, Rm );
3.189 load_reg( R_ECX, Rn );
3.190 CMP_r32_r32( R_EAX, R_ECX );
3.191 SETAE_t();
3.192 + sh4_x86.tstate = TSTATE_AE;
3.193 :}
3.194 CMP/PL Rn {:
3.195 load_reg( R_EAX, Rn );
3.196 CMP_imm8s_r32( 0, R_EAX );
3.197 SETG_t();
3.198 + sh4_x86.tstate = TSTATE_G;
3.199 :}
3.200 CMP/PZ Rn {:
3.201 load_reg( R_EAX, Rn );
3.202 CMP_imm8s_r32( 0, R_EAX );
3.203 SETGE_t();
3.204 + sh4_x86.tstate = TSTATE_GE;
3.205 :}
3.206 CMP/STR Rm, Rn {:
3.207 load_reg( R_EAX, Rm );
3.208 @@ -627,6 +670,7 @@
3.209 JMP_TARGET(target2);
3.210 JMP_TARGET(target3);
3.211 SETE_t();
3.212 + sh4_x86.tstate = TSTATE_E;
3.213 :}
3.214 DIV0S Rm, Rn {:
3.215 load_reg( R_EAX, Rm );
3.216 @@ -637,17 +681,21 @@
3.217 store_spreg( R_ECX, R_Q );
3.218 CMP_r32_r32( R_EAX, R_ECX );
3.219 SETNE_t();
3.220 + sh4_x86.tstate = TSTATE_NE;
3.221 :}
3.222 DIV0U {:
3.223 XOR_r32_r32( R_EAX, R_EAX );
3.224 store_spreg( R_EAX, R_Q );
3.225 store_spreg( R_EAX, R_M );
3.226 store_spreg( R_EAX, R_T );
3.227 + sh4_x86.tstate = TSTATE_C; // works for DIV1
3.228 :}
3.229 DIV1 Rm, Rn {:
3.230 load_spreg( R_ECX, R_M );
3.231 load_reg( R_EAX, Rn );
3.232 - LDC_t();
3.233 + if( sh4_x86.tstate != TSTATE_C ) {
3.234 + LDC_t();
3.235 + }
3.236 RCL1_r32( R_EAX );
3.237 SETC_r8( R_DL ); // Q'
3.238 CMP_sh4r_r32( R_Q, R_ECX );
3.239 @@ -665,6 +713,7 @@
3.240 XOR_imm8s_r32( 1, R_AL ); // T = !Q'
3.241 MOVZX_r8_r32( R_AL, R_EAX );
3.242 store_spreg( R_EAX, R_T );
3.243 + sh4_x86.tstate = TSTATE_NONE;
3.244 :}
3.245 DMULS.L Rm, Rn {:
3.246 load_reg( R_EAX, Rm );
3.247 @@ -672,6 +721,7 @@
3.248 IMUL_r32(R_ECX);
3.249 store_spreg( R_EDX, R_MACH );
3.250 store_spreg( R_EAX, R_MACL );
3.251 + sh4_x86.tstate = TSTATE_NONE;
3.252 :}
3.253 DMULU.L Rm, Rn {:
3.254 load_reg( R_EAX, Rm );
3.255 @@ -679,12 +729,14 @@
3.256 MUL_r32(R_ECX);
3.257 store_spreg( R_EDX, R_MACH );
3.258 store_spreg( R_EAX, R_MACL );
3.259 + sh4_x86.tstate = TSTATE_NONE;
3.260 :}
3.261 DT Rn {:
3.262 load_reg( R_EAX, Rn );
3.263 ADD_imm8s_r32( -1, R_EAX );
3.264 store_reg( R_EAX, Rn );
3.265 SETE_t();
3.266 + sh4_x86.tstate = TSTATE_E;
3.267 :}
3.268 EXTS.B Rm, Rn {:
3.269 load_reg( R_EAX, Rm );
3.270 @@ -728,6 +780,7 @@
3.271 JE_rel8( 7, nosat );
3.272 call_func0( signsat48 );
3.273 JMP_TARGET( nosat );
3.274 + sh4_x86.tstate = TSTATE_NONE;
3.275 :}
3.276 MAC.W @Rm+, @Rn+ {:
3.277 load_reg( R_ECX, Rm );
3.278 @@ -768,6 +821,7 @@
3.279 JMP_TARGET(end);
3.280 JMP_TARGET(end2);
3.281 JMP_TARGET(end3);
3.282 + sh4_x86.tstate = TSTATE_NONE;
3.283 :}
3.284 MOVT Rn {:
3.285 load_spreg( R_EAX, R_T );
3.286 @@ -778,23 +832,27 @@
3.287 load_reg( R_ECX, Rn );
3.288 MUL_r32( R_ECX );
3.289 store_spreg( R_EAX, R_MACL );
3.290 + sh4_x86.tstate = TSTATE_NONE;
3.291 :}
3.292 MULS.W Rm, Rn {:
3.293 load_reg16s( R_EAX, Rm );
3.294 load_reg16s( R_ECX, Rn );
3.295 MUL_r32( R_ECX );
3.296 store_spreg( R_EAX, R_MACL );
3.297 + sh4_x86.tstate = TSTATE_NONE;
3.298 :}
3.299 MULU.W Rm, Rn {:
3.300 load_reg16u( R_EAX, Rm );
3.301 load_reg16u( R_ECX, Rn );
3.302 MUL_r32( R_ECX );
3.303 store_spreg( R_EAX, R_MACL );
3.304 + sh4_x86.tstate = TSTATE_NONE;
3.305 :}
3.306 NEG Rm, Rn {:
3.307 load_reg( R_EAX, Rm );
3.308 NEG_r32( R_EAX );
3.309 store_reg( R_EAX, Rn );
3.310 + sh4_x86.tstate = TSTATE_NONE;
3.311 :}
3.312 NEGC Rm, Rn {:
3.313 load_reg( R_EAX, Rm );
3.314 @@ -803,22 +861,26 @@
3.315 SBB_r32_r32( R_EAX, R_ECX );
3.316 store_reg( R_ECX, Rn );
3.317 SETC_t();
3.318 + sh4_x86.tstate = TSTATE_C;
3.319 :}
3.320 NOT Rm, Rn {:
3.321 load_reg( R_EAX, Rm );
3.322 NOT_r32( R_EAX );
3.323 store_reg( R_EAX, Rn );
3.324 + sh4_x86.tstate = TSTATE_NONE;
3.325 :}
3.326 OR Rm, Rn {:
3.327 load_reg( R_EAX, Rm );
3.328 load_reg( R_ECX, Rn );
3.329 OR_r32_r32( R_EAX, R_ECX );
3.330 store_reg( R_ECX, Rn );
3.331 + sh4_x86.tstate = TSTATE_NONE;
3.332 :}
3.333 OR #imm, R0 {:
3.334 load_reg( R_EAX, 0 );
3.335 OR_imm32_r32(imm, R_EAX);
3.336 store_reg( R_EAX, 0 );
3.337 + sh4_x86.tstate = TSTATE_NONE;
3.338 :}
3.339 OR.B #imm, @(R0, GBR) {:
3.340 load_reg( R_EAX, 0 );
3.341 @@ -829,32 +891,41 @@
3.342 POP_r32(R_ECX);
3.343 OR_imm32_r32(imm, R_EAX );
3.344 MEM_WRITE_BYTE( R_ECX, R_EAX );
3.345 + sh4_x86.tstate = TSTATE_NONE;
3.346 :}
3.347 ROTCL Rn {:
3.348 load_reg( R_EAX, Rn );
3.349 - LDC_t();
3.350 + if( sh4_x86.tstate != TSTATE_C ) {
3.351 + LDC_t();
3.352 + }
3.353 RCL1_r32( R_EAX );
3.354 store_reg( R_EAX, Rn );
3.355 SETC_t();
3.356 + sh4_x86.tstate = TSTATE_C;
3.357 :}
3.358 ROTCR Rn {:
3.359 load_reg( R_EAX, Rn );
3.360 - LDC_t();
3.361 + if( sh4_x86.tstate != TSTATE_C ) {
3.362 + LDC_t();
3.363 + }
3.364 RCR1_r32( R_EAX );
3.365 store_reg( R_EAX, Rn );
3.366 SETC_t();
3.367 + sh4_x86.tstate = TSTATE_C;
3.368 :}
3.369 ROTL Rn {:
3.370 load_reg( R_EAX, Rn );
3.371 ROL1_r32( R_EAX );
3.372 store_reg( R_EAX, Rn );
3.373 SETC_t();
3.374 + sh4_x86.tstate = TSTATE_C;
3.375 :}
3.376 ROTR Rn {:
3.377 load_reg( R_EAX, Rn );
3.378 ROR1_r32( R_EAX );
3.379 store_reg( R_EAX, Rn );
3.380 SETC_t();
3.381 + sh4_x86.tstate = TSTATE_C;
3.382 :}
3.383 SHAD Rm, Rn {:
3.384 /* Annoyingly enough, not directly convertible */
3.385 @@ -879,6 +950,7 @@
3.386 JMP_TARGET(end);
3.387 JMP_TARGET(end2);
3.388 store_reg( R_EAX, Rn );
3.389 + sh4_x86.tstate = TSTATE_NONE;
3.390 :}
3.391 SHLD Rm, Rn {:
3.392 load_reg( R_EAX, Rn );
3.393 @@ -902,74 +974,89 @@
3.394 JMP_TARGET(end);
3.395 JMP_TARGET(end2);
3.396 store_reg( R_EAX, Rn );
3.397 + sh4_x86.tstate = TSTATE_NONE;
3.398 :}
3.399 SHAL Rn {:
3.400 load_reg( R_EAX, Rn );
3.401 SHL1_r32( R_EAX );
3.402 SETC_t();
3.403 store_reg( R_EAX, Rn );
3.404 + sh4_x86.tstate = TSTATE_C;
3.405 :}
3.406 SHAR Rn {:
3.407 load_reg( R_EAX, Rn );
3.408 SAR1_r32( R_EAX );
3.409 SETC_t();
3.410 store_reg( R_EAX, Rn );
3.411 + sh4_x86.tstate = TSTATE_C;
3.412 :}
3.413 SHLL Rn {:
3.414 load_reg( R_EAX, Rn );
3.415 SHL1_r32( R_EAX );
3.416 SETC_t();
3.417 store_reg( R_EAX, Rn );
3.418 + sh4_x86.tstate = TSTATE_C;
3.419 :}
3.420 SHLL2 Rn {:
3.421 load_reg( R_EAX, Rn );
3.422 SHL_imm8_r32( 2, R_EAX );
3.423 store_reg( R_EAX, Rn );
3.424 + sh4_x86.tstate = TSTATE_NONE;
3.425 :}
3.426 SHLL8 Rn {:
3.427 load_reg( R_EAX, Rn );
3.428 SHL_imm8_r32( 8, R_EAX );
3.429 store_reg( R_EAX, Rn );
3.430 + sh4_x86.tstate = TSTATE_NONE;
3.431 :}
3.432 SHLL16 Rn {:
3.433 load_reg( R_EAX, Rn );
3.434 SHL_imm8_r32( 16, R_EAX );
3.435 store_reg( R_EAX, Rn );
3.436 + sh4_x86.tstate = TSTATE_NONE;
3.437 :}
3.438 SHLR Rn {:
3.439 load_reg( R_EAX, Rn );
3.440 SHR1_r32( R_EAX );
3.441 SETC_t();
3.442 store_reg( R_EAX, Rn );
3.443 + sh4_x86.tstate = TSTATE_C;
3.444 :}
3.445 SHLR2 Rn {:
3.446 load_reg( R_EAX, Rn );
3.447 SHR_imm8_r32( 2, R_EAX );
3.448 store_reg( R_EAX, Rn );
3.449 + sh4_x86.tstate = TSTATE_NONE;
3.450 :}
3.451 SHLR8 Rn {:
3.452 load_reg( R_EAX, Rn );
3.453 SHR_imm8_r32( 8, R_EAX );
3.454 store_reg( R_EAX, Rn );
3.455 + sh4_x86.tstate = TSTATE_NONE;
3.456 :}
3.457 SHLR16 Rn {:
3.458 load_reg( R_EAX, Rn );
3.459 SHR_imm8_r32( 16, R_EAX );
3.460 store_reg( R_EAX, Rn );
3.461 + sh4_x86.tstate = TSTATE_NONE;
3.462 :}
3.463 SUB Rm, Rn {:
3.464 load_reg( R_EAX, Rm );
3.465 load_reg( R_ECX, Rn );
3.466 SUB_r32_r32( R_EAX, R_ECX );
3.467 store_reg( R_ECX, Rn );
3.468 + sh4_x86.tstate = TSTATE_NONE;
3.469 :}
3.470 SUBC Rm, Rn {:
3.471 load_reg( R_EAX, Rm );
3.472 load_reg( R_ECX, Rn );
3.473 - LDC_t();
3.474 + if( sh4_x86.tstate != TSTATE_C ) {
3.475 + LDC_t();
3.476 + }
3.477 SBB_r32_r32( R_EAX, R_ECX );
3.478 store_reg( R_ECX, Rn );
3.479 SETC_t();
3.480 + sh4_x86.tstate = TSTATE_C;
3.481 :}
3.482 SUBV Rm, Rn {:
3.483 load_reg( R_EAX, Rm );
3.484 @@ -977,6 +1064,7 @@
3.485 SUB_r32_r32( R_EAX, R_ECX );
3.486 store_reg( R_ECX, Rn );
3.487 SETO_t();
3.488 + sh4_x86.tstate = TSTATE_O;
3.489 :}
3.490 SWAP.B Rm, Rn {:
3.491 load_reg( R_EAX, Rm );
3.492 @@ -990,6 +1078,7 @@
3.493 SHR_imm8_r32( 16, R_EAX );
3.494 OR_r32_r32( R_EAX, R_ECX );
3.495 store_reg( R_ECX, Rn );
3.496 + sh4_x86.tstate = TSTATE_NONE;
3.497 :}
3.498 TAS.B @Rn {:
3.499 load_reg( R_ECX, Rn );
3.500 @@ -999,17 +1088,20 @@
3.501 OR_imm8_r8( 0x80, R_AL );
3.502 load_reg( R_ECX, Rn );
3.503 MEM_WRITE_BYTE( R_ECX, R_EAX );
3.504 + sh4_x86.tstate = TSTATE_NONE;
3.505 :}
3.506 TST Rm, Rn {:
3.507 load_reg( R_EAX, Rm );
3.508 load_reg( R_ECX, Rn );
3.509 TEST_r32_r32( R_EAX, R_ECX );
3.510 SETE_t();
3.511 + sh4_x86.tstate = TSTATE_E;
3.512 :}
3.513 TST #imm, R0 {:
3.514 load_reg( R_EAX, 0 );
3.515 TEST_imm32_r32( imm, R_EAX );
3.516 SETE_t();
3.517 + sh4_x86.tstate = TSTATE_E;
3.518 :}
3.519 TST.B #imm, @(R0, GBR) {:
3.520 load_reg( R_EAX, 0);
3.521 @@ -1018,17 +1110,20 @@
3.522 MEM_READ_BYTE( R_ECX, R_EAX );
3.523 TEST_imm8_r8( imm, R_AL );
3.524 SETE_t();
3.525 + sh4_x86.tstate = TSTATE_E;
3.526 :}
3.527 XOR Rm, Rn {:
3.528 load_reg( R_EAX, Rm );
3.529 load_reg( R_ECX, Rn );
3.530 XOR_r32_r32( R_EAX, R_ECX );
3.531 store_reg( R_ECX, Rn );
3.532 + sh4_x86.tstate = TSTATE_NONE;
3.533 :}
3.534 XOR #imm, R0 {:
3.535 load_reg( R_EAX, 0 );
3.536 XOR_imm32_r32( imm, R_EAX );
3.537 store_reg( R_EAX, 0 );
3.538 + sh4_x86.tstate = TSTATE_NONE;
3.539 :}
3.540 XOR.B #imm, @(R0, GBR) {:
3.541 load_reg( R_EAX, 0 );
3.542 @@ -1039,6 +1134,7 @@
3.543 POP_r32(R_ECX);
3.544 XOR_imm32_r32( imm, R_EAX );
3.545 MEM_WRITE_BYTE( R_ECX, R_EAX );
3.546 + sh4_x86.tstate = TSTATE_NONE;
3.547 :}
3.548 XTRCT Rm, Rn {:
3.549 load_reg( R_EAX, Rm );
3.550 @@ -1047,6 +1143,7 @@
3.551 SHR_imm8_r32( 16, R_ECX );
3.552 OR_r32_r32( R_EAX, R_ECX );
3.553 store_reg( R_ECX, Rn );
3.554 + sh4_x86.tstate = TSTATE_NONE;
3.555 :}
3.556
3.557 /* Data move instructions */
3.558 @@ -1062,6 +1159,7 @@
3.559 load_reg( R_EAX, Rm );
3.560 load_reg( R_ECX, Rn );
3.561 MEM_WRITE_BYTE( R_ECX, R_EAX );
3.562 + sh4_x86.tstate = TSTATE_NONE;
3.563 :}
3.564 MOV.B Rm, @-Rn {:
3.565 load_reg( R_EAX, Rm );
3.566 @@ -1069,6 +1167,7 @@
3.567 ADD_imm8s_r32( -1, R_ECX );
3.568 store_reg( R_ECX, Rn );
3.569 MEM_WRITE_BYTE( R_ECX, R_EAX );
3.570 + sh4_x86.tstate = TSTATE_NONE;
3.571 :}
3.572 MOV.B Rm, @(R0, Rn) {:
3.573 load_reg( R_EAX, 0 );
3.574 @@ -1076,23 +1175,27 @@
3.575 ADD_r32_r32( R_EAX, R_ECX );
3.576 load_reg( R_EAX, Rm );
3.577 MEM_WRITE_BYTE( R_ECX, R_EAX );
3.578 + sh4_x86.tstate = TSTATE_NONE;
3.579 :}
3.580 MOV.B R0, @(disp, GBR) {:
3.581 load_reg( R_EAX, 0 );
3.582 load_spreg( R_ECX, R_GBR );
3.583 ADD_imm32_r32( disp, R_ECX );
3.584 MEM_WRITE_BYTE( R_ECX, R_EAX );
3.585 + sh4_x86.tstate = TSTATE_NONE;
3.586 :}
3.587 MOV.B R0, @(disp, Rn) {:
3.588 load_reg( R_EAX, 0 );
3.589 load_reg( R_ECX, Rn );
3.590 ADD_imm32_r32( disp, R_ECX );
3.591 MEM_WRITE_BYTE( R_ECX, R_EAX );
3.592 + sh4_x86.tstate = TSTATE_NONE;
3.593 :}
3.594 MOV.B @Rm, Rn {:
3.595 load_reg( R_ECX, Rm );
3.596 MEM_READ_BYTE( R_ECX, R_EAX );
3.597 store_reg( R_EAX, Rn );
3.598 + sh4_x86.tstate = TSTATE_NONE;
3.599 :}
3.600 MOV.B @Rm+, Rn {:
3.601 load_reg( R_ECX, Rm );
3.602 @@ -1101,6 +1204,7 @@
3.603 store_reg( R_EAX, Rm );
3.604 MEM_READ_BYTE( R_ECX, R_EAX );
3.605 store_reg( R_EAX, Rn );
3.606 + sh4_x86.tstate = TSTATE_NONE;
3.607 :}
3.608 MOV.B @(R0, Rm), Rn {:
3.609 load_reg( R_EAX, 0 );
3.610 @@ -1108,18 +1212,21 @@
3.611 ADD_r32_r32( R_EAX, R_ECX );
3.612 MEM_READ_BYTE( R_ECX, R_EAX );
3.613 store_reg( R_EAX, Rn );
3.614 + sh4_x86.tstate = TSTATE_NONE;
3.615 :}
3.616 MOV.B @(disp, GBR), R0 {:
3.617 load_spreg( R_ECX, R_GBR );
3.618 ADD_imm32_r32( disp, R_ECX );
3.619 MEM_READ_BYTE( R_ECX, R_EAX );
3.620 store_reg( R_EAX, 0 );
3.621 + sh4_x86.tstate = TSTATE_NONE;
3.622 :}
3.623 MOV.B @(disp, Rm), R0 {:
3.624 load_reg( R_ECX, Rm );
3.625 ADD_imm32_r32( disp, R_ECX );
3.626 MEM_READ_BYTE( R_ECX, R_EAX );
3.627 store_reg( R_EAX, 0 );
3.628 + sh4_x86.tstate = TSTATE_NONE;
3.629 :}
3.630 MOV.L Rm, @Rn {:
3.631 load_reg( R_EAX, Rm );
3.632 @@ -1127,6 +1234,7 @@
3.633 precheck();
3.634 check_walign32(R_ECX);
3.635 MEM_WRITE_LONG( R_ECX, R_EAX );
3.636 + sh4_x86.tstate = TSTATE_NONE;
3.637 :}
3.638 MOV.L Rm, @-Rn {:
3.639 load_reg( R_EAX, Rm );
3.640 @@ -1136,6 +1244,7 @@
3.641 ADD_imm8s_r32( -4, R_ECX );
3.642 store_reg( R_ECX, Rn );
3.643 MEM_WRITE_LONG( R_ECX, R_EAX );
3.644 + sh4_x86.tstate = TSTATE_NONE;
3.645 :}
3.646 MOV.L Rm, @(R0, Rn) {:
3.647 load_reg( R_EAX, 0 );
3.648 @@ -1145,6 +1254,7 @@
3.649 check_walign32( R_ECX );
3.650 load_reg( R_EAX, Rm );
3.651 MEM_WRITE_LONG( R_ECX, R_EAX );
3.652 + sh4_x86.tstate = TSTATE_NONE;
3.653 :}
3.654 MOV.L R0, @(disp, GBR) {:
3.655 load_spreg( R_ECX, R_GBR );
3.656 @@ -1153,6 +1263,7 @@
3.657 precheck();
3.658 check_walign32( R_ECX );
3.659 MEM_WRITE_LONG( R_ECX, R_EAX );
3.660 + sh4_x86.tstate = TSTATE_NONE;
3.661 :}
3.662 MOV.L Rm, @(disp, Rn) {:
3.663 load_reg( R_ECX, Rn );
3.664 @@ -1161,6 +1272,7 @@
3.665 precheck();
3.666 check_walign32( R_ECX );
3.667 MEM_WRITE_LONG( R_ECX, R_EAX );
3.668 + sh4_x86.tstate = TSTATE_NONE;
3.669 :}
3.670 MOV.L @Rm, Rn {:
3.671 load_reg( R_ECX, Rm );
3.672 @@ -1168,6 +1280,7 @@
3.673 check_ralign32( R_ECX );
3.674 MEM_READ_LONG( R_ECX, R_EAX );
3.675 store_reg( R_EAX, Rn );
3.676 + sh4_x86.tstate = TSTATE_NONE;
3.677 :}
3.678 MOV.L @Rm+, Rn {:
3.679 load_reg( R_EAX, Rm );
3.680 @@ -1178,6 +1291,7 @@
3.681 store_reg( R_EAX, Rm );
3.682 MEM_READ_LONG( R_ECX, R_EAX );
3.683 store_reg( R_EAX, Rn );
3.684 + sh4_x86.tstate = TSTATE_NONE;
3.685 :}
3.686 MOV.L @(R0, Rm), Rn {:
3.687 load_reg( R_EAX, 0 );
3.688 @@ -1187,6 +1301,7 @@
3.689 check_ralign32( R_ECX );
3.690 MEM_READ_LONG( R_ECX, R_EAX );
3.691 store_reg( R_EAX, Rn );
3.692 + sh4_x86.tstate = TSTATE_NONE;
3.693 :}
3.694 MOV.L @(disp, GBR), R0 {:
3.695 load_spreg( R_ECX, R_GBR );
3.696 @@ -1195,6 +1310,7 @@
3.697 check_ralign32( R_ECX );
3.698 MEM_READ_LONG( R_ECX, R_EAX );
3.699 store_reg( R_EAX, 0 );
3.700 + sh4_x86.tstate = TSTATE_NONE;
3.701 :}
3.702 MOV.L @(disp, PC), Rn {:
3.703 if( sh4_x86.in_delay_slot ) {
3.704 @@ -1209,6 +1325,7 @@
3.705 MEM_READ_LONG( R_ECX, R_EAX );
3.706 }
3.707 store_reg( R_EAX, Rn );
3.708 + sh4_x86.tstate = TSTATE_NONE;
3.709 }
3.710 :}
3.711 MOV.L @(disp, Rm), Rn {:
3.712 @@ -1218,6 +1335,7 @@
3.713 check_ralign32( R_ECX );
3.714 MEM_READ_LONG( R_ECX, R_EAX );
3.715 store_reg( R_EAX, Rn );
3.716 + sh4_x86.tstate = TSTATE_NONE;
3.717 :}
3.718 MOV.W Rm, @Rn {:
3.719 load_reg( R_ECX, Rn );
3.720 @@ -1225,6 +1343,7 @@
3.721 check_walign16( R_ECX );
3.722 load_reg( R_EAX, Rm );
3.723 MEM_WRITE_WORD( R_ECX, R_EAX );
3.724 + sh4_x86.tstate = TSTATE_NONE;
3.725 :}
3.726 MOV.W Rm, @-Rn {:
3.727 load_reg( R_ECX, Rn );
3.728 @@ -1234,6 +1353,7 @@
3.729 ADD_imm8s_r32( -2, R_ECX );
3.730 store_reg( R_ECX, Rn );
3.731 MEM_WRITE_WORD( R_ECX, R_EAX );
3.732 + sh4_x86.tstate = TSTATE_NONE;
3.733 :}
3.734 MOV.W Rm, @(R0, Rn) {:
3.735 load_reg( R_EAX, 0 );
3.736 @@ -1243,6 +1363,7 @@
3.737 check_walign16( R_ECX );
3.738 load_reg( R_EAX, Rm );
3.739 MEM_WRITE_WORD( R_ECX, R_EAX );
3.740 + sh4_x86.tstate = TSTATE_NONE;
3.741 :}
3.742 MOV.W R0, @(disp, GBR) {:
3.743 load_spreg( R_ECX, R_GBR );
3.744 @@ -1251,6 +1372,7 @@
3.745 precheck();
3.746 check_walign16( R_ECX );
3.747 MEM_WRITE_WORD( R_ECX, R_EAX );
3.748 + sh4_x86.tstate = TSTATE_NONE;
3.749 :}
3.750 MOV.W R0, @(disp, Rn) {:
3.751 load_reg( R_ECX, Rn );
3.752 @@ -1259,6 +1381,7 @@
3.753 precheck();
3.754 check_walign16( R_ECX );
3.755 MEM_WRITE_WORD( R_ECX, R_EAX );
3.756 + sh4_x86.tstate = TSTATE_NONE;
3.757 :}
3.758 MOV.W @Rm, Rn {:
3.759 load_reg( R_ECX, Rm );
3.760 @@ -1266,6 +1389,7 @@
3.761 check_ralign16( R_ECX );
3.762 MEM_READ_WORD( R_ECX, R_EAX );
3.763 store_reg( R_EAX, Rn );
3.764 + sh4_x86.tstate = TSTATE_NONE;
3.765 :}
3.766 MOV.W @Rm+, Rn {:
3.767 load_reg( R_EAX, Rm );
3.768 @@ -1276,6 +1400,7 @@
3.769 store_reg( R_EAX, Rm );
3.770 MEM_READ_WORD( R_ECX, R_EAX );
3.771 store_reg( R_EAX, Rn );
3.772 + sh4_x86.tstate = TSTATE_NONE;
3.773 :}
3.774 MOV.W @(R0, Rm), Rn {:
3.775 load_reg( R_EAX, 0 );
3.776 @@ -1285,6 +1410,7 @@
3.777 check_ralign16( R_ECX );
3.778 MEM_READ_WORD( R_ECX, R_EAX );
3.779 store_reg( R_EAX, Rn );
3.780 + sh4_x86.tstate = TSTATE_NONE;
3.781 :}
3.782 MOV.W @(disp, GBR), R0 {:
3.783 load_spreg( R_ECX, R_GBR );
3.784 @@ -1293,6 +1419,7 @@
3.785 check_ralign16( R_ECX );
3.786 MEM_READ_WORD( R_ECX, R_EAX );
3.787 store_reg( R_EAX, 0 );
3.788 + sh4_x86.tstate = TSTATE_NONE;
3.789 :}
3.790 MOV.W @(disp, PC), Rn {:
3.791 if( sh4_x86.in_delay_slot ) {
3.792 @@ -1301,6 +1428,7 @@
3.793 load_imm32( R_ECX, pc + disp + 4 );
3.794 MEM_READ_WORD( R_ECX, R_EAX );
3.795 store_reg( R_EAX, Rn );
3.796 + sh4_x86.tstate = TSTATE_NONE;
3.797 }
3.798 :}
3.799 MOV.W @(disp, Rm), R0 {:
3.800 @@ -1310,6 +1438,7 @@
3.801 check_ralign16( R_ECX );
3.802 MEM_READ_WORD( R_ECX, R_EAX );
3.803 store_reg( R_EAX, 0 );
3.804 + sh4_x86.tstate = TSTATE_NONE;
3.805 :}
3.806 MOVA @(disp, PC), R0 {:
3.807 if( sh4_x86.in_delay_slot ) {
3.808 @@ -1325,6 +1454,7 @@
3.809 precheck();
3.810 check_walign32( R_ECX );
3.811 MEM_WRITE_LONG( R_ECX, R_EAX );
3.812 + sh4_x86.tstate = TSTATE_NONE;
3.813 :}
3.814
3.815 /* Control transfer instructions */
3.816 @@ -1332,8 +1462,7 @@
3.817 if( sh4_x86.in_delay_slot ) {
3.818 SLOTILLEGAL();
3.819 } else {
3.820 - CMP_imm8s_sh4r( 0, R_T );
3.821 - JNE_rel8( 29, nottaken );
3.822 + JT_rel8( 29, nottaken );
3.823 exit_block( disp + pc + 4, pc+2 );
3.824 JMP_TARGET(nottaken);
3.825 return 2;
3.826 @@ -1344,8 +1473,11 @@
3.827 SLOTILLEGAL();
3.828 } else {
3.829 sh4_x86.in_delay_slot = TRUE;
3.830 - CMP_imm8s_sh4r( 0, R_T );
3.831 - OP(0x0F); OP(0x85); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32
3.832 + if( sh4_x86.tstate == TSTATE_NONE ) {
3.833 + CMP_imm8s_sh4r( 1, R_T );
3.834 + sh4_x86.tstate = TSTATE_E;
3.835 + }
3.836 + OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32
3.837 sh4_x86_translate_instruction(pc+2);
3.838 exit_block( disp + pc + 4, pc+4 );
3.839 // not taken
3.840 @@ -1373,6 +1505,7 @@
3.841 ADD_imm32_r32( pc + 4, R_EAX );
3.842 store_spreg( R_EAX, REG_OFFSET(pc) );
3.843 sh4_x86.in_delay_slot = TRUE;
3.844 + sh4_x86.tstate = TSTATE_NONE;
3.845 sh4_x86_translate_instruction( pc + 2 );
3.846 exit_block_pcset(pc+2);
3.847 sh4_x86.branch_taken = TRUE;
3.848 @@ -1401,6 +1534,7 @@
3.849 ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_ECX );
3.850 store_spreg( R_ECX, REG_OFFSET(pc) );
3.851 sh4_x86.in_delay_slot = TRUE;
3.852 + sh4_x86.tstate = TSTATE_NONE;
3.853 sh4_x86_translate_instruction( pc + 2 );
3.854 exit_block_pcset(pc+2);
3.855 sh4_x86.branch_taken = TRUE;
3.856 @@ -1411,8 +1545,7 @@
3.857 if( sh4_x86.in_delay_slot ) {
3.858 SLOTILLEGAL();
3.859 } else {
3.860 - CMP_imm8s_sh4r( 0, R_T );
3.861 - JE_rel8( 29, nottaken );
3.862 + JF_rel8( 29, nottaken );
3.863 exit_block( disp + pc + 4, pc+2 );
3.864 JMP_TARGET(nottaken);
3.865 return 2;
3.866 @@ -1423,8 +1556,11 @@
3.867 SLOTILLEGAL();
3.868 } else {
3.869 sh4_x86.in_delay_slot = TRUE;
3.870 - CMP_imm8s_sh4r( 0, R_T );
3.871 - OP(0x0F); OP(0x84); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
3.872 + if( sh4_x86.tstate == TSTATE_NONE ) {
3.873 + CMP_imm8s_sh4r( 1, R_T );
3.874 + sh4_x86.tstate = TSTATE_E;
3.875 + }
3.876 + OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
3.877 sh4_x86_translate_instruction(pc+2);
3.878 exit_block( disp + pc + 4, pc+4 );
3.879 // not taken
3.880 @@ -1473,6 +1609,7 @@
3.881 sh4_x86.in_delay_slot = TRUE;
3.882 sh4_x86.priv_checked = FALSE;
3.883 sh4_x86.fpuen_checked = FALSE;
3.884 + sh4_x86.tstate = TSTATE_NONE;
3.885 sh4_x86_translate_instruction(pc+2);
3.886 exit_block_pcset(pc+2);
3.887 sh4_x86.branch_taken = TRUE;
3.888 @@ -1499,6 +1636,7 @@
3.889 PUSH_imm32( imm );
3.890 call_func0( sh4_raise_trap );
3.891 ADD_imm8s_r32( 4, R_ESP );
3.892 + sh4_x86.tstate = TSTATE_NONE;
3.893 exit_block_pcset(pc);
3.894 sh4_x86.branch_taken = TRUE;
3.895 return 2;
3.896 @@ -1518,22 +1656,27 @@
3.897 XOR_r32_r32(R_EAX, R_EAX);
3.898 store_spreg( R_EAX, R_MACL );
3.899 store_spreg( R_EAX, R_MACH );
3.900 + sh4_x86.tstate = TSTATE_NONE;
3.901 :}
3.902 CLRS {:
3.903 CLC();
3.904 SETC_sh4r(R_S);
3.905 + sh4_x86.tstate = TSTATE_C;
3.906 :}
3.907 CLRT {:
3.908 CLC();
3.909 SETC_t();
3.910 + sh4_x86.tstate = TSTATE_C;
3.911 :}
3.912 SETS {:
3.913 STC();
3.914 SETC_sh4r(R_S);
3.915 + sh4_x86.tstate = TSTATE_C;
3.916 :}
3.917 SETT {:
3.918 STC();
3.919 SETC_t();
3.920 + sh4_x86.tstate = TSTATE_C;
3.921 :}
3.922
3.923 /* Floating point moves */
3.924 @@ -1585,6 +1728,7 @@
3.925 JMP_TARGET(end);
3.926 }
3.927 }
3.928 + sh4_x86.tstate = TSTATE_NONE;
3.929 :}
3.930 FMOV FRm, @Rn {:
3.931 precheck();
3.932 @@ -1614,6 +1758,7 @@
3.933 MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
3.934 JMP_TARGET(end);
3.935 }
3.936 + sh4_x86.tstate = TSTATE_NONE;
3.937 :}
3.938 FMOV @Rm, FRn {:
3.939 precheck();
3.940 @@ -1644,6 +1789,7 @@
3.941 store_fr( R_EDX, R_ECX, FRn|0x01 );
3.942 JMP_TARGET(end);
3.943 }
3.944 + sh4_x86.tstate = TSTATE_NONE;
3.945 :}
3.946 FMOV FRm, @-Rn {:
3.947 precheck();
3.948 @@ -1679,6 +1825,7 @@
3.949 MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
3.950 JMP_TARGET(end);
3.951 }
3.952 + sh4_x86.tstate = TSTATE_NONE;
3.953 :}
3.954 FMOV @Rm+, FRn {:
3.955 precheck();
3.956 @@ -1715,6 +1862,7 @@
3.957 store_fr( R_EDX, R_ECX, FRn|0x01 );
3.958 JMP_TARGET(end);
3.959 }
3.960 + sh4_x86.tstate = TSTATE_NONE;
3.961 :}
3.962 FMOV FRm, @(R0, Rn) {:
3.963 precheck();
3.964 @@ -1745,6 +1893,7 @@
3.965 MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
3.966 JMP_TARGET(end);
3.967 }
3.968 + sh4_x86.tstate = TSTATE_NONE;
3.969 :}
3.970 FMOV @(R0, Rm), FRn {:
3.971 precheck();
3.972 @@ -1776,6 +1925,7 @@
3.973 store_fr( R_EDX, R_ECX, FRn|0x01 );
3.974 JMP_TARGET(end);
3.975 }
3.976 + sh4_x86.tstate = TSTATE_NONE;
3.977 :}
3.978 FLDI0 FRn {: /* IFF PR=0 */
3.979 check_fpuen();
3.980 @@ -1786,6 +1936,7 @@
3.981 load_spreg( R_ECX, REG_OFFSET(fr_bank) );
3.982 store_fr( R_ECX, R_EAX, FRn );
3.983 JMP_TARGET(end);
3.984 + sh4_x86.tstate = TSTATE_NONE;
3.985 :}
3.986 FLDI1 FRn {: /* IFF PR=0 */
3.987 check_fpuen();
3.988 @@ -1796,6 +1947,7 @@
3.989 load_spreg( R_ECX, REG_OFFSET(fr_bank) );
3.990 store_fr( R_ECX, R_EAX, FRn );
3.991 JMP_TARGET(end);
3.992 + sh4_x86.tstate = TSTATE_NONE;
3.993 :}
3.994
3.995 FLOAT FPUL, FRn {:
3.996 @@ -1810,6 +1962,7 @@
3.997 JMP_TARGET(doubleprec);
3.998 pop_dr( R_EDX, FRn );
3.999 JMP_TARGET(end);
3.1000 + sh4_x86.tstate = TSTATE_NONE;
3.1001 :}
3.1002 FTRC FRm, FPUL {:
3.1003 check_fpuen();
3.1004 @@ -1844,18 +1997,21 @@
3.1005 store_spreg( R_ECX, R_FPUL );
3.1006 FPOP_st();
3.1007 JMP_TARGET(end);
3.1008 + sh4_x86.tstate = TSTATE_NONE;
3.1009 :}
3.1010 FLDS FRm, FPUL {:
3.1011 check_fpuen();
3.1012 load_fr_bank( R_ECX );
3.1013 load_fr( R_ECX, R_EAX, FRm );
3.1014 store_spreg( R_EAX, R_FPUL );
3.1015 + sh4_x86.tstate = TSTATE_NONE;
3.1016 :}
3.1017 FSTS FPUL, FRn {:
3.1018 check_fpuen();
3.1019 load_fr_bank( R_ECX );
3.1020 load_spreg( R_EAX, R_FPUL );
3.1021 store_fr( R_ECX, R_EAX, FRn );
3.1022 + sh4_x86.tstate = TSTATE_NONE;
3.1023 :}
3.1024 FCNVDS FRm, FPUL {:
3.1025 check_fpuen();
3.1026 @@ -1866,6 +2022,7 @@
3.1027 push_dr( R_ECX, FRm );
3.1028 pop_fpul();
3.1029 JMP_TARGET(end);
3.1030 + sh4_x86.tstate = TSTATE_NONE;
3.1031 :}
3.1032 FCNVSD FPUL, FRn {:
3.1033 check_fpuen();
3.1034 @@ -1876,6 +2033,7 @@
3.1035 push_fpul();
3.1036 pop_dr( R_ECX, FRn );
3.1037 JMP_TARGET(end);
3.1038 + sh4_x86.tstate = TSTATE_NONE;
3.1039 :}
3.1040
3.1041 /* Floating point instructions */
3.1042 @@ -1894,6 +2052,7 @@
3.1043 FABS_st0();
3.1044 pop_dr(R_EDX, FRn);
3.1045 JMP_TARGET(end);
3.1046 + sh4_x86.tstate = TSTATE_NONE;
3.1047 :}
3.1048 FADD FRm, FRn {:
3.1049 check_fpuen();
3.1050 @@ -1912,6 +2071,7 @@
3.1051 FADDP_st(1);
3.1052 pop_dr(R_EDX, FRn);
3.1053 JMP_TARGET(end);
3.1054 + sh4_x86.tstate = TSTATE_NONE;
3.1055 :}
3.1056 FDIV FRm, FRn {:
3.1057 check_fpuen();
3.1058 @@ -1930,6 +2090,7 @@
3.1059 FDIVP_st(1);
3.1060 pop_dr(R_EDX, FRn);
3.1061 JMP_TARGET(end);
3.1062 + sh4_x86.tstate = TSTATE_NONE;
3.1063 :}
3.1064 FMAC FR0, FRm, FRn {:
3.1065 check_fpuen();
3.1066 @@ -1952,6 +2113,7 @@
3.1067 FADDP_st(1);
3.1068 pop_dr( R_EDX, FRn );
3.1069 JMP_TARGET(end);
3.1070 + sh4_x86.tstate = TSTATE_NONE;
3.1071 :}
3.1072
3.1073 FMUL FRm, FRn {:
3.1074 @@ -1971,6 +2133,7 @@
3.1075 FMULP_st(1);
3.1076 pop_dr(R_EDX, FRn);
3.1077 JMP_TARGET(end);
3.1078 + sh4_x86.tstate = TSTATE_NONE;
3.1079 :}
3.1080 FNEG FRn {:
3.1081 check_fpuen();
3.1082 @@ -1987,6 +2150,7 @@
3.1083 FCHS_st0();
3.1084 pop_dr(R_EDX, FRn);
3.1085 JMP_TARGET(end);
3.1086 + sh4_x86.tstate = TSTATE_NONE;
3.1087 :}
3.1088 FSRRA FRn {:
3.1089 check_fpuen();
3.1090 @@ -2000,6 +2164,7 @@
3.1091 FDIVP_st(1);
3.1092 pop_fr(R_EDX, FRn);
3.1093 JMP_TARGET(end);
3.1094 + sh4_x86.tstate = TSTATE_NONE;
3.1095 :}
3.1096 FSQRT FRn {:
3.1097 check_fpuen();
3.1098 @@ -2016,6 +2181,7 @@
3.1099 FSQRT_st0();
3.1100 pop_dr(R_EDX, FRn);
3.1101 JMP_TARGET(end);
3.1102 + sh4_x86.tstate = TSTATE_NONE;
3.1103 :}
3.1104 FSUB FRm, FRn {:
3.1105 check_fpuen();
3.1106 @@ -2034,6 +2200,7 @@
3.1107 FSUBP_st(1);
3.1108 pop_dr(R_EDX, FRn);
3.1109 JMP_TARGET(end);
3.1110 + sh4_x86.tstate = TSTATE_NONE;
3.1111 :}
3.1112
3.1113 FCMP/EQ FRm, FRn {:
3.1114 @@ -2052,6 +2219,7 @@
3.1115 FCOMIP_st(1);
3.1116 SETE_t();
3.1117 FPOP_st();
3.1118 + sh4_x86.tstate = TSTATE_NONE;
3.1119 :}
3.1120 FCMP/GT FRm, FRn {:
3.1121 check_fpuen();
3.1122 @@ -2069,6 +2237,7 @@
3.1123 FCOMIP_st(1);
3.1124 SETA_t();
3.1125 FPOP_st();
3.1126 + sh4_x86.tstate = TSTATE_NONE;
3.1127 :}
3.1128
3.1129 FSCA FPUL, FRn {:
3.1130 @@ -2081,6 +2250,7 @@
3.1131 load_spreg( R_EDX, R_FPUL );
3.1132 call_func2( sh4_fsca, R_EDX, R_ECX );
3.1133 JMP_TARGET(doubleprec);
3.1134 + sh4_x86.tstate = TSTATE_NONE;
3.1135 :}
3.1136 FIPR FVm, FVn {:
3.1137 check_fpuen();
3.1138 @@ -2106,6 +2276,7 @@
3.1139 FADDP_st(1);
3.1140 pop_fr( R_ECX, (FVn<<2)+3);
3.1141 JMP_TARGET(doubleprec);
3.1142 + sh4_x86.tstate = TSTATE_NONE;
3.1143 :}
3.1144 FTRV XMTRX, FVn {:
3.1145 check_fpuen();
3.1146 @@ -2117,6 +2288,7 @@
3.1147 load_xf_bank( R_ECX ); // 12
3.1148 call_func2( sh4_ftrv, R_EDX, R_ECX ); // 12
3.1149 JMP_TARGET(doubleprec);
3.1150 + sh4_x86.tstate = TSTATE_NONE;
3.1151 :}
3.1152
3.1153 FRCHG {:
3.1154 @@ -2125,12 +2297,14 @@
3.1155 XOR_imm32_r32( FPSCR_FR, R_ECX );
3.1156 store_spreg( R_ECX, R_FPSCR );
3.1157 update_fr_bank( R_ECX );
3.1158 + sh4_x86.tstate = TSTATE_NONE;
3.1159 :}
3.1160 FSCHG {:
3.1161 check_fpuen();
3.1162 load_spreg( R_ECX, R_FPSCR );
3.1163 XOR_imm32_r32( FPSCR_SZ, R_ECX );
3.1164 store_spreg( R_ECX, R_FPSCR );
3.1165 + sh4_x86.tstate = TSTATE_NONE;
3.1166 :}
3.1167
3.1168 /* Processor control instructions */
3.1169 @@ -2143,6 +2317,7 @@
3.1170 call_func1( sh4_write_sr, R_EAX );
3.1171 sh4_x86.priv_checked = FALSE;
3.1172 sh4_x86.fpuen_checked = FALSE;
3.1173 + sh4_x86.tstate = TSTATE_NONE;
3.1174 }
3.1175 :}
3.1176 LDC Rm, GBR {:
3.1177 @@ -2153,31 +2328,37 @@
3.1178 check_priv();
3.1179 load_reg( R_EAX, Rm );
3.1180 store_spreg( R_EAX, R_VBR );
3.1181 + sh4_x86.tstate = TSTATE_NONE;
3.1182 :}
3.1183 LDC Rm, SSR {:
3.1184 check_priv();
3.1185 load_reg( R_EAX, Rm );
3.1186 store_spreg( R_EAX, R_SSR );
3.1187 + sh4_x86.tstate = TSTATE_NONE;
3.1188 :}
3.1189 LDC Rm, SGR {:
3.1190 check_priv();
3.1191 load_reg( R_EAX, Rm );
3.1192 store_spreg( R_EAX, R_SGR );
3.1193 + sh4_x86.tstate = TSTATE_NONE;
3.1194 :}
3.1195 LDC Rm, SPC {:
3.1196 check_priv();
3.1197 load_reg( R_EAX, Rm );
3.1198 store_spreg( R_EAX, R_SPC );
3.1199 + sh4_x86.tstate = TSTATE_NONE;
3.1200 :}
3.1201 LDC Rm, DBR {:
3.1202 check_priv();
3.1203 load_reg( R_EAX, Rm );
3.1204 store_spreg( R_EAX, R_DBR );
3.1205 + sh4_x86.tstate = TSTATE_NONE;
3.1206 :}
3.1207 LDC Rm, Rn_BANK {:
3.1208 check_priv();
3.1209 load_reg( R_EAX, Rm );
3.1210 store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
3.1211 + sh4_x86.tstate = TSTATE_NONE;
3.1212 :}
3.1213 LDC.L @Rm+, GBR {:
3.1214 load_reg( R_EAX, Rm );
3.1215 @@ -2188,6 +2369,7 @@
3.1216 store_reg( R_EAX, Rm );
3.1217 MEM_READ_LONG( R_ECX, R_EAX );
3.1218 store_spreg( R_EAX, R_GBR );
3.1219 + sh4_x86.tstate = TSTATE_NONE;
3.1220 :}
3.1221 LDC.L @Rm+, SR {:
3.1222 if( sh4_x86.in_delay_slot ) {
3.1223 @@ -2204,6 +2386,7 @@
3.1224 call_func1( sh4_write_sr, R_EAX );
3.1225 sh4_x86.priv_checked = FALSE;
3.1226 sh4_x86.fpuen_checked = FALSE;
3.1227 + sh4_x86.tstate = TSTATE_NONE;
3.1228 }
3.1229 :}
3.1230 LDC.L @Rm+, VBR {:
3.1231 @@ -2216,6 +2399,7 @@
3.1232 store_reg( R_EAX, Rm );
3.1233 MEM_READ_LONG( R_ECX, R_EAX );
3.1234 store_spreg( R_EAX, R_VBR );
3.1235 + sh4_x86.tstate = TSTATE_NONE;
3.1236 :}
3.1237 LDC.L @Rm+, SSR {:
3.1238 precheck();
3.1239 @@ -2227,6 +2411,7 @@
3.1240 store_reg( R_EAX, Rm );
3.1241 MEM_READ_LONG( R_ECX, R_EAX );
3.1242 store_spreg( R_EAX, R_SSR );
3.1243 + sh4_x86.tstate = TSTATE_NONE;
3.1244 :}
3.1245 LDC.L @Rm+, SGR {:
3.1246 precheck();
3.1247 @@ -2238,6 +2423,7 @@
3.1248 store_reg( R_EAX, Rm );
3.1249 MEM_READ_LONG( R_ECX, R_EAX );
3.1250 store_spreg( R_EAX, R_SGR );
3.1251 + sh4_x86.tstate = TSTATE_NONE;
3.1252 :}
3.1253 LDC.L @Rm+, SPC {:
3.1254 precheck();
3.1255 @@ -2249,6 +2435,7 @@
3.1256 store_reg( R_EAX, Rm );
3.1257 MEM_READ_LONG( R_ECX, R_EAX );
3.1258 store_spreg( R_EAX, R_SPC );
3.1259 + sh4_x86.tstate = TSTATE_NONE;
3.1260 :}
3.1261 LDC.L @Rm+, DBR {:
3.1262 precheck();
3.1263 @@ -2260,6 +2447,7 @@
3.1264 store_reg( R_EAX, Rm );
3.1265 MEM_READ_LONG( R_ECX, R_EAX );
3.1266 store_spreg( R_EAX, R_DBR );
3.1267 + sh4_x86.tstate = TSTATE_NONE;
3.1268 :}
3.1269 LDC.L @Rm+, Rn_BANK {:
3.1270 precheck();
3.1271 @@ -2271,11 +2459,13 @@
3.1272 store_reg( R_EAX, Rm );
3.1273 MEM_READ_LONG( R_ECX, R_EAX );
3.1274 store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
3.1275 + sh4_x86.tstate = TSTATE_NONE;
3.1276 :}
3.1277 LDS Rm, FPSCR {:
3.1278 load_reg( R_EAX, Rm );
3.1279 store_spreg( R_EAX, R_FPSCR );
3.1280 update_fr_bank( R_EAX );
3.1281 + sh4_x86.tstate = TSTATE_NONE;
3.1282 :}
3.1283 LDS.L @Rm+, FPSCR {:
3.1284 load_reg( R_EAX, Rm );
3.1285 @@ -2287,6 +2477,7 @@
3.1286 MEM_READ_LONG( R_ECX, R_EAX );
3.1287 store_spreg( R_EAX, R_FPSCR );
3.1288 update_fr_bank( R_EAX );
3.1289 + sh4_x86.tstate = TSTATE_NONE;
3.1290 :}
3.1291 LDS Rm, FPUL {:
3.1292 load_reg( R_EAX, Rm );
3.1293 @@ -2301,6 +2492,7 @@
3.1294 store_reg( R_EAX, Rm );
3.1295 MEM_READ_LONG( R_ECX, R_EAX );
3.1296 store_spreg( R_EAX, R_FPUL );
3.1297 + sh4_x86.tstate = TSTATE_NONE;
3.1298 :}
3.1299 LDS Rm, MACH {:
3.1300 load_reg( R_EAX, Rm );
3.1301 @@ -2315,6 +2507,7 @@
3.1302 store_reg( R_EAX, Rm );
3.1303 MEM_READ_LONG( R_ECX, R_EAX );
3.1304 store_spreg( R_EAX, R_MACH );
3.1305 + sh4_x86.tstate = TSTATE_NONE;
3.1306 :}
3.1307 LDS Rm, MACL {:
3.1308 load_reg( R_EAX, Rm );
3.1309 @@ -2329,6 +2522,7 @@
3.1310 store_reg( R_EAX, Rm );
3.1311 MEM_READ_LONG( R_ECX, R_EAX );
3.1312 store_spreg( R_EAX, R_MACL );
3.1313 + sh4_x86.tstate = TSTATE_NONE;
3.1314 :}
3.1315 LDS Rm, PR {:
3.1316 load_reg( R_EAX, Rm );
3.1317 @@ -2343,6 +2537,7 @@
3.1318 store_reg( R_EAX, Rm );
3.1319 MEM_READ_LONG( R_ECX, R_EAX );
3.1320 store_spreg( R_EAX, R_PR );
3.1321 + sh4_x86.tstate = TSTATE_NONE;
3.1322 :}
3.1323 LDTLB {: :}
3.1324 OCBI @Rn {: :}
3.1325 @@ -2357,10 +2552,12 @@
3.1326 call_func0( sh4_flush_store_queue );
3.1327 JMP_TARGET(end);
3.1328 ADD_imm8s_r32( 4, R_ESP );
3.1329 + sh4_x86.tstate = TSTATE_NONE;
3.1330 :}
3.1331 SLEEP {:
3.1332 check_priv();
3.1333 call_func0( sh4_sleep );
3.1334 + sh4_x86.tstate = TSTATE_NONE;
3.1335 sh4_x86.in_delay_slot = FALSE;
3.1336 return 2;
3.1337 :}
3.1338 @@ -2368,6 +2565,7 @@
3.1339 check_priv();
3.1340 call_func0(sh4_read_sr);
3.1341 store_reg( R_EAX, Rn );
3.1342 + sh4_x86.tstate = TSTATE_NONE;
3.1343 :}
3.1344 STC GBR, Rn {:
3.1345 load_spreg( R_EAX, R_GBR );
3.1346 @@ -2377,31 +2575,37 @@
3.1347 check_priv();
3.1348 load_spreg( R_EAX, R_VBR );
3.1349 store_reg( R_EAX, Rn );
3.1350 + sh4_x86.tstate = TSTATE_NONE;
3.1351 :}
3.1352 STC SSR, Rn {:
3.1353 check_priv();
3.1354 load_spreg( R_EAX, R_SSR );
3.1355 store_reg( R_EAX, Rn );
3.1356 + sh4_x86.tstate = TSTATE_NONE;
3.1357 :}
3.1358 STC SPC, Rn {:
3.1359 check_priv();
3.1360 load_spreg( R_EAX, R_SPC );
3.1361 store_reg( R_EAX, Rn );
3.1362 + sh4_x86.tstate = TSTATE_NONE;
3.1363 :}
3.1364 STC SGR, Rn {:
3.1365 check_priv();
3.1366 load_spreg( R_EAX, R_SGR );
3.1367 store_reg( R_EAX, Rn );
3.1368 + sh4_x86.tstate = TSTATE_NONE;
3.1369 :}
3.1370 STC DBR, Rn {:
3.1371 check_priv();
3.1372 load_spreg( R_EAX, R_DBR );
3.1373 store_reg( R_EAX, Rn );
3.1374 + sh4_x86.tstate = TSTATE_NONE;
3.1375 :}
3.1376 STC Rm_BANK, Rn {:
3.1377 check_priv();
3.1378 load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
3.1379 store_reg( R_EAX, Rn );
3.1380 + sh4_x86.tstate = TSTATE_NONE;
3.1381 :}
3.1382 STC.L SR, @-Rn {:
3.1383 precheck();
3.1384 @@ -2412,6 +2616,7 @@
3.1385 ADD_imm8s_r32( -4, R_ECX );
3.1386 store_reg( R_ECX, Rn );
3.1387 MEM_WRITE_LONG( R_ECX, R_EAX );
3.1388 + sh4_x86.tstate = TSTATE_NONE;
3.1389 :}
3.1390 STC.L VBR, @-Rn {:
3.1391 precheck();
3.1392 @@ -2422,6 +2627,7 @@
3.1393 store_reg( R_ECX, Rn );
3.1394 load_spreg( R_EAX, R_VBR );
3.1395 MEM_WRITE_LONG( R_ECX, R_EAX );
3.1396 + sh4_x86.tstate = TSTATE_NONE;
3.1397 :}
3.1398 STC.L SSR, @-Rn {:
3.1399 precheck();
3.1400 @@ -2432,6 +2638,7 @@
3.1401 store_reg( R_ECX, Rn );
3.1402 load_spreg( R_EAX, R_SSR );
3.1403 MEM_WRITE_LONG( R_ECX, R_EAX );
3.1404 + sh4_x86.tstate = TSTATE_NONE;
3.1405 :}
3.1406 STC.L SPC, @-Rn {:
3.1407 precheck();
3.1408 @@ -2442,6 +2649,7 @@
3.1409 store_reg( R_ECX, Rn );
3.1410 load_spreg( R_EAX, R_SPC );
3.1411 MEM_WRITE_LONG( R_ECX, R_EAX );
3.1412 + sh4_x86.tstate = TSTATE_NONE;
3.1413 :}
3.1414 STC.L SGR, @-Rn {:
3.1415 precheck();
3.1416 @@ -2452,6 +2660,7 @@
3.1417 store_reg( R_ECX, Rn );
3.1418 load_spreg( R_EAX, R_SGR );
3.1419 MEM_WRITE_LONG( R_ECX, R_EAX );
3.1420 + sh4_x86.tstate = TSTATE_NONE;
3.1421 :}
3.1422 STC.L DBR, @-Rn {:
3.1423 precheck();
3.1424 @@ -2462,6 +2671,7 @@
3.1425 store_reg( R_ECX, Rn );
3.1426 load_spreg( R_EAX, R_DBR );
3.1427 MEM_WRITE_LONG( R_ECX, R_EAX );
3.1428 + sh4_x86.tstate = TSTATE_NONE;
3.1429 :}
3.1430 STC.L Rm_BANK, @-Rn {:
3.1431 precheck();
3.1432 @@ -2472,6 +2682,7 @@
3.1433 store_reg( R_ECX, Rn );
3.1434 load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
3.1435 MEM_WRITE_LONG( R_ECX, R_EAX );
3.1436 + sh4_x86.tstate = TSTATE_NONE;
3.1437 :}
3.1438 STC.L GBR, @-Rn {:
3.1439 load_reg( R_ECX, Rn );
3.1440 @@ -2481,6 +2692,7 @@
3.1441 store_reg( R_ECX, Rn );
3.1442 load_spreg( R_EAX, R_GBR );
3.1443 MEM_WRITE_LONG( R_ECX, R_EAX );
3.1444 + sh4_x86.tstate = TSTATE_NONE;
3.1445 :}
3.1446 STS FPSCR, Rn {:
3.1447 load_spreg( R_EAX, R_FPSCR );
3.1448 @@ -2494,6 +2706,7 @@
3.1449 store_reg( R_ECX, Rn );
3.1450 load_spreg( R_EAX, R_FPSCR );
3.1451 MEM_WRITE_LONG( R_ECX, R_EAX );
3.1452 + sh4_x86.tstate = TSTATE_NONE;
3.1453 :}
3.1454 STS FPUL, Rn {:
3.1455 load_spreg( R_EAX, R_FPUL );
3.1456 @@ -2507,6 +2720,7 @@
3.1457 store_reg( R_ECX, Rn );
3.1458 load_spreg( R_EAX, R_FPUL );
3.1459 MEM_WRITE_LONG( R_ECX, R_EAX );
3.1460 + sh4_x86.tstate = TSTATE_NONE;
3.1461 :}
3.1462 STS MACH, Rn {:
3.1463 load_spreg( R_EAX, R_MACH );
3.1464 @@ -2520,6 +2734,7 @@
3.1465 store_reg( R_ECX, Rn );
3.1466 load_spreg( R_EAX, R_MACH );
3.1467 MEM_WRITE_LONG( R_ECX, R_EAX );
3.1468 + sh4_x86.tstate = TSTATE_NONE;
3.1469 :}
3.1470 STS MACL, Rn {:
3.1471 load_spreg( R_EAX, R_MACL );
3.1472 @@ -2533,6 +2748,7 @@
3.1473 store_reg( R_ECX, Rn );
3.1474 load_spreg( R_EAX, R_MACL );
3.1475 MEM_WRITE_LONG( R_ECX, R_EAX );
3.1476 + sh4_x86.tstate = TSTATE_NONE;
3.1477 :}
3.1478 STS PR, Rn {:
3.1479 load_spreg( R_EAX, R_PR );
3.1480 @@ -2546,6 +2762,7 @@
3.1481 store_reg( R_ECX, Rn );
3.1482 load_spreg( R_EAX, R_PR );
3.1483 MEM_WRITE_LONG( R_ECX, R_EAX );
3.1484 + sh4_x86.tstate = TSTATE_NONE;
3.1485 :}
3.1486
3.1487 NOP {: /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */ :}
.