lxdream 0.9.1revision 395:c473acbde186
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raw | bz2 | zip | gz | changeset | 395:c473acbde186 |
| parent | 394:7eb172bfeefe |
| child | 396:0738dbc01d95 |
| author | nkeynes |
| date | Wed Sep 19 10:04:16 2007 +0000 (14 years ago) |
Add alignment checks to LDC.L/STC.L/LDS.L/STS.L
 | src/sh4/sh4x86.c | view | annotate | diff | log | |
| src/sh4/sh4x86.in | view | annotate | diff | log |
1.1 --- a/src/sh4/sh4x86.c Wed Sep 19 09:15:18 2007 +00001.2 +++ b/src/sh4/sh4x86.c Wed Sep 19 10:04:16 2007 +00001.3 @@ -1,5 +1,5 @@1.4 /**1.5 - * $Id: sh4x86.c,v 1.11 2007-09-19 09:15:18 nkeynes Exp $1.6 + * $Id: sh4x86.c,v 1.12 2007-09-19 10:04:16 nkeynes Exp $1.7 *1.8 * SH4 => x86 translation. This version does no real optimization, it just1.9 * outputs straight-line x86 code - it mainly exists to provide a baseline1.10 @@ -1328,6 +1328,7 @@1.11 { /* STS.L MACH, @-Rn */1.12 uint32_t Rn = ((ir>>8)&0xF);1.13 load_reg( R_ECX, Rn );1.14 + check_walign32( R_ECX );1.15 ADD_imm8s_r32( -4, R_ECX );1.16 store_reg( R_ECX, Rn );1.17 load_spreg( R_EAX, R_MACH );1.18 @@ -1338,6 +1339,7 @@1.19 { /* STS.L MACL, @-Rn */1.20 uint32_t Rn = ((ir>>8)&0xF);1.21 load_reg( R_ECX, Rn );1.22 + check_walign32( R_ECX );1.23 ADD_imm8s_r32( -4, R_ECX );1.24 store_reg( R_ECX, Rn );1.25 load_spreg( R_EAX, R_MACL );1.26 @@ -1348,6 +1350,7 @@1.27 { /* STS.L PR, @-Rn */1.28 uint32_t Rn = ((ir>>8)&0xF);1.29 load_reg( R_ECX, Rn );1.30 + check_walign32( R_ECX );1.31 ADD_imm8s_r32( -4, R_ECX );1.32 store_reg( R_ECX, Rn );1.33 load_spreg( R_EAX, R_PR );1.34 @@ -1359,6 +1362,7 @@1.35 uint32_t Rn = ((ir>>8)&0xF);1.36 check_priv();1.37 load_reg( R_ECX, Rn );1.38 + check_walign32( R_ECX );1.39 ADD_imm8s_r32( -4, R_ECX );1.40 store_reg( R_ECX, Rn );1.41 load_spreg( R_EAX, R_SGR );1.42 @@ -1369,6 +1373,7 @@1.43 { /* STS.L FPUL, @-Rn */1.44 uint32_t Rn = ((ir>>8)&0xF);1.45 load_reg( R_ECX, Rn );1.46 + check_walign32( R_ECX );1.47 ADD_imm8s_r32( -4, R_ECX );1.48 store_reg( R_ECX, Rn );1.49 load_spreg( R_EAX, R_FPUL );1.50 @@ -1379,6 +1384,7 @@1.51 { /* STS.L FPSCR, @-Rn */1.52 uint32_t Rn = ((ir>>8)&0xF);1.53 load_reg( R_ECX, Rn );1.54 + check_walign32( R_ECX );1.55 ADD_imm8s_r32( -4, R_ECX );1.56 store_reg( R_ECX, Rn );1.57 load_spreg( R_EAX, R_FPSCR );1.58 @@ -1390,6 +1396,7 @@1.59 uint32_t Rn = ((ir>>8)&0xF);1.60 check_priv();1.61 load_reg( R_ECX, Rn );1.62 + check_walign32( R_ECX );1.63 ADD_imm8s_r32( -4, R_ECX );1.64 store_reg( R_ECX, Rn );1.65 load_spreg( R_EAX, R_DBR );1.66 @@ -1409,10 +1416,11 @@1.67 { /* STC.L SR, @-Rn */1.68 uint32_t Rn = ((ir>>8)&0xF);1.69 check_priv();1.70 + call_func0( sh4_read_sr );1.71 load_reg( R_ECX, Rn );1.72 + check_walign32( R_ECX );1.73 ADD_imm8s_r32( -4, R_ECX );1.74 store_reg( R_ECX, Rn );1.75 - call_func0( sh4_read_sr );1.76 MEM_WRITE_LONG( R_ECX, R_EAX );1.77 }1.78 break;1.79 @@ -1420,6 +1428,7 @@1.80 { /* STC.L GBR, @-Rn */1.81 uint32_t Rn = ((ir>>8)&0xF);1.82 load_reg( R_ECX, Rn );1.83 + check_walign32( R_ECX );1.84 ADD_imm8s_r32( -4, R_ECX );1.85 store_reg( R_ECX, Rn );1.86 load_spreg( R_EAX, R_GBR );1.87 @@ -1431,6 +1440,7 @@1.88 uint32_t Rn = ((ir>>8)&0xF);1.89 check_priv();1.90 load_reg( R_ECX, Rn );1.91 + check_walign32( R_ECX );1.92 ADD_imm8s_r32( -4, R_ECX );1.93 store_reg( R_ECX, Rn );1.94 load_spreg( R_EAX, R_VBR );1.95 @@ -1442,6 +1452,7 @@1.96 uint32_t Rn = ((ir>>8)&0xF);1.97 check_priv();1.98 load_reg( R_ECX, Rn );1.99 + check_walign32( R_ECX );1.100 ADD_imm8s_r32( -4, R_ECX );1.101 store_reg( R_ECX, Rn );1.102 load_spreg( R_EAX, R_SSR );1.103 @@ -1453,6 +1464,7 @@1.104 uint32_t Rn = ((ir>>8)&0xF);1.105 check_priv();1.106 load_reg( R_ECX, Rn );1.107 + check_walign32( R_ECX );1.108 ADD_imm8s_r32( -4, R_ECX );1.109 store_reg( R_ECX, Rn );1.110 load_spreg( R_EAX, R_SPC );1.111 @@ -1469,6 +1481,7 @@1.112 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);1.113 check_priv();1.114 load_reg( R_ECX, Rn );1.115 + check_walign32( R_ECX );1.116 ADD_imm8s_r32( -4, R_ECX );1.117 store_reg( R_ECX, Rn );1.118 load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );1.119 @@ -1543,6 +1556,7 @@1.120 { /* LDS.L @Rm+, MACH */1.121 uint32_t Rm = ((ir>>8)&0xF);1.122 load_reg( R_EAX, Rm );1.123 + check_ralign32( R_EAX );1.124 MOV_r32_r32( R_EAX, R_ECX );1.125 ADD_imm8s_r32( 4, R_EAX );1.126 store_reg( R_EAX, Rm );1.127 @@ -1554,6 +1568,7 @@1.128 { /* LDS.L @Rm+, MACL */1.129 uint32_t Rm = ((ir>>8)&0xF);1.130 load_reg( R_EAX, Rm );1.131 + check_ralign32( R_EAX );1.132 MOV_r32_r32( R_EAX, R_ECX );1.133 ADD_imm8s_r32( 4, R_EAX );1.134 store_reg( R_EAX, Rm );1.135 @@ -1565,6 +1580,7 @@1.136 { /* LDS.L @Rm+, PR */1.137 uint32_t Rm = ((ir>>8)&0xF);1.138 load_reg( R_EAX, Rm );1.139 + check_ralign32( R_EAX );1.140 MOV_r32_r32( R_EAX, R_ECX );1.141 ADD_imm8s_r32( 4, R_EAX );1.142 store_reg( R_EAX, Rm );1.143 @@ -1577,6 +1593,7 @@1.144 uint32_t Rm = ((ir>>8)&0xF);1.145 check_priv();1.146 load_reg( R_EAX, Rm );1.147 + check_ralign32( R_EAX );1.148 MOV_r32_r32( R_EAX, R_ECX );1.149 ADD_imm8s_r32( 4, R_EAX );1.150 store_reg( R_EAX, Rm );1.151 @@ -1588,6 +1605,7 @@1.152 { /* LDS.L @Rm+, FPUL */1.153 uint32_t Rm = ((ir>>8)&0xF);1.154 load_reg( R_EAX, Rm );1.155 + check_ralign32( R_EAX );1.156 MOV_r32_r32( R_EAX, R_ECX );1.157 ADD_imm8s_r32( 4, R_EAX );1.158 store_reg( R_EAX, Rm );1.159 @@ -1599,6 +1617,7 @@1.160 { /* LDS.L @Rm+, FPSCR */1.161 uint32_t Rm = ((ir>>8)&0xF);1.162 load_reg( R_EAX, Rm );1.163 + check_ralign32( R_EAX );1.164 MOV_r32_r32( R_EAX, R_ECX );1.165 ADD_imm8s_r32( 4, R_EAX );1.166 store_reg( R_EAX, Rm );1.167 @@ -1612,6 +1631,7 @@1.168 uint32_t Rm = ((ir>>8)&0xF);1.169 check_priv();1.170 load_reg( R_EAX, Rm );1.171 + check_ralign32( R_EAX );1.172 MOV_r32_r32( R_EAX, R_ECX );1.173 ADD_imm8s_r32( 4, R_EAX );1.174 store_reg( R_EAX, Rm );1.175 @@ -1636,6 +1656,7 @@1.176 } else {1.177 check_priv();1.178 load_reg( R_EAX, Rm );1.179 + check_ralign32( R_EAX );1.180 MOV_r32_r32( R_EAX, R_ECX );1.181 ADD_imm8s_r32( 4, R_EAX );1.182 store_reg( R_EAX, Rm );1.183 @@ -1650,6 +1671,7 @@1.184 { /* LDC.L @Rm+, GBR */1.185 uint32_t Rm = ((ir>>8)&0xF);1.186 load_reg( R_EAX, Rm );1.187 + check_ralign32( R_EAX );1.188 MOV_r32_r32( R_EAX, R_ECX );1.189 ADD_imm8s_r32( 4, R_EAX );1.190 store_reg( R_EAX, Rm );1.191 @@ -1662,6 +1684,7 @@1.192 uint32_t Rm = ((ir>>8)&0xF);1.193 check_priv();1.194 load_reg( R_EAX, Rm );1.195 + check_ralign32( R_EAX );1.196 MOV_r32_r32( R_EAX, R_ECX );1.197 ADD_imm8s_r32( 4, R_EAX );1.198 store_reg( R_EAX, Rm );1.199 @@ -1686,6 +1709,7 @@1.200 uint32_t Rm = ((ir>>8)&0xF);1.201 check_priv();1.202 load_reg( R_EAX, Rm );1.203 + check_ralign32( R_EAX );1.204 MOV_r32_r32( R_EAX, R_ECX );1.205 ADD_imm8s_r32( 4, R_EAX );1.206 store_reg( R_EAX, Rm );1.207 @@ -1703,6 +1727,7 @@1.208 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);1.209 check_priv();1.210 load_reg( R_EAX, Rm );1.211 + check_ralign32( R_EAX );1.212 MOV_r32_r32( R_EAX, R_ECX );1.213 ADD_imm8s_r32( 4, R_EAX );1.214 store_reg( R_EAX, Rm );
2.1 --- a/src/sh4/sh4x86.in Wed Sep 19 09:15:18 2007 +00002.2 +++ b/src/sh4/sh4x86.in Wed Sep 19 10:04:16 2007 +00002.3 @@ -1,5 +1,5 @@2.4 /**2.5 - * $Id: sh4x86.in,v 1.12 2007-09-19 09:15:18 nkeynes Exp $2.6 + * $Id: sh4x86.in,v 1.13 2007-09-19 10:04:16 nkeynes Exp $2.7 *2.8 * SH4 => x86 translation. This version does no real optimization, it just2.9 * outputs straight-line x86 code - it mainly exists to provide a baseline2.10 @@ -2120,6 +2120,7 @@2.11 :}2.12 LDC.L @Rm+, GBR {:2.13 load_reg( R_EAX, Rm );2.14 + check_ralign32( R_EAX );2.15 MOV_r32_r32( R_EAX, R_ECX );2.16 ADD_imm8s_r32( 4, R_EAX );2.17 store_reg( R_EAX, Rm );2.18 @@ -2132,6 +2133,7 @@2.19 } else {2.20 check_priv();2.21 load_reg( R_EAX, Rm );2.22 + check_ralign32( R_EAX );2.23 MOV_r32_r32( R_EAX, R_ECX );2.24 ADD_imm8s_r32( 4, R_EAX );2.25 store_reg( R_EAX, Rm );2.26 @@ -2144,6 +2146,7 @@2.27 LDC.L @Rm+, VBR {:2.28 check_priv();2.29 load_reg( R_EAX, Rm );2.30 + check_ralign32( R_EAX );2.31 MOV_r32_r32( R_EAX, R_ECX );2.32 ADD_imm8s_r32( 4, R_EAX );2.33 store_reg( R_EAX, Rm );2.34 @@ -2162,6 +2165,7 @@2.35 LDC.L @Rm+, SGR {:2.36 check_priv();2.37 load_reg( R_EAX, Rm );2.38 + check_ralign32( R_EAX );2.39 MOV_r32_r32( R_EAX, R_ECX );2.40 ADD_imm8s_r32( 4, R_EAX );2.41 store_reg( R_EAX, Rm );2.42 @@ -2171,6 +2175,7 @@2.43 LDC.L @Rm+, SPC {:2.44 check_priv();2.45 load_reg( R_EAX, Rm );2.46 + check_ralign32( R_EAX );2.47 MOV_r32_r32( R_EAX, R_ECX );2.48 ADD_imm8s_r32( 4, R_EAX );2.49 store_reg( R_EAX, Rm );2.50 @@ -2180,6 +2185,7 @@2.51 LDC.L @Rm+, DBR {:2.52 check_priv();2.53 load_reg( R_EAX, Rm );2.54 + check_ralign32( R_EAX );2.55 MOV_r32_r32( R_EAX, R_ECX );2.56 ADD_imm8s_r32( 4, R_EAX );2.57 store_reg( R_EAX, Rm );2.58 @@ -2189,6 +2195,7 @@2.59 LDC.L @Rm+, Rn_BANK {:2.60 check_priv();2.61 load_reg( R_EAX, Rm );2.62 + check_ralign32( R_EAX );2.63 MOV_r32_r32( R_EAX, R_ECX );2.64 ADD_imm8s_r32( 4, R_EAX );2.65 store_reg( R_EAX, Rm );2.66 @@ -2202,6 +2209,7 @@2.67 :}2.68 LDS.L @Rm+, FPSCR {:2.69 load_reg( R_EAX, Rm );2.70 + check_ralign32( R_EAX );2.71 MOV_r32_r32( R_EAX, R_ECX );2.72 ADD_imm8s_r32( 4, R_EAX );2.73 store_reg( R_EAX, Rm );2.74 @@ -2215,6 +2223,7 @@2.75 :}2.76 LDS.L @Rm+, FPUL {:2.77 load_reg( R_EAX, Rm );2.78 + check_ralign32( R_EAX );2.79 MOV_r32_r32( R_EAX, R_ECX );2.80 ADD_imm8s_r32( 4, R_EAX );2.81 store_reg( R_EAX, Rm );2.82 @@ -2227,6 +2236,7 @@2.83 :}2.84 LDS.L @Rm+, MACH {:2.85 load_reg( R_EAX, Rm );2.86 + check_ralign32( R_EAX );2.87 MOV_r32_r32( R_EAX, R_ECX );2.88 ADD_imm8s_r32( 4, R_EAX );2.89 store_reg( R_EAX, Rm );2.90 @@ -2239,6 +2249,7 @@2.91 :}2.92 LDS.L @Rm+, MACL {:2.93 load_reg( R_EAX, Rm );2.94 + check_ralign32( R_EAX );2.95 MOV_r32_r32( R_EAX, R_ECX );2.96 ADD_imm8s_r32( 4, R_EAX );2.97 store_reg( R_EAX, Rm );2.98 @@ -2251,6 +2262,7 @@2.99 :}2.100 LDS.L @Rm+, PR {:2.101 load_reg( R_EAX, Rm );2.102 + check_ralign32( R_EAX );2.103 MOV_r32_r32( R_EAX, R_ECX );2.104 ADD_imm8s_r32( 4, R_EAX );2.105 store_reg( R_EAX, Rm );2.106 @@ -2320,15 +2332,17 @@2.107 :}2.108 STC.L SR, @-Rn {:2.109 check_priv();2.110 + call_func0( sh4_read_sr );2.111 load_reg( R_ECX, Rn );2.112 + check_walign32( R_ECX );2.113 ADD_imm8s_r32( -4, R_ECX );2.114 store_reg( R_ECX, Rn );2.115 - call_func0( sh4_read_sr );2.116 MEM_WRITE_LONG( R_ECX, R_EAX );2.117 :}2.118 STC.L VBR, @-Rn {:2.119 check_priv();2.120 load_reg( R_ECX, Rn );2.121 + check_walign32( R_ECX );2.122 ADD_imm8s_r32( -4, R_ECX );2.123 store_reg( R_ECX, Rn );2.124 load_spreg( R_EAX, R_VBR );2.125 @@ -2337,6 +2351,7 @@2.126 STC.L SSR, @-Rn {:2.127 check_priv();2.128 load_reg( R_ECX, Rn );2.129 + check_walign32( R_ECX );2.130 ADD_imm8s_r32( -4, R_ECX );2.131 store_reg( R_ECX, Rn );2.132 load_spreg( R_EAX, R_SSR );2.133 @@ -2345,6 +2360,7 @@2.134 STC.L SPC, @-Rn {:2.135 check_priv();2.136 load_reg( R_ECX, Rn );2.137 + check_walign32( R_ECX );2.138 ADD_imm8s_r32( -4, R_ECX );2.139 store_reg( R_ECX, Rn );2.140 load_spreg( R_EAX, R_SPC );2.141 @@ -2353,6 +2369,7 @@2.142 STC.L SGR, @-Rn {:2.143 check_priv();2.144 load_reg( R_ECX, Rn );2.145 + check_walign32( R_ECX );2.146 ADD_imm8s_r32( -4, R_ECX );2.147 store_reg( R_ECX, Rn );2.148 load_spreg( R_EAX, R_SGR );2.149 @@ -2361,6 +2378,7 @@2.150 STC.L DBR, @-Rn {:2.151 check_priv();2.152 load_reg( R_ECX, Rn );2.153 + check_walign32( R_ECX );2.154 ADD_imm8s_r32( -4, R_ECX );2.155 store_reg( R_ECX, Rn );2.156 load_spreg( R_EAX, R_DBR );2.157 @@ -2369,6 +2387,7 @@2.158 STC.L Rm_BANK, @-Rn {:2.159 check_priv();2.160 load_reg( R_ECX, Rn );2.161 + check_walign32( R_ECX );2.162 ADD_imm8s_r32( -4, R_ECX );2.163 store_reg( R_ECX, Rn );2.164 load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );2.165 @@ -2376,6 +2395,7 @@2.166 :}2.167 STC.L GBR, @-Rn {:2.168 load_reg( R_ECX, Rn );2.169 + check_walign32( R_ECX );2.170 ADD_imm8s_r32( -4, R_ECX );2.171 store_reg( R_ECX, Rn );2.172 load_spreg( R_EAX, R_GBR );2.173 @@ -2387,6 +2407,7 @@2.174 :}2.175 STS.L FPSCR, @-Rn {:2.176 load_reg( R_ECX, Rn );2.177 + check_walign32( R_ECX );2.178 ADD_imm8s_r32( -4, R_ECX );2.179 store_reg( R_ECX, Rn );2.180 load_spreg( R_EAX, R_FPSCR );2.181 @@ -2398,6 +2419,7 @@2.182 :}2.183 STS.L FPUL, @-Rn {:2.184 load_reg( R_ECX, Rn );2.185 + check_walign32( R_ECX );2.186 ADD_imm8s_r32( -4, R_ECX );2.187 store_reg( R_ECX, Rn );2.188 load_spreg( R_EAX, R_FPUL );2.189 @@ -2409,6 +2431,7 @@2.190 :}2.191 STS.L MACH, @-Rn {:2.192 load_reg( R_ECX, Rn );2.193 + check_walign32( R_ECX );2.194 ADD_imm8s_r32( -4, R_ECX );2.195 store_reg( R_ECX, Rn );2.196 load_spreg( R_EAX, R_MACH );2.197 @@ -2420,6 +2443,7 @@2.198 :}2.199 STS.L MACL, @-Rn {:2.200 load_reg( R_ECX, Rn );2.201 + check_walign32( R_ECX );2.202 ADD_imm8s_r32( -4, R_ECX );2.203 store_reg( R_ECX, Rn );2.204 load_spreg( R_EAX, R_MACL );2.205 @@ -2431,6 +2455,7 @@2.206 :}2.207 STS.L PR, @-Rn {:2.208 load_reg( R_ECX, Rn );2.209 + check_walign32( R_ECX );2.210 ADD_imm8s_r32( -4, R_ECX );2.211 store_reg( R_ECX, Rn );2.212 load_spreg( R_EAX, R_PR );
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