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lxdream.org :: lxdream :: r260:c82e26ec0cac
lxdream 0.9.1
released Jun 29
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changeset260:c82e26ec0cac
parent259:7c6881790cc2
child261:93fdb2a70e18
authornkeynes
dateWed Jan 03 09:00:17 2007 +0000 (13 years ago)
Adjust timers when they're read rather than waiting until the next time
slice. Also temporarily cut the CPU time by 4.
Initialize the FRQCR register to 0x0E0A for convenience
src/sh4/sh4core.c
src/sh4/sh4core.h
src/sh4/timer.c
1.1 --- a/src/sh4/sh4core.c Fri Dec 29 00:24:43 2006 +0000
1.2 +++ b/src/sh4/sh4core.c Wed Jan 03 09:00:17 2007 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: sh4core.c,v 1.35 2006-12-19 09:54:03 nkeynes Exp $
1.6 + * $Id: sh4core.c,v 1.36 2007-01-03 09:00:17 nkeynes Exp $
1.7 *
1.8 * SH4 emulation core, and parent module for all the SH4 peripheral
1.9 * modules.
1.10 @@ -90,6 +90,7 @@
1.11 MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
1.12
1.13 /* Peripheral modules */
1.14 + CPG_reset();
1.15 INTC_reset();
1.16 TMU_reset();
1.17 SCIF_reset();
2.1 --- a/src/sh4/sh4core.h Fri Dec 29 00:24:43 2006 +0000
2.2 +++ b/src/sh4/sh4core.h Wed Jan 03 09:00:17 2007 +0000
2.3 @@ -1,5 +1,5 @@
2.4 /**
2.5 - * $Id: sh4core.h,v 1.14 2006-12-19 09:54:03 nkeynes Exp $
2.6 + * $Id: sh4core.h,v 1.15 2007-01-03 09:00:17 nkeynes Exp $
2.7 *
2.8 * This file defines the internal functions exported/used by the SH4 core,
2.9 * except for disassembly functions defined in sh4dasm.h
2.10 @@ -107,6 +107,7 @@
2.11 int32_t sh4_read_phys_word( uint32_t addr );
2.12
2.13 /* Peripheral functions */
2.14 +void CPG_reset( void );
2.15 void TMU_run_slice( uint32_t );
2.16 void TMU_update_clocks( void );
2.17 void TMU_reset( void );
3.1 --- a/src/sh4/timer.c Fri Dec 29 00:24:43 2006 +0000
3.2 +++ b/src/sh4/timer.c Wed Jan 03 09:00:17 2007 +0000
3.3 @@ -1,5 +1,5 @@
3.4 /**
3.5 - * $Id: timer.c,v 1.4 2006-03-17 12:13:12 nkeynes Exp $
3.6 + * $Id: timer.c,v 1.5 2007-01-03 09:00:17 nkeynes Exp $
3.7 *
3.8 * SH4 Timer/Clock peripheral modules (CPG, TMU, RTC), combined together to
3.9 * keep things simple (they intertwine a bit).
3.10 @@ -53,7 +53,7 @@
3.11 case FRQCR: /* Frequency control */
3.12 div = ifc_divider[(val >> 6) & 0x07];
3.13 sh4_cpu_freq = sh4_input_freq / div;
3.14 - sh4_cpu_period = 1000 * div / sh4_input_freq;
3.15 + sh4_cpu_period = 4000 * div / sh4_input_freq;
3.16 div = ifc_divider[(val >> 3) & 0x07];
3.17 sh4_bus_freq = sh4_input_freq / div;
3.18 sh4_bus_period = 1000 * div / sh4_input_freq;
3.19 @@ -71,6 +71,17 @@
3.20 MMIO_WRITE( CPG, reg, val );
3.21 }
3.22
3.23 +/**
3.24 + * We don't really know what the default reset value is as it's determined
3.25 + * by the mode select pins. This is the standard value that the BIOS sets,
3.26 + * however, so it works for now.
3.27 + */
3.28 +void CPG_reset( )
3.29 +{
3.30 + mmio_region_CPG_write( FRQCR, 0x0E0A );
3.31 +}
3.32 +
3.33 +
3.34 /********************************** RTC *************************************/
3.35
3.36 uint32_t rtc_output_period;
3.37 @@ -87,6 +98,9 @@
3.38
3.39 /********************************** TMU *************************************/
3.40
3.41 +uint32_t TMU_count( int timer, uint32_t nanosecs );
3.42 +
3.43 +
3.44 #define TCR_ICPF 0x0200
3.45 #define TCR_UNF 0x0100
3.46 #define TCR_UNIE 0x0020
3.47 @@ -103,6 +117,20 @@
3.48
3.49 int32_t mmio_region_TMU_read( uint32_t reg )
3.50 {
3.51 + switch( reg ) {
3.52 + case TCNT0:
3.53 + TMU_count( 0, sh4r.slice_cycle );
3.54 + TMU_timers[0].timer_run = sh4r.slice_cycle;
3.55 + break;
3.56 + case TCNT1:
3.57 + TMU_count( 1, sh4r.slice_cycle );
3.58 + TMU_timers[1].timer_run = sh4r.slice_cycle;
3.59 + break;
3.60 + case TCNT2:
3.61 + TMU_count( 2, sh4r.slice_cycle );
3.62 + TMU_timers[2].timer_run = sh4r.slice_cycle;
3.63 + break;
3.64 + }
3.65 return MMIO_READ( TMU, reg );
3.66 }
3.67
3.68 @@ -159,7 +187,7 @@
3.69
3.70 void TMU_start( int timer )
3.71 {
3.72 - TMU_timers[timer].timer_run = 0;
3.73 + TMU_timers[timer].timer_run = sh4r.slice_cycle;
3.74 TMU_timers[timer].timer_remainder = 0;
3.75 }
3.76
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