revision 582:c89a69dc427d
summary |
tree |
shortlog |
changelog |
graph |
changeset |
raw | bz2 | zip | gz changeset | 582:c89a69dc427d |
parent | 581:430515437e55 |
child | 583:ba995fadf173 |
author | nkeynes |
date | Tue Jan 15 10:03:27 2008 +0000 (16 years ago) |
branch | lxdream-mmu |
Fix emu instruction translation
1.1 --- a/src/sh4/sh4core.c Tue Jan 15 08:48:28 2008 +00001.2 +++ b/src/sh4/sh4core.c Tue Jan 15 10:03:27 2008 +00001.3 @@ -18,6 +18,7 @@1.4 */1.6 #define MODULE sh4_module1.7 +#include <assert.h>1.8 #include <math.h>1.9 #include "dream.h"1.10 #include "dreamcast.h"1.11 @@ -234,15 +235,20 @@1.12 CHECKRALIGN16(pc);1.14 /* Read instruction */1.15 - uint32_t pageaddr = pc >> 12;1.16 if( !IS_IN_ICACHE(pc) ) {1.17 - mmu_update_icache(pc);1.18 + if( !mmu_update_icache(pc) ) {1.19 + // Fault - look for the fault handler1.20 + if( !mmu_update_icache(sh4r.pc) ) {1.21 + // double fault - halt1.22 + ERROR( "Double fault - halting" );1.23 + dreamcast_stop();1.24 + return FALSE;1.25 + }1.26 + }1.27 + pc = sh4r.pc;1.28 }1.29 - if( IS_IN_ICACHE(pc) ) {1.30 - ir = *(uint16_t *)GET_ICACHE_PTR(pc);1.31 - } else {1.32 - ir = sh4_read_word(pc);1.33 - }1.34 + assert( IS_IN_ICACHE(pc) );1.35 + ir = *(uint16_t *)GET_ICACHE_PTR(sh4r.pc);1.36 switch( (ir&0xF000) >> 12 ) {1.37 case 0x0:1.38 switch( ir&0xF ) {
2.1 --- a/src/sh4/sh4core.in Tue Jan 15 08:48:28 2008 +00002.2 +++ b/src/sh4/sh4core.in Tue Jan 15 10:03:27 2008 +00002.3 @@ -18,6 +18,7 @@2.4 */2.6 #define MODULE sh4_module2.7 +#include <assert.h>2.8 #include <math.h>2.9 #include "dream.h"2.10 #include "dreamcast.h"2.11 @@ -234,15 +235,20 @@2.12 CHECKRALIGN16(pc);2.14 /* Read instruction */2.15 - uint32_t pageaddr = pc >> 12;2.16 if( !IS_IN_ICACHE(pc) ) {2.17 - mmu_update_icache(pc);2.18 + if( !mmu_update_icache(pc) ) {2.19 + // Fault - look for the fault handler2.20 + if( !mmu_update_icache(sh4r.pc) ) {2.21 + // double fault - halt2.22 + ERROR( "Double fault - halting" );2.23 + dreamcast_stop();2.24 + return FALSE;2.25 + }2.26 + }2.27 + pc = sh4r.pc;2.28 }2.29 - if( IS_IN_ICACHE(pc) ) {2.30 - ir = *(uint16_t *)GET_ICACHE_PTR(pc);2.31 - } else {2.32 - ir = sh4_read_word(pc);2.33 - }2.34 + assert( IS_IN_ICACHE(pc) );2.35 + ir = *(uint16_t *)GET_ICACHE_PTR(sh4r.pc);2.36 %%2.37 AND Rm, Rn {: sh4r.r[Rn] &= sh4r.r[Rm]; :}2.38 AND #imm, R0 {: R0 &= imm; :}
.