revision 124:ceb38f08619a
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raw | bz2 | zip | gz changeset | 124:ceb38f08619a |
parent | 123:2ad156e10657 |
child | 125:49bf45f8210a |
author | nkeynes |
date | Wed Mar 22 14:27:40 2006 +0000 (18 years ago) |
Fix FMOV for writes to the back bank (ie FMOV @R1, XD2)
src/sh4/sh4core.c | view | annotate | diff | log |
1.1 --- a/src/sh4/sh4core.c Wed Mar 22 11:58:01 2006 +00001.2 +++ b/src/sh4/sh4core.c Wed Mar 22 14:27:40 2006 +00001.3 @@ -1,5 +1,5 @@1.4 /**1.5 - * $Id: sh4core.c,v 1.25 2006-03-22 11:58:01 nkeynes Exp $1.6 + * $Id: sh4core.c,v 1.26 2006-03-22 14:27:40 nkeynes Exp $1.7 *1.8 * SH4 emulation core, and parent module for all the SH4 peripheral1.9 * modules.1.10 @@ -222,23 +222,11 @@1.11 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)1.12 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)1.14 -#define MEM_FR_READ( addr, reg ) *((uint32_t *)&FR(reg)) = sh4_read_long(addr)1.15 -1.16 -#define MEM_DR_READ( addr, reg ) do { \1.17 - *((uint32_t *)&FR((reg) & 0x0E)) = sh4_read_long(addr); \1.18 - *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4); } while(0)1.19 -1.20 -#define MEM_FR_WRITE( addr, reg ) sh4_write_long( addr, *((uint32_t *)&FR((reg))) )1.21 -1.22 -#define MEM_DR_WRITE( addr, reg ) do { \1.23 - sh4_write_long( addr, *((uint32_t *)&FR((reg)&0x0E)) ); \1.24 - sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) ); } while(0)1.25 -1.26 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)1.28 -#define MEM_FP_READ( addr, reg ) if( IS_FPU_DOUBLESIZE() ) MEM_DR_READ(addr, reg ); else MEM_FR_READ( addr, reg )1.29 +#define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );1.31 -#define MEM_FP_WRITE( addr, reg ) if( IS_FPU_DOUBLESIZE() ) MEM_DR_WRITE(addr, reg ); else MEM_FR_WRITE( addr, reg )1.32 +#define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );1.34 #define CHECK( x, c, v ) if( !x ) RAISE( c, v )1.35 #define CHECKPRIV() CHECK( IS_SH4_PRIVMODE(), EXC_ILLEGAL, EXV_ILLEGAL )1.36 @@ -267,6 +255,36 @@1.37 intc_mask_changed();1.38 }1.40 +static void sh4_write_float( uint32_t addr, int reg )1.41 +{1.42 + if( IS_FPU_DOUBLESIZE() ) {1.43 + if( reg & 1 ) {1.44 + sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );1.45 + sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );1.46 + } else {1.47 + sh4_write_long( addr, *((uint32_t *)&FR(reg)) );1.48 + sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );1.49 + }1.50 + } else {1.51 + sh4_write_long( addr, *((uint32_t *)&FR((reg))) );1.52 + }1.53 +}1.54 +1.55 +static void sh4_read_float( uint32_t addr, int reg )1.56 +{1.57 + if( IS_FPU_DOUBLESIZE() ) {1.58 + if( reg & 1 ) {1.59 + *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);1.60 + *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);1.61 + } else {1.62 + *((uint32_t *)&FR(reg)) = sh4_read_long(addr);1.63 + *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);1.64 + }1.65 + } else {1.66 + *((uint32_t *)&FR(reg)) = sh4_read_long(addr);1.67 + }1.68 +}1.69 +1.70 static uint32_t sh4_read_sr( void )1.71 {1.72 /* synchronize sh4r.sr with the various bitflags */
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