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lxdream.org :: lxdream :: r564:dc7b5ffb0535
lxdream 0.9.1
released Jun 29
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changeset564:dc7b5ffb0535 lxdream-mmu
parent563:72ccfd1f432b
child565:a44f0465bbbe
authornkeynes
dateTue Jan 01 08:37:26 2008 +0000 (11 years ago)
branchlxdream-mmu
Refactor sh4core.h to extract the "public" material into a new sh4.h
src/Makefile.am
src/Makefile.in
src/asic.c
src/bios.c
src/dcload.c
src/eventq.c
src/main.c
src/pvr2/pvr2.c
src/sh4/sh4.h
src/sh4/sh4core.h
src/syscall.c
src/util.c
src/x86dasm/x86dasm.c
1.1 --- a/src/Makefile.am Tue Jan 01 05:51:04 2008 +0000
1.2 +++ b/src/Makefile.am Tue Jan 01 08:37:26 2008 +0000
1.3 @@ -29,7 +29,7 @@
1.4 sh4/sh4.c sh4/intc.c sh4/intc.h sh4/sh4mem.c sh4/timer.c sh4/dmac.c \
1.5 sh4/mmu.c sh4/sh4core.c sh4/sh4core.h sh4/sh4dasm.c sh4/sh4dasm.h \
1.6 sh4/sh4mmio.c sh4/sh4mmio.h sh4/scif.c sh4/sh4stat.c sh4/sh4stat.h \
1.7 - sh4/xltcache.c sh4/xltcache.h \
1.8 + sh4/xltcache.c sh4/xltcache.h sh4/sh4.h \
1.9 aica/armcore.c aica/armcore.h aica/armdasm.c aica/armmem.c \
1.10 aica/aica.c aica/aica.h aica/audio.c aica/audio.h \
1.11 pvr2/pvr2.c pvr2/pvr2.h pvr2/pvr2mem.c \
2.1 --- a/src/Makefile.in Tue Jan 01 05:51:04 2008 +0000
2.2 +++ b/src/Makefile.in Tue Jan 01 08:37:26 2008 +0000
2.3 @@ -213,7 +213,7 @@
2.4 sh4/sh4.c sh4/intc.c sh4/intc.h sh4/sh4mem.c sh4/timer.c sh4/dmac.c \
2.5 sh4/mmu.c sh4/sh4core.c sh4/sh4core.h sh4/sh4dasm.c sh4/sh4dasm.h \
2.6 sh4/sh4mmio.c sh4/sh4mmio.h sh4/scif.c sh4/sh4stat.c sh4/sh4stat.h \
2.7 - sh4/xltcache.c sh4/xltcache.h \
2.8 + sh4/xltcache.c sh4/xltcache.h sh4/sh4.h \
2.9 aica/armcore.c aica/armcore.h aica/armdasm.c aica/armmem.c \
2.10 aica/aica.c aica/aica.h aica/audio.c aica/audio.h \
2.11 pvr2/pvr2.c pvr2/pvr2.h pvr2/pvr2mem.c \
2.12 @@ -271,25 +271,25 @@
2.13 sh4/intc.h sh4/sh4mem.c sh4/timer.c sh4/dmac.c sh4/mmu.c \
2.14 sh4/sh4core.c sh4/sh4core.h sh4/sh4dasm.c sh4/sh4dasm.h \
2.15 sh4/sh4mmio.c sh4/sh4mmio.h sh4/scif.c sh4/sh4stat.c \
2.16 - sh4/sh4stat.h sh4/xltcache.c sh4/xltcache.h aica/armcore.c \
2.17 - aica/armcore.h aica/armdasm.c aica/armmem.c aica/aica.c \
2.18 - aica/aica.h aica/audio.c aica/audio.h pvr2/pvr2.c pvr2/pvr2.h \
2.19 - pvr2/pvr2mem.c pvr2/tacore.c pvr2/render.c pvr2/rendcore.c \
2.20 - pvr2/rendbkg.c pvr2/rendsort.c pvr2/texcache.c pvr2/yuv.c \
2.21 - pvr2/rendsave.c maple/maple.c maple/maple.h maple/controller.c \
2.22 - maple/controller.h loader.c bootstrap.c util.c display.c \
2.23 - display.h drivers/audio_null.c drivers/video_null.c \
2.24 - drivers/gl_common.c drivers/gl_common.h drivers/gl_fbo.c \
2.25 - drivers/gl_sl.c drivers/gl_slsrc.c sh4/sh4x86.c sh4/x86op.h \
2.26 - sh4/ia32abi.h sh4/ia32mac.h sh4/ia64abi.h sh4/sh4trans.c \
2.27 - sh4/sh4trans.h x86dasm/x86dasm.c x86dasm/x86dasm.h \
2.28 - x86dasm/i386-dis.c x86dasm/dis-init.c x86dasm/dis-buf.c \
2.29 - gtkui/gtkui.c gtkui/gtkui.h gtkui/main_win.c gtkui/gtkcb.c \
2.30 - gtkui/mmio_win.c gtkui/debug_win.c gtkui/dump_win.c \
2.31 - gtkui/ctrl_dlg.c gtkui/path_dlg.c gtkui/gdrom_menu.c \
2.32 - drivers/video_gtk.c drivers/video_gtk.h drivers/video_glx.c \
2.33 - drivers/video_glx.h drivers/cd_linux.c drivers/cd_none.c \
2.34 - drivers/audio_esd.c
2.35 + sh4/sh4stat.h sh4/xltcache.c sh4/xltcache.h sh4/sh4.h \
2.36 + aica/armcore.c aica/armcore.h aica/armdasm.c aica/armmem.c \
2.37 + aica/aica.c aica/aica.h aica/audio.c aica/audio.h pvr2/pvr2.c \
2.38 + pvr2/pvr2.h pvr2/pvr2mem.c pvr2/tacore.c pvr2/render.c \
2.39 + pvr2/rendcore.c pvr2/rendbkg.c pvr2/rendsort.c pvr2/texcache.c \
2.40 + pvr2/yuv.c pvr2/rendsave.c maple/maple.c maple/maple.h \
2.41 + maple/controller.c maple/controller.h loader.c bootstrap.c \
2.42 + util.c display.c display.h drivers/audio_null.c \
2.43 + drivers/video_null.c drivers/gl_common.c drivers/gl_common.h \
2.44 + drivers/gl_fbo.c drivers/gl_sl.c drivers/gl_slsrc.c \
2.45 + sh4/sh4x86.c sh4/x86op.h sh4/ia32abi.h sh4/ia32mac.h \
2.46 + sh4/ia64abi.h sh4/sh4trans.c sh4/sh4trans.h x86dasm/x86dasm.c \
2.47 + x86dasm/x86dasm.h x86dasm/i386-dis.c x86dasm/dis-init.c \
2.48 + x86dasm/dis-buf.c gtkui/gtkui.c gtkui/gtkui.h gtkui/main_win.c \
2.49 + gtkui/gtkcb.c gtkui/mmio_win.c gtkui/debug_win.c \
2.50 + gtkui/dump_win.c gtkui/ctrl_dlg.c gtkui/path_dlg.c \
2.51 + gtkui/gdrom_menu.c drivers/video_gtk.c drivers/video_gtk.h \
2.52 + drivers/video_glx.c drivers/video_glx.h drivers/cd_linux.c \
2.53 + drivers/cd_none.c drivers/audio_esd.c
2.54 @BUILD_SH4X86_TRUE@am__objects_1 = sh4x86.$(OBJEXT) sh4trans.$(OBJEXT) \
2.55 @BUILD_SH4X86_TRUE@ x86dasm.$(OBJEXT) i386-dis.$(OBJEXT) \
2.56 @BUILD_SH4X86_TRUE@ dis-init.$(OBJEXT) dis-buf.$(OBJEXT)
3.1 --- a/src/asic.c Tue Jan 01 05:51:04 2008 +0000
3.2 +++ b/src/asic.c Tue Jan 01 08:37:26 2008 +0000
3.3 @@ -25,7 +25,7 @@
3.4 #include "mem.h"
3.5 #include "sh4/intc.h"
3.6 #include "sh4/dmac.h"
3.7 -#include "sh4/sh4core.h"
3.8 +#include "sh4/sh4.h"
3.9 #include "dreamcast.h"
3.10 #include "maple/maple.h"
3.11 #include "gdrom/ide.h"
3.12 @@ -387,11 +387,6 @@
3.13 {
3.14 int32_t val;
3.15 switch( reg ) {
3.16 - /*
3.17 - case 0x89C:
3.18 - sh4_stop();
3.19 - return 0x000000B;
3.20 - */
3.21 case PIRQ0:
3.22 case PIRQ1:
3.23 case PIRQ2:
3.24 @@ -531,8 +526,6 @@
3.25 case PVRDMA2CTL2:
3.26 if( val != 0 ) {
3.27 ERROR( "Write to unimplemented DMA control register %08X", reg );
3.28 - //dreamcast_stop();
3.29 - //sh4_stop();
3.30 }
3.31 break;
3.32 default:
4.1 --- a/src/bios.c Tue Jan 01 05:51:04 2008 +0000
4.2 +++ b/src/bios.c Tue Jan 01 08:37:26 2008 +0000
4.3 @@ -20,7 +20,7 @@
4.4 #include "mem.h"
4.5 #include "syscall.h"
4.6 #include "dreamcast.h"
4.7 -#include "sh4/sh4core.h"
4.8 +#include "sh4/sh4.h"
4.9
4.10 #define COMMAND_QUEUE_LENGTH 16
4.11
5.1 --- a/src/dcload.c Tue Jan 01 05:51:04 2008 +0000
5.2 +++ b/src/dcload.c Tue Jan 01 08:37:26 2008 +0000
5.3 @@ -24,7 +24,7 @@
5.4 #include "mem.h"
5.5 #include "dreamcast.h"
5.6 #include "syscall.h"
5.7 -#include "sh4/sh4core.h"
5.8 +#include "sh4/sh4.h"
5.9
5.10 #define SYS_READ 0
5.11 #define SYS_WRITE 1
6.1 --- a/src/eventq.c Tue Jan 01 05:51:04 2008 +0000
6.2 +++ b/src/eventq.c Tue Jan 01 08:37:26 2008 +0000
6.3 @@ -23,7 +23,7 @@
6.4 #include "dreamcast.h"
6.5 #include "eventq.h"
6.6 #include "asic.h"
6.7 -#include "sh4core.h"
6.8 +#include "sh4.h"
6.9
6.10 #define LONG_SCAN_PERIOD 1000000000 /* 1 second */
6.11
7.1 --- a/src/main.c Tue Jan 01 05:51:04 2008 +0000
7.2 +++ b/src/main.c Tue Jan 01 08:37:26 2008 +0000
7.3 @@ -30,7 +30,7 @@
7.4 #include "aica/audio.h"
7.5 #include "gdrom/gdrom.h"
7.6 #include "maple/maple.h"
7.7 -#include "sh4/sh4core.h"
7.8 +#include "sh4/sh4.h"
7.9
7.10 #define S3M_PLAYER "s3mplay.bin"
7.11
8.1 --- a/src/pvr2/pvr2.c Tue Jan 01 05:51:04 2008 +0000
8.2 +++ b/src/pvr2/pvr2.c Tue Jan 01 08:37:26 2008 +0000
8.3 @@ -25,7 +25,7 @@
8.4 #include "asic.h"
8.5 #include "clock.h"
8.6 #include "pvr2/pvr2.h"
8.7 -#include "sh4/sh4core.h"
8.8 +#include "sh4/sh4.h"
8.9 #define MMIO_IMPL
8.10 #include "pvr2/pvr2mmio.h"
8.11
9.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
9.2 +++ b/src/sh4/sh4.h Tue Jan 01 08:37:26 2008 +0000
9.3 @@ -0,0 +1,125 @@
9.4 +/**
9.5 + * $Id: sh4.h 577 2008-01-01 05:08:38Z nkeynes $
9.6 + *
9.7 + * This file defines the public functions and definitions exported by the SH4
9.8 + * modules.
9.9 + *
9.10 + * Copyright (c) 2005 Nathan Keynes.
9.11 + *
9.12 + * This program is free software; you can redistribute it and/or modify
9.13 + * it under the terms of the GNU General Public License as published by
9.14 + * the Free Software Foundation; either version 2 of the License, or
9.15 + * (at your option) any later version.
9.16 + *
9.17 + * This program is distributed in the hope that it will be useful,
9.18 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
9.19 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9.20 + * GNU General Public License for more details.
9.21 + */
9.22 +
9.23 +#ifndef lxdream_sh4_H
9.24 +#define lxdream_sh4_H 1
9.25 +
9.26 +#include "lxdream.h"
9.27 +
9.28 +#ifdef __cplusplus
9.29 +extern "C" {
9.30 +#endif
9.31 +
9.32 +
9.33 +/**
9.34 + * SH4 is running normally
9.35 + */
9.36 +#define SH4_STATE_RUNNING 1
9.37 +/**
9.38 + * SH4 is not executing instructions but all peripheral modules are still
9.39 + * running
9.40 + */
9.41 +#define SH4_STATE_SLEEP 2
9.42 +/**
9.43 + * SH4 is not executing instructions, DMAC is halted, but all other peripheral
9.44 + * modules are still running
9.45 + */
9.46 +#define SH4_STATE_DEEP_SLEEP 3
9.47 +/**
9.48 + * SH4 is not executing instructions and all peripheral modules are also
9.49 + * stopped. As close as you can get to powered-off without actually being
9.50 + * off.
9.51 + */
9.52 +#define SH4_STATE_STANDBY 4
9.53 +
9.54 +/**
9.55 + * sh4r.event_types flag indicating a pending IRQ
9.56 + */
9.57 +#define PENDING_IRQ 1
9.58 +
9.59 +/**
9.60 + * sh4r.event_types flag indicating a pending event (from the event queue)
9.61 + */
9.62 +#define PENDING_EVENT 2
9.63 +
9.64 +/**
9.65 + * SH4 register structure
9.66 + */
9.67 +struct sh4_registers {
9.68 + uint32_t r[16];
9.69 + uint32_t sr, pr, pc, fpscr;
9.70 + uint32_t t, m, q, s; /* really boolean - 0 or 1 */
9.71 + int32_t fpul;
9.72 + float *fr_bank;
9.73 + float fr[2][16];
9.74 + uint64_t mac;
9.75 + uint32_t gbr, ssr, spc, sgr, dbr, vbr;
9.76 +
9.77 + uint32_t r_bank[8]; /* hidden banked registers */
9.78 + int32_t store_queue[16]; /* technically 2 banks of 32 bytes */
9.79 +
9.80 + uint32_t new_pc; /* Not a real register, but used to handle delay slots */
9.81 + uint32_t event_pending; /* slice cycle time of the next pending event, or FFFFFFFF
9.82 + when no events are pending */
9.83 + uint32_t event_types; /* bit 0 = IRQ pending, bit 1 = general event pending */
9.84 + int in_delay_slot; /* flag to indicate the current instruction is in
9.85 + * a delay slot (certain rules apply) */
9.86 + uint32_t slice_cycle; /* Current nanosecond within the timeslice */
9.87 + int sh4_state; /* Current power-on state (one of the SH4_STATE_* values ) */
9.88 +};
9.89 +
9.90 +extern struct sh4_registers sh4r;
9.91 +
9.92 +/**
9.93 + * Switch between translation and emulation execution modes. Note that this
9.94 + * should only be used while the system is stopped. If the system was built
9.95 + * without translation support, this method has no effect.
9.96 + *
9.97 + * @param use TRUE for translation mode, FALSE for emulation mode.
9.98 + */
9.99 +void sh4_set_use_xlat( gboolean use );
9.100 +
9.101 +/**
9.102 + * Explicitly set the SH4 PC to the supplied value - this will be the next
9.103 + * instruction executed. This should only be called while the system is stopped.
9.104 + */
9.105 +void sh4_set_pc( int pc );
9.106 +
9.107 +/**
9.108 + * Execute (using the emulator) a single instruction (in other words, perform a
9.109 + * single-step operation).
9.110 + */
9.111 +gboolean sh4_execute_instruction( void );
9.112 +
9.113 +/* SH4 breakpoints */
9.114 +
9.115 +#define BREAK_ONESHOT 1
9.116 +#define BREAK_PERM 2
9.117 +
9.118 +void sh4_set_breakpoint( uint32_t pc, int type );
9.119 +gboolean sh4_clear_breakpoint( uint32_t pc, int type );
9.120 +int sh4_get_breakpoint( uint32_t pc );
9.121 +
9.122 +
9.123 +
9.124 +
9.125 +#ifdef __cplusplus
9.126 +}
9.127 +#endif
9.128 +#endif /* !lxdream_sh4_H */
10.1 --- a/src/sh4/sh4core.h Tue Jan 01 05:51:04 2008 +0000
10.2 +++ b/src/sh4/sh4core.h Tue Jan 01 08:37:26 2008 +0000
10.3 @@ -24,96 +24,55 @@
10.4 #include <stdint.h>
10.5 #include <stdio.h>
10.6 #include "mem.h"
10.7 +#include "sh4/sh4.h"
10.8
10.9 #ifdef __cplusplus
10.10 extern "C" {
10.11 -#if 0
10.12 -}
10.13 -#endif
10.14 #endif
10.15
10.16 -
10.17 -/**
10.18 - * SH4 is running normally
10.19 - */
10.20 -#define SH4_STATE_RUNNING 1
10.21 -/**
10.22 - * SH4 is not executing instructions but all peripheral modules are still
10.23 - * running
10.24 - */
10.25 -#define SH4_STATE_SLEEP 2
10.26 -/**
10.27 - * SH4 is not executing instructions, DMAC is halted, but all other peripheral
10.28 - * modules are still running
10.29 - */
10.30 -#define SH4_STATE_DEEP_SLEEP 3
10.31 -/**
10.32 - * SH4 is not executing instructions and all peripheral modules are also
10.33 - * stopped. As close as you can get to powered-off without actually being
10.34 - * off.
10.35 - */
10.36 -#define SH4_STATE_STANDBY 4
10.37 -
10.38 -#define PENDING_IRQ 1
10.39 -#define PENDING_EVENT 2
10.40 -
10.41 -struct sh4_registers {
10.42 - uint32_t r[16];
10.43 - uint32_t sr, pr, pc, fpscr;
10.44 - uint32_t t, m, q, s; /* really boolean - 0 or 1 */
10.45 - int32_t fpul;
10.46 - float *fr_bank;
10.47 - float fr[2][16];
10.48 - uint64_t mac;
10.49 - uint32_t gbr, ssr, spc, sgr, dbr, vbr;
10.50 -
10.51 - uint32_t r_bank[8]; /* hidden banked registers */
10.52 - int32_t store_queue[16]; /* technically 2 banks of 32 bytes */
10.53 -
10.54 - uint32_t new_pc; /* Not a real register, but used to handle delay slots */
10.55 - uint32_t event_pending; /* slice cycle time of the next pending event, or FFFFFFFF
10.56 - when no events are pending */
10.57 - uint32_t event_types; /* bit 0 = IRQ pending, bit 1 = general event pending */
10.58 - int in_delay_slot; /* flag to indicate the current instruction is in
10.59 - * a delay slot (certain rules apply) */
10.60 - uint32_t slice_cycle; /* Current nanosecond within the timeslice */
10.61 - int sh4_state; /* Current power-on state (one of the SH4_STATE_* values ) */
10.62 -};
10.63 -
10.64 -extern struct sh4_registers sh4r;
10.65 +/* Breakpoint data structure */
10.66 extern struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
10.67 extern int sh4_breakpoint_count;
10.68
10.69 -
10.70 -/* Public functions */
10.71 -void sh4_set_use_xlat( gboolean use );
10.72 +/* SH4 module functions */
10.73 void sh4_init( void );
10.74 void sh4_reset( void );
10.75 void sh4_run( void );
10.76 -void sh4_runto( uint32_t pc, uint32_t count );
10.77 -void sh4_runfor( uint32_t count );
10.78 -int sh4_isrunning( void );
10.79 void sh4_stop( void );
10.80 -void sh4_set_pc( int );
10.81 +
10.82 +/* SH4 peripheral module functions */
10.83 +void CPG_reset( void );
10.84 +void DMAC_reset( void );
10.85 +void DMAC_run_slice( uint32_t );
10.86 +void DMAC_save_state( FILE * );
10.87 +int DMAC_load_state( FILE * );
10.88 +void INTC_reset( void );
10.89 +void INTC_save_state( FILE *f );
10.90 +int INTC_load_state( FILE *f );
10.91 +void MMU_init( void );
10.92 +void MMU_reset( void );
10.93 +void MMU_save_state( FILE *f );
10.94 +int MMU_load_state( FILE *f );
10.95 +void MMU_ldtlb();
10.96 +void SCIF_reset( void );
10.97 +void SCIF_run_slice( uint32_t );
10.98 +void SCIF_save_state( FILE *f );
10.99 +int SCIF_load_state( FILE *f );
10.100 +void SCIF_update_line_speed(void);
10.101 +void TMU_reset( void );
10.102 +void TMU_run_slice( uint32_t );
10.103 +void TMU_save_state( FILE * );
10.104 +int TMU_load_state( FILE * );
10.105 +void TMU_update_clocks( void );
10.106 +
10.107 +/* SH4 instruction support methods */
10.108 void sh4_sleep( void );
10.109 void sh4_fsca( uint32_t angle, float *fr );
10.110 void sh4_ftrv( float *fv, float *xmtrx );
10.111 +uint32_t sh4_read_sr(void);
10.112 +void sh4_write_sr(uint32_t val);
10.113 void signsat48(void);
10.114
10.115 -gboolean sh4_execute_instruction( void );
10.116 -gboolean sh4_raise_exception( int );
10.117 -gboolean sh4_raise_reset( int );
10.118 -gboolean sh4_raise_trap( int );
10.119 -gboolean sh4_raise_slot_exception( int, int );
10.120 -gboolean sh4_raise_tlb_exception( int );
10.121 -void sh4_set_breakpoint( uint32_t pc, int type );
10.122 -gboolean sh4_clear_breakpoint( uint32_t pc, int type );
10.123 -int sh4_get_breakpoint( uint32_t pc );
10.124 -void sh4_accept_interrupt( void );
10.125 -
10.126 -#define BREAK_ONESHOT 1
10.127 -#define BREAK_PERM 2
10.128 -
10.129 /* SH4 Memory */
10.130 uint64_t mmu_vma_to_phys_read( sh4addr_t addr );
10.131 uint64_t mmu_vma_to_phys_write( sh4addr_t addr );
10.132 @@ -131,34 +90,33 @@
10.133 void sh4_flush_store_queue( sh4addr_t addr );
10.134 sh4ptr_t sh4_get_region_by_vma( sh4addr_t addr );
10.135
10.136 -/* SH4 Support methods */
10.137 -uint32_t sh4_read_sr(void);
10.138 -void sh4_write_sr(uint32_t val);
10.139 +/* SH4 Exceptions */
10.140 +#define EXC_POWER_RESET 0x000 /* reset vector */
10.141 +#define EXC_MANUAL_RESET 0x020 /* reset vector */
10.142 +#define EXC_TLB_MISS_READ 0x040 /* TLB vector */
10.143 +#define EXC_TLB_MISS_WRITE 0x060 /* TLB vector */
10.144 +#define EXC_INIT_PAGE_WRITE 0x080
10.145 +#define EXC_TLB_PROT_READ 0x0A0
10.146 +#define EXC_TLB_PROT_WRITE 0x0C0
10.147 +#define EXC_DATA_ADDR_READ 0x0E0
10.148 +#define EXC_DATA_ADDR_WRITE 0x100
10.149 +#define EXC_TLB_MULTI_HIT 0x140
10.150 +#define EXC_SLOT_ILLEGAL 0x1A0
10.151 +#define EXC_ILLEGAL 0x180
10.152 +#define EXC_TRAP 0x160
10.153 +#define EXC_FPU_DISABLED 0x800
10.154 +#define EXC_SLOT_FPU_DISABLED 0x820
10.155
10.156 -/* Peripheral functions */
10.157 -void CPG_reset( void );
10.158 -void TMU_run_slice( uint32_t );
10.159 -void TMU_update_clocks( void );
10.160 -void TMU_reset( void );
10.161 -void TMU_save_state( FILE * );
10.162 -int TMU_load_state( FILE * );
10.163 -void DMAC_reset( void );
10.164 -void DMAC_run_slice( uint32_t );
10.165 -void DMAC_save_state( FILE * );
10.166 -int DMAC_load_state( FILE * );
10.167 -void SCIF_reset( void );
10.168 -void SCIF_run_slice( uint32_t );
10.169 -void SCIF_save_state( FILE *f );
10.170 -int SCIF_load_state( FILE *f );
10.171 -void INTC_reset( void );
10.172 -void INTC_save_state( FILE *f );
10.173 -int INTC_load_state( FILE *f );
10.174 -void MMU_init( void );
10.175 -void MMU_reset( void );
10.176 -void MMU_save_state( FILE *f );
10.177 -int MMU_load_state( FILE *f );
10.178 -void MMU_ldtlb();
10.179 -void SCIF_update_line_speed(void);
10.180 +#define EXV_EXCEPTION 0x100 /* General exception vector */
10.181 +#define EXV_TLBMISS 0x400 /* TLB-miss exception vector */
10.182 +#define EXV_INTERRUPT 0x600 /* External interrupt vector */
10.183 +
10.184 +gboolean sh4_raise_exception( int );
10.185 +gboolean sh4_raise_reset( int );
10.186 +gboolean sh4_raise_trap( int );
10.187 +gboolean sh4_raise_slot_exception( int, int );
10.188 +gboolean sh4_raise_tlb_exception( int );
10.189 +void sh4_accept_interrupt( void );
10.190
10.191 #define SIGNEXT4(n) ((((int32_t)(n))<<28)>>28)
10.192 #define SIGNEXT8(n) ((int32_t)((int8_t)(n)))
10.193 @@ -207,44 +165,6 @@
10.194 #define FPULf *((float *)&sh4r.fpul)
10.195 #define FPULi (sh4r.fpul)
10.196
10.197 -/* CPU-generated exception code/vector pairs */
10.198 -#define EXC_POWER_RESET 0x000 /* vector special */
10.199 -#define EXC_MANUAL_RESET 0x020
10.200 -#define EXC_TLB_MISS_READ 0x040
10.201 -#define EXC_TLB_MISS_WRITE 0x060
10.202 -#define EXC_INIT_PAGE_WRITE 0x080
10.203 -#define EXC_TLB_PROT_READ 0x0A0
10.204 -#define EXC_TLB_PROT_WRITE 0x0C0
10.205 -#define EXC_DATA_ADDR_READ 0x0E0
10.206 -#define EXC_DATA_ADDR_WRITE 0x100
10.207 -#define EXC_TLB_MULTI_HIT 0x140
10.208 -#define EXC_SLOT_ILLEGAL 0x1A0
10.209 -#define EXC_ILLEGAL 0x180
10.210 -#define EXC_TRAP 0x160
10.211 -#define EXC_FPU_DISABLED 0x800
10.212 -#define EXC_SLOT_FPU_DISABLED 0x820
10.213 -
10.214 -#define EXV_EXCEPTION 0x100 /* General exception vector */
10.215 -#define EXV_TLBMISS 0x400 /* TLB-miss exception vector */
10.216 -#define EXV_INTERRUPT 0x600 /* External interrupt vector */
10.217 -
10.218 -/* Exceptions (for use with sh4_raise_exception) */
10.219 -
10.220 -#define EX_ILLEGAL_INSTRUCTION 0x180, 0x100
10.221 -#define EX_SLOT_ILLEGAL 0x1A0, 0x100
10.222 -#define EX_TLB_MISS_READ 0x040, 0x400
10.223 -#define EX_TLB_MISS_WRITE 0x060, 0x400
10.224 -#define EX_INIT_PAGE_WRITE 0x080, 0x100
10.225 -#define EX_TLB_PROT_READ 0x0A0, 0x100
10.226 -#define EX_TLB_PROT_WRITE 0x0C0, 0x100
10.227 -#define EX_DATA_ADDR_READ 0x0E0, 0x100
10.228 -#define EX_DATA_ADDR_WRITE 0x100, 0x100
10.229 -#define EX_FPU_EXCEPTION 0x120, 0x100
10.230 -#define EX_TRAPA 0x160, 0x100
10.231 -#define EX_BREAKPOINT 0x1E0, 0x100
10.232 -#define EX_FPU_DISABLED 0x800, 0x100
10.233 -#define EX_SLOT_FPU_DISABLED 0x820, 0x100
10.234 -
10.235 #define SH4_WRITE_STORE_QUEUE(addr,val) sh4r.store_queue[(addr>>2)&0xF] = val;
10.236
10.237 #ifdef __cplusplus
11.1 --- a/src/syscall.c Tue Jan 01 05:51:04 2008 +0000
11.2 +++ b/src/syscall.c Tue Jan 01 08:37:26 2008 +0000
11.3 @@ -19,7 +19,7 @@
11.4 #include "dream.h"
11.5 #include "mem.h"
11.6 #include "syscall.h"
11.7 -#include "sh4/sh4core.h"
11.8 +#include "sh4/sh4.h"
11.9
11.10
11.11 struct syscall_hook {
12.1 --- a/src/util.c Tue Jan 01 05:51:04 2008 +0000
12.2 +++ b/src/util.c Tue Jan 01 08:37:26 2008 +0000
12.3 @@ -31,7 +31,7 @@
12.4 #include "dream.h"
12.5 #include "display.h"
12.6 #include "gui.h"
12.7 -#include "sh4/sh4core.h"
12.8 +#include "sh4/sh4.h"
12.9
12.10 char *msg_levels[] = { "FATAL", "ERROR", "WARN", "INFO", "DEBUG", "TRACE" };
12.11 int global_msg_level = EMIT_WARN;
13.1 --- a/src/x86dasm/x86dasm.c Tue Jan 01 05:51:04 2008 +0000
13.2 +++ b/src/x86dasm/x86dasm.c Tue Jan 01 08:37:26 2008 +0000
13.3 @@ -22,7 +22,7 @@
13.4 #include "x86dasm.h"
13.5 #include "bfd.h"
13.6 #include "dis-asm.h"
13.7 -#include "sh4/sh4core.h"
13.8 +#include "sh4/sh4.h"
13.9 #include "sh4/sh4trans.h"
13.10
13.11 extern const struct reg_desc_struct sh4_reg_map[];
.