Search
lxdream.org :: lxdream :: r191:df4441cf3128
lxdream 0.9.1
released Jun 29
Download Now
changeset191:df4441cf3128
parent190:f7653df5e832
child192:580d6c4d7802
authornkeynes
dateWed Aug 02 06:24:08 2006 +0000 (13 years ago)
Add more register masks (in line with test case)
Rename renderer registers for consistency
src/pvr2/pvr2.c
src/pvr2/pvr2mmio.h
src/pvr2/rendcore.c
src/pvr2/render.c
src/pvr2/texcache.c
1.1 --- a/src/pvr2/pvr2.c Wed Aug 02 04:13:15 2006 +0000
1.2 +++ b/src/pvr2/pvr2.c Wed Aug 02 06:24:08 2006 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: pvr2.c,v 1.28 2006-08-02 04:06:45 nkeynes Exp $
1.6 + * $Id: pvr2.c,v 1.29 2006-08-02 06:24:08 nkeynes Exp $
1.7 *
1.8 * PVR2 (Video) Core module implementation and MMIO registers.
1.9 *
1.10 @@ -222,10 +222,31 @@
1.11 case TA_LISTPOS:
1.12 /* Readonly registers */
1.13 break;
1.14 - case RENDSTART:
1.15 + case RENDER_START:
1.16 if( val == 0xFFFFFFFF )
1.17 pvr2_render_scene();
1.18 break;
1.19 + case PVRUNK1:
1.20 + MMIO_WRITE( PVR2, reg, val&0x000007FF );
1.21 + break;
1.22 + case RENDER_POLYBASE:
1.23 + MMIO_WRITE( PVR2, reg, val&0x00F00000 );
1.24 + break;
1.25 + case RENDER_TSPCFG:
1.26 + MMIO_WRITE( PVR2, reg, val&0x00010101 );
1.27 + break;
1.28 + case DISPBORDER:
1.29 + MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
1.30 + break;
1.31 + case DISPMODE:
1.32 + MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
1.33 + break;
1.34 + case RENDER_MODE:
1.35 + MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
1.36 + break;
1.37 + case RENDER_SIZE:
1.38 + MMIO_WRITE( PVR2, reg, val&0x000001FF );
1.39 + break;
1.40 case DISPADDR1:
1.41 val &= 0x00FFFFFC;
1.42 MMIO_WRITE( PVR2, reg, val );
1.43 @@ -234,14 +255,24 @@
1.44 pvr2_state.retrace = FALSE;
1.45 }
1.46 break;
1.47 - case HCLIP:
1.48 - MMIO_WRITE( PVR2, reg, val & 0x07FF07FF );
1.49 + case DISPADDR2:
1.50 + MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
1.51 + break;
1.52 + case DISPSIZE:
1.53 + MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
1.54 + break;
1.55 + case RENDER_ADDR1:
1.56 + case RENDER_ADDR2:
1.57 + MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
1.58 + break;
1.59 + case RENDER_HCLIP:
1.60 + MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
1.61 break;
1.62 - case VCLIP:
1.63 - MMIO_WRITE( PVR2, reg, val & 0x03FF03FF );
1.64 + case RENDER_VCLIP:
1.65 + MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
1.66 break;
1.67 case HPOS_IRQ:
1.68 - MMIO_WRITE( PVR2, reg, val & 0x03FF33FF );
1.69 + MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
1.70 break;
1.71 case VPOS_IRQ:
1.72 val = val & 0x03FF03FF;
1.73 @@ -249,26 +280,48 @@
1.74 pvr2_state.irq_vpos2 = val & 0x03FF;
1.75 MMIO_WRITE( PVR2, reg, val );
1.76 break;
1.77 + case RENDER_SHADOW:
1.78 + MMIO_WRITE( PVR2, reg, val&0x000001FF );
1.79 + break;
1.80 + case RENDER_OBJCFG:
1.81 + MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
1.82 + break;
1.83 + case RENDER_TSPCLIP:
1.84 + MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
1.85 + break;
1.86 + case RENDER_BGPLANE:
1.87 + MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
1.88 + break;
1.89 + case RENDER_ISPCFG:
1.90 + MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
1.91 + break;
1.92 case TA_TILEBASE:
1.93 case TA_TILEEND:
1.94 case TA_LISTBASE:
1.95 - MMIO_WRITE( PVR2, reg, val & 0x00FFFFE0 );
1.96 + MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
1.97 break;
1.98 + case RENDER_TILEBASE:
1.99 case TA_POLYBASE:
1.100 case TA_POLYEND:
1.101 - MMIO_WRITE( PVR2, reg, val & 0x00FFFFFC );
1.102 + MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
1.103 break;
1.104 case TA_TILESIZE:
1.105 - MMIO_WRITE( PVR2, reg, val & 0x000F003F );
1.106 + MMIO_WRITE( PVR2, reg, val&0x000F003F );
1.107 break;
1.108 case TA_TILECFG:
1.109 - MMIO_WRITE( PVR2, reg, val & 0x00133333 );
1.110 + MMIO_WRITE( PVR2, reg, val&0x00133333 );
1.111 break;
1.112 case TA_INIT:
1.113 if( val & 0x80000000 )
1.114 pvr2_ta_init();
1.115 break;
1.116
1.117 + /* Nonexistent registers (as far as we know, anyway) */
1.118 + case 0x01C:
1.119 + case 0x024:
1.120 + case 0x028:
1.121 + case 0x058:
1.122 + break;
1.123 default:
1.124 MMIO_WRITE( PVR2, reg, val );
1.125 }
2.1 --- a/src/pvr2/pvr2mmio.h Wed Aug 02 04:13:15 2006 +0000
2.2 +++ b/src/pvr2/pvr2mmio.h Wed Aug 02 06:24:08 2006 +0000
2.3 @@ -1,5 +1,5 @@
2.4 /**
2.5 - * $Id: pvr2mmio.h,v 1.4 2006-08-02 04:06:45 nkeynes Exp $
2.6 + * $Id: pvr2mmio.h,v 1.5 2006-08-02 06:24:08 nkeynes Exp $
2.7 *
2.8 * PVR2 (video chip) MMIO register definitions.
2.9 *
2.10 @@ -22,32 +22,34 @@
2.11 LONG_PORT( 0x000, PVRID, PORT_R, 0x17FD11DB, "PVR2 Core ID" )
2.12 LONG_PORT( 0x004, PVRVER, PORT_R, 0x00000011, "PVR2 Core Version" )
2.13 LONG_PORT( 0x008, PVRRST, PORT_MRW, 0, "PVR2 Reset" )
2.14 - LONG_PORT( 0x014, RENDSTART, PORT_W, 0, "Start render" )
2.15 - LONG_PORT( 0x020, OBJBASE, PORT_MRW, 0, "Object buffer base offset" )
2.16 - LONG_PORT( 0x02C, TILEBASE, PORT_MRW, 0, "Tile buffer base offset" )
2.17 + LONG_PORT( 0x014, RENDER_START, PORT_W, 0, "Start render" )
2.18 + LONG_PORT( 0x018, PVRUNK1, PORT_MRW, 0, "PVR2 unknown register 1" )
2.19 + LONG_PORT( 0x020, RENDER_POLYBASE, PORT_MRW, 0, "Object buffer base offset" )
2.20 + LONG_PORT( 0x02C, RENDER_TILEBASE, PORT_MRW, 0, "Tile buffer base offset" )
2.21 + LONG_PORT( 0x030, RENDER_TSPCFG, PORT_MRW, 0, "TSP config?" )
2.22 LONG_PORT( 0x040, DISPBORDER, PORT_MRW, 0, "Border Colour (RGB)" )
2.23 LONG_PORT( 0x044, DISPMODE, PORT_MRW, 0, "Display Mode" )
2.24 - LONG_PORT( 0x048, RENDMODE, PORT_MRW, 0, "Rendering Mode" )
2.25 - LONG_PORT( 0x04C, RENDSIZE, PORT_MRW, 0, "Rendering width (bytes/2)" )
2.26 + LONG_PORT( 0x048, RENDER_MODE, PORT_MRW, 0, "Rendering Mode" )
2.27 + LONG_PORT( 0x04C, RENDER_SIZE, PORT_MRW, 0, "Rendering width (bytes/2)" )
2.28 LONG_PORT( 0x050, DISPADDR1, PORT_MRW, 0, "Video memory base 1" )
2.29 LONG_PORT( 0x054, DISPADDR2, PORT_MRW, 0, "Video memory base 2" )
2.30 LONG_PORT( 0x05C, DISPSIZE, PORT_MRW, 0, "Display size" )
2.31 - LONG_PORT( 0x060, RENDADDR1, PORT_MRW, 0, "Rendering memory base 1" )
2.32 - LONG_PORT( 0x064, RENDADDR2, PORT_MRW, 0, "Rendering memory base 2" )
2.33 - LONG_PORT( 0x068, HCLIP, PORT_MRW, 0, "Horizontal clipping area" )
2.34 - LONG_PORT( 0x06C, VCLIP, PORT_MRW, 0, "Vertical clipping area" )
2.35 - LONG_PORT( 0x074, SHADOW, PORT_MRW, 0, "Shadowing" )
2.36 - LONG_PORT( 0x078, OBJCLIP, PORT_MRW, 0, "Object clip distance (float32)" )
2.37 - LONG_PORT( 0x07C, OBJCFG, PORT_MRW, 0, "Object config" )
2.38 - LONG_PORT( 0x084, TSPCLIP, PORT_MRW, 0, "Texture clip distance (float32)" )
2.39 - LONG_PORT( 0x088, BGPLANEZ, PORT_MRW, 0, "Background plane depth (float32)" )
2.40 - LONG_PORT( 0x08C, BGPLANE, PORT_MRW, 0, "Background plane config" )
2.41 - LONG_PORT( 0x098, ISPCFG, PORT_MRW, 0, "ISP config" )
2.42 - LONG_PORT( 0x0B0, FOGTBLCOL, PORT_MRW, 0, "Fog table colour" )
2.43 - LONG_PORT( 0x0B4, FOGVRTCOL, PORT_MRW, 0, "Fog vertex colour" )
2.44 - LONG_PORT( 0x0B8, FOGCOEFF, PORT_MRW, 0, "Fog density coefficient (float16)" )
2.45 - LONG_PORT( 0x0BC, CLAMPHI, PORT_MRW, 0, "Clamp high colour" )
2.46 - LONG_PORT( 0x0C0, CLAMPLO, PORT_MRW, 0, "Clamp low colour" )
2.47 + LONG_PORT( 0x060, RENDER_ADDR1, PORT_MRW, 0, "Rendering memory base 1" )
2.48 + LONG_PORT( 0x064, RENDER_ADDR2, PORT_MRW, 0, "Rendering memory base 2" )
2.49 + LONG_PORT( 0x068, RENDER_HCLIP, PORT_MRW, 0, "Horizontal clipping area" )
2.50 + LONG_PORT( 0x06C, RENDER_VCLIP, PORT_MRW, 0, "Vertical clipping area" )
2.51 + LONG_PORT( 0x074, RENDER_SHADOW, PORT_MRW, 0, "Shadowing" )
2.52 + LONG_PORT( 0x078, RENDER_NEARCLIP, PORT_MRW, 0, "Object clip distance (float32)" )
2.53 + LONG_PORT( 0x07C, RENDER_OBJCFG, PORT_MRW, 0, "Object config" )
2.54 + LONG_PORT( 0x084, RENDER_TSPCLIP, PORT_MRW, 0, "Texture clip distance (float32)" )
2.55 + LONG_PORT( 0x088, RENDER_FARCLIP, PORT_MRW, 0, "Background plane depth (float32)" )
2.56 + LONG_PORT( 0x08C, RENDER_BGPLANE, PORT_MRW, 0, "Background plane config" )
2.57 + LONG_PORT( 0x098, RENDER_ISPCFG, PORT_MRW, 0, "ISP config" )
2.58 + LONG_PORT( 0x0B0, RENDER_FOGTBLCOL, PORT_MRW, 0, "Fog table colour" )
2.59 + LONG_PORT( 0x0B4, RENDER_FOGVRTCOL, PORT_MRW, 0, "Fog vertex colour" )
2.60 + LONG_PORT( 0x0B8, RENDER_FOGCOEFF, PORT_MRW, 0, "Fog density coefficient (float16)" )
2.61 + LONG_PORT( 0x0BC, RENDER_CLAMPHI, PORT_MRW, 0, "Clamp high colour" )
2.62 + LONG_PORT( 0x0C0, RENDER_CLAMPLO, PORT_MRW, 0, "Clamp low colour" )
2.63 LONG_PORT( 0x0C4, GUNPOS, PORT_MRW, 0, "Lightgun position" )
2.64 LONG_PORT( 0x0C8, HPOS_IRQ, PORT_MRW, 0, "Raster horizontal event position" )
2.65 LONG_PORT( 0x0CC, VPOS_IRQ, PORT_MRW, 0, "Raster event position" )
2.66 @@ -56,11 +58,11 @@
2.67 LONG_PORT( 0x0D8, REFRESH, PORT_MRW, 0, "Refresh rates?" )
2.68 LONG_PORT( 0x0DC, VBORDER, PORT_MRW, 0, "Vertical border area" )
2.69 LONG_PORT( 0x0E0, SYNCPOS, PORT_MRW, 0, "Sync pulse timing" )
2.70 - LONG_PORT( 0x0E4, TSPCFG, PORT_MRW, 0, "Texture modulo width" )
2.71 + LONG_PORT( 0x0E4, RENDER_TEXSIZE, PORT_MRW, 0, "Texture modulo width" )
2.72 LONG_PORT( 0x0E8, DISPCFG2, PORT_MRW, 0, "Video configuration 2" )
2.73 LONG_PORT( 0x0F0, VPOS, PORT_MRW, 0, "Vertical display position" )
2.74 LONG_PORT( 0x0F4, SCALERCFG, PORT_MRW, 0, "Scaler configuration (?)" )
2.75 - LONG_PORT( 0x108, PALETTECFG, PORT_MRW, 0, "Palette configuration" )
2.76 + LONG_PORT( 0x108, RENDER_PALETTE, PORT_MRW, 0, "Palette configuration" )
2.77 LONG_PORT( 0x10C, BEAMPOS, PORT_R, 0, "Raster beam position" )
2.78 LONG_PORT( 0x124, TA_TILEBASE, PORT_MRW, 0, "TA Tile matrix start" )
2.79 LONG_PORT( 0x128, TA_POLYBASE, PORT_MRW, 0, "TA Polygon buffer start" )
3.1 --- a/src/pvr2/rendcore.c Wed Aug 02 04:13:15 2006 +0000
3.2 +++ b/src/pvr2/rendcore.c Wed Aug 02 06:24:08 2006 +0000
3.3 @@ -1,5 +1,5 @@
3.4 /**
3.5 - * $Id: rendcore.c,v 1.1 2006-08-02 04:06:45 nkeynes Exp $
3.6 + * $Id: rendcore.c,v 1.2 2006-08-02 06:24:08 nkeynes Exp $
3.7 *
3.8 * PVR2 renderer core.
3.9 *
3.10 @@ -269,13 +269,13 @@
3.11 void pvr2_render_tilebuffer( int width, int height, int clipx1, int clipy1,
3.12 int clipx2, int clipy2 ) {
3.13
3.14 - pvraddr_t segmentbase = MMIO_READ( PVR2, TILEBASE );
3.15 + pvraddr_t segmentbase = MMIO_READ( PVR2, RENDER_TILEBASE );
3.16 int tile_sort;
3.17 gboolean cheap_shadow;
3.18
3.19 - int obj_config = MMIO_READ( PVR2, OBJCFG );
3.20 - int isp_config = MMIO_READ( PVR2, ISPCFG );
3.21 - int shadow_cfg = MMIO_READ( PVR2, SHADOW );
3.22 + int obj_config = MMIO_READ( PVR2, RENDER_OBJCFG );
3.23 + int isp_config = MMIO_READ( PVR2, RENDER_ISPCFG );
3.24 + int shadow_cfg = MMIO_READ( PVR2, RENDER_SHADOW );
3.25
3.26 if( obj_config & 0x00200000 ) {
3.27 if( isp_config & 1 ) {
4.1 --- a/src/pvr2/render.c Wed Aug 02 04:13:15 2006 +0000
4.2 +++ b/src/pvr2/render.c Wed Aug 02 06:24:08 2006 +0000
4.3 @@ -1,5 +1,5 @@
4.4 /**
4.5 - * $Id: render.c,v 1.11 2006-08-02 04:06:45 nkeynes Exp $
4.6 + * $Id: render.c,v 1.12 2006-08-02 06:24:08 nkeynes Exp $
4.7 *
4.8 * PVR2 Renderer support. This part is primarily
4.9 *
4.10 @@ -235,7 +235,7 @@
4.11 if( bg->colour1 != bg->colour2 || bg->colour2 != bg->colour3 ) {
4.12 WARN( "Multiple background colours specified. Confused" );
4.13 fprintf( stderr, "bgplane mode: %08X PBUF: %08X\n", mode,
4.14 - MMIO_READ( PVR2, OBJBASE ) );
4.15 + MMIO_READ( PVR2, RENDER_POLYBASE ) );
4.16 fwrite_dump( poly, 80, stderr );
4.17 }
4.18 float x1 = MIN3( bg->x1, bg->x2, bg->x3 );
4.19 @@ -267,9 +267,9 @@
4.20 void pvr2_render_scene( )
4.21 {
4.22 struct tile_descriptor *tile_desc =
4.23 - (struct tile_descriptor *)mem_get_region(PVR2_RAM_BASE + MMIO_READ( PVR2, TILEBASE ));
4.24 + (struct tile_descriptor *)mem_get_region(PVR2_RAM_BASE + MMIO_READ( PVR2, RENDER_TILEBASE ));
4.25
4.26 - uint32_t render_addr = MMIO_READ( PVR2, RENDADDR1 );
4.27 + uint32_t render_addr = MMIO_READ( PVR2, RENDER_ADDR1 );
4.28 gboolean render_to_tex;
4.29 if( render_addr & 0x01000000 ) {
4.30 render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE_INT;
4.31 @@ -284,25 +284,25 @@
4.32 render_to_tex = FALSE;
4.33 }
4.34
4.35 - float bgplanez = MMIO_READF( PVR2, BGPLANEZ );
4.36 - uint32_t render_mode = MMIO_READ( PVR2, RENDMODE );
4.37 + float bgplanez = MMIO_READF( PVR2, RENDER_FARCLIP );
4.38 + uint32_t render_mode = MMIO_READ( PVR2, RENDER_MODE );
4.39 int width = 640; /* FIXME - get this from the tile buffer */
4.40 int height = 480;
4.41 int colour_format = pvr2_render_colour_format[render_mode&0x07];
4.42 pvr2_render_prepare_context( render_addr, width, height, colour_format,
4.43 bgplanez, render_to_tex );
4.44
4.45 - int clip_x = MMIO_READ( PVR2, HCLIP ) & 0x03FF;
4.46 - int clip_y = MMIO_READ( PVR2, VCLIP ) & 0x03FF;
4.47 - int clip_width = ((MMIO_READ( PVR2, HCLIP ) >> 16) & 0x03FF) - clip_x + 1;
4.48 - int clip_height= ((MMIO_READ( PVR2, VCLIP ) >> 16) & 0x03FF) - clip_y + 1;
4.49 + int clip_x = MMIO_READ( PVR2, RENDER_HCLIP ) & 0x03FF;
4.50 + int clip_y = MMIO_READ( PVR2, RENDER_VCLIP ) & 0x03FF;
4.51 + int clip_width = ((MMIO_READ( PVR2, RENDER_HCLIP ) >> 16) & 0x03FF) - clip_x + 1;
4.52 + int clip_height= ((MMIO_READ( PVR2, RENDER_VCLIP ) >> 16) & 0x03FF) - clip_y + 1;
4.53
4.54 /* Fog setup goes here */
4.55
4.56 /* Render the background plane */
4.57 - uint32_t bgplane_mode = MMIO_READ(PVR2, BGPLANE);
4.58 + uint32_t bgplane_mode = MMIO_READ(PVR2, RENDER_BGPLANE);
4.59 uint32_t *display_list =
4.60 - (uint32_t *)mem_get_region(PVR2_RAM_BASE + MMIO_READ( PVR2, OBJBASE ));
4.61 + (uint32_t *)mem_get_region(PVR2_RAM_BASE + MMIO_READ( PVR2, RENDER_POLYBASE ));
4.62
4.63 uint32_t *bgplane = display_list + (((bgplane_mode & 0x00FFFFFF)) >> 3) ;
4.64 pvr2_render_draw_backplane( bgplane_mode, bgplane );
5.1 --- a/src/pvr2/texcache.c Wed Aug 02 04:13:15 2006 +0000
5.2 +++ b/src/pvr2/texcache.c Wed Aug 02 06:24:08 2006 +0000
5.3 @@ -1,5 +1,5 @@
5.4 /**
5.5 - * $Id: texcache.c,v 1.6 2006-03-30 11:25:42 nkeynes Exp $
5.6 + * $Id: texcache.c,v 1.7 2006-08-02 06:24:08 nkeynes Exp $
5.7 *
5.8 * Texture cache. Responsible for maintaining a working set of OpenGL
5.9 * textures.
5.10 @@ -235,7 +235,7 @@
5.11
5.12 if( tex_format == PVR2_TEX_FORMAT_IDX8 ||
5.13 tex_format == PVR2_TEX_FORMAT_IDX4 ) {
5.14 - switch( MMIO_READ( PVR2, PALETTECFG ) & 0x03 ) {
5.15 + switch( MMIO_READ( PVR2, RENDER_PALETTE ) & 0x03 ) {
5.16 case 0: /* ARGB1555 */
5.17 intFormat = GL_RGB5_A1;
5.18 format = GL_RGBA;
.