1.1 --- a/src/sh4/mmu.c	Tue Aug 19 08:37:34 2008 +0000
     1.2 +++ b/src/sh4/mmu.c	Tue Aug 19 08:38:10 2008 +0000
     1.3 @@ -169,7 +169,8 @@
     1.4          }
     1.5          break;
     1.6      case CCR:
     1.7 -        mmu_set_cache_mode( val & (CCR_OIX|CCR_ORA) );
     1.8 +        mmu_set_cache_mode( val & (CCR_OIX|CCR_ORA|CCR_OCE) );
     1.9 +        val &= 0x81A7;
    1.10          break;
    1.11      default:
    1.12          break;

     2.1 --- a/src/sh4/sh4mmio.h	Tue Aug 19 08:37:34 2008 +0000
     2.2 +++ b/src/sh4/sh4mmio.h	Tue Aug 19 08:38:10 2008 +0000
     2.3 @@ -209,9 +209,8 @@
     2.4  #define CCR_MASK   0x000089AF
     2.5  #define CCR_RMASK  0x000081A7 /* Read mask */
     2.6  
     2.7 -#define MEM_OC_DISABLED 0
     2.8 -#define MEM_OC_INDEX0   CCR_ORA
     2.9 -#define MEM_OC_INDEX1   CCR_ORA|CCR_OIX
    2.10 +#define MEM_OC_INDEX0   (CCR_ORA|CCR_OCE)
    2.11 +#define MEM_OC_INDEX1   (CCR_ORA|CCR_OIX|CCR_OCE)
    2.12  
    2.13  /* MMU functions */
    2.14  void mmu_init(void);

     3.1 --- a/test/testregs.c	Tue Aug 19 08:37:34 2008 +0000
     3.2 +++ b/test/testregs.c	Tue Aug 19 08:38:10 2008 +0000
     3.3 @@ -192,6 +192,7 @@
     3.4      { 0xA05F81F4, 0xFFFFFFFF, 0 },
     3.5      { 0xA05F81F8, 0xFFFFFFFF, 0 },
     3.6      { 0xA05F81FC, 0xFFFFFFFF, 0 },
     3.7 +    { 0xFF00001C, 0xFFFFFFFF, 0x000081A7 },
     3.8      { 0, 0, 0 } };
     3.9      
    3.10  int main( int argc, char *argv[] )