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lxdream.org :: lxdream :: r1004:eae001858134
lxdream 0.9.1
released Jun 29
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changeset1004:eae001858134
parent1003:7b2688cbbca3
child1005:7c6ff471751c
child1007:dbc83607f07d
authornkeynes
dateSat Apr 04 10:17:57 2009 +0000 (10 years ago)
Remove last lingering bits of SH4-specific code from the ABI headers
src/sh4/sh4x86.in
src/xlat/x86/amd64abi.h
src/xlat/x86/ia32abi.h
1.1 --- a/src/sh4/sh4x86.in Fri Mar 27 06:13:34 2009 +0000
1.2 +++ b/src/sh4/sh4x86.in Sat Apr 04 10:17:57 2009 +0000
1.3 @@ -291,6 +291,8 @@
1.4 TESTL_imms_r32( 0x00000007, x86reg ); \
1.5 JNE_exc(EXC_DATA_ADDR_WRITE);
1.6
1.7 +#define address_space() ((sh4r.xlat_sh4_mode&SR_MD) ? (uintptr_t)sh4_address_space : (uintptr_t)sh4_user_address_space)
1.8 +
1.9 #define UNDEF(ir)
1.10 /* Note: For SR.MD == 1 && MMUCR.AT == 0, there are no memory exceptions, so
1.11 * don't waste the cycles expecting them. Otherwise we need to save the exception pointer.
1.12 @@ -298,7 +300,7 @@
1.13 #ifdef HAVE_FRAME_ADDRESS
1.14 static void call_read_func(int addr_reg, int value_reg, int offset, int pc)
1.15 {
1.16 - decode_address(addr_reg);
1.17 + decode_address(address_space(), addr_reg);
1.18 if( !sh4_x86.tlb_on && (sh4r.xlat_sh4_mode & SR_MD) ) {
1.19 CALL1_r32disp_r32(REG_ECX, offset, addr_reg);
1.20 } else {
1.21 @@ -316,7 +318,7 @@
1.22
1.23 static void call_write_func(int addr_reg, int value_reg, int offset, int pc)
1.24 {
1.25 - decode_address(addr_reg);
1.26 + decode_address(address_space(), addr_reg);
1.27 if( !sh4_x86.tlb_on && (sh4r.xlat_sh4_mode & SR_MD) ) {
1.28 CALL2_r32disp_r32_r32(REG_ECX, offset, addr_reg, value_reg);
1.29 } else {
1.30 @@ -340,7 +342,7 @@
1.31 #else
1.32 static void call_read_func(int addr_reg, int value_reg, int offset, int pc)
1.33 {
1.34 - decode_address(addr_reg);
1.35 + decode_address(address_space(), addr_reg);
1.36 CALL1_r32disp_r32(REG_ECX, offset, addr_reg);
1.37 if( value_reg != REG_RESULT1 ) {
1.38 MOVL_r32_r32( REG_RESULT1, value_reg );
1.39 @@ -349,7 +351,7 @@
1.40
1.41 static void call_write_func(int addr_reg, int value_reg, int offset, int pc)
1.42 {
1.43 - decode_address(addr_reg);
1.44 + decode_address(address_space(), addr_reg);
1.45 CALL2_r32disp_r32_r32(REG_ECX, offset, addr_reg, value_reg);
1.46 }
1.47 #endif
1.48 @@ -369,6 +371,7 @@
1.49 void sh4_translate_begin_block( sh4addr_t pc )
1.50 {
1.51 enter_block();
1.52 + MOVP_immptr_rptr( ((uint8_t *)&sh4r) + 128, REG_EBP );
1.53 sh4_x86.in_delay_slot = FALSE;
1.54 sh4_x86.fpuen_checked = FALSE;
1.55 sh4_x86.branch_taken = FALSE;
2.1 --- a/src/xlat/x86/amd64abi.h Fri Mar 27 06:13:34 2009 +0000
2.2 +++ b/src/xlat/x86/amd64abi.h Sat Apr 04 10:17:57 2009 +0000
2.3 @@ -23,9 +23,8 @@
2.4 #define REG_RESULT1 REG_RAX
2.5 #define MAX_REG_ARG 3 /* There's more, but we don't use more than 3 here anyway */
2.6
2.7 -static inline void decode_address( int addr_reg )
2.8 +static inline void decode_address( uintptr_t base, int addr_reg )
2.9 {
2.10 - uintptr_t base = (sh4r.xlat_sh4_mode&SR_MD) ? (uintptr_t)sh4_address_space : (uintptr_t)sh4_user_address_space;
2.11 MOVL_r32_r32( addr_reg, REG_ECX );
2.12 SHRL_imm_r32( 12, REG_ECX );
2.13 MOVP_immptr_rptr( base, REG_RDI );
2.14 @@ -102,7 +101,6 @@
2.15 static inline void enter_block( )
2.16 {
2.17 PUSH_r32(REG_RBP);
2.18 - MOVP_immptr_rptr( ((uint8_t *)&sh4r) + 128, REG_EBP );
2.19 SUBQ_imms_r64( 16, REG_RSP );
2.20 }
2.21
3.1 --- a/src/xlat/x86/ia32abi.h Fri Mar 27 06:13:34 2009 +0000
3.2 +++ b/src/xlat/x86/ia32abi.h Sat Apr 04 10:17:57 2009 +0000
3.3 @@ -26,9 +26,8 @@
3.4 #define REG_RESULT1 REG_EAX
3.5 #define MAX_REG_ARG 2
3.6
3.7 -static inline void decode_address( int addr_reg )
3.8 +static inline void decode_address( uintptr_t base, int addr_reg )
3.9 {
3.10 - uintptr_t base = (sh4r.xlat_sh4_mode&SR_MD) ? (uintptr_t)sh4_address_space : (uintptr_t)sh4_user_address_space;
3.11 MOVL_r32_r32( addr_reg, REG_ECX );
3.12 SHRL_imm_r32( 12, REG_ECX );
3.13 MOVP_sib_rptr( 2, REG_ECX, -1, base, REG_ECX );
3.14 @@ -142,7 +141,6 @@
3.15 static inline void enter_block( )
3.16 {
3.17 PUSH_r32(REG_EBP);
3.18 - MOVP_immptr_rptr( ((uint8_t *)&sh4r) + 128, REG_EBP );
3.19 SUBL_imms_r32( 8, REG_ESP );
3.20 }
3.21
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