Search
lxdream.org :: lxdream :: r61:eb7a73c9bcae
lxdream 0.9.1
released Jun 29
Download Now
changeset61:eb7a73c9bcae
parent60:d09f85b2a583
child62:a1cb6dfefec1
authornkeynes
dateMon Jan 02 14:50:12 2006 +0000 (14 years ago)
AICA IRQ event work in progress
src/aica/aica.c
src/aica/aica.h
1.1 --- a/src/aica/aica.c Mon Jan 02 14:49:51 2006 +0000
1.2 +++ b/src/aica/aica.c Mon Jan 02 14:50:12 2006 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: aica.c,v 1.9 2005-12-26 11:52:56 nkeynes Exp $
1.6 + * $Id: aica.c,v 1.10 2006-01-02 14:50:12 nkeynes Exp $
1.7 *
1.8 * This is the core sound system (ie the bit which does the actual work)
1.9 *
1.10 @@ -21,6 +21,7 @@
1.11 #include "dream.h"
1.12 #include "mem.h"
1.13 #include "aica.h"
1.14 +#include "armcore.h"
1.15 #define MMIO_IMPL
1.16 #include "aica.h"
1.17
1.18 @@ -90,6 +91,47 @@
1.19 return arm_load_state( f );
1.20 }
1.21
1.22 +int aica_event_pending = 0;
1.23 +int aica_clear_count = 0;
1.24 +
1.25 +/* Note: This is probably not necessarily technically correct but it should
1.26 + * work in the meantime.
1.27 + */
1.28 +
1.29 +void aica_event( int event )
1.30 +{
1.31 + if( aica_event_pending == 0 )
1.32 + armr.int_pending |= CPSR_F;
1.33 + aica_event_pending |= (1<<event);
1.34 +
1.35 + int pending = MMIO_READ( AICA2, AICA_IRQ );
1.36 + if( pending == 0 || event < pending )
1.37 + MMIO_WRITE( AICA2, AICA_IRQ, event );
1.38 +}
1.39 +
1.40 +void aica_clear_event( )
1.41 +{
1.42 + aica_clear_count++;
1.43 + if( aica_clear_count == 4 ) {
1.44 + int i;
1.45 + aica_clear_count = 0;
1.46 +
1.47 + for( i=0; i<8; i++ ) {
1.48 + if( aica_event_pending & (1<<i) ) {
1.49 + aica_event_pending &= ~(1<<i);
1.50 + break;
1.51 + }
1.52 + }
1.53 + for( ;i<8; i++ ) {
1.54 + if( aica_event_pending & (1<<i) ) {
1.55 + MMIO_WRITE( AICA2, AICA_IRQ, i );
1.56 + break;
1.57 + }
1.58 + }
1.59 + if( aica_event_pending == 0 )
1.60 + armr.int_pending &= ~CPSR_F;
1.61 + }
1.62 +}
1.63 /** Channel register structure:
1.64 * 00 4 Channel config
1.65 * 04 4 Waveform address lo (16 bits)
1.66 @@ -142,6 +184,9 @@
1.67 }
1.68 MMIO_WRITE( AICA2, AICA_RESET, val );
1.69 break;
1.70 + case AICA_IRQCLEAR:
1.71 + aica_clear_event();
1.72 + break;
1.73 default:
1.74 MMIO_WRITE( AICA2, reg, val );
1.75 break;
2.1 --- a/src/aica/aica.h Mon Jan 02 14:49:51 2006 +0000
2.2 +++ b/src/aica/aica.h Mon Jan 02 14:50:12 2006 +0000
2.3 @@ -1,5 +1,5 @@
2.4 /**
2.5 - * $Id: aica.h,v 1.4 2005-12-27 08:42:57 nkeynes Exp $
2.6 + * $Id: aica.h,v 1.5 2006-01-02 14:50:12 nkeynes Exp $
2.7 *
2.8 * MMIO definitions for the AICA sound chip. Note that the regions defined
2.9 * here are relative to the SH4 memory map (0x00700000 based), rather than
2.10 @@ -32,14 +32,17 @@
2.11 LONG_PORT( 0x040, CDDA_VOL_L, PORT_MRW, 0, "CDDA Volume left" )
2.12 LONG_PORT( 0x044, CDDA_VOL_R, PORT_MRW, 0, "CDDA Volume right" )
2.13 LONG_PORT( 0x800, VOL_MASTER, PORT_MRW, UNDEFINED, "Master volume" )
2.14 -LONG_PORT( 0x890, AICA_TIMER, PORT_MRW, 0, "IRQ Timer (?)" )
2.15 +LONG_PORT( 0x808, AICA_UNK7, PORT_MRW, 0, "AICA ??? 7" )
2.16 +LONG_PORT( 0x880, AICA_TIMER1, PORT_MRW, 0, "AICA Timer 1" )
2.17 +LONG_PORT( 0x890, AICA_TIMER2, PORT_MRW, 0, "AICA Timer 2" )
2.18 LONG_PORT( 0x89C, AICA_UNK1, PORT_MRW, 0, "AICA ??? 1" )
2.19 LONG_PORT( 0x8A4, AICA_UNK2, PORT_MRW, 0, "AICA ??? 2" )
2.20 BYTE_PORT( 0x8A8, AICA_UNK3, PORT_MRW, 0, "AICA ??? 3" )
2.21 BYTE_PORT( 0x8AC, AICA_UNK4, PORT_MRW, 0, "AICA ??? 4" )
2.22 BYTE_PORT( 0x8B0, AICA_UNK5, PORT_MRW, 0, "AICA ??? 5" )
2.23 LONG_PORT( 0xC00, AICA_RESET,PORT_MRW, 1, "AICA reset" )
2.24 -LONG_PORT( 0xD04, AICA_UNK6, PORT_MRW, 0, "AICA ??? 6" )
2.25 +LONG_PORT( 0xD00, AICA_IRQ, PORT_MR, 1, "AICA IRQ Pending" )
2.26 +LONG_PORT( 0xD04, AICA_IRQCLEAR, PORT_MRW, 0, "AICA IRQ Clear" )
2.27 MMIO_REGION_END
2.28
2.29 MMIO_REGION_LIST_BEGIN( spu )
2.30 @@ -50,3 +53,8 @@
2.31
2.32 void aica_init( void );
2.33 void aica_reset( void );
2.34 +
2.35 +#define AICA_EVENT_TIMER 2
2.36 +#define AICA_EVENT_OTHER 5
2.37 +
2.38 +void aica_event( int event );
.