revision 819:ef4fec10a63a
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raw | bz2 | zip | gz changeset | 819:ef4fec10a63a |
parent | 818:2e08d8237d33 |
child | 820:de3af5480989 |
author | nkeynes |
date | Tue Aug 19 22:58:05 2008 +0000 (12 years ago) |
Add stubs for the (undocumented) SH4 performance counter registers
![]() | src/sh4/mmu.c | view | annotate | diff | log | |
![]() | src/sh4/sh4mmio.h | view | annotate | diff | log |
1.1 --- a/src/sh4/mmu.c Tue Aug 19 13:00:46 2008 +00001.2 +++ b/src/sh4/mmu.c Tue Aug 19 22:58:05 2008 +00001.3 @@ -174,6 +174,12 @@1.4 mmu_set_cache_mode( val & (CCR_OIX|CCR_ORA|CCR_OCE) );1.5 val &= 0x81A7;1.6 break;1.7 + case PMCR1:1.8 + case PMCR2:1.9 + if( val != 0 ) {1.10 + WARN( "Performance counters not implemented" );1.11 + }1.12 + break;1.13 default:1.14 break;1.15 }1.16 @@ -941,3 +947,19 @@1.17 return TRUE;1.18 }1.20 +/********************************* PMM *************************************/1.21 +1.22 +/**1.23 + * Side note - this is here (rather than in sh4mmio.c) as the control registers1.24 + * are part of the MMU block, and it seems simplest to keep it all together.1.25 + */1.26 +1.27 +int32_t mmio_region_PMM_read( uint32_t reg )1.28 +{1.29 + return MMIO_READ( PMM, reg );1.30 +}1.31 +1.32 +void mmio_region_PMM_write( uint32_t reg, uint32_t val )1.33 +{1.34 + /* Read-only */1.35 +}
2.1 --- a/src/sh4/sh4mmio.h Tue Aug 19 13:00:46 2008 +00002.2 +++ b/src/sh4/sh4mmio.h Tue Aug 19 22:58:05 2008 +00002.3 @@ -50,6 +50,16 @@2.4 LONG_PORT( 0x034, PTEA, PORT_MRW, UNDEFINED, "Page table entry assistance" )2.5 LONG_PORT( 0x038, QACR0,PORT_MRW, UNDEFINED, "Queue address control 0" )2.6 LONG_PORT( 0x03C, QACR1,PORT_MRW, UNDEFINED, "Queue address control 1" )2.7 + WORD_PORT( 0x084, PMCR1, PORT_MRW, 0, "Performance counter control 1" )2.8 + WORD_PORT( 0x088, PMCR2, PORT_MRW, 0, "Performance counter control 2" )2.9 +MMIO_REGION_END2.10 +2.11 +/* Performance counter values (undocumented) */2.12 +MMIO_REGION_BEGIN( 0xFF100000, PMM, "Performance monitoring" )2.13 + LONG_PORT (0x004, PMCTR1H, PORT_MR, 0, "Performance counter 1 High" )2.14 + LONG_PORT (0x008, PMCTR1L, PORT_MR, 0, "Performance counter 1 Low" )2.15 + LONG_PORT (0x00C, PMCTR2H, PORT_MR, 0, "Performance counter 2 High" )2.16 + LONG_PORT (0x010, PMCTR2L, PORT_MR, 0, "Performance counter 2 Low" )2.17 MMIO_REGION_END2.19 /* User Break Controller (Page 717 [757] of sh7750h manual) */2.20 @@ -182,6 +192,7 @@2.21 MMIO_REGION( TMU )2.22 MMIO_REGION( SCI )2.23 MMIO_REGION( SCIF )2.24 + MMIO_REGION( PMM )2.25 MMIO_REGION_LIST_END2.27 /* mmucr register bits */2.28 @@ -213,6 +224,11 @@2.29 #define MEM_OC_INDEX0 (CCR_ORA|CCR_OCE)2.30 #define MEM_OC_INDEX1 (CCR_ORA|CCR_OIX|CCR_OCE)2.32 +#define PMCR_CLKF 0x01002.33 +#define PMCR_PMCLR 0x20002.34 +#define PMCR_PMST 0x40002.35 +#define PMCR_PMEN 0x80002.36 +2.37 /* MMU functions */2.38 void mmu_init(void);2.39 void mmu_set_cache_mode( int );
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