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lxdream.org :: lxdream :: r86:f151e63f9754
lxdream 0.9.1
released Jun 29
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changeset86:f151e63f9754
parent85:71e239d20c5d
child87:11208d725b61
authornkeynes
dateSun Jan 22 22:40:05 2006 +0000 (14 years ago)
Add aica_enable() function for aica-only mode, disable by default
Halt ARM on invalid address but leave everything else running
Error if ESD can't start
src/aica/aica.c
src/aica/aica.h
src/aica/armcore.c
src/aica/armcore.h
src/drivers/audio_esd.c
1.1 --- a/src/aica/aica.c Sun Jan 22 22:38:51 2006 +0000
1.2 +++ b/src/aica/aica.c Sun Jan 22 22:40:05 2006 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: aica.c,v 1.15 2006-01-17 12:54:02 nkeynes Exp $
1.6 + * $Id: aica.c,v 1.16 2006-01-22 22:40:05 nkeynes Exp $
1.7 *
1.8 * This is the core sound system (ie the bit which does the actual work)
1.9 *
1.10 @@ -150,6 +150,11 @@
1.11 }
1.12 }
1.13
1.14 +void aica_enable( void )
1.15 +{
1.16 + mmio_region_AICA2_write( AICA_RESET, MMIO_READ(AICA2,AICA_RESET) & ~1 );
1.17 +}
1.18 +
1.19 /** Channel register structure:
1.20 * 00 4 Channel config
1.21 * 04 4 Waveform address lo (16 bits)
2.1 --- a/src/aica/aica.h Sun Jan 22 22:38:51 2006 +0000
2.2 +++ b/src/aica/aica.h Sun Jan 22 22:40:05 2006 +0000
2.3 @@ -1,5 +1,5 @@
2.4 /**
2.5 - * $Id: aica.h,v 1.7 2006-01-10 13:56:54 nkeynes Exp $
2.6 + * $Id: aica.h,v 1.8 2006-01-22 22:40:05 nkeynes Exp $
2.7 *
2.8 * MMIO definitions for the AICA sound chip. Note that the regions defined
2.9 * here are relative to the SH4 memory map (0x00700000 based), rather than
2.10 @@ -40,7 +40,7 @@
2.11 BYTE_PORT( 0x8A8, AICA_UNK3, PORT_MRW, 0, "AICA ??? 3" )
2.12 BYTE_PORT( 0x8AC, AICA_UNK4, PORT_MRW, 0, "AICA ??? 4" )
2.13 BYTE_PORT( 0x8B0, AICA_UNK5, PORT_MRW, 0, "AICA ??? 5" )
2.14 -LONG_PORT( 0xC00, AICA_RESET,PORT_MRW, 0, "AICA reset" )
2.15 +LONG_PORT( 0xC00, AICA_RESET,PORT_MRW, 1, "AICA reset" )
2.16 LONG_PORT( 0xD00, AICA_IRQ, PORT_MR, 0, "AICA IRQ Pending" )
2.17 LONG_PORT( 0xD04, AICA_IRQCLEAR, PORT_MRW, 0, "AICA IRQ Clear" )
2.18 MMIO_REGION_END
2.19 @@ -53,6 +53,7 @@
2.20
2.21 void aica_init( void );
2.22 void aica_reset( void );
2.23 +void aica_enable( void );
2.24
2.25 #define AICA_EVENT_TIMER 2
2.26 #define AICA_EVENT_OTHER 5
3.1 --- a/src/aica/armcore.c Sun Jan 22 22:38:51 2006 +0000
3.2 +++ b/src/aica/armcore.c Sun Jan 22 22:40:05 2006 +0000
3.3 @@ -1,5 +1,5 @@
3.4 /**
3.5 - * $Id: armcore.c,v 1.19 2006-01-17 12:53:39 nkeynes Exp $
3.6 + * $Id: armcore.c,v 1.20 2006-01-22 22:40:05 nkeynes Exp $
3.7 *
3.8 * ARM7TDMI CPU emulation core.
3.9 *
3.10 @@ -90,6 +90,10 @@
3.11 uint32_t arm_run_slice( uint32_t num_samples )
3.12 {
3.13 int i,j,k;
3.14 +
3.15 + if( !armr.running )
3.16 + return num_samples;
3.17 +
3.18 for( i=0; i<num_samples; i++ ) {
3.19 for( j=0; j < CYCLES_PER_SAMPLE; j++ ) {
3.20 armr.icount++;
3.21 @@ -143,6 +147,7 @@
3.22
3.23 armr.cpsr = MODE_SVC | CPSR_I | CPSR_F;
3.24 armr.r[15] = 0x00000000;
3.25 + armr.running = TRUE;
3.26 }
3.27
3.28 #define SET_CPSR_CONTROL 0x00010000
3.29 @@ -757,8 +762,7 @@
3.30 cond = 0;
3.31 UNDEF(ir);
3.32 }
3.33 - if( !cond )
3.34 - return TRUE;
3.35 + if( cond ) {
3.36
3.37 /**
3.38 * Condition passed, now for the actual instructions...
3.39 @@ -1369,9 +1373,12 @@
3.40 }
3.41 break;
3.42 }
3.43 - if( armr.r[15] > 0x00200000 ) {
3.44 - dreamcast_stop();
3.45 - ERROR( "BRANCH to fishkill at %08X", pc );
3.46 +
3.47 + }
3.48 +
3.49 + if( armr.r[15] >= 0x00200000 ) {
3.50 + armr.running = FALSE;
3.51 + ERROR( "ARM Halted: BRANCH to invalid address %08X at %08X", armr.r[15], pc );
3.52 return FALSE;
3.53 }
3.54 return TRUE;
4.1 --- a/src/aica/armcore.h Sun Jan 22 22:38:51 2006 +0000
4.2 +++ b/src/aica/armcore.h Sun Jan 22 22:40:05 2006 +0000
4.3 @@ -1,5 +1,5 @@
4.4 /**
4.5 - * $Id: armcore.h,v 1.13 2006-01-12 11:30:19 nkeynes Exp $
4.6 + * $Id: armcore.h,v 1.14 2006-01-22 22:40:05 nkeynes Exp $
4.7 *
4.8 * Interface definitions for the ARM CPU emulation core proper.
4.9 *
4.10 @@ -52,6 +52,8 @@
4.11 uint32_t int_pending; /* Mask of CPSR_I and CPSR_F */
4.12 uint32_t shift_c; /* used for temporary storage of shifter results */
4.13 uint32_t icount; /* Instruction counter */
4.14 + gboolean running; /* Indicates that the ARM is operational, as opposed to
4.15 + * halted */
4.16 };
4.17
4.18 #define CPSR_N 0x80000000 /* Negative flag */
5.1 --- a/src/drivers/audio_esd.c Sun Jan 22 22:38:51 2006 +0000
5.2 +++ b/src/drivers/audio_esd.c Sun Jan 22 22:40:05 2006 +0000
5.3 @@ -1,5 +1,5 @@
5.4 /**
5.5 - * $Id: audio_esd.c,v 1.4 2006-01-16 11:22:41 nkeynes Exp $
5.6 + * $Id: audio_esd.c,v 1.5 2006-01-22 22:40:05 nkeynes Exp $
5.7 *
5.8 * The esd (esound) audio driver
5.9 *
5.10 @@ -38,6 +38,9 @@
5.11 else esd_format |= ESD_MONO;
5.12
5.13 esd_handle = esd_play_stream( esd_format, rate, "localhost", "dreamon" );
5.14 + if( esd_handle == -1 ) {
5.15 + ERROR( "Unable to open audio output (ESD)" );
5.16 + }
5.17 return TRUE;
5.18 }
5.19
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