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lxdream.org :: lxdream :: r197:f65ff8c8320d
lxdream 0.9.1
released Jun 29
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changeset197:f65ff8c8320d
parent196:3d3c761afbf4
child198:627220aa0e3b
authornkeynes
dateSun Aug 06 02:47:08 2006 +0000 (13 years ago)
Add masks on all PVR2 registers
Add missing registers and rename display registers for consistency
src/pvr2/pvr2.c
src/pvr2/pvr2mmio.h
1.1 --- a/src/pvr2/pvr2.c Sun Aug 06 02:46:09 2006 +0000
1.2 +++ b/src/pvr2/pvr2.c Sun Aug 06 02:47:08 2006 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: pvr2.c,v 1.30 2006-08-04 01:38:27 nkeynes Exp $
1.6 + * $Id: pvr2.c,v 1.31 2006-08-06 02:47:08 nkeynes Exp $
1.7 *
1.8 * PVR2 (Video) Core module implementation and MMIO registers.
1.9 *
1.10 @@ -148,11 +148,11 @@
1.11 */
1.12 void pvr2_display_frame( void )
1.13 {
1.14 - uint32_t display_addr = MMIO_READ( PVR2, DISPADDR1 );
1.15 + uint32_t display_addr = MMIO_READ( PVR2, DISP_ADDR1 );
1.16
1.17 - int dispsize = MMIO_READ( PVR2, DISPSIZE );
1.18 - int dispmode = MMIO_READ( PVR2, DISPMODE );
1.19 - int vidcfg = MMIO_READ( PVR2, DISPCFG );
1.20 + int dispsize = MMIO_READ( PVR2, DISP_SIZE );
1.21 + int dispmode = MMIO_READ( PVR2, DISP_MODE );
1.22 + int vidcfg = MMIO_READ( PVR2, DISP_CFG );
1.23 int vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1;
1.24 int vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
1.25 int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
1.26 @@ -162,7 +162,7 @@
1.27 video_buffer_idx = !video_buffer_idx;
1.28 video_buffer_t last = &video_buffer[video_buffer_idx];
1.29 buffer->rowstride = (vid_ppl + vid_stride) << 2;
1.30 - buffer->data = video_base + MMIO_READ( PVR2, DISPADDR1 );
1.31 + buffer->data = video_base + MMIO_READ( PVR2, DISP_ADDR1 );
1.32 buffer->vres = vid_lpf;
1.33 if( interlaced ) buffer->vres <<= 1;
1.34 switch( (dispmode & DISPMODE_COL) >> 2 ) {
1.35 @@ -197,8 +197,8 @@
1.36 }
1.37 if( !bEnabled ) {
1.38 display_driver->display_blank_frame( 0 );
1.39 - } else if( MMIO_READ( PVR2, DISPCFG2 ) & 0x08 ) { /* Blanked */
1.40 - uint32_t colour = MMIO_READ( PVR2, DISPBORDER );
1.41 + } else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) { /* Blanked */
1.42 + uint32_t colour = MMIO_READ( PVR2, DISP_BORDER );
1.43 display_driver->display_blank_frame( colour );
1.44 } else if( !pvr2_render_display_frame( PVR2_RAM_BASE + display_addr ) ) {
1.45 display_driver->display_frame( buffer );
1.46 @@ -207,11 +207,14 @@
1.47 pvr2_state.frame_count++;
1.48 }
1.49
1.50 +/**
1.51 + * This has to handle every single register individually as they all get masked
1.52 + * off differently (and its easier to do it at write time)
1.53 + */
1.54 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
1.55 {
1.56 if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
1.57 MMIO_WRITE( PVR2, reg, val );
1.58 - /* I don't want to hear about these */
1.59 return;
1.60 }
1.61
1.62 @@ -223,6 +226,10 @@
1.63 case TA_LISTPOS:
1.64 /* Readonly registers */
1.65 break;
1.66 + case PVRRESET:
1.67 + val &= 0x00000007; /* Do stuff? */
1.68 + MMIO_WRITE( PVR2, reg, val );
1.69 + break;
1.70 case RENDER_START:
1.71 if( val == 0xFFFFFFFF )
1.72 pvr2_render_scene();
1.73 @@ -236,10 +243,10 @@
1.74 case RENDER_TSPCFG:
1.75 MMIO_WRITE( PVR2, reg, val&0x00010101 );
1.76 break;
1.77 - case DISPBORDER:
1.78 + case DISP_BORDER:
1.79 MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
1.80 break;
1.81 - case DISPMODE:
1.82 + case DISP_MODE:
1.83 MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
1.84 break;
1.85 case RENDER_MODE:
1.86 @@ -248,7 +255,7 @@
1.87 case RENDER_SIZE:
1.88 MMIO_WRITE( PVR2, reg, val&0x000001FF );
1.89 break;
1.90 - case DISPADDR1:
1.91 + case DISP_ADDR1:
1.92 val &= 0x00FFFFFC;
1.93 MMIO_WRITE( PVR2, reg, val );
1.94 if( pvr2_state.retrace ) {
1.95 @@ -256,10 +263,10 @@
1.96 pvr2_state.retrace = FALSE;
1.97 }
1.98 break;
1.99 - case DISPADDR2:
1.100 + case DISP_ADDR2:
1.101 MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
1.102 break;
1.103 - case DISPSIZE:
1.104 + case DISP_SIZE:
1.105 MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
1.106 break;
1.107 case RENDER_ADDR1:
1.108 @@ -272,30 +279,97 @@
1.109 case RENDER_VCLIP:
1.110 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
1.111 break;
1.112 - case HPOS_IRQ:
1.113 + case DISP_HPOSIRQ:
1.114 MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
1.115 break;
1.116 - case VPOS_IRQ:
1.117 + case DISP_VPOSIRQ:
1.118 val = val & 0x03FF03FF;
1.119 pvr2_state.irq_vpos1 = (val >> 16);
1.120 pvr2_state.irq_vpos2 = val & 0x03FF;
1.121 MMIO_WRITE( PVR2, reg, val );
1.122 break;
1.123 + case RENDER_NEARCLIP:
1.124 + MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );
1.125 + break;
1.126 case RENDER_SHADOW:
1.127 MMIO_WRITE( PVR2, reg, val&0x000001FF );
1.128 break;
1.129 case RENDER_OBJCFG:
1.130 MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
1.131 break;
1.132 + case PVRUNK2:
1.133 + MMIO_WRITE( PVR2, reg, val&0x00000007 );
1.134 + break;
1.135 case RENDER_TSPCLIP:
1.136 MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
1.137 break;
1.138 + case RENDER_FARCLIP:
1.139 + MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );
1.140 + break;
1.141 case RENDER_BGPLANE:
1.142 MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
1.143 break;
1.144 case RENDER_ISPCFG:
1.145 MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
1.146 break;
1.147 + case VRAM_CFG1:
1.148 + MMIO_WRITE( PVR2, reg, val&0x000000FF );
1.149 + break;
1.150 + case VRAM_CFG2:
1.151 + MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
1.152 + break;
1.153 + case VRAM_CFG3:
1.154 + MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
1.155 + break;
1.156 + case RENDER_FOGTBLCOL:
1.157 + case RENDER_FOGVRTCOL:
1.158 + MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );
1.159 + break;
1.160 + case RENDER_FOGCOEFF:
1.161 + MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
1.162 + break;
1.163 + case RENDER_CLAMPHI:
1.164 + case RENDER_CLAMPLO:
1.165 + MMIO_WRITE( PVR2, reg, val );
1.166 + break;
1.167 + case DISP_CFG:
1.168 + MMIO_WRITE( PVR2, reg, val&0x000003FF );
1.169 + break;
1.170 + case DISP_HBORDER:
1.171 + case DISP_SYNC:
1.172 + case DISP_VBORDER:
1.173 + MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
1.174 + break;
1.175 + case DISP_SYNC2:
1.176 + MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );
1.177 + break;
1.178 + case RENDER_TEXSIZE:
1.179 + MMIO_WRITE( PVR2, reg, val&0x00031F1F );
1.180 + break;
1.181 + case DISP_CFG2:
1.182 + MMIO_WRITE( PVR2, reg, val&0x003F01FF );
1.183 + break;
1.184 + case DISP_HPOS:
1.185 + MMIO_WRITE( PVR2, reg, val&0x000003FF );
1.186 + break;
1.187 + case DISP_VPOS:
1.188 + MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
1.189 + break;
1.190 + case SCALERCFG:
1.191 + MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
1.192 + break;
1.193 + case RENDER_PALETTE:
1.194 + MMIO_WRITE( PVR2, reg, val&0x00000003 );
1.195 + break;
1.196 + case PVRUNK3:
1.197 + MMIO_WRITE( PVR2, reg, val&0x000FFF3F );
1.198 + break;
1.199 + case PVRUNK5:
1.200 + MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
1.201 + break;
1.202 + case PVRUNK6:
1.203 + MMIO_WRITE( PVR2, reg, val&0x000000FF );
1.204 + break;
1.205 case TA_TILEBASE:
1.206 case TA_LISTEND:
1.207 case TA_LISTBASE:
1.208 @@ -312,26 +386,28 @@
1.209 case TA_TILECFG:
1.210 MMIO_WRITE( PVR2, reg, val&0x00133333 );
1.211 break;
1.212 + case YUV_ADDR:
1.213 + MMIO_WRITE( PVR2, reg, val&0x00FFFFF8 );
1.214 + break;
1.215 + case YUV_CFG:
1.216 + MMIO_WRITE( PVR2, reg, val&0x01013F3F );
1.217 + break;
1.218 case TA_INIT:
1.219 if( val & 0x80000000 )
1.220 pvr2_ta_init();
1.221 break;
1.222 -
1.223 - /* Nonexistent registers (as far as we know, anyway) */
1.224 - case 0x01C:
1.225 - case 0x024:
1.226 - case 0x028:
1.227 - case 0x058:
1.228 - break;
1.229 - default:
1.230 - MMIO_WRITE( PVR2, reg, val );
1.231 + case TA_REINIT:
1.232 + break;
1.233 + case PVRUNK7:
1.234 + MMIO_WRITE( PVR2, reg, val&0x00000001 );
1.235 + break;
1.236 }
1.237 }
1.238
1.239 MMIO_REGION_READ_FN( PVR2, reg )
1.240 {
1.241 switch( reg ) {
1.242 - case BEAMPOS:
1.243 + case DISP_BEAMPOS:
1.244 return sh4r.icount&0x20 ? 0x2000 : 1;
1.245 default:
1.246 return MMIO_READ( PVR2, reg );
1.247 @@ -342,7 +418,7 @@
1.248
1.249 void pvr2_set_base_address( uint32_t base )
1.250 {
1.251 - mmio_region_PVR2_write( DISPADDR1, base );
1.252 + mmio_region_PVR2_write( DISP_ADDR1, base );
1.253 }
1.254
1.255
2.1 --- a/src/pvr2/pvr2mmio.h Sun Aug 06 02:46:09 2006 +0000
2.2 +++ b/src/pvr2/pvr2mmio.h Sun Aug 06 02:47:08 2006 +0000
2.3 @@ -1,5 +1,5 @@
2.4 /**
2.5 - * $Id: pvr2mmio.h,v 1.6 2006-08-04 01:38:27 nkeynes Exp $
2.6 + * $Id: pvr2mmio.h,v 1.7 2006-08-06 02:47:08 nkeynes Exp $
2.7 *
2.8 * PVR2 (video chip) MMIO register definitions.
2.9 *
2.10 @@ -21,19 +21,19 @@
2.11 MMIO_REGION_BEGIN( 0x005F8000, PVR2, "Power VR/2" )
2.12 LONG_PORT( 0x000, PVRID, PORT_R, 0x17FD11DB, "PVR2 Core ID" )
2.13 LONG_PORT( 0x004, PVRVER, PORT_R, 0x00000011, "PVR2 Core Version" )
2.14 - LONG_PORT( 0x008, PVRRST, PORT_MRW, 0, "PVR2 Reset" )
2.15 + LONG_PORT( 0x008, PVRRESET, PORT_MRW, 0, "PVR2 Reset" )
2.16 LONG_PORT( 0x014, RENDER_START, PORT_W, 0, "Start render" )
2.17 LONG_PORT( 0x018, PVRUNK1, PORT_MRW, 0, "PVR2 unknown register 1" )
2.18 LONG_PORT( 0x020, RENDER_POLYBASE, PORT_MRW, 0, "Object buffer base offset" )
2.19 LONG_PORT( 0x02C, RENDER_TILEBASE, PORT_MRW, 0, "Tile buffer base offset" )
2.20 LONG_PORT( 0x030, RENDER_TSPCFG, PORT_MRW, 0, "TSP config?" )
2.21 - LONG_PORT( 0x040, DISPBORDER, PORT_MRW, 0, "Border Colour (RGB)" )
2.22 - LONG_PORT( 0x044, DISPMODE, PORT_MRW, 0, "Display Mode" )
2.23 + LONG_PORT( 0x040, DISP_BORDER, PORT_MRW, 0, "Border Colour (RGB)" )
2.24 + LONG_PORT( 0x044, DISP_MODE, PORT_MRW, 0, "Display Mode" )
2.25 LONG_PORT( 0x048, RENDER_MODE, PORT_MRW, 0, "Rendering Mode" )
2.26 LONG_PORT( 0x04C, RENDER_SIZE, PORT_MRW, 0, "Rendering width (bytes/2)" )
2.27 - LONG_PORT( 0x050, DISPADDR1, PORT_MRW, 0, "Video memory base 1" )
2.28 - LONG_PORT( 0x054, DISPADDR2, PORT_MRW, 0, "Video memory base 2" )
2.29 - LONG_PORT( 0x05C, DISPSIZE, PORT_MRW, 0, "Display size" )
2.30 + LONG_PORT( 0x050, DISP_ADDR1, PORT_MRW, 0, "Video memory base 1" )
2.31 + LONG_PORT( 0x054, DISP_ADDR2, PORT_MRW, 0, "Video memory base 2" )
2.32 + LONG_PORT( 0x05C, DISP_SIZE, PORT_MRW, 0, "Display size" )
2.33 LONG_PORT( 0x060, RENDER_ADDR1, PORT_MRW, 0, "Rendering memory base 1" )
2.34 LONG_PORT( 0x064, RENDER_ADDR2, PORT_MRW, 0, "Rendering memory base 2" )
2.35 LONG_PORT( 0x068, RENDER_HCLIP, PORT_MRW, 0, "Horizontal clipping area" )
2.36 @@ -41,29 +41,38 @@
2.37 LONG_PORT( 0x074, RENDER_SHADOW, PORT_MRW, 0, "Shadowing" )
2.38 LONG_PORT( 0x078, RENDER_NEARCLIP, PORT_MRW, 0, "Object clip distance (float32)" )
2.39 LONG_PORT( 0x07C, RENDER_OBJCFG, PORT_MRW, 0, "Object config" )
2.40 + LONG_PORT( 0x080, PVRUNK2, PORT_MRW, 0, "PVR2 unknown register 2" )
2.41 LONG_PORT( 0x084, RENDER_TSPCLIP, PORT_MRW, 0, "Texture clip distance (float32)" )
2.42 LONG_PORT( 0x088, RENDER_FARCLIP, PORT_MRW, 0, "Background plane depth (float32)" )
2.43 LONG_PORT( 0x08C, RENDER_BGPLANE, PORT_MRW, 0, "Background plane config" )
2.44 LONG_PORT( 0x098, RENDER_ISPCFG, PORT_MRW, 0, "ISP config" )
2.45 + LONG_PORT( 0x0A0, VRAM_CFG1, PORT_MRW, 0, "VRAM config 1" )
2.46 + LONG_PORT( 0x0A4, VRAM_CFG2, PORT_MRW, 0, "VRAM config 2" )
2.47 + LONG_PORT( 0x0A8, VRAM_CFG3, PORT_MRW, 0, "VRAM config 3" )
2.48 LONG_PORT( 0x0B0, RENDER_FOGTBLCOL, PORT_MRW, 0, "Fog table colour" )
2.49 LONG_PORT( 0x0B4, RENDER_FOGVRTCOL, PORT_MRW, 0, "Fog vertex colour" )
2.50 LONG_PORT( 0x0B8, RENDER_FOGCOEFF, PORT_MRW, 0, "Fog density coefficient (float16)" )
2.51 LONG_PORT( 0x0BC, RENDER_CLAMPHI, PORT_MRW, 0, "Clamp high colour" )
2.52 LONG_PORT( 0x0C0, RENDER_CLAMPLO, PORT_MRW, 0, "Clamp low colour" )
2.53 LONG_PORT( 0x0C4, GUNPOS, PORT_MRW, 0, "Lightgun position" )
2.54 - LONG_PORT( 0x0C8, HPOS_IRQ, PORT_MRW, 0, "Raster horizontal event position" )
2.55 - LONG_PORT( 0x0CC, VPOS_IRQ, PORT_MRW, 0, "Raster event position" )
2.56 - LONG_PORT( 0x0D0, DISPCFG, PORT_MRW, 0, "Sync configuration & enable" )
2.57 - LONG_PORT( 0x0D4, HBORDER, PORT_MRW, 0, "Horizontal border area" )
2.58 - LONG_PORT( 0x0D8, REFRESH, PORT_MRW, 0, "Refresh rates?" )
2.59 - LONG_PORT( 0x0DC, VBORDER, PORT_MRW, 0, "Vertical border area" )
2.60 - LONG_PORT( 0x0E0, SYNCPOS, PORT_MRW, 0, "Sync pulse timing" )
2.61 + LONG_PORT( 0x0C8, DISP_HPOSIRQ, PORT_MRW, 0, "Raster horizontal event position" )
2.62 + LONG_PORT( 0x0CC, DISP_VPOSIRQ, PORT_MRW, 0, "Raster event position" )
2.63 + LONG_PORT( 0x0D0, DISP_CFG, PORT_MRW, 0, "Sync configuration & enable" )
2.64 + LONG_PORT( 0x0D4, DISP_HBORDER, PORT_MRW, 0, "Horizontal border area" )
2.65 + LONG_PORT( 0x0D8, DISP_SYNC, PORT_MRW, 0, "Sync pulse timing" )
2.66 + LONG_PORT( 0x0DC, DISP_VBORDER, PORT_MRW, 0, "Vertical border area" )
2.67 + LONG_PORT( 0x0E0, DISP_SYNC2, PORT_MRW, 0, "Sync pulse widths" )
2.68 LONG_PORT( 0x0E4, RENDER_TEXSIZE, PORT_MRW, 0, "Texture modulo width" )
2.69 - LONG_PORT( 0x0E8, DISPCFG2, PORT_MRW, 0, "Video configuration 2" )
2.70 - LONG_PORT( 0x0F0, VPOS, PORT_MRW, 0, "Vertical display position" )
2.71 + LONG_PORT( 0x0E8, DISP_CFG2, PORT_MRW, 0, "Video configuration 2" )
2.72 + LONG_PORT( 0x0EC, DISP_HPOS, PORT_MRW, 0, "Horizontal display position" )
2.73 + LONG_PORT( 0x0F0, DISP_VPOS, PORT_MRW, 0, "Vertical display position" )
2.74 LONG_PORT( 0x0F4, SCALERCFG, PORT_MRW, 0, "Scaler configuration (?)" )
2.75 LONG_PORT( 0x108, RENDER_PALETTE, PORT_MRW, 0, "Palette configuration" )
2.76 - LONG_PORT( 0x10C, BEAMPOS, PORT_R, 0, "Raster beam position" )
2.77 + LONG_PORT( 0x10C, DISP_BEAMPOS, PORT_R, 0, "Raster beam position" )
2.78 + LONG_PORT( 0x110, PVRUNK3, PORT_MRW, 0, "PVR2 unknown register 3" )
2.79 + LONG_PORT( 0x114, PVRUNK4, PORT_MRW, 0, "PVR2 unknown register 4" )
2.80 + LONG_PORT( 0x118, PVRUNK5, PORT_MRW, 0, "PVR2 unkown register 5" )
2.81 + LONG_PORT( 0x11C, PVRUNK6, PORT_MRW, 0, "PVR2 unkown register 6" )
2.82 LONG_PORT( 0x124, TA_TILEBASE, PORT_MRW, 0, "TA Tile matrix start" )
2.83 LONG_PORT( 0x128, TA_POLYBASE, PORT_MRW, 0, "TA Polygon buffer start" )
2.84 LONG_PORT( 0x12C, TA_LISTEND, PORT_MRW, 0, "TA Tile matrix end" )
2.85 @@ -73,7 +82,12 @@
2.86 LONG_PORT( 0x13C, TA_TILESIZE, PORT_MRW, 0, "TA Tile matrix size" )
2.87 LONG_PORT( 0x140, TA_TILECFG, PORT_MRW, 0, "TA Tile matrix config" )
2.88 LONG_PORT( 0x144, TA_INIT, PORT_W, 0, "TA Initialize" )
2.89 + LONG_PORT( 0x148, YUV_ADDR, PORT_MRW, 0, "YUV conversion address" )
2.90 + LONG_PORT( 0x14C, YUV_CFG, PORT_MRW, 0, "YUV configuration" )
2.91 + LONG_PORT( 0x150, YUV_COUNT, PORT_MR, 0, "YUV conversion count" )
2.92 + LONG_PORT( 0x160, TA_REINIT, PORT_W, 0, "TA re-initialize" )
2.93 LONG_PORT( 0x164, TA_LISTBASE, PORT_MRW, 0, "TA Tile list start" )
2.94 + LONG_PORT( 0x1A8, PVRUNK7, PORT_MRW, 0, "PVR2 unknown register 7" )
2.95 MMIO_REGION_END
2.96
2.97 MMIO_REGION_BEGIN( 0x005F9000, PVR2PAL, "Power VR/2 CLUT Palettes" )
.