revision 401:f79327f39818
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raw | bz2 | zip | gz changeset | 401:f79327f39818 |
parent | 400:049d72a7a229 |
child | 402:85fd4a4582be |
author | nkeynes |
date | Thu Sep 20 08:37:19 2007 +0000 (16 years ago) |
Move support routines to sh4.c
src/sh4/sh4.c | view | annotate | diff | log | ||
src/sh4/sh4core.c | view | annotate | diff | log | ||
src/sh4/sh4core.h | view | annotate | diff | log | ||
src/sh4/sh4core.in | view | annotate | diff | log | ||
src/sh4/sh4x86.c | view | annotate | diff | log | ||
src/sh4/sh4x86.in | view | annotate | diff | log |
1.1 --- a/src/sh4/sh4.c Thu Sep 20 08:35:04 2007 +00001.2 +++ b/src/sh4/sh4.c Thu Sep 20 08:37:19 2007 +00001.3 @@ -1,5 +1,5 @@1.4 /**1.5 - * $Id: sh4.c,v 1.1 2007-09-12 09:20:38 nkeynes Exp $1.6 + * $Id: sh4.c,v 1.2 2007-09-20 08:37:19 nkeynes Exp $1.7 *1.8 * SH4 parent module for all CPU modes and SH4 peripheral1.9 * modules.1.10 @@ -27,6 +27,10 @@1.11 #include "clock.h"1.12 #include "syscall.h"1.14 +#define EXV_EXCEPTION 0x100 /* General exception vector */1.15 +#define EXV_TLBMISS 0x400 /* TLB-miss exception vector */1.16 +#define EXV_INTERRUPT 0x600 /* External interrupt vector */1.17 +1.18 void sh4_init( void );1.19 void sh4_reset( void );1.20 void sh4_start( void );1.21 @@ -87,6 +91,7 @@1.22 MMU_reset();1.23 TMU_reset();1.24 SCIF_reset();1.25 + sh4_stats_reset();1.26 }1.28 void sh4_stop(void)1.29 @@ -96,6 +101,12 @@1.31 void sh4_save_state( FILE *f )1.32 {1.33 + if( sh4_module.run_time_slice == sh4_xlat_run_slice ) {1.34 + /* If we were running with the translator, update new_pc and in_delay_slot */1.35 + sh4r.new_pc = sh4r.pc+2;1.36 + sh4r.in_delay_slot = FALSE;1.37 + }1.38 +1.39 fwrite( &sh4r, sizeof(sh4r), 1, f );1.40 MMU_save_state( f );1.41 INTC_save_state( f );1.42 @@ -148,3 +159,147 @@1.43 return 0;1.44 }1.46 +void sh4_set_pc( int pc )1.47 +{1.48 + sh4r.pc = pc;1.49 + sh4r.new_pc = pc+2;1.50 +}1.51 +1.52 +1.53 +/******************************* Support methods ***************************/1.54 +1.55 +static void sh4_switch_banks( )1.56 +{1.57 + uint32_t tmp[8];1.58 +1.59 + memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );1.60 + memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );1.61 + memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );1.62 +}1.63 +1.64 +void sh4_write_sr( uint32_t newval )1.65 +{1.66 + if( (newval ^ sh4r.sr) & SR_RB )1.67 + sh4_switch_banks();1.68 + sh4r.sr = newval;1.69 + sh4r.t = (newval&SR_T) ? 1 : 0;1.70 + sh4r.s = (newval&SR_S) ? 1 : 0;1.71 + sh4r.m = (newval&SR_M) ? 1 : 0;1.72 + sh4r.q = (newval&SR_Q) ? 1 : 0;1.73 + intc_mask_changed();1.74 +}1.75 +1.76 +uint32_t sh4_read_sr( void )1.77 +{1.78 + /* synchronize sh4r.sr with the various bitflags */1.79 + sh4r.sr &= SR_MQSTMASK;1.80 + if( sh4r.t ) sh4r.sr |= SR_T;1.81 + if( sh4r.s ) sh4r.sr |= SR_S;1.82 + if( sh4r.m ) sh4r.sr |= SR_M;1.83 + if( sh4r.q ) sh4r.sr |= SR_Q;1.84 + return sh4r.sr;1.85 +}1.86 +1.87 +1.88 +1.89 +#define RAISE( x, v ) do{ \1.90 + if( sh4r.vbr == 0 ) { \1.91 + ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \1.92 + dreamcast_stop(); return FALSE; \1.93 + } else { \1.94 + sh4r.spc = sh4r.pc; \1.95 + sh4r.ssr = sh4_read_sr(); \1.96 + sh4r.sgr = sh4r.r[15]; \1.97 + MMIO_WRITE(MMU,EXPEVT,x); \1.98 + sh4r.pc = sh4r.vbr + v; \1.99 + sh4r.new_pc = sh4r.pc + 2; \1.100 + sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \1.101 + if( sh4r.in_delay_slot ) { \1.102 + sh4r.in_delay_slot = 0; \1.103 + sh4r.spc -= 2; \1.104 + } \1.105 + } \1.106 + return TRUE; } while(0)1.107 +1.108 +/**1.109 + * Raise a general CPU exception for the specified exception code.1.110 + * (NOT for TRAPA or TLB exceptions)1.111 + */1.112 +gboolean sh4_raise_exception( int code )1.113 +{1.114 + RAISE( code, EXV_EXCEPTION );1.115 +}1.116 +1.117 +gboolean sh4_raise_trap( int trap )1.118 +{1.119 + MMIO_WRITE( MMU, TRA, trap<<2 );1.120 + return sh4_raise_exception( EXC_TRAP );1.121 +}1.122 +1.123 +gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {1.124 + if( sh4r.in_delay_slot ) {1.125 + return sh4_raise_exception(slot_code);1.126 + } else {1.127 + return sh4_raise_exception(normal_code);1.128 + }1.129 +}1.130 +1.131 +gboolean sh4_raise_tlb_exception( int code )1.132 +{1.133 + RAISE( code, EXV_TLBMISS );1.134 +}1.135 +1.136 +void sh4_accept_interrupt( void )1.137 +{1.138 + uint32_t code = intc_accept_interrupt();1.139 + sh4r.ssr = sh4_read_sr();1.140 + sh4r.spc = sh4r.pc;1.141 + sh4r.sgr = sh4r.r[15];1.142 + sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );1.143 + MMIO_WRITE( MMU, INTEVT, code );1.144 + sh4r.pc = sh4r.vbr + 0x600;1.145 + sh4r.new_pc = sh4r.pc + 2;1.146 + // WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );1.147 +}1.148 +1.149 +void signsat48( void )1.150 +{1.151 + if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )1.152 + sh4r.mac = 0xFFFF800000000000LL;1.153 + else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL )1.154 + sh4r.mac = 0x00007FFFFFFFFFFFLL;1.155 +}1.156 +1.157 +void sh4_fsca( uint32_t anglei, float *fr )1.158 +{1.159 + float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI;1.160 + *fr++ = cosf(angle);1.161 + *fr = sinf(angle);1.162 +}1.163 +1.164 +void sh4_sleep(void)1.165 +{1.166 + if( MMIO_READ( CPG, STBCR ) & 0x80 ) {1.167 + sh4r.sh4_state = SH4_STATE_STANDBY;1.168 + } else {1.169 + sh4r.sh4_state = SH4_STATE_SLEEP;1.170 + }1.171 +}1.172 +1.173 +/**1.174 + * Compute the matrix tranform of fv given the matrix xf.1.175 + * Both fv and xf are word-swapped as per the sh4r.fr banks1.176 + */1.177 +void sh4_ftrv( float *target, float *xf )1.178 +{1.179 + float fv[4] = { target[1], target[0], target[3], target[2] };1.180 + target[1] = xf[1] * fv[0] + xf[5]*fv[1] +1.181 + xf[9]*fv[2] + xf[13]*fv[3];1.182 + target[0] = xf[0] * fv[0] + xf[4]*fv[1] +1.183 + xf[8]*fv[2] + xf[12]*fv[3];1.184 + target[3] = xf[3] * fv[0] + xf[7]*fv[1] +1.185 + xf[11]*fv[2] + xf[15]*fv[3];1.186 + target[2] = xf[2] * fv[0] + xf[6]*fv[1] +1.187 + xf[10]*fv[2] + xf[14]*fv[3];1.188 +}1.189 +
2.1 --- a/src/sh4/sh4core.c Thu Sep 20 08:35:04 2007 +00002.2 +++ b/src/sh4/sh4core.c Thu Sep 20 08:37:19 2007 +00002.3 @@ -1,5 +1,5 @@2.4 /**2.5 - * $Id: sh4core.c,v 1.47 2007-09-18 09:14:20 nkeynes Exp $2.6 + * $Id: sh4core.c,v 1.48 2007-09-20 08:37:19 nkeynes Exp $2.7 *2.8 * SH4 emulation core, and parent module for all the SH4 peripheral2.9 * modules.2.10 @@ -34,14 +34,8 @@2.11 #define MAX_INTF 2147483647.02.12 #define MIN_INTF -2147483648.02.14 -#define EXV_EXCEPTION 0x100 /* General exception vector */2.15 -#define EXV_TLBMISS 0x400 /* TLB-miss exception vector */2.16 -#define EXV_INTERRUPT 0x600 /* External interrupt vector */2.17 -2.18 /********************** SH4 Module Definition ****************************/2.20 -uint32_t sh4_run_slice( uint32_t );2.21 -2.22 uint16_t *sh4_icache = NULL;2.23 uint32_t sh4_icache_addr = 0;2.25 @@ -68,7 +62,6 @@2.26 sh4_accept_interrupt();2.27 }2.28 }2.29 - // sh4_stats_add( sh4r.pc );2.30 if( !sh4_execute_instruction() ) {2.31 break;2.32 }2.33 @@ -119,12 +112,6 @@2.35 /********************** SH4 emulation core ****************************/2.37 -void sh4_set_pc( int pc )2.38 -{2.39 - sh4r.pc = pc;2.40 - sh4r.new_pc = pc+2;2.41 -}2.42 -2.43 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)2.44 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)2.46 @@ -175,25 +162,6 @@2.47 #define TRACE_RETURN( source, dest )2.48 #endif2.50 -#define RAISE( x, v ) do{ \2.51 - if( sh4r.vbr == 0 ) { \2.52 - ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \2.53 - dreamcast_stop(); return FALSE; \2.54 - } else { \2.55 - sh4r.spc = sh4r.pc; \2.56 - sh4r.ssr = sh4_read_sr(); \2.57 - sh4r.sgr = sh4r.r[15]; \2.58 - MMIO_WRITE(MMU,EXPEVT,x); \2.59 - sh4r.pc = sh4r.vbr + v; \2.60 - sh4r.new_pc = sh4r.pc + 2; \2.61 - sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \2.62 - if( sh4r.in_delay_slot ) { \2.63 - sh4r.in_delay_slot = 0; \2.64 - sh4r.spc -= 2; \2.65 - } \2.66 - } \2.67 - return TRUE; } while(0)2.68 -2.69 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)2.70 #define MEM_READ_WORD( addr ) sh4_read_word(addr)2.71 #define MEM_READ_LONG( addr ) sh4_read_long(addr)2.72 @@ -216,27 +184,6 @@2.73 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }2.74 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)2.76 -static void sh4_switch_banks( )2.77 -{2.78 - uint32_t tmp[8];2.79 -2.80 - memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );2.81 - memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );2.82 - memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );2.83 -}2.84 -2.85 -void sh4_write_sr( uint32_t newval )2.86 -{2.87 - if( (newval ^ sh4r.sr) & SR_RB )2.88 - sh4_switch_banks();2.89 - sh4r.sr = newval;2.90 - sh4r.t = (newval&SR_T) ? 1 : 0;2.91 - sh4r.s = (newval&SR_S) ? 1 : 0;2.92 - sh4r.m = (newval&SR_M) ? 1 : 0;2.93 - sh4r.q = (newval&SR_Q) ? 1 : 0;2.94 - intc_mask_changed();2.95 -}2.96 -2.97 static void sh4_write_float( uint32_t addr, int reg )2.98 {2.99 if( IS_FPU_DOUBLESIZE() ) {2.100 @@ -267,58 +214,6 @@2.101 }2.102 }2.104 -uint32_t sh4_read_sr( void )2.105 -{2.106 - /* synchronize sh4r.sr with the various bitflags */2.107 - sh4r.sr &= SR_MQSTMASK;2.108 - if( sh4r.t ) sh4r.sr |= SR_T;2.109 - if( sh4r.s ) sh4r.sr |= SR_S;2.110 - if( sh4r.m ) sh4r.sr |= SR_M;2.111 - if( sh4r.q ) sh4r.sr |= SR_Q;2.112 - return sh4r.sr;2.113 -}2.114 -2.115 -/**2.116 - * Raise a general CPU exception for the specified exception code.2.117 - * (NOT for TRAPA or TLB exceptions)2.118 - */2.119 -gboolean sh4_raise_exception( int code )2.120 -{2.121 - RAISE( code, EXV_EXCEPTION );2.122 -}2.123 -2.124 -gboolean sh4_raise_trap( int trap )2.125 -{2.126 - MMIO_WRITE( MMU, TRA, trap<<2 );2.127 - return sh4_raise_exception( EXC_TRAP );2.128 -}2.129 -2.130 -gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {2.131 - if( sh4r.in_delay_slot ) {2.132 - return sh4_raise_exception(slot_code);2.133 - } else {2.134 - return sh4_raise_exception(normal_code);2.135 - }2.136 -}2.137 -2.138 -gboolean sh4_raise_tlb_exception( int code )2.139 -{2.140 - RAISE( code, EXV_TLBMISS );2.141 -}2.142 -2.143 -void sh4_accept_interrupt( void )2.144 -{2.145 - uint32_t code = intc_accept_interrupt();2.146 - sh4r.ssr = sh4_read_sr();2.147 - sh4r.spc = sh4r.pc;2.148 - sh4r.sgr = sh4r.r[15];2.149 - sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );2.150 - MMIO_WRITE( MMU, INTEVT, code );2.151 - sh4r.pc = sh4r.vbr + 0x600;2.152 - sh4r.new_pc = sh4r.pc + 2;2.153 - // WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );2.154 -}2.155 -2.156 gboolean sh4_execute_instruction( void )2.157 {2.158 uint32_t pc;
3.1 --- a/src/sh4/sh4core.h Thu Sep 20 08:35:04 2007 +00003.2 +++ b/src/sh4/sh4core.h Thu Sep 20 08:37:19 2007 +00003.3 @@ -1,5 +1,5 @@3.4 /**3.5 - * $Id: sh4core.h,v 1.24 2007-09-18 09:14:20 nkeynes Exp $3.6 + * $Id: sh4core.h,v 1.25 2007-09-20 08:37:19 nkeynes Exp $3.7 *3.8 * This file defines the internal functions exported/used by the SH4 core,3.9 * except for disassembly functions defined in sh4dasm.h3.10 @@ -95,6 +95,10 @@3.11 int sh4_isrunning( void );3.12 void sh4_stop( void );3.13 void sh4_set_pc( int );3.14 +void sh4_sleep( void );3.15 +void sh4_fsca( uint32_t angle, float *fr );3.16 +void sh4_ftrv( float *fv, float *xmtrx );3.17 +void signsat48(void);3.19 gboolean sh4_execute_instruction( void );3.20 gboolean sh4_raise_exception( int );
4.1 --- a/src/sh4/sh4core.in Thu Sep 20 08:35:04 2007 +00004.2 +++ b/src/sh4/sh4core.in Thu Sep 20 08:37:19 2007 +00004.3 @@ -1,5 +1,5 @@4.4 /**4.5 - * $Id: sh4core.in,v 1.7 2007-09-18 09:14:20 nkeynes Exp $4.6 + * $Id: sh4core.in,v 1.8 2007-09-20 08:37:19 nkeynes Exp $4.7 *4.8 * SH4 emulation core, and parent module for all the SH4 peripheral4.9 * modules.4.10 @@ -34,14 +34,8 @@4.11 #define MAX_INTF 2147483647.04.12 #define MIN_INTF -2147483648.04.14 -#define EXV_EXCEPTION 0x100 /* General exception vector */4.15 -#define EXV_TLBMISS 0x400 /* TLB-miss exception vector */4.16 -#define EXV_INTERRUPT 0x600 /* External interrupt vector */4.17 -4.18 /********************** SH4 Module Definition ****************************/4.20 -uint32_t sh4_run_slice( uint32_t );4.21 -4.22 uint16_t *sh4_icache = NULL;4.23 uint32_t sh4_icache_addr = 0;4.25 @@ -68,7 +62,6 @@4.26 sh4_accept_interrupt();4.27 }4.28 }4.29 - // sh4_stats_add( sh4r.pc );4.30 if( !sh4_execute_instruction() ) {4.31 break;4.32 }4.33 @@ -119,12 +112,6 @@4.35 /********************** SH4 emulation core ****************************/4.37 -void sh4_set_pc( int pc )4.38 -{4.39 - sh4r.pc = pc;4.40 - sh4r.new_pc = pc+2;4.41 -}4.42 -4.43 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)4.44 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)4.46 @@ -175,25 +162,6 @@4.47 #define TRACE_RETURN( source, dest )4.48 #endif4.50 -#define RAISE( x, v ) do{ \4.51 - if( sh4r.vbr == 0 ) { \4.52 - ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \4.53 - dreamcast_stop(); return FALSE; \4.54 - } else { \4.55 - sh4r.spc = sh4r.pc; \4.56 - sh4r.ssr = sh4_read_sr(); \4.57 - sh4r.sgr = sh4r.r[15]; \4.58 - MMIO_WRITE(MMU,EXPEVT,x); \4.59 - sh4r.pc = sh4r.vbr + v; \4.60 - sh4r.new_pc = sh4r.pc + 2; \4.61 - sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \4.62 - if( sh4r.in_delay_slot ) { \4.63 - sh4r.in_delay_slot = 0; \4.64 - sh4r.spc -= 2; \4.65 - } \4.66 - } \4.67 - return TRUE; } while(0)4.68 -4.69 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)4.70 #define MEM_READ_WORD( addr ) sh4_read_word(addr)4.71 #define MEM_READ_LONG( addr ) sh4_read_long(addr)4.72 @@ -216,27 +184,6 @@4.73 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }4.74 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)4.76 -static void sh4_switch_banks( )4.77 -{4.78 - uint32_t tmp[8];4.79 -4.80 - memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );4.81 - memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );4.82 - memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );4.83 -}4.84 -4.85 -void sh4_write_sr( uint32_t newval )4.86 -{4.87 - if( (newval ^ sh4r.sr) & SR_RB )4.88 - sh4_switch_banks();4.89 - sh4r.sr = newval;4.90 - sh4r.t = (newval&SR_T) ? 1 : 0;4.91 - sh4r.s = (newval&SR_S) ? 1 : 0;4.92 - sh4r.m = (newval&SR_M) ? 1 : 0;4.93 - sh4r.q = (newval&SR_Q) ? 1 : 0;4.94 - intc_mask_changed();4.95 -}4.96 -4.97 static void sh4_write_float( uint32_t addr, int reg )4.98 {4.99 if( IS_FPU_DOUBLESIZE() ) {4.100 @@ -267,58 +214,6 @@4.101 }4.102 }4.104 -uint32_t sh4_read_sr( void )4.105 -{4.106 - /* synchronize sh4r.sr with the various bitflags */4.107 - sh4r.sr &= SR_MQSTMASK;4.108 - if( sh4r.t ) sh4r.sr |= SR_T;4.109 - if( sh4r.s ) sh4r.sr |= SR_S;4.110 - if( sh4r.m ) sh4r.sr |= SR_M;4.111 - if( sh4r.q ) sh4r.sr |= SR_Q;4.112 - return sh4r.sr;4.113 -}4.114 -4.115 -/**4.116 - * Raise a general CPU exception for the specified exception code.4.117 - * (NOT for TRAPA or TLB exceptions)4.118 - */4.119 -gboolean sh4_raise_exception( int code )4.120 -{4.121 - RAISE( code, EXV_EXCEPTION );4.122 -}4.123 -4.124 -gboolean sh4_raise_trap( int trap )4.125 -{4.126 - MMIO_WRITE( MMU, TRA, trap<<2 );4.127 - return sh4_raise_exception( EXC_TRAP );4.128 -}4.129 -4.130 -gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {4.131 - if( sh4r.in_delay_slot ) {4.132 - return sh4_raise_exception(slot_code);4.133 - } else {4.134 - return sh4_raise_exception(normal_code);4.135 - }4.136 -}4.137 -4.138 -gboolean sh4_raise_tlb_exception( int code )4.139 -{4.140 - RAISE( code, EXV_TLBMISS );4.141 -}4.142 -4.143 -void sh4_accept_interrupt( void )4.144 -{4.145 - uint32_t code = intc_accept_interrupt();4.146 - sh4r.ssr = sh4_read_sr();4.147 - sh4r.spc = sh4r.pc;4.148 - sh4r.sgr = sh4r.r[15];4.149 - sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );4.150 - MMIO_WRITE( MMU, INTEVT, code );4.151 - sh4r.pc = sh4r.vbr + 0x600;4.152 - sh4r.new_pc = sh4r.pc + 2;4.153 - // WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );4.154 -}4.155 -4.156 gboolean sh4_execute_instruction( void )4.157 {4.158 uint32_t pc;
5.1 --- a/src/sh4/sh4x86.c Thu Sep 20 08:35:04 2007 +00005.2 +++ b/src/sh4/sh4x86.c Thu Sep 20 08:37:19 2007 +00005.3 @@ -1,5 +1,5 @@5.4 /**5.5 - * $Id: sh4x86.c,v 1.13 2007-09-19 11:30:30 nkeynes Exp $5.6 + * $Id: sh4x86.c,v 1.14 2007-09-20 08:37:19 nkeynes Exp $5.7 *5.8 * SH4 => x86 translation. This version does no real optimization, it just5.9 * outputs straight-line x86 code - it mainly exists to provide a baseline5.10 @@ -63,48 +63,6 @@5.11 static uint32_t min_int = 0x80000000;5.12 static uint32_t save_fcw; /* save value for fpu control word */5.13 static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */5.14 -void signsat48( void )5.15 -{5.16 - if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )5.17 - sh4r.mac = 0xFFFF800000000000LL;5.18 - else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL )5.19 - sh4r.mac = 0x00007FFFFFFFFFFFLL;5.20 -}5.21 -5.22 -void sh4_fsca( uint32_t anglei, float *fr )5.23 -{5.24 - float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI;5.25 - *fr++ = cosf(angle);5.26 - *fr = sinf(angle);5.27 -}5.28 -5.29 -void sh4_sleep()5.30 -{5.31 - if( MMIO_READ( CPG, STBCR ) & 0x80 ) {5.32 - sh4r.sh4_state = SH4_STATE_STANDBY;5.33 - } else {5.34 - sh4r.sh4_state = SH4_STATE_SLEEP;5.35 - }5.36 -}5.37 -5.38 -/**5.39 - * Compute the matrix tranform of fv given the matrix xf.5.40 - * Both fv and xf are word-swapped as per the sh4r.fr banks5.41 - */5.42 -void sh4_ftrv( float *target, float *xf )5.43 -{5.44 - float fv[4] = { target[1], target[0], target[3], target[2] };5.45 - target[1] = xf[1] * fv[0] + xf[5]*fv[1] +5.46 - xf[9]*fv[2] + xf[13]*fv[3];5.47 - target[0] = xf[0] * fv[0] + xf[4]*fv[1] +5.48 - xf[8]*fv[2] + xf[12]*fv[3];5.49 - target[3] = xf[3] * fv[0] + xf[7]*fv[1] +5.50 - xf[11]*fv[2] + xf[15]*fv[3];5.51 - target[2] = xf[2] * fv[0] + xf[6]*fv[1] +5.52 - xf[10]*fv[2] + xf[14]*fv[3];5.53 -}5.54 -5.55 -5.57 void sh4_x86_init()5.58 {
6.1 --- a/src/sh4/sh4x86.in Thu Sep 20 08:35:04 2007 +00006.2 +++ b/src/sh4/sh4x86.in Thu Sep 20 08:37:19 2007 +00006.3 @@ -1,5 +1,5 @@6.4 /**6.5 - * $Id: sh4x86.in,v 1.14 2007-09-19 11:30:30 nkeynes Exp $6.6 + * $Id: sh4x86.in,v 1.15 2007-09-20 08:37:19 nkeynes Exp $6.7 *6.8 * SH4 => x86 translation. This version does no real optimization, it just6.9 * outputs straight-line x86 code - it mainly exists to provide a baseline6.10 @@ -63,48 +63,6 @@6.11 static uint32_t min_int = 0x80000000;6.12 static uint32_t save_fcw; /* save value for fpu control word */6.13 static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */6.14 -void signsat48( void )6.15 -{6.16 - if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )6.17 - sh4r.mac = 0xFFFF800000000000LL;6.18 - else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL )6.19 - sh4r.mac = 0x00007FFFFFFFFFFFLL;6.20 -}6.21 -6.22 -void sh4_fsca( uint32_t anglei, float *fr )6.23 -{6.24 - float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI;6.25 - *fr++ = cosf(angle);6.26 - *fr = sinf(angle);6.27 -}6.28 -6.29 -void sh4_sleep()6.30 -{6.31 - if( MMIO_READ( CPG, STBCR ) & 0x80 ) {6.32 - sh4r.sh4_state = SH4_STATE_STANDBY;6.33 - } else {6.34 - sh4r.sh4_state = SH4_STATE_SLEEP;6.35 - }6.36 -}6.37 -6.38 -/**6.39 - * Compute the matrix tranform of fv given the matrix xf.6.40 - * Both fv and xf are word-swapped as per the sh4r.fr banks6.41 - */6.42 -void sh4_ftrv( float *target, float *xf )6.43 -{6.44 - float fv[4] = { target[1], target[0], target[3], target[2] };6.45 - target[1] = xf[1] * fv[0] + xf[5]*fv[1] +6.46 - xf[9]*fv[2] + xf[13]*fv[3];6.47 - target[0] = xf[0] * fv[0] + xf[4]*fv[1] +6.48 - xf[8]*fv[2] + xf[12]*fv[3];6.49 - target[3] = xf[3] * fv[0] + xf[7]*fv[1] +6.50 - xf[11]*fv[2] + xf[15]*fv[3];6.51 - target[2] = xf[2] * fv[0] + xf[6]*fv[1] +6.52 - xf[10]*fv[2] + xf[14]*fv[3];6.53 -}6.54 -6.55 -6.57 void sh4_x86_init()6.58 {
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