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lxdream.org :: lxdream :: r233:f8333b94f503
lxdream 0.9.1
released Jun 29
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changeset233:f8333b94f503
parent232:9c8ef78376ed
child234:8759d0067e9d
authornkeynes
dateWed Sep 27 10:21:34 2006 +0000 (14 years ago)
Add user mode/system mode switch
Add undefined instruction tests
test/Makefile
test/interrupt.s
test/sh4/excslot.s
test/sh4/inc.s
test/sh4/testsh4.c
test/sh4/undef.s
1.1 --- a/test/Makefile Tue Sep 26 11:09:13 2006 +0000
1.2 +++ b/test/Makefile Wed Sep 27 10:21:34 2006 +0000
1.3 @@ -74,7 +74,7 @@
1.4 testsh4: crt0.so sh4/testsh4.so timer.so interrupt.so \
1.5 sh4/add.so sh4/addc.so sh4/addv.so sh4/and.so sh4/andi.so \
1.6 sh4/bf.so sh4/bt.so sh4/cmp.so \
1.7 - sh4/excslot.so
1.8 + sh4/excslot.so sh4/undef.so
1.9 $(SH4CC) $(SH4LDFLAGS) $^ -o $@ $(SH4LIBS)
1.10 $(SH4OBJCOPY) testsh4 testsh4.bin
1.11
2.1 --- a/test/interrupt.s Tue Sep 26 11:09:13 2006 +0000
2.2 +++ b/test/interrupt.s Wed Sep 27 10:21:34 2006 +0000
2.3 @@ -177,6 +177,26 @@
2.4 nop
2.5
2.6 ex_dontcare: ! Not the event we were waiting for.
2.7 +! Check if its a trapa #42 ("Switch to system mode")
2.8 + mov.l trapa_exc_k, r0
2.9 + cmp/eq r0,r1
2.10 + bf ex_chain
2.11 + mov.l trapa_k, r0
2.12 + mov.l @r0, r0
2.13 + shlr2 r0
2.14 + cmp/eq #42, r0
2.15 + bf ex_chain
2.16 +! Yes, yes it is - update SSR and return without chaining
2.17 + stc ssr, r0
2.18 + mov #0x40, r1
2.19 + mov #24, r2
2.20 + shld r2, r1
2.21 + or r0, r1
2.22 + ldc r1, ssr
2.23 + bra ex_nochain
2.24 + nop
2.25 +
2.26 +ex_chain:
2.27 mov.l old_vbr_k, r2
2.28 mov.l @r2, r2
2.29 xor r0, r0
2.30 @@ -213,9 +233,9 @@
2.31 mov.l @r15+, r2
2.32 mov.l @r15+, r1
2.33 mov.l @r15+, r0
2.34 + stc sgr, r15
2.35 rte
2.36 - stc sgr, r15
2.37 -
2.38 + nop
2.39 .align 4
2.40 expected_intevt_k:
2.41 .long expected_intevt
3.1 --- a/test/sh4/excslot.s Tue Sep 26 11:09:13 2006 +0000
3.2 +++ b/test/sh4/excslot.s Wed Sep 27 10:21:34 2006 +0000
3.3 @@ -31,10 +31,6 @@
3.4 bsr test_slot_fail
3.5 jsr @r3
3.6 assert_exc_caught test_slot_str_k1 test_slot_2_pc
3.7 - bra test_slot_3
3.8 - nop
3.9 -test_slot_str_k1:
3.10 - .long test_slot_str
3.11
3.12 test_slot_3: ! BRA
3.13 add #1, r12
3.14 @@ -42,7 +38,7 @@
3.15 test_slot_3_pc:
3.16 bsr test_slot_fail
3.17 bra test_slot_fail
3.18 - assert_exc_caught test_slot_str_k test_slot_3_pc
3.19 + assert_exc_caught test_slot_str_k1 test_slot_3_pc
3.20
3.21 test_slot_4: ! BRAF
3.22 add #1, r12
3.23 @@ -103,7 +99,12 @@
3.24 bt/s test_slot_10_fail
3.25 test_slot_10_fail:
3.26 assert_exc_caught test_slot_str_k test_slot_10_pc
3.27 + bra test_slot_11
3.28 + nop
3.29 +test_slot_str_k1:
3.30 + .long test_slot_str
3.31
3.32 +
3.33 test_slot_11: ! TRAPA
3.34 add #1, r12
3.35 expect_exc 0x000001A0
3.36 @@ -171,8 +172,19 @@
3.37 !
3.38 ! Ok now the privilege tests. These should raise SLOT_ILLEGAL when executed
3.39 ! in a delay slot (otherwise it's GENERAL_ILLEGAL)
3.40 -! TODO: need mode-switch code
3.41 +
3.42 +test_slot_18: ! LDC Rn, SPC in user mode
3.43 + add #1, r12
3.44 + expect_exc 0x000001A0
3.45 + stc spc, r4
3.46 + usermode
3.47 +test_slot_18_pc:
3.48 + bsr test_slot_fail
3.49 + ldc r4, spc
3.50 + systemmode
3.51 + assert_exc_caught test_slot_str_k test_slot_18_pc
3.52
3.53 +
3.54 test_slot_end:
3.55 end_test test_slot_str_k
3.56
4.1 --- a/test/sh4/inc.s Tue Sep 26 11:09:13 2006 +0000
4.2 +++ b/test/sh4/inc.s Wed Sep 27 10:21:34 2006 +0000
4.3 @@ -140,6 +140,25 @@
4.4 addc r0, r0
4.5 .endm
4.6
4.7 +! Switch to user-mode
4.8 +.macro usermode
4.9 + stc sr, r0
4.10 + mov #64, r1
4.11 + mov #24, r2
4.12 + shld r2, r1
4.13 + not r1, r1
4.14 + and r0, r1
4.15 + ldc r1, sr
4.16 +.endm
4.17 +
4.18 +! Switch to system-mode
4.19 +! NB: implemented as a trap to the interrupt handler, as obviously
4.20 +! we can't just update SR...
4.21 +.macro systemmode
4.22 + trapa #42
4.23 + nop
4.24 +.endm
4.25 +
4.26 .macro clearbl
4.27 LOCAL L1
4.28 LOCAL L2
5.1 --- a/test/sh4/testsh4.c Tue Sep 26 11:09:13 2006 +0000
5.2 +++ b/test/sh4/testsh4.c Wed Sep 27 10:21:34 2006 +0000
5.3 @@ -60,6 +60,7 @@
5.4
5.5 fprintf( stdout, "Exception tests...\n" );
5.6 test_slot_illegal();
5.7 + test_undefined();
5.8 remove_interrupt_handler();
5.9
5.10 fprintf( stdout, "Total: %d/%d tests passed (%d%%)\n", total_tests-total_fails,
6.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
6.2 +++ b/test/sh4/undef.s Wed Sep 27 10:21:34 2006 +0000
6.3 @@ -0,0 +1,57 @@
6.4 +.section .text
6.5 +.include "sh4/inc.s"
6.6 +!
6.7 +! Test for undefined/unknown instructions. The only "official"
6.8 +! undefined instruction is 0xFFFD, but this tests everything
6.9 +! that doesn't match a known instruction pattern. Undefined
6.10 +! instructions are expected to raise general-illegal when not
6.11 +! in a delay slot, and slot-illegal when in a delay slot.
6.12 +
6.13 +.global _test_undefined
6.14 +_test_undefined:
6.15 + start_test
6.16 +
6.17 +test_undef_1: ! First the official one
6.18 + add #1, r12
6.19 + expect_exc 0x00000180
6.20 +test_undef_1_pc:
6.21 + .word 0xFFFD
6.22 + assert_exc_caught test_undef_str_k test_undef_1_pc
6.23 +
6.24 +! Gaps in the STC range (0x0nn2)
6.25 +test_undef_2: ! 0x52
6.26 + add #1, r12
6.27 + expect_exc 0x00000180
6.28 +test_undef_2_pc:
6.29 + .word 0x0052
6.30 + assert_exc_caught test_undef_str_k test_undef_2_pc
6.31 +
6.32 +test_undef_3: ! 0x62
6.33 + add #1, r12
6.34 + expect_exc 0x00000180
6.35 +test_undef_3_pc:
6.36 + .word 0x0062
6.37 + assert_exc_caught test_undef_str_k test_undef_3_pc
6.38 +
6.39 +test_undef_4: ! 0x72
6.40 + add #1, r12
6.41 + expect_exc 0x00000180
6.42 +test_undef_4_pc:
6.43 + .word 0x0072
6.44 + assert_exc_caught test_undef_str_k test_undef_4_pc
6.45 +
6.46 +! Test undefined FP instructions w/ and w/o FP disable
6.47 +test_undef_fpu_1:
6.48 + add #1, r12
6.49 + expect_exc 0x00000180
6.50 +test_undef_fpu_1_pc:
6.51 + .word 0xF0CD
6.52 + assert_exc_caught test_undef_str_k test_undef_fpu_1_pc
6.53 +
6.54 +test_undef_end:
6.55 + end_test test_undef_str_k
6.56 +
6.57 +test_undef_str_k:
6.58 + .long test_undef_str
6.59 +test_undef_str:
6.60 + .string "UNDEFINED-INSTRUCTION"
.