revision 414:fd8e96bc513e
summary |
tree |
shortlog |
changelog |
graph |
changeset |
raw | bz2 | zip | gz changeset | 414:fd8e96bc513e |
parent | 413:bff683bc5228 |
child | 415:5e57f29bfd4d |
author | nkeynes |
date | Wed Oct 03 08:22:27 2007 +0000 (15 years ago) |
Add (probably temporary) CPU frequency scaling command-line option
![]() | src/main.c | view | annotate | diff | log | |
![]() | src/sh4/timer.c | view | annotate | diff | log |
1.1 --- a/src/main.c Tue Oct 02 08:48:27 2007 +00001.2 +++ b/src/main.c Wed Oct 03 08:22:27 2007 +00001.3 @@ -1,5 +1,5 @@1.4 /**1.5 - * $Id: main.c,v 1.25 2007-09-20 08:42:40 nkeynes Exp $1.6 + * $Id: main.c,v 1.26 2007-10-03 08:22:27 nkeynes Exp $1.7 *1.8 * Main program, initializes dreamcast and gui, then passes control off to1.9 * the gtk main loop (currently).1.10 @@ -35,7 +35,7 @@1.12 #define S3M_PLAYER "s3mplay.bin"1.14 -char *option_list = "a:s:A:V:puhbd:c:t:xD";1.15 +char *option_list = "a:m:s:A:V:puhbd:c:t:xD";1.16 struct option longopts[1] = { { NULL, 0, 0, 0 } };1.17 char *aica_program = NULL;1.18 char *s3m_file = NULL;1.19 @@ -50,6 +50,7 @@1.20 gboolean show_debugger = FALSE;1.21 uint32_t time_secs = 0;1.22 uint32_t time_nanos = 0;1.23 +extern uint32_t sh4_cpu_multiplier;1.25 audio_driver_t audio_driver_list[] = { &audio_null_driver,1.26 &audio_esd_driver,1.27 @@ -82,6 +83,10 @@1.28 case 'D': /* Launch w/ debugger */1.29 show_debugger = TRUE;1.30 break;1.31 + case 'm': /* Set SH4 CPU clock multiplier (default 0.5) */1.32 + t = strtod(optarg, NULL);1.33 + sh4_cpu_multiplier = (int)(1000.0/t);1.34 + break;1.35 case 's': /* AICA-only w/ S3M player */1.36 aica_program = S3M_PLAYER;1.37 s3m_file = optarg;
2.1 --- a/src/sh4/timer.c Tue Oct 02 08:48:27 2007 +00002.2 +++ b/src/sh4/timer.c Wed Oct 03 08:22:27 2007 +00002.3 @@ -1,5 +1,5 @@2.4 /**2.5 - * $Id: timer.c,v 1.7 2007-01-25 10:18:42 nkeynes Exp $2.6 + * $Id: timer.c,v 1.8 2007-10-03 08:22:27 nkeynes Exp $2.7 *2.8 * SH4 Timer/Clock peripheral modules (CPG, TMU, RTC), combined together to2.9 * keep things simple (they intertwine a bit).2.10 @@ -28,6 +28,8 @@2.11 /* This is the base clock from which all other clocks are derived */2.12 uint32_t sh4_input_freq = SH4_BASE_RATE;2.14 +uint32_t sh4_cpu_multiplier = 2000; /* = 0.5 * frequency */2.15 +2.16 uint32_t sh4_cpu_freq = SH4_BASE_RATE;2.17 uint32_t sh4_bus_freq = SH4_BASE_RATE;2.18 uint32_t sh4_peripheral_freq = SH4_BASE_RATE / 2;2.19 @@ -53,7 +55,7 @@2.20 case FRQCR: /* Frequency control */2.21 div = ifc_divider[(val >> 6) & 0x07];2.22 sh4_cpu_freq = sh4_input_freq / div;2.23 - sh4_cpu_period = 2000 * div / sh4_input_freq;2.24 + sh4_cpu_period = sh4_cpu_multiplier * div / sh4_input_freq;2.25 div = ifc_divider[(val >> 3) & 0x07];2.26 sh4_bus_freq = sh4_input_freq / div;2.27 sh4_bus_period = 1000 * div / sh4_input_freq;
.