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lxdream 0.9.1
released Jun 29
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changeset1011:fdd58619b760 xlat-refactor
parent1006:3a169c224c12
child1012:0b8cc74ac83a
authornkeynes
dateSun Apr 12 07:24:45 2009 +0000 (10 years ago)
branchxlat-refactor
Restructure operand types -
rename to forms to avoid conflict for actual data types
temporary operands are now a first class form
remove explicit types for immediates - now implied by opcode
Initial work on promote-source-reg pass
src/Makefile.am
src/Makefile.in
src/sh4/sh4x86.in
src/sh4/sh4xir.in
src/test/testsh4xir.c
src/test/testxir.c
src/xlat/regalloc.c
src/xlat/regalloc.h
src/xlat/x86/x86gen.c
src/xlat/x86/x86op.h
src/xlat/x86/x86target.c
src/xlat/xir.c
src/xlat/xir.h
src/xlat/xirsup.c
src/xlat/xlat.h
1.1 --- a/src/Makefile.am Tue Apr 07 10:55:03 2009 +0000
1.2 +++ b/src/Makefile.am Sun Apr 12 07:24:45 2009 +0000
1.3 @@ -83,10 +83,10 @@
1.4 xlat/xltcache.h mem.c util.c
1.5
1.6 test_testsh4xir_LDADD = @GLIB_LIBS@ @GTK_LIBS@ @LIBPNG_LIBS@
1.7 -test_testsh4xir_SOURCES = test/testsh4xir.c xlat/xir.c xlat/xir.h sh4/sh4xir.c xlat/x86/x86target.c xlat/x86/x86gen.c
1.8 +test_testsh4xir_SOURCES = test/testsh4xir.c xlat/xir.c xlat/xir.h sh4/sh4xir.c xlat/x86/x86target.c xlat/x86/x86gen.c xlat/regalloc.c
1.9
1.10 test_testxir_LDADD = @GLIB_LIBS@ @GTK_LIBS@ @LIBPNG_LIBS@
1.11 -test_testxir_SOURCES = test/testxir.c xlat/xir.c xlat/xir.h xlat/xirsup.c xlat/xiropt.c xlat/xiropt.h
1.12 +test_testxir_SOURCES = test/testxir.c xlat/xir.c xlat/xir.h xlat/xirsup.c xlat/xiropt.h
1.13
1.14 check_PROGRAMS += test/testsh4x86 test/testsh4xir test/testxir
1.15 endif
2.1 --- a/src/Makefile.in Tue Apr 07 10:55:03 2009 +0000
2.2 +++ b/src/Makefile.in Sun Apr 12 07:24:45 2009 +0000
2.3 @@ -216,17 +216,18 @@
2.4 test_testsh4x86_DEPENDENCIES =
2.5 am__dirstamp = $(am__leading_dot)dirstamp
2.6 am__test_testsh4xir_SOURCES_DIST = test/testsh4xir.c xlat/xir.c \
2.7 - xlat/xir.h sh4/sh4xir.c xlat/x86/x86target.c xlat/x86/x86gen.c
2.8 + xlat/xir.h sh4/sh4xir.c xlat/x86/x86target.c xlat/x86/x86gen.c \
2.9 + xlat/regalloc.c
2.10 @BUILD_SH4X86_TRUE@am_test_testsh4xir_OBJECTS = testsh4xir.$(OBJEXT) \
2.11 @BUILD_SH4X86_TRUE@ xir.$(OBJEXT) sh4xir.$(OBJEXT) \
2.12 -@BUILD_SH4X86_TRUE@ x86target.$(OBJEXT) x86gen.$(OBJEXT)
2.13 +@BUILD_SH4X86_TRUE@ x86target.$(OBJEXT) x86gen.$(OBJEXT) \
2.14 +@BUILD_SH4X86_TRUE@ regalloc.$(OBJEXT)
2.15 test_testsh4xir_OBJECTS = $(am_test_testsh4xir_OBJECTS)
2.16 test_testsh4xir_DEPENDENCIES =
2.17 am__test_testxir_SOURCES_DIST = test/testxir.c xlat/xir.c xlat/xir.h \
2.18 - xlat/xirsup.c xlat/xiropt.c xlat/xiropt.h
2.19 + xlat/xirsup.c xlat/xiropt.h
2.20 @BUILD_SH4X86_TRUE@am_test_testxir_OBJECTS = testxir.$(OBJEXT) \
2.21 -@BUILD_SH4X86_TRUE@ xir.$(OBJEXT) xirsup.$(OBJEXT) \
2.22 -@BUILD_SH4X86_TRUE@ xiropt.$(OBJEXT)
2.23 +@BUILD_SH4X86_TRUE@ xir.$(OBJEXT) xirsup.$(OBJEXT)
2.24 test_testxir_OBJECTS = $(am_test_testxir_OBJECTS)
2.25 test_testxir_DEPENDENCIES =
2.26 am_test_testxlt_OBJECTS = testxlt.$(OBJEXT) xltcache.$(OBJEXT)
2.27 @@ -491,9 +492,9 @@
2.28 @BUILD_SH4X86_TRUE@ xlat/xltcache.h mem.c util.c
2.29
2.30 @BUILD_SH4X86_TRUE@test_testsh4xir_LDADD = @GLIB_LIBS@ @GTK_LIBS@ @LIBPNG_LIBS@
2.31 -@BUILD_SH4X86_TRUE@test_testsh4xir_SOURCES = test/testsh4xir.c xlat/xir.c xlat/xir.h sh4/sh4xir.c xlat/x86/x86target.c xlat/x86/x86gen.c
2.32 +@BUILD_SH4X86_TRUE@test_testsh4xir_SOURCES = test/testsh4xir.c xlat/xir.c xlat/xir.h sh4/sh4xir.c xlat/x86/x86target.c xlat/x86/x86gen.c xlat/regalloc.c
2.33 @BUILD_SH4X86_TRUE@test_testxir_LDADD = @GLIB_LIBS@ @GTK_LIBS@ @LIBPNG_LIBS@
2.34 -@BUILD_SH4X86_TRUE@test_testxir_SOURCES = test/testxir.c xlat/xir.c xlat/xir.h xlat/xirsup.c xlat/xiropt.c xlat/xiropt.h
2.35 +@BUILD_SH4X86_TRUE@test_testxir_SOURCES = test/testxir.c xlat/xir.c xlat/xir.h xlat/xirsup.c xlat/xiropt.h
2.36 lxdream_LDADD = @GLIB_LIBS@ @GTK_LIBS@ @LIBPNG_LIBS@ @PULSE_LIBS@ @ESOUND_LIBS@ @ALSA_LIBS@ @SDL_LIBS@ $(INTLLIBS)
2.37 gendec_LDADD = @GLIB_LIBS@ @GTK_LIBS@ $(INTLLIBS)
2.38 genglsl_LDADD = @GLIB_LIBS@ @GTK_LIBS@ $(INTLLIBS)
2.39 @@ -674,6 +675,7 @@
2.40 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pmm.Po@am__quote@
2.41 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pvr2.Po@am__quote@
2.42 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pvr2mem.Po@am__quote@
2.43 +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/regalloc.Po@am__quote@
2.44 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/rendsave.Po@am__quote@
2.45 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/rendsort.Po@am__quote@
2.46 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/scene.Po@am__quote@
2.47 @@ -710,7 +712,6 @@
2.48 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/x86gen.Po@am__quote@
2.49 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/x86target.Po@am__quote@
2.50 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xir.Po@am__quote@
2.51 -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xiropt.Po@am__quote@
2.52 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xirsup.Po@am__quote@
2.53 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xltcache.Po@am__quote@
2.54 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/yuv.Po@am__quote@
2.55 @@ -1933,6 +1934,20 @@
2.56 @AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
2.57 @am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o x86gen.obj `if test -f 'xlat/x86/x86gen.c'; then $(CYGPATH_W) 'xlat/x86/x86gen.c'; else $(CYGPATH_W) '$(srcdir)/xlat/x86/x86gen.c'; fi`
2.58
2.59 +regalloc.o: xlat/regalloc.c
2.60 +@am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT regalloc.o -MD -MP -MF "$(DEPDIR)/regalloc.Tpo" -c -o regalloc.o `test -f 'xlat/regalloc.c' || echo '$(srcdir)/'`xlat/regalloc.c; \
2.61 +@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/regalloc.Tpo" "$(DEPDIR)/regalloc.Po"; else rm -f "$(DEPDIR)/regalloc.Tpo"; exit 1; fi
2.62 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='xlat/regalloc.c' object='regalloc.o' libtool=no @AMDEPBACKSLASH@
2.63 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
2.64 +@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o regalloc.o `test -f 'xlat/regalloc.c' || echo '$(srcdir)/'`xlat/regalloc.c
2.65 +
2.66 +regalloc.obj: xlat/regalloc.c
2.67 +@am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT regalloc.obj -MD -MP -MF "$(DEPDIR)/regalloc.Tpo" -c -o regalloc.obj `if test -f 'xlat/regalloc.c'; then $(CYGPATH_W) 'xlat/regalloc.c'; else $(CYGPATH_W) '$(srcdir)/xlat/regalloc.c'; fi`; \
2.68 +@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/regalloc.Tpo" "$(DEPDIR)/regalloc.Po"; else rm -f "$(DEPDIR)/regalloc.Tpo"; exit 1; fi
2.69 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='xlat/regalloc.c' object='regalloc.obj' libtool=no @AMDEPBACKSLASH@
2.70 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
2.71 +@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o regalloc.obj `if test -f 'xlat/regalloc.c'; then $(CYGPATH_W) 'xlat/regalloc.c'; else $(CYGPATH_W) '$(srcdir)/xlat/regalloc.c'; fi`
2.72 +
2.73 testxir.o: test/testxir.c
2.74 @am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT testxir.o -MD -MP -MF "$(DEPDIR)/testxir.Tpo" -c -o testxir.o `test -f 'test/testxir.c' || echo '$(srcdir)/'`test/testxir.c; \
2.75 @am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/testxir.Tpo" "$(DEPDIR)/testxir.Po"; else rm -f "$(DEPDIR)/testxir.Tpo"; exit 1; fi
2.76 @@ -1961,20 +1976,6 @@
2.77 @AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
2.78 @am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o xirsup.obj `if test -f 'xlat/xirsup.c'; then $(CYGPATH_W) 'xlat/xirsup.c'; else $(CYGPATH_W) '$(srcdir)/xlat/xirsup.c'; fi`
2.79
2.80 -xiropt.o: xlat/xiropt.c
2.81 -@am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT xiropt.o -MD -MP -MF "$(DEPDIR)/xiropt.Tpo" -c -o xiropt.o `test -f 'xlat/xiropt.c' || echo '$(srcdir)/'`xlat/xiropt.c; \
2.82 -@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/xiropt.Tpo" "$(DEPDIR)/xiropt.Po"; else rm -f "$(DEPDIR)/xiropt.Tpo"; exit 1; fi
2.83 -@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='xlat/xiropt.c' object='xiropt.o' libtool=no @AMDEPBACKSLASH@
2.84 -@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
2.85 -@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o xiropt.o `test -f 'xlat/xiropt.c' || echo '$(srcdir)/'`xlat/xiropt.c
2.86 -
2.87 -xiropt.obj: xlat/xiropt.c
2.88 -@am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT xiropt.obj -MD -MP -MF "$(DEPDIR)/xiropt.Tpo" -c -o xiropt.obj `if test -f 'xlat/xiropt.c'; then $(CYGPATH_W) 'xlat/xiropt.c'; else $(CYGPATH_W) '$(srcdir)/xlat/xiropt.c'; fi`; \
2.89 -@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/xiropt.Tpo" "$(DEPDIR)/xiropt.Po"; else rm -f "$(DEPDIR)/xiropt.Tpo"; exit 1; fi
2.90 -@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='xlat/xiropt.c' object='xiropt.obj' libtool=no @AMDEPBACKSLASH@
2.91 -@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
2.92 -@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o xiropt.obj `if test -f 'xlat/xiropt.c'; then $(CYGPATH_W) 'xlat/xiropt.c'; else $(CYGPATH_W) '$(srcdir)/xlat/xiropt.c'; fi`
2.93 -
2.94 testxlt.o: test/testxlt.c
2.95 @am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT testxlt.o -MD -MP -MF "$(DEPDIR)/testxlt.Tpo" -c -o testxlt.o `test -f 'test/testxlt.c' || echo '$(srcdir)/'`test/testxlt.c; \
2.96 @am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/testxlt.Tpo" "$(DEPDIR)/testxlt.Po"; else rm -f "$(DEPDIR)/testxlt.Tpo"; exit 1; fi
3.1 --- a/src/sh4/sh4x86.in Tue Apr 07 10:55:03 2009 +0000
3.2 +++ b/src/sh4/sh4x86.in Sun Apr 12 07:24:45 2009 +0000
3.3 @@ -2379,11 +2379,11 @@
3.4 check_fpuen();
3.5 if( sh4_x86.double_prec == 0 ) {
3.6 if( sh4_x86.sse3_enabled ) {
3.7 - MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[0][FVm<<2]), 4 );
3.8 - MULPS_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 );
3.9 + MOVAPS_r32disp_xmm( REG_RBP, REG_OFFSET(fr[0][FVm<<2]), 4 );
3.10 + MULPS_r32disp_xmm( REG_RBP, REG_OFFSET(fr[0][FVn<<2]), 4 );
3.11 HADDPS_xmm_xmm( 4, 4 );
3.12 HADDPS_xmm_xmm( 4, 4 );
3.13 - MOVSS_xmm_rbpdisp( 4, REG_OFFSET(fr[0][(FVn<<2)+2]) );
3.14 + MOVSS_xmm_r32disp( 4, REG_RBP, REG_OFFSET(fr[0][(FVn<<2)+2]) );
3.15 } else {
3.16 push_fr( FVm<<2 );
3.17 push_fr( FVn<<2 );
3.18 @@ -2409,13 +2409,13 @@
3.19 check_fpuen();
3.20 if( sh4_x86.double_prec == 0 ) {
3.21 if( sh4_x86.sse3_enabled ) {
3.22 - MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][0]), 1 ); // M1 M0 M3 M2
3.23 - MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][4]), 0 ); // M5 M4 M7 M6
3.24 - MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][8]), 3 ); // M9 M8 M11 M10
3.25 - MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][12]), 2 );// M13 M12 M15 M14
3.26 + MOVAPS_r32disp_xmm( REG_RBP, REG_OFFSET(fr[1][0]), 1 ); // M1 M0 M3 M2
3.27 + MOVAPS_r32disp_xmm( REG_RBP, REG_OFFSET(fr[1][4]), 0 ); // M5 M4 M7 M6
3.28 + MOVAPS_r32disp_xmm( REG_RBP, REG_OFFSET(fr[1][8]), 3 ); // M9 M8 M11 M10
3.29 + MOVAPS_r32disp_xmm( REG_RBP, REG_OFFSET(fr[1][12]), 2 );// M13 M12 M15 M14
3.30
3.31 - MOVSLDUP_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 ); // V1 V1 V3 V3
3.32 - MOVSHDUP_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 5 ); // V0 V0 V2 V2
3.33 + MOVSLDUP_r32disp_xmm( REG_RBP, REG_OFFSET(fr[0][FVn<<2]), 4 ); // V1 V1 V3 V3
3.34 + MOVSHDUP_r32disp_xmm( REG_RBP, REG_OFFSET(fr[0][FVn<<2]), 5 ); // V0 V0 V2 V2
3.35 MOV_xmm_xmm( 4, 6 );
3.36 MOV_xmm_xmm( 5, 7 );
3.37 MOVLHPS_xmm_xmm( 4, 4 ); // V1 V1 V1 V1
3.38 @@ -2429,7 +2429,7 @@
3.39 ADDPS_xmm_xmm( 5, 4 );
3.40 ADDPS_xmm_xmm( 7, 6 );
3.41 ADDPS_xmm_xmm( 6, 4 );
3.42 - MOVAPS_xmm_rbpdisp( 4, REG_OFFSET(fr[0][FVn<<2]) );
3.43 + MOVAPS_xmm_r32disp( 4, REG_RBP, REG_OFFSET(fr[0][FVn<<2]) );
3.44 } else {
3.45 LEAP_rbpdisp_rptr( REG_OFFSET(fr[0][FVn<<2]), REG_EAX );
3.46 CALL1_ptr_r32( sh4_ftrv, REG_EAX );
4.1 --- a/src/sh4/sh4xir.in Tue Apr 07 10:55:03 2009 +0000
4.2 +++ b/src/sh4/sh4xir.in Sun Apr 12 07:24:45 2009 +0000
4.3 @@ -37,11 +37,11 @@
4.4 #define R_Q REG_OFFSET(q)
4.5 #define R_S REG_OFFSET(s)
4.6 #define R_FR(frn) REG_OFFSET(fr[0][(frn)^1])
4.7 -#define R_DR(frn) REG_OFFSET(fr[0][frn])
4.8 +#define R_DR(frn) REG_OFFSET(fr[0][(frn)&0x0E])
4.9 #define R_DRL(f) REG_OFFSET(fr[(f)&1][(f)|0x01])
4.10 #define R_DRH(f) REG_OFFSET(fr[(f)&1][(f)&0x0E])
4.11 #define R_XF(frn) REG_OFFSET(fr[1][(frn)^1])
4.12 -#define R_XD(frn) REG_OFFSET(fr[1][frn^1])
4.13 +#define R_XD(frn) REG_OFFSET(fr[1][(frn)&0x0E])
4.14 #define R_FV(fvn) REG_OFFSET(fr[0][fvn<<2])
4.15 #define R_XMTRX R_XD(0)
4.16 #define R_FPSCR REG_OFFSET(fpscr)
4.17 @@ -72,8 +72,46 @@
4.18 "store_queue", 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4.19 "new_pc", "event_pending", "event_type", "delay_slot", "slice_cycle", "bus_cycle", "state", "xlat_mode" };
4.20
4.21 -struct xlat_source_machine sh4_source_machine = { "sH4", &sh4r,
4.22 - sh4_register_names, R_PC, R_NEW_PC, R_T, R_M, R_Q, R_S,
4.23 +static const char *sh4_quad_register_names[] = /* From FR1 to MACH */
4.24 + {"dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
4.25 + "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14",
4.26 + NULL, "mac" };
4.27 +static const char *sh4_vec4_register_names[] = /* From FR1 to XF14 */
4.28 + {"fv0", "fv4", "fv8", "fv12", "xfv0", "xfv4", "xfv8", "xfv12" };
4.29 +
4.30 +static const char *sh4_get_register_name( uint32_t reg, xir_type_t ty )
4.31 +{
4.32 + switch( ty ) {
4.33 + case XTY_LONG:
4.34 + case XTY_FLOAT:
4.35 + if( reg <= R_SH4_MODE ) {
4.36 + return sh4_register_names[reg>>2];
4.37 + }
4.38 + break;
4.39 + case XTY_QUAD:
4.40 + case XTY_DOUBLE:
4.41 + if( reg >= R_DR(0) && reg <= R_MACH ) {
4.42 + return sh4_quad_register_names[(reg-R_DR(0))>>3];
4.43 + }
4.44 + break;
4.45 + case XTY_VEC4F:
4.46 + if( reg >= R_DR(0) && reg <= R_XD(14) ) {
4.47 + return sh4_vec4_register_names[(reg-R_DR(0))>>4];
4.48 + }
4.49 + break;
4.50 + case XTY_MAT16F:
4.51 + if( reg = R_XMTRX ) {
4.52 + return "xmtrx";
4.53 + } else if( reg == R_DR(0) ) {
4.54 + return "mtrx";
4.55 + }
4.56 + }
4.57 + return NULL;
4.58 +}
4.59 +
4.60 +struct xlat_source_machine sh4_source_machine = { "SH4", &sh4r,
4.61 + R_PC, R_NEW_PC, R_T, R_M, R_Q, R_S,
4.62 + sh4_get_register_name,
4.63 sh4_decode_basic_block };
4.64
4.65 /**
4.66 @@ -89,21 +127,55 @@
4.67
4.68 static struct sh4_xir_state sh4_xir;
4.69
4.70 -#define XOP1E( op, arg0 ) do{ \
4.71 - xir_op_t ins = xir_append_op2(xbb, op, SOURCE_REGISTER_OPERAND, arg0, NO_OPERAND, 0); \
4.72 - ins->exc = write_postexc(xbb, (in_delay_slot ? pc-2 : pc) ); \
4.73 - ins->next = xbb->ir_ptr; \
4.74 - xbb->ir_ptr->prev = ins; \
4.75 - } while(0)
4.76 -#define XOP2E( op, arg0, arg1 ) do{ \
4.77 - xir_op_t ins = xir_append_op2(xbb, op, SOURCE_REGISTER_OPERAND, arg0, SOURCE_REGISTER_OPERAND, arg1); \
4.78 - ins->exc = write_postexc(xbb, (in_delay_slot ? pc-2 : pc) ); \
4.79 - ins->exc->prev = ins; \
4.80 - ins->next = xbb->ir_ptr; \
4.81 - xbb->ir_ptr->prev = ins; \
4.82 - } while(0)
4.83 +/**
4.84 + * Create a standard exception-taking stub sub-block - updates SPC, slice_cycle, and exits
4.85 + * @return the first xir_op_t of the exception block.
4.86 + */
4.87 +static inline xir_op_t write_exc( xir_basic_block_t xbb, sh4addr_t pc, int exc_code )
4.88 +{
4.89 + xir_op_t start = xbb->ir_ptr;
4.90 + XOPCALL1I( sh4_raise_exception, exc_code );
4.91 + if( pc != xbb->pc_begin ) {
4.92 + XOP2IS( OP_ADD, pc - xbb->pc_begin, R_SPC );
4.93 + }
4.94 + XOP2IS( OP_ADD, (pc+2 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
4.95 + XOP1S( OP_BR, R_SPC )->next = NULL;
4.96 + start->prev = NULL;
4.97 + return start;
4.98 +}
4.99 +
4.100 +/**
4.101 + * Create an instruction with a standard post-exception stub sub-block (ie
4.102 + * sh4_raise_exception or similar has already been called - update SPC +
4.103 + * slice_cycle and exit).
4.104 + * @return the first xir_op_t of the exception block.
4.105 + */
4.106 +static xir_op_t xir_append_op2_exc( xir_basic_block_t xbb, int op, int arg0form, uint32_t arg0, int arg1form, uint32_t arg1, sh4addr_t pc )
4.107 +{
4.108 + xir_op_t ins = xir_append_op2( xbb, op, arg0form, arg0, arg1form, arg1 );
4.109 + ins->exc = xbb->ir_ptr;
4.110 + ins->exc->prev = ins;
4.111 +
4.112 + if( pc != xbb->pc_begin ) {
4.113 + XOP2IS( OP_ADD, pc - xbb->pc_begin, R_SPC );
4.114 + }
4.115 + XOP2IS( OP_ADD, (pc+2 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
4.116 + XOP1S( OP_BR, R_SPC )->next = NULL;
4.117 +
4.118 + ins->next = xbb->ir_ptr;
4.119 + xbb->ir_ptr->prev = ins;
4.120 + return ins;
4.121 +}
4.122 +
4.123 +#define XOP1SE( op, arg0 ) xir_append_op2_exc( xbb, op, SOURCE_OPERAND, arg0, NO_OPERAND, 0, (in_delay_slot ? pc-2 : pc))
4.124 +#define XOP1TE( op, arg0 ) xir_append_op2_exc( xbb, op, TEMP_OPERAND, arg0, NO_OPERAND, 0, (in_delay_slot ? pc-2 : pc))
4.125 +#define XOP2SSE( op, arg0, arg1 ) xir_append_op2_exc( xbb, op, SOURCE_OPERAND, arg0, SOURCE_OPERAND, arg1, (in_delay_slot ? pc-2 : pc))
4.126 +#define XOP2STE( op, arg0, arg1 ) xir_append_op2_exc( xbb, op, SOURCE_OPERAND, arg0, TEMP_OPERAND, arg1, (in_delay_slot ? pc-2 : pc))
4.127 +#define XOP2TSE( op, arg0, arg1 ) xir_append_op2_exc( xbb, op, TEMP_OPERAND, arg0, SOURCE_OPERAND, arg1, (in_delay_slot ? pc-2 : pc))
4.128 +#define XOP2TTE( op, arg0, arg1 ) xir_append_op2_exc( xbb, op, TEMP_OPERAND, arg0, TEMP_OPERAND, arg1, (in_delay_slot ? pc-2 : pc))
4.129 +
4.130 #define ALIGN(m,r,code) do { \
4.131 - xir_op_t ins = xir_append_op2(xbb, OP_RAISEMNE, INT_IMM_OPERAND, m, SOURCE_REGISTER_OPERAND, r); \
4.132 + xir_op_t ins = xir_append_op2(xbb, OP_RAISEMNE, IMMEDIATE_OPERAND, m, SOURCE_OPERAND, r); \
4.133 ins->exc = write_exc(xbb, (in_delay_slot ? pc-2 : pc), code); \
4.134 ins->exc->prev = ins; \
4.135 ins->next = xbb->ir_ptr; \
4.136 @@ -115,7 +187,7 @@
4.137
4.138 #define UNDEF(ir) if( in_delay_slot ) { SLOTILLEGAL(); return 2; } else { ILLEGAL(); return 2; }
4.139 #define CHECKFPUEN() if( !sh4_xir.fpuen_checked ) { \
4.140 - xir_op_t ins = XOP2I( OP_RAISEMNE, SR_FD, R_SR ); \
4.141 + xir_op_t ins = XOP2IS( OP_RAISEMNE, SR_FD, R_SR ); \
4.142 if( in_delay_slot ) { \
4.143 ins->exc = write_exc(xbb, pc-2, EXC_SLOT_FPU_DISABLED); \
4.144 } else { \
4.145 @@ -138,370 +210,336 @@
4.146 #define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc)
4.147
4.148 #define EMU_DELAY_SLOT() do { \
4.149 - XOP2I( OP_ADD, (pc+2 - xbb->pc_begin), R_PC ); \
4.150 - XOP2I( OP_MOV, 1, R_DELAY_SLOT ); \
4.151 + XOP2IS( OP_ADD, (pc+2 - xbb->pc_begin), R_PC ); \
4.152 + XOP2IS( OP_MOV, 1, R_DELAY_SLOT ); \
4.153 XOP0( OP_BARRIER ); \
4.154 XOPCALL0( sh4_execute_instruction ); \
4.155 - XOP1( OP_BR, R_PC ); \
4.156 + XOP1S( OP_BR, R_PC ); \
4.157 } while(0)
4.158
4.159
4.160 -/**
4.161 - * Create a standard post-exception stub sub-block (ie sh4_raise_exception or similar has
4.162 - * already been called - update SPC + slice_cycle and exit).
4.163 - * @return the first xir_op_t of the exception block.
4.164 - */
4.165 -static inline xir_op_t write_postexc( xir_basic_block_t xbb, sh4addr_t pc )
4.166 -{
4.167 - xir_op_t start = xbb->ir_ptr;
4.168 - if( pc != xbb->pc_begin ) {
4.169 - XOP2I( OP_ADD, pc - xbb->pc_begin, R_SPC );
4.170 - }
4.171 - XOP2I( OP_ADD, (pc+2 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
4.172 - XOP1( OP_BR, R_SPC )->next = NULL;
4.173 - start->prev = NULL;
4.174 - return start;
4.175 -}
4.176 -
4.177 -/**
4.178 - * Create a standard exception-taking stub sub-block - updates SPC, slice_cycle, and exits
4.179 - * @return the first xir_op_t of the exception block.
4.180 - */
4.181 -static inline xir_op_t write_exc( xir_basic_block_t xbb, sh4addr_t pc, int exc_code )
4.182 -{
4.183 - xir_op_t start = xbb->ir_ptr;
4.184 - XOPCALL1I( sh4_raise_exception, exc_code );
4.185 - if( pc != xbb->pc_begin ) {
4.186 - XOP2I( OP_ADD, pc - xbb->pc_begin, R_SPC );
4.187 - }
4.188 - XOP2I( OP_ADD, (pc+2 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
4.189 - XOP1( OP_BR, R_SPC )->next = NULL;
4.190 - start->prev = NULL;
4.191 - return start;
4.192 -}
4.193 -
4.194 static sh4addr_t sh4_decode_instruction( xir_basic_block_t xbb, sh4addr_t pc, gboolean in_delay_slot )
4.195 {
4.196 assert( IS_IN_ICACHE(pc) );
4.197 uint16_t ir = *(uint16_t *)GET_ICACHE_PTR(pc);
4.198
4.199 %%
4.200 -ADD Rm, Rn {: XOP2( OP_ADD, R_R(Rm), R_R(Rn) ); :}
4.201 -ADD #imm, Rn {: XOP2I( OP_ADD, imm, R_R(Rn) ); :}
4.202 +ADD Rm, Rn {: XOP2SS( OP_ADD, R_R(Rm), R_R(Rn) ); :}
4.203 +ADD #imm, Rn {: XOP2IS( OP_ADD, imm, R_R(Rn) ); :}
4.204 ADDC Rm, Rn {:
4.205 - XOP1CC( OP_LD, CC_C, R_T );
4.206 - XOP2( OP_ADDCS, R_R(Rm), R_R(Rn) );
4.207 - XOP1CC( OP_ST, CC_C, R_T );
4.208 + XOP1SCC( OP_LD, CC_C, R_T );
4.209 + XOP2SS( OP_ADDCS, R_R(Rm), R_R(Rn) );
4.210 + XOP1SCC( OP_ST, CC_C, R_T );
4.211 :}
4.212 -ADDV Rm, Rn {: XOP2( OP_ADDS, R_R(Rm), R_R(Rn) ); XOP1CC( OP_ST, CC_OV, R_T ); :}
4.213 -AND Rm, Rn {: XOP2( OP_AND, R_R(Rm), R_R(Rn) ); :}
4.214 -AND #imm, R0 {: XOP2I( OP_AND, imm, R_R0 ); :}
4.215 -CMP/EQ Rm, Rn {: XOP2( OP_CMP, Rm, R_R(Rn) ); XOP1CC( OP_ST, CC_EQ, R_T ); :}
4.216 -CMP/EQ #imm, R0 {: XOP2I( OP_CMP, imm, R_R0 ); XOP1CC( OP_ST, CC_EQ, R_T ); :}
4.217 -CMP/GE Rm, Rn {: XOP2( OP_CMP, R_R(Rm), R_R(Rn) ); XOP1CC( OP_ST, CC_SGE, R_T ); :}
4.218 -CMP/GT Rm, Rn {: XOP2( OP_CMP, R_R(Rm), R_R(Rn) ); XOP1CC( OP_ST, CC_SGT, R_T ); :}
4.219 -CMP/HI Rm, Rn {: XOP2( OP_CMP, R_R(Rm), R_R(Rn) ); XOP1CC( OP_ST, CC_UGT, R_T ); :}
4.220 -CMP/HS Rm, Rn {: XOP2( OP_CMP, R_R(Rm), R_R(Rn) ); XOP1CC( OP_ST, CC_UGE, R_T ); :}
4.221 -CMP/PL Rn {: XOP2I( OP_CMP, 0, R_R(Rn) ); XOP1CC( OP_ST, CC_SGT, R_T ); :}
4.222 -CMP/PZ Rn {: XOP2I( OP_CMP, 0, R_R(Rn) ); XOP1CC( OP_ST, CC_SGE, R_T ); :}
4.223 -CMP/STR Rm, Rn {: XOP2( OP_CMPSTR, R_R(Rm), R_R(Rn) ); :}
4.224 +ADDV Rm, Rn {: XOP2SS( OP_ADDS, R_R(Rm), R_R(Rn) ); XOP1SCC( OP_ST, CC_OV, R_T ); :}
4.225 +AND Rm, Rn {: XOP2SS( OP_AND, R_R(Rm), R_R(Rn) ); :}
4.226 +AND #imm, R0 {: XOP2IS( OP_AND, imm, R_R0 ); :}
4.227 +CMP/EQ Rm, Rn {: XOP2SS( OP_CMP, Rm, R_R(Rn) ); XOP1SCC( OP_ST, CC_EQ, R_T ); :}
4.228 +CMP/EQ #imm, R0 {: XOP2IS( OP_CMP, imm, R_R0 ); XOP1SCC( OP_ST, CC_EQ, R_T ); :}
4.229 +CMP/GE Rm, Rn {: XOP2SS( OP_CMP, R_R(Rm), R_R(Rn) ); XOP1SCC( OP_ST, CC_SGE, R_T ); :}
4.230 +CMP/GT Rm, Rn {: XOP2SS( OP_CMP, R_R(Rm), R_R(Rn) ); XOP1SCC( OP_ST, CC_SGT, R_T ); :}
4.231 +CMP/HI Rm, Rn {: XOP2SS( OP_CMP, R_R(Rm), R_R(Rn) ); XOP1SCC( OP_ST, CC_UGT, R_T ); :}
4.232 +CMP/HS Rm, Rn {: XOP2SS( OP_CMP, R_R(Rm), R_R(Rn) ); XOP1SCC( OP_ST, CC_UGE, R_T ); :}
4.233 +CMP/PL Rn {: XOP2IS( OP_CMP, 0, R_R(Rn) ); XOP1SCC( OP_ST, CC_SGT, R_T ); :}
4.234 +CMP/PZ Rn {: XOP2IS( OP_CMP, 0, R_R(Rn) ); XOP1SCC( OP_ST, CC_SGE, R_T ); :}
4.235 +CMP/STR Rm, Rn {: XOP2SS( OP_CMPSTR, R_R(Rm), R_R(Rn) ); :}
4.236 DIV0S Rm, Rn {:
4.237 - XOP2( OP_MOV, R_R(Rm), R_M );
4.238 - XOP2I( OP_SLR, 31, R_M );
4.239 - XOP2( OP_MOV, R_R(Rn), R_Q );
4.240 - XOP2I( OP_SLR, 31, R_Q );
4.241 - XOP2( OP_CMP, R_M, R_Q );
4.242 - XOP1CC( OP_ST, CC_NE, R_T );
4.243 + XOP2SS( OP_MOV, R_R(Rm), R_M );
4.244 + XOP2IS( OP_SLR, 31, R_M );
4.245 + XOP2SS( OP_MOV, R_R(Rn), R_Q );
4.246 + XOP2IS( OP_SLR, 31, R_Q );
4.247 + XOP2SS( OP_CMP, R_M, R_Q );
4.248 + XOP1SCC( OP_ST, CC_NE, R_T );
4.249 :}
4.250 DIV0U {:
4.251 - XOP2I( OP_MOV, 0, R_M );
4.252 - XOP2I( OP_MOV, 0, R_Q );
4.253 - XOP2I( OP_MOV, 0, R_T );
4.254 + XOP2IS( OP_MOV, 0, R_M );
4.255 + XOP2IS( OP_MOV, 0, R_Q );
4.256 + XOP2IS( OP_MOV, 0, R_T );
4.257 :}
4.258 -DIV1 Rm, Rn {: XOP2( OP_DIV1, R_R(Rm), R_R(Rn) ); :}
4.259 +DIV1 Rm, Rn {: XOP2SS( OP_DIV1, R_R(Rm), R_R(Rn) ); :}
4.260 DMULS.L Rm, Rn {:
4.261 - XOP2( OP_MOVSX32, R_R(Rm), R_MAC );
4.262 - XOP2( OP_MOVSX32, R_R(Rn), REG_TMP0 );
4.263 - XOP2( OP_MULQ, REG_TMPQ0, R_MAC );
4.264 + XOP2SS( OP_MOVSX32, R_R(Rm), R_MAC );
4.265 + XOP2ST( OP_MOVSX32, R_R(Rn), REG_TMP0 );
4.266 + XOP2TS( OP_MULQ, REG_TMPQ0, R_MAC );
4.267 :}
4.268 DMULU.L Rm, Rn {:
4.269 - XOP2( OP_MOVZX32, R_R(Rm), R_MAC );
4.270 - XOP2( OP_MOVZX32, R_R(Rn), REG_TMP0 ) ;
4.271 - XOP2( OP_MULQ, REG_TMP0, R_MAC );
4.272 + XOP2SS( OP_MOVZX32, R_R(Rm), R_MAC );
4.273 + XOP2ST( OP_MOVZX32, R_R(Rn), REG_TMP0 ) ;
4.274 + XOP2TS( OP_MULQ, REG_TMP0, R_MAC );
4.275 :}
4.276 -DT Rn {: XOP1( OP_DEC, R_R(Rn) ); :}
4.277 -EXTS.B Rm, Rn {: XOP2( OP_MOVSX8, R_R(Rm), R_R(Rn)); :}
4.278 -EXTS.W Rm, Rn {: XOP2( OP_MOVSX16, R_R(Rm), R_R(Rn)); :}
4.279 -EXTU.B Rm, Rn {: XOP2( OP_MOVZX8, R_R(Rm), R_R(Rn)); :}
4.280 -EXTU.W Rm, Rn {: XOP2( OP_MOVZX16, R_R(Rm), R_R(Rn)); :}
4.281 +DT Rn {: XOP1S( OP_DEC, R_R(Rn) ); :}
4.282 +EXTS.B Rm, Rn {: XOP2SS( OP_MOVSX8, R_R(Rm), R_R(Rn)); :}
4.283 +EXTS.W Rm, Rn {: XOP2SS( OP_MOVSX16, R_R(Rm), R_R(Rn)); :}
4.284 +EXTU.B Rm, Rn {: XOP2SS( OP_MOVZX8, R_R(Rm), R_R(Rn)); :}
4.285 +EXTU.W Rm, Rn {: XOP2SS( OP_MOVZX16, R_R(Rm), R_R(Rn)); :}
4.286 MAC.L @Rm+, @Rn+ {:
4.287 RALIGN32(R_R(Rm));
4.288 if( Rm == Rn ) {
4.289 - XOP2E( OP_LOADL, R_R(Rm), REG_TMP0 );
4.290 - XOP2( OP_MOV, R_R(Rm), REG_TMP1 );
4.291 - XOP2I( OP_ADD, 4, REG_TMP1 );
4.292 - XOP2E( OP_LOADL, REG_TMP1, REG_TMP1 );
4.293 - XOP2I( OP_ADD, 8, R_R(Rm) );
4.294 + XOP2STE( OP_LOADL, R_R(Rm), REG_TMP0 );
4.295 + XOP2ST( OP_MOV, R_R(Rm), REG_TMP1 );
4.296 + XOP2IT( OP_ADD, 4, REG_TMP1 );
4.297 + XOP2TTE( OP_LOADL, REG_TMP1, REG_TMP1 );
4.298 + XOP2IS( OP_ADD, 8, R_R(Rm) );
4.299 } else {
4.300 RALIGN32(R_R(Rn));
4.301 - XOP2E( OP_LOADL, R_R(Rm), REG_TMP0 );
4.302 - XOP2E( OP_LOADL, R_R(Rn), REG_TMP1 );
4.303 - XOP2I( OP_ADD, 4, R_R(Rm) );
4.304 - XOP2I( OP_ADD, 4, R_R(Rn) );
4.305 + XOP2STE( OP_LOADL, R_R(Rm), REG_TMP0 );
4.306 + XOP2STE( OP_LOADL, R_R(Rn), REG_TMP1 );
4.307 + XOP2IS( OP_ADD, 4, R_R(Rm) );
4.308 + XOP2IS( OP_ADD, 4, R_R(Rn) );
4.309 }
4.310 - XOP2( OP_MOVSX32, REG_TMP0, REG_TMPQ0 );
4.311 - XOP2( OP_MOVSX32, REG_TMP1, REG_TMPQ1 );
4.312 - XOP2( OP_MULQ, REG_TMPQ0, REG_TMPQ1 );
4.313 - XOP2( OP_ADDQSAT48, REG_TMPQ1, R_MAC );
4.314 + XOP2TT( OP_MOVSX32, REG_TMP0, REG_TMPQ0 );
4.315 + XOP2TT( OP_MOVSX32, REG_TMP1, REG_TMPQ1 );
4.316 + XOP2TT( OP_MULQ, REG_TMPQ0, REG_TMPQ1 );
4.317 + XOP2TS( OP_ADDQSAT48, REG_TMPQ1, R_MAC );
4.318 :}
4.319 MAC.W @Rm+, @Rn+ {:
4.320 RALIGN32(R_R(Rm));
4.321 if( Rm == Rn ) {
4.322 - XOP2E( OP_LOADW, R_R(Rm), REG_TMP0 );
4.323 - XOP2( OP_MOV, R_R(Rm), REG_TMP1 );
4.324 - XOP2I( OP_ADD, 2, REG_TMP1 );
4.325 - XOP2E( OP_LOADW, REG_TMP1, REG_TMP1 );
4.326 - XOP2I( OP_ADD, 4, R_R(Rm) );
4.327 + XOP2STE( OP_LOADW, R_R(Rm), REG_TMP0 );
4.328 + XOP2ST( OP_MOV, R_R(Rm), REG_TMP1 );
4.329 + XOP2IT( OP_ADD, 2, REG_TMP1 );
4.330 + XOP2TTE( OP_LOADW, REG_TMP1, REG_TMP1 );
4.331 + XOP2IS( OP_ADD, 4, R_R(Rm) );
4.332 } else {
4.333 RALIGN32(Rn);
4.334 - XOP2E( OP_LOADW, R_R(Rm), REG_TMP0 );
4.335 - XOP2E( OP_LOADW, R_R(Rn), REG_TMP1 );
4.336 - XOP2I( OP_ADD, 2, R_R(Rm) );
4.337 - XOP2I( OP_ADD, 2, R_R(Rn) );
4.338 + XOP2STE( OP_LOADW, R_R(Rm), REG_TMP0 );
4.339 + XOP2STE( OP_LOADW, R_R(Rn), REG_TMP1 );
4.340 + XOP2IS( OP_ADD, 2, R_R(Rm) );
4.341 + XOP2IS( OP_ADD, 2, R_R(Rn) );
4.342 }
4.343 - XOP2( OP_MOVSX32, REG_TMP0, REG_TMPQ0 );
4.344 - XOP2( OP_MOVSX32, REG_TMP1, REG_TMPQ1 );
4.345 - XOP2( OP_MULQ, REG_TMPQ0, REG_TMPQ1 );
4.346 - XOP2( OP_ADDQSAT32, REG_TMPQ1, R_MAC );
4.347 + XOP2TT( OP_MOVSX32, REG_TMP0, REG_TMPQ0 );
4.348 + XOP2TT( OP_MOVSX32, REG_TMP1, REG_TMPQ1 );
4.349 + XOP2TT( OP_MULQ, REG_TMPQ0, REG_TMPQ1 );
4.350 + XOP2TS( OP_ADDQSAT32, REG_TMPQ1, R_MAC );
4.351 :}
4.352 -MOVT Rn {: XOP2( OP_MOV, R_R(Rn), R_T ); :}
4.353 +MOVT Rn {: XOP2SS( OP_MOV, R_R(Rn), R_T ); :}
4.354 MUL.L Rm, Rn {:
4.355 - XOP2( OP_MOV, R_R(Rm), R_MACL );
4.356 - XOP2( OP_MUL, R_R(Rn), R_MACL );
4.357 + XOP2SS( OP_MOV, R_R(Rm), R_MACL );
4.358 + XOP2SS( OP_MUL, R_R(Rn), R_MACL );
4.359 :}
4.360 MULS.W Rm, Rn {:
4.361 - XOP2( OP_MOVSX16, R_R(Rm), REG_TMP0 );
4.362 - XOP2( OP_MOVSX16, R_R(Rn), R_MACL );
4.363 - XOP2( OP_MUL, REG_TMP0, R_MACL );
4.364 + XOP2ST( OP_MOVSX16, R_R(Rm), REG_TMP0 );
4.365 + XOP2SS( OP_MOVSX16, R_R(Rn), R_MACL );
4.366 + XOP2TS( OP_MUL, REG_TMP0, R_MACL );
4.367 :}
4.368 MULU.W Rm, Rn {:
4.369 - XOP2( OP_MOVZX16, R_R(Rm), REG_TMP0 );
4.370 - XOP2( OP_MOVZX16, R_R(Rn), R_MACL );
4.371 - XOP2( OP_MUL, REG_TMP0, R_MACL );
4.372 + XOP2ST( OP_MOVZX16, R_R(Rm), REG_TMP0 );
4.373 + XOP2SS( OP_MOVZX16, R_R(Rn), R_MACL );
4.374 + XOP2TS( OP_MUL, REG_TMP0, R_MACL );
4.375 :}
4.376 NEG Rm, Rn {:
4.377 - XOP2( OP_NEG, R_R(Rm), R_R(Rn) );
4.378 + XOP2SS( OP_NEG, R_R(Rm), R_R(Rn) );
4.379 :}
4.380 NEGC Rm, Rn {:
4.381 - XOP1CC( OP_LD, CC_C, R_T );
4.382 + XOP1SCC( OP_LD, CC_C, R_T );
4.383 if( Rm == Rn ) {
4.384 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
4.385 - XOP2I(OP_MOV, 0, R_R(Rn) );
4.386 - XOP2( OP_SUBBS, REG_TMP0, R_R(Rn) );
4.387 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
4.388 + XOP2IS(OP_MOV, 0, R_R(Rn) );
4.389 + XOP2TS( OP_SUBBS, REG_TMP0, R_R(Rn) );
4.390 } else {
4.391 - XOP2I(OP_MOV, 0, R_R(Rn) );
4.392 - XOP2( OP_SUBBS, R_R(Rm), R_R(Rn) );
4.393 + XOP2IS(OP_MOV, 0, R_R(Rn) );
4.394 + XOP2SS( OP_SUBBS, R_R(Rm), R_R(Rn) );
4.395 }
4.396 - XOP1CC( OP_ST, CC_C, R_T );
4.397 + XOP1SCC( OP_ST, CC_C, R_T );
4.398 :}
4.399 NOT Rm, Rn {:
4.400 - XOP2( OP_NOT, R_R(Rm), R_R(Rn) );
4.401 + XOP2SS( OP_NOT, R_R(Rm), R_R(Rn) );
4.402 :}
4.403 -OR Rm, Rn {: XOP2( OP_OR, R_R(Rm), R_R(Rn) ); :}
4.404 -OR #imm, R0 {: XOP2I( OP_OR, imm, R_R0 ); :}
4.405 -ROTCL Rn {: XOP1CC( OP_LD, CC_C, R_T ); XOP2I( OP_RCL, 1, R_R(Rn) ); XOP1CC( OP_ST, CC_C, R_T); :}
4.406 -ROTCR Rn {: XOP1CC( OP_LD, CC_C, R_T ); XOP2I( OP_RCR, 1, R_R(Rn) ); XOP1CC( OP_ST, CC_C, R_T); :}
4.407 -ROTL Rn {: XOP2I( OP_ROL, 1, R_R(Rn) ); :}
4.408 -ROTR Rn {: XOP2I( OP_ROR, 1, R_R(Rn) ); :}
4.409 -SHAD Rm, Rn {: XOP2( OP_SHAD, R_R(Rm), R_R(Rn) ); :}
4.410 -SHLD Rm, Rn {: XOP2( OP_SHLD, R_R(Rm), R_R(Rn) ); :}
4.411 -SHAL Rn {: XOP2I( OP_SLLS, 1, R_R(Rn) ); XOP1CC( OP_ST, CC_C, R_T); :}
4.412 -SHAR Rn {: XOP2I( OP_SARS, 1, R_R(Rn) ); XOP1CC( OP_ST, CC_C, R_T); :}
4.413 -SHLL Rn {: XOP2I( OP_SLLS, 1, R_R(Rn) ); XOP1CC( OP_ST, CC_C, R_T); :}
4.414 -SHLL2 Rn {: XOP2I( OP_SLL, 2, R_R(Rn) ); :}
4.415 -SHLL8 Rn {: XOP2I( OP_SLL, 8, R_R(Rn) ); :}
4.416 -SHLL16 Rn {: XOP2I( OP_SLL, 16, R_R(Rn) ); :}
4.417 -SHLR Rn {: XOP2I( OP_SLRS, 1, R_R(Rn) ); XOP1CC( OP_ST, CC_C, R_T); :}
4.418 -SHLR2 Rn {: XOP2I( OP_SLR, 2, R_R(Rn) ); :}
4.419 -SHLR8 Rn {: XOP2I( OP_SLR, 8, R_R(Rn) ); :}
4.420 -SHLR16 Rn {: XOP2I( OP_SLR, 16, R_R(Rn) ); :}
4.421 +OR Rm, Rn {: XOP2SS( OP_OR, R_R(Rm), R_R(Rn) ); :}
4.422 +OR #imm, R0 {: XOP2IS( OP_OR, imm, R_R0 ); :}
4.423 +ROTCL Rn {: XOP1SCC( OP_LD, CC_C, R_T ); XOP2IS( OP_RCL, 1, R_R(Rn) ); XOP1SCC( OP_ST, CC_C, R_T); :}
4.424 +ROTCR Rn {: XOP1SCC( OP_LD, CC_C, R_T ); XOP2IS( OP_RCR, 1, R_R(Rn) ); XOP1SCC( OP_ST, CC_C, R_T); :}
4.425 +ROTL Rn {: XOP2IS( OP_ROL, 1, R_R(Rn) ); :}
4.426 +ROTR Rn {: XOP2IS( OP_ROR, 1, R_R(Rn) ); :}
4.427 +SHAD Rm, Rn {: XOP2SS( OP_SHAD, R_R(Rm), R_R(Rn) ); :}
4.428 +SHLD Rm, Rn {: XOP2SS( OP_SHLD, R_R(Rm), R_R(Rn) ); :}
4.429 +SHAL Rn {: XOP2IS( OP_SLLS, 1, R_R(Rn) ); XOP1SCC( OP_ST, CC_C, R_T); :}
4.430 +SHAR Rn {: XOP2IS( OP_SARS, 1, R_R(Rn) ); XOP1SCC( OP_ST, CC_C, R_T); :}
4.431 +SHLL Rn {: XOP2IS( OP_SLLS, 1, R_R(Rn) ); XOP1SCC( OP_ST, CC_C, R_T); :}
4.432 +SHLL2 Rn {: XOP2IS( OP_SLL, 2, R_R(Rn) ); :}
4.433 +SHLL8 Rn {: XOP2IS( OP_SLL, 8, R_R(Rn) ); :}
4.434 +SHLL16 Rn {: XOP2IS( OP_SLL, 16, R_R(Rn) ); :}
4.435 +SHLR Rn {: XOP2IS( OP_SLRS, 1, R_R(Rn) ); XOP1SCC( OP_ST, CC_C, R_T); :}
4.436 +SHLR2 Rn {: XOP2IS( OP_SLR, 2, R_R(Rn) ); :}
4.437 +SHLR8 Rn {: XOP2IS( OP_SLR, 8, R_R(Rn) ); :}
4.438 +SHLR16 Rn {: XOP2IS( OP_SLR, 16, R_R(Rn) ); :}
4.439 SUB Rm, Rn {:
4.440 if( Rm == Rn ) {
4.441 /* Break false dependence */
4.442 - XOP2I( OP_MOV, 0, R_R(Rn) );
4.443 + XOP2IS( OP_MOV, 0, R_R(Rn) );
4.444 } else {
4.445 - XOP2( OP_SUB, R_R(Rm), R_R(Rn) );
4.446 + XOP2SS( OP_SUB, R_R(Rm), R_R(Rn) );
4.447 }
4.448 :}
4.449 -SUBC Rm, Rn {: XOP1CC( OP_LD, CC_C, R_T ); XOP2( OP_SUBBS, R_R(Rm), R_R(Rn) ); XOP1CC( OP_ST, CC_C, R_T ); :}
4.450 -SUBV Rm, Rn {: XOP2( OP_SUB, R_R(Rm), R_R(Rn) ); XOP1CC( OP_ST, CC_OV, R_T ); :}
4.451 +SUBC Rm, Rn {: XOP1SCC( OP_LD, CC_C, R_T ); XOP2SS( OP_SUBBS, R_R(Rm), R_R(Rn) ); XOP1SCC( OP_ST, CC_C, R_T ); :}
4.452 +SUBV Rm, Rn {: XOP2SS( OP_SUB, R_R(Rm), R_R(Rn) ); XOP1SCC( OP_ST, CC_OV, R_T ); :}
4.453 SWAP.B Rm, Rn {:
4.454 if( Rm != Rn ) {
4.455 - XOP2( OP_MOV, R_R(Rm), R_R(Rn) );
4.456 + XOP2SS( OP_MOV, R_R(Rm), R_R(Rn) );
4.457 }
4.458 - XOP2I( OP_SHUFFLE, 0x1243, R_R(Rn) );
4.459 + XOP2IS( OP_SHUFFLE, 0x1243, R_R(Rn) );
4.460 :}
4.461 SWAP.W Rm, Rn {:
4.462 if( Rm != Rn ) {
4.463 - XOP2( OP_MOV, R_R(Rm), R_R(Rn) );
4.464 + XOP2SS( OP_MOV, R_R(Rm), R_R(Rn) );
4.465 }
4.466 - XOP2I( OP_SHUFFLE, 0x3412, R_R(Rn) );
4.467 + XOP2IS( OP_SHUFFLE, 0x3412, R_R(Rn) );
4.468 :}
4.469 -TST Rm, Rn {: XOP2( OP_TST, R_R(Rm), R_R(Rn) ); XOP1CC( OP_ST, CC_EQ, R_T ); :}
4.470 -TST #imm, R0 {: XOP2I( OP_TST, imm, R_R0 ); XOP1CC( OP_ST, CC_EQ, R_T ); :}
4.471 +TST Rm, Rn {: XOP2SS( OP_TST, R_R(Rm), R_R(Rn) ); XOP1SCC( OP_ST, CC_EQ, R_T ); :}
4.472 +TST #imm, R0 {: XOP2IS( OP_TST, imm, R_R0 ); XOP1SCC( OP_ST, CC_EQ, R_T ); :}
4.473 XOR Rm, Rn {:
4.474 if( Rm == Rn ) {
4.475 /* Break false dependence */
4.476 - XOP2I( OP_MOV, 0, R_R(Rn) );
4.477 + XOP2IS( OP_MOV, 0, R_R(Rn) );
4.478 } else {
4.479 - XOP2( OP_XOR, R_R(Rm), R_R(Rn) );
4.480 + XOP2SS( OP_XOR, R_R(Rm), R_R(Rn) );
4.481 }
4.482 :}
4.483 -XOR #imm, R0 {: XOP2I( OP_XOR, imm, R_R0 ); :}
4.484 +XOR #imm, R0 {: XOP2IS( OP_XOR, imm, R_R0 ); :}
4.485 XTRCT Rm, Rn {:
4.486 - XOP2( OP_MOV, R_R(Rm), REG_TMP0 );
4.487 - XOP2I( OP_SLL, 16, REG_TMP0 );
4.488 - XOP2I( OP_SLR, 16, R_R(Rn) );
4.489 - XOP2( OP_OR, REG_TMP0, R_R(Rn) );
4.490 + XOP2ST( OP_MOV, R_R(Rm), REG_TMP0 );
4.491 + XOP2IT( OP_SLL, 16, REG_TMP0 );
4.492 + XOP2IS( OP_SLR, 16, R_R(Rn) );
4.493 + XOP2TS( OP_OR, REG_TMP0, R_R(Rn) );
4.494 :}
4.495 -MOV Rm, Rn {: XOP2( OP_MOV, R_R(Rm), R_R(Rn) ); :}
4.496 -MOV #imm, Rn {: XOP2I( OP_MOV, imm, R_R(Rn) ); :}
4.497 +MOV Rm, Rn {: XOP2SS( OP_MOV, R_R(Rm), R_R(Rn) ); :}
4.498 +MOV #imm, Rn {: XOP2IS( OP_MOV, imm, R_R(Rn) ); :}
4.499
4.500 AND.B #imm, @(R0, GBR) {:
4.501 - XOP2( OP_MOV, R_R0, REG_TMP0 );
4.502 - XOP2( OP_ADD, R_GBR, REG_TMP0 );
4.503 - XOP2E( OP_LOADBFW, REG_TMP0, REG_TMP1 );
4.504 - XOP2I( OP_AND, imm, REG_TMP1 );
4.505 - XOP2E( OP_STOREB, REG_TMP0, REG_TMP1 );
4.506 + XOP2ST( OP_MOV, R_R0, REG_TMP0 );
4.507 + XOP2ST( OP_ADD, R_GBR, REG_TMP0 );
4.508 + XOP2TTE( OP_LOADBFW, REG_TMP0, REG_TMP1 );
4.509 + XOP2IT( OP_AND, imm, REG_TMP1 );
4.510 + XOP2TTE( OP_STOREB, REG_TMP0, REG_TMP1 );
4.511 :}
4.512 OR.B #imm, @(R0, GBR) {:
4.513 - XOP2( OP_MOV, R_R0, REG_TMP0 );
4.514 - XOP2( OP_ADD, R_GBR, REG_TMP0 );
4.515 - XOP2E( OP_LOADBFW, REG_TMP0, REG_TMP1 );
4.516 - XOP2I( OP_OR, imm, REG_TMP1 );
4.517 - XOP2E( OP_STOREB, REG_TMP0, REG_TMP1 );
4.518 + XOP2ST( OP_MOV, R_R0, REG_TMP0 );
4.519 + XOP2ST( OP_ADD, R_GBR, REG_TMP0 );
4.520 + XOP2TTE( OP_LOADBFW, REG_TMP0, REG_TMP1 );
4.521 + XOP2IT( OP_OR, imm, REG_TMP1 );
4.522 + XOP2TTE( OP_STOREB, REG_TMP0, REG_TMP1 );
4.523 :}
4.524 TAS.B @Rn {:
4.525 - XOP1( OP_OCBP, R_R(Rn) );
4.526 - XOP2E( OP_LOADBFW, R_R(Rn), REG_TMP0 );
4.527 - XOP2I( OP_CMP, 0, REG_TMP0 );
4.528 - XOP1CC(OP_ST, CC_EQ, R_T );
4.529 - XOP2I( OP_OR, 0x80, REG_TMP0 );
4.530 - XOP2E( OP_STOREB, R_R(Rn), REG_TMP0 );
4.531 + XOP1S( OP_OCBP, R_R(Rn) );
4.532 + XOP2STE( OP_LOADBFW, R_R(Rn), REG_TMP0 );
4.533 + XOP2IT( OP_CMP, 0, REG_TMP0 );
4.534 + XOP1SCC(OP_ST, CC_EQ, R_T );
4.535 + XOP2IT( OP_OR, 0x80, REG_TMP0 );
4.536 + XOP2STE( OP_STOREB, R_R(Rn), REG_TMP0 );
4.537 :}
4.538 TST.B #imm, @(R0, GBR) {:
4.539 - XOP2( OP_MOV, R_R0, REG_TMP0 );
4.540 - XOP2( OP_ADD, R_GBR, REG_TMP0 );
4.541 - XOP2E( OP_LOADB, REG_TMP0, REG_TMP0 );
4.542 - XOP2I( OP_TST, imm, REG_TMP0 );
4.543 + XOP2ST( OP_MOV, R_R0, REG_TMP0 );
4.544 + XOP2ST( OP_ADD, R_GBR, REG_TMP0 );
4.545 + XOP2TTE( OP_LOADB, REG_TMP0, REG_TMP0 );
4.546 + XOP2IT( OP_TST, imm, REG_TMP0 );
4.547 :}
4.548 XOR.B #imm, @(R0, GBR) {:
4.549 - XOP2( OP_MOV, R_R0, REG_TMP0 );
4.550 - XOP2( OP_ADD, R_GBR, REG_TMP0 );
4.551 - XOP2E( OP_LOADBFW, REG_TMP0, REG_TMP1 );
4.552 - XOP2I( OP_XOR, imm, REG_TMP1 );
4.553 - XOP2E( OP_STOREB, REG_TMP0, REG_TMP1 );
4.554 + XOP2ST( OP_MOV, R_R0, REG_TMP0 );
4.555 + XOP2ST( OP_ADD, R_GBR, REG_TMP0 );
4.556 + XOP2TTE( OP_LOADBFW, REG_TMP0, REG_TMP1 );
4.557 + XOP2IT( OP_XOR, imm, REG_TMP1 );
4.558 + XOP2TTE( OP_STOREB, REG_TMP0, REG_TMP1 );
4.559 :}
4.560
4.561 MOV.B Rm, @Rn {:
4.562 - XOP2E( OP_STOREB, R_R(Rn), R_R(Rm) );
4.563 + XOP2SSE( OP_STOREB, R_R(Rn), R_R(Rm) );
4.564 :}
4.565 MOV.B Rm, @-Rn {:
4.566 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
4.567 - XOP2I( OP_ADD, -1, REG_TMP0 );
4.568 - XOP2E( OP_STOREB, REG_TMP0, R_R(Rm) );
4.569 - XOP2I( OP_ADD, -1, R_R(Rn) );
4.570 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
4.571 + XOP2IT( OP_ADD, -1, REG_TMP0 );
4.572 + XOP2TSE( OP_STOREB, REG_TMP0, R_R(Rm) );
4.573 + XOP2IS( OP_ADD, -1, R_R(Rn) );
4.574 :}
4.575 MOV.B Rm, @(R0, Rn) {:
4.576 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
4.577 - XOP2( OP_ADD, R_R0, REG_TMP0 );
4.578 - XOP2E( OP_STOREB, REG_TMP0, R_R(Rm) );
4.579 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
4.580 + XOP2ST( OP_ADD, R_R0, REG_TMP0 );
4.581 + XOP2TSE( OP_STOREB, REG_TMP0, R_R(Rm) );
4.582 :}
4.583 MOV.B R0, @(disp, GBR) {:
4.584 - XOP2( OP_MOV, R_GBR, REG_TMP0 );
4.585 - XOP2I( OP_ADD, disp, REG_TMP0 );
4.586 - XOP2E( OP_STOREB, REG_TMP0, R_R0 );
4.587 + XOP2ST( OP_MOV, R_GBR, REG_TMP0 );
4.588 + XOP2IT( OP_ADD, disp, REG_TMP0 );
4.589 + XOP2TSE( OP_STOREB, REG_TMP0, R_R0 );
4.590 :}
4.591 MOV.B R0, @(disp, Rn) {:
4.592 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
4.593 - XOP2I( OP_ADD, disp, REG_TMP0 );
4.594 - XOP2E( OP_STOREB, REG_TMP0, R_R0 );
4.595 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
4.596 + XOP2IT( OP_ADD, disp, REG_TMP0 );
4.597 + XOP2TSE( OP_STOREB, REG_TMP0, R_R0 );
4.598 :}
4.599 MOV.B @Rm, Rn {:
4.600 - XOP2E( OP_LOADB, R_R(Rm), R_R(Rn) );
4.601 + XOP2SSE( OP_LOADB, R_R(Rm), R_R(Rn) );
4.602 :}
4.603 MOV.B @Rm+, Rn {:
4.604 - XOP2E( OP_LOADB, R_R(Rm), R_R(Rn) );
4.605 + XOP2SSE( OP_LOADB, R_R(Rm), R_R(Rn) );
4.606 if( Rm != Rn ) {
4.607 - XOP2I( OP_ADD, 1, R_R(Rm) );
4.608 + XOP2IS( OP_ADD, 1, R_R(Rm) );
4.609 }
4.610 :}
4.611 MOV.B @(R0, Rm), Rn {:
4.612 - XOP2( OP_MOV, R_R(Rm), REG_TMP0 );
4.613 - XOP2( OP_ADD, R_R0, REG_TMP0 );
4.614 - XOP2E(OP_LOADB, REG_TMP0, R_R(Rn) );
4.615 + XOP2ST( OP_MOV, R_R(Rm), REG_TMP0 );
4.616 + XOP2ST( OP_ADD, R_R0, REG_TMP0 );
4.617 + XOP2TSE(OP_LOADB, REG_TMP0, R_R(Rn) );
4.618 :}
4.619 MOV.B @(disp, GBR), R0 {:
4.620 - XOP2( OP_MOV, R_GBR, REG_TMP0 );
4.621 - XOP2I(OP_ADD, disp, REG_TMP0 );
4.622 - XOP2E(OP_LOADB, REG_TMP0, R_R0 );
4.623 + XOP2ST( OP_MOV, R_GBR, REG_TMP0 );
4.624 + XOP2IT(OP_ADD, disp, REG_TMP0 );
4.625 + XOP2TSE(OP_LOADB, REG_TMP0, R_R0 );
4.626 :}
4.627 MOV.B @(disp, Rm), R0 {:
4.628 - XOP2( OP_MOV, R_R(Rm), REG_TMP0 );
4.629 - XOP2I(OP_ADD, disp, REG_TMP0 );
4.630 - XOP2E(OP_LOADB, REG_TMP0, R_R0 );
4.631 + XOP2ST( OP_MOV, R_R(Rm), REG_TMP0 );
4.632 + XOP2IT(OP_ADD, disp, REG_TMP0 );
4.633 + XOP2TSE(OP_LOADB, REG_TMP0, R_R0 );
4.634 :}
4.635 MOV.L Rm, @Rn {:
4.636 WALIGN32( R_R(Rn) );
4.637 - XOP2E( OP_STOREL, R_R(Rn), R_R(Rm) );
4.638 + XOP2SSE( OP_STOREL, R_R(Rn), R_R(Rm) );
4.639 :}
4.640 MOV.L Rm, @-Rn {:
4.641 WALIGN32( R_R(Rn) );
4.642 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
4.643 - XOP2I(OP_ADD, -4, REG_TMP0 );
4.644 - XOP2( OP_STOREL, REG_TMP0, R_R(Rm) );
4.645 - XOP2I(OP_ADD, -4, R_R(Rn) );
4.646 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
4.647 + XOP2IT(OP_ADD, -4, REG_TMP0 );
4.648 + XOP2TS( OP_STOREL, REG_TMP0, R_R(Rm) );
4.649 + XOP2IS(OP_ADD, -4, R_R(Rn) );
4.650 :}
4.651 MOV.L Rm, @(R0, Rn) {:
4.652 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
4.653 - XOP2( OP_ADD, R_R0, REG_TMP0 );
4.654 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
4.655 + XOP2ST( OP_ADD, R_R0, REG_TMP0 );
4.656 WALIGN32( REG_TMP0 );
4.657 - XOP2E(OP_STOREL, REG_TMP0, R_R(Rm) );
4.658 + XOP2TSE(OP_STOREL, REG_TMP0, R_R(Rm) );
4.659 :}
4.660 MOV.L R0, @(disp, GBR) {:
4.661 - XOP2( OP_MOV, R_GBR, REG_TMP0 );
4.662 - XOP2I(OP_ADD, disp, REG_TMP0 );
4.663 + XOP2ST( OP_MOV, R_GBR, REG_TMP0 );
4.664 + XOP2IT(OP_ADD, disp, REG_TMP0 );
4.665 WALIGN32( REG_TMP0 );
4.666 - XOP2E(OP_STOREL, REG_TMP0, R_R0 );
4.667 + XOP2TSE(OP_STOREL, REG_TMP0, R_R0 );
4.668 :}
4.669 MOV.L Rm, @(disp, Rn) {:
4.670 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
4.671 - XOP2I(OP_ADD, disp, REG_TMP0 );
4.672 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
4.673 + XOP2IT(OP_ADD, disp, REG_TMP0 );
4.674 WALIGN32( REG_TMP0 );
4.675 - XOP2E(OP_STOREL, REG_TMP0, R_R(Rm) );
4.676 + XOP2TSE(OP_STOREL, REG_TMP0, R_R(Rm) );
4.677 :}
4.678 MOV.L @Rm, Rn {:
4.679 RALIGN32( R_R(Rm) );
4.680 - XOP2E(OP_LOADL, R_R(Rm), R_R(Rn) );
4.681 + XOP2SSE(OP_LOADL, R_R(Rm), R_R(Rn) );
4.682 :}
4.683 MOV.L @Rm+, Rn {:
4.684 RALIGN32( R_R(Rm) );
4.685 - XOP2E( OP_LOADL, R_R(Rm), R_R(Rn) );
4.686 + XOP2SSE( OP_LOADL, R_R(Rm), R_R(Rn) );
4.687 if( R_R(Rm) != R_R(Rn) ) {
4.688 - XOP2I( OP_ADD, 4, R_R(Rm) );
4.689 + XOP2IS( OP_ADD, 4, R_R(Rm) );
4.690 }
4.691 :}
4.692 MOV.L @(R0, Rm), Rn {:
4.693 - XOP2( OP_MOV, R_R0, REG_TMP0 );
4.694 - XOP2( OP_ADD, R_R(Rm), REG_TMP0 );
4.695 + XOP2ST( OP_MOV, R_R0, REG_TMP0 );
4.696 + XOP2ST( OP_ADD, R_R(Rm), REG_TMP0 );
4.697 RALIGN32( REG_TMP0 );
4.698 - XOP2E(OP_LOADL, REG_TMP0, R_R(Rn) );
4.699 + XOP2TSE(OP_LOADL, REG_TMP0, R_R(Rn) );
4.700 :}
4.701 MOV.L @(disp, GBR), R0 {:
4.702 - XOP2( OP_MOV, R_GBR, REG_TMP0 );
4.703 - XOP2I(OP_ADD, disp, REG_TMP0 );
4.704 + XOP2ST( OP_MOV, R_GBR, REG_TMP0 );
4.705 + XOP2IT(OP_ADD, disp, REG_TMP0 );
4.706 RALIGN32( REG_TMP0 );
4.707 - XOP2E(OP_LOADL, REG_TMP0, R_R0 );
4.708 + XOP2TSE(OP_LOADL, REG_TMP0, R_R0 );
4.709 :}
4.710 MOV.L @(disp, PC), Rn {:
4.711 if( in_delay_slot ) {
4.712 @@ -520,74 +558,74 @@
4.713 // behaviour to confirm) Unlikely to be anyone depending on this
4.714 // behaviour though.
4.715 sh4ptr_t ptr = GET_ICACHE_PTR(target);
4.716 - XOP2P( OP_MOV, ptr, R_R(Rn) );
4.717 + XOP2PS( OP_LOADPTRL, ptr, R_R(Rn) );
4.718 } else {
4.719 // Note: we use sh4r.pc for the calc as we could be running at a
4.720 // different virtual address than the translation was done with,
4.721 // but we can safely assume that the low bits are the same.
4.722 - XOP2( OP_MOV, R_PC, REG_TMP0 );
4.723 - XOP2( OP_ADD, (pc-xbb->pc_begin) + disp + 4 - (pc&0x03), REG_TMP0 );
4.724 - XOP2E(OP_LOADL, REG_TMP0, R_R(Rn) );
4.725 + XOP2ST( OP_MOV, R_PC, REG_TMP0 );
4.726 + XOP2IT( OP_ADD, (pc-xbb->pc_begin) + disp + 4 - (pc&0x03), REG_TMP0 );
4.727 + XOP2TSE(OP_LOADL, REG_TMP0, R_R(Rn) );
4.728 }
4.729 }
4.730 :}
4.731 MOV.L @(disp, Rm), Rn {:
4.732 - XOP2( OP_MOV, R_R(Rm), REG_TMP0 );
4.733 - XOP2I(OP_ADD, disp, REG_TMP0 );
4.734 + XOP2ST( OP_MOV, R_R(Rm), REG_TMP0 );
4.735 + XOP2IT(OP_ADD, disp, REG_TMP0 );
4.736 RALIGN32( REG_TMP0 );
4.737 - XOP2E(OP_LOADL, REG_TMP0, R_R(Rn) );
4.738 + XOP2TSE(OP_LOADL, REG_TMP0, R_R(Rn) );
4.739 :}
4.740 MOV.W Rm, @Rn {:
4.741 WALIGN16( R_R(Rn) );
4.742 - XOP2E(OP_STOREW, R_R(Rn), R_R(Rm) );
4.743 + XOP2SSE(OP_STOREW, R_R(Rn), R_R(Rm) );
4.744 :}
4.745 MOV.W Rm, @-Rn {:
4.746 WALIGN16( R_R(Rn) );
4.747 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
4.748 - XOP2I(OP_ADD, -2, REG_TMP0 );
4.749 - XOP2E(OP_STOREW, REG_TMP0, R_R(Rm) );
4.750 - XOP2I(OP_ADD, -2, R_R(Rn) );
4.751 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
4.752 + XOP2IT(OP_ADD, -2, REG_TMP0 );
4.753 + XOP2TSE(OP_STOREW, REG_TMP0, R_R(Rm) );
4.754 + XOP2IS(OP_ADD, -2, R_R(Rn) );
4.755 :}
4.756 MOV.W Rm, @(R0, Rn) {:
4.757 - XOP2( OP_MOV, R_R0, REG_TMP0 );
4.758 - XOP2( OP_ADD, R_R(Rn), REG_TMP0 );
4.759 + XOP2ST( OP_MOV, R_R0, REG_TMP0 );
4.760 + XOP2ST( OP_ADD, R_R(Rn), REG_TMP0 );
4.761 WALIGN16( REG_TMP0 );
4.762 - XOP2E(OP_STOREW, REG_TMP0, R_R(Rm) );
4.763 + XOP2TSE(OP_STOREW, REG_TMP0, R_R(Rm) );
4.764 :}
4.765 MOV.W R0, @(disp, GBR) {:
4.766 - XOP2( OP_MOV, R_GBR, REG_TMP0 );
4.767 - XOP2I(OP_ADD, disp, REG_TMP0 );
4.768 + XOP2ST( OP_MOV, R_GBR, REG_TMP0 );
4.769 + XOP2IT(OP_ADD, disp, REG_TMP0 );
4.770 WALIGN16( REG_TMP0 );
4.771 - XOP2( OP_STOREW, REG_TMP0, R_R0 );
4.772 + XOP2TS( OP_STOREW, REG_TMP0, R_R0 );
4.773 :}
4.774 MOV.W R0, @(disp, Rn) {:
4.775 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
4.776 - XOP2I(OP_ADD, disp, REG_TMP0 );
4.777 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
4.778 + XOP2IT(OP_ADD, disp, REG_TMP0 );
4.779 WALIGN16( REG_TMP0 );
4.780 - XOP2E(OP_STOREW, REG_TMP0, R_R0 );
4.781 + XOP2TSE(OP_STOREW, REG_TMP0, R_R0 );
4.782 :}
4.783 MOV.W @Rm, Rn {:
4.784 RALIGN16( R_R(Rm) );
4.785 - XOP2E(OP_LOADW, R_R(Rm), R_R(Rn) );
4.786 + XOP2SSE(OP_LOADW, R_R(Rm), R_R(Rn) );
4.787 :}
4.788 MOV.W @Rm+, Rn {:
4.789 RALIGN16( R_R(Rm) );
4.790 - XOP2E(OP_LOADW, R_R(Rm), R_R(Rn) );
4.791 + XOP2SSE(OP_LOADW, R_R(Rm), R_R(Rn) );
4.792 if( Rm != Rn ) {
4.793 - XOP2I( OP_ADD, 2, R_R(Rm) );
4.794 + XOP2IS( OP_ADD, 2, R_R(Rm) );
4.795 }
4.796 :}
4.797 MOV.W @(R0, Rm), Rn {:
4.798 - XOP2( OP_MOV, R_R0, REG_TMP0 );
4.799 - XOP2( OP_ADD, R_R(Rm), REG_TMP0 );
4.800 + XOP2ST( OP_MOV, R_R0, REG_TMP0 );
4.801 + XOP2ST( OP_ADD, R_R(Rm), REG_TMP0 );
4.802 RALIGN16( REG_TMP0 );
4.803 - XOP2E(OP_LOADW, REG_TMP0, R_R(Rn) );
4.804 + XOP2TSE(OP_LOADW, REG_TMP0, R_R(Rn) );
4.805 :}
4.806 MOV.W @(disp, GBR), R0 {:
4.807 - XOP2( OP_MOV, R_GBR, REG_TMP0 );
4.808 - XOP2I(OP_ADD, disp, REG_TMP0 );
4.809 + XOP2ST( OP_MOV, R_GBR, REG_TMP0 );
4.810 + XOP2IT(OP_ADD, disp, REG_TMP0 );
4.811 RALIGN16( REG_TMP0 );
4.812 - XOP2E(OP_LOADW, REG_TMP0, R_R0 );
4.813 + XOP2TSE(OP_LOADW, REG_TMP0, R_R0 );
4.814 :}
4.815 MOV.W @(disp, PC), Rn {:
4.816 if( in_delay_slot ) {
4.817 @@ -606,296 +644,296 @@
4.818 // behaviour to confirm) Unlikely to be anyone depending on this
4.819 // behaviour though.
4.820 sh4ptr_t ptr = GET_ICACHE_PTR(target);
4.821 - XOP2P( OP_MOV, ptr, REG_TMP0 );
4.822 - XOP2( OP_MOVSX16, REG_TMP0, R_R(Rn) );
4.823 + XOP2PT( OP_LOADPTRL, ptr, REG_TMP0 );
4.824 + XOP2TS( OP_MOVSX16, REG_TMP0, R_R(Rn) );
4.825 } else {
4.826 // Note: we use sh4r.pc for the calc as we could be running at a
4.827 // different virtual address than the translation was done with,
4.828 // but we can safely assume that the low bits are the same.
4.829 - XOP2( OP_MOV, R_PC, REG_TMP0 );
4.830 - XOP2( OP_ADD, (pc - xbb->pc_begin) + disp + 4, REG_TMP0 );
4.831 - XOP2E(OP_LOADW, REG_TMP0, R_R(Rn) );
4.832 + XOP2ST( OP_MOV, R_PC, REG_TMP0 );
4.833 + XOP2IT( OP_ADD, (pc - xbb->pc_begin) + disp + 4, REG_TMP0 );
4.834 + XOP2TSE(OP_LOADW, REG_TMP0, R_R(Rn) );
4.835 }
4.836 }
4.837 :}
4.838 MOV.W @(disp, Rm), R0 {:
4.839 - XOP2( OP_MOV, R_R(Rm), REG_TMP0 );
4.840 - XOP2I(OP_ADD, disp, REG_TMP0 );
4.841 + XOP2ST( OP_MOV, R_R(Rm), REG_TMP0 );
4.842 + XOP2IT(OP_ADD, disp, REG_TMP0 );
4.843 RALIGN16( REG_TMP0 );
4.844 - XOP2E(OP_LOADW, REG_TMP0, R_R0 );
4.845 + XOP2TSE(OP_LOADW, REG_TMP0, R_R0 );
4.846 :}
4.847 MOVA @(disp, PC), R0 {:
4.848 if( in_delay_slot ) {
4.849 SLOTILLEGAL();
4.850 return 2;
4.851 } else {
4.852 - XOP2( OP_MOV, R_PC, R_R0 );
4.853 - XOP2I( OP_ADD, (pc - xbb->pc_begin) + disp + 4 - (pc&0x03), R_R0 );
4.854 + XOP2SS( OP_MOV, R_PC, R_R0 );
4.855 + XOP2IS( OP_ADD, (pc - xbb->pc_begin) + disp + 4 - (pc&0x03), R_R0 );
4.856 }
4.857 :}
4.858 MOVCA.L R0, @Rn {:
4.859 - XOP2E(OP_STORELCA, R_R(Rn), R_R0 );
4.860 + XOP2SSE(OP_STORELCA, R_R(Rn), R_R0 );
4.861 :}
4.862 LDTLB {:
4.863 CHECKPRIV();
4.864 XOPCALL0( MMU_ldtlb );
4.865 :}
4.866 -OCBI @Rn {: XOP1E( OP_OCBI, R_R(Rn) ); :}
4.867 -OCBP @Rn {: XOP1E( OP_OCBP, R_R(Rn) ); :}
4.868 -OCBWB @Rn {: XOP1E( OP_OCBWB, R_R(Rn) ); :}
4.869 -PREF @Rn {: XOP1E( OP_PREF, R_R(Rn) ); :}
4.870 +OCBI @Rn {: XOP1SE( OP_OCBI, R_R(Rn) ); :}
4.871 +OCBP @Rn {: XOP1SE( OP_OCBP, R_R(Rn) ); :}
4.872 +OCBWB @Rn {: XOP1SE( OP_OCBWB, R_R(Rn) ); :}
4.873 +PREF @Rn {: XOP1SE( OP_PREF, R_R(Rn) ); :}
4.874
4.875 CLRMAC {:
4.876 - XOP2I( OP_MOV, 0, R_MACL );
4.877 - XOP2I( OP_MOV, 0, R_MACH );
4.878 + XOP2IS( OP_MOV, 0, R_MACL );
4.879 + XOP2IS( OP_MOV, 0, R_MACH );
4.880 :}
4.881 -CLRS {: XOP2I( OP_MOV, 0, R_S ); :}
4.882 -CLRT {: XOP2I( OP_MOV, 0, R_T ); :}
4.883 -SETS {: XOP2I( OP_MOV, 1, R_S ); :}
4.884 -SETT {: XOP2I( OP_MOV, 1, R_T ); :}
4.885 +CLRS {: XOP2IS( OP_MOV, 0, R_S ); :}
4.886 +CLRT {: XOP2IS( OP_MOV, 0, R_T ); :}
4.887 +SETS {: XOP2IS( OP_MOV, 1, R_S ); :}
4.888 +SETT {: XOP2IS( OP_MOV, 1, R_T ); :}
4.889 FMOV FRm, FRn {:
4.890 CHECKFPUEN();
4.891 if( sh4_xir.double_size ) {
4.892 - XOP2( OP_MOVQ, (FRm&1) ? R_XD(FRm) : R_DR(FRm), (FRn&1) ? R_XD(FRn) : R_DR(FRn) );
4.893 + XOP2SS( OP_MOVQ, (FRm&1) ? R_XD(FRm) : R_DR(FRm), (FRn&1) ? R_XD(FRn) : R_DR(FRn) );
4.894 } else {
4.895 - XOP2( OP_MOV, R_FR(FRm), R_FR(FRn) );
4.896 + XOP2SS( OP_MOV, R_FR(FRm), R_FR(FRn) );
4.897 }
4.898 :}
4.899 FMOV FRm, @Rn {:
4.900 CHECKFPUEN();
4.901 if( sh4_xir.double_size ) {
4.902 WALIGN64( R_R(Rn) );
4.903 - XOP2E( OP_STOREQ, R_R(Rn), (FRm&1) ? R_XD(FRm) : R_DR(FRm) );
4.904 + XOP2SSE( OP_STOREQ, R_R(Rn), (FRm&1) ? R_XD(FRm) : R_DR(FRm) );
4.905 } else {
4.906 WALIGN32( R_R(Rn) );
4.907 - XOP2E( OP_STOREL, R_R(Rn), R_FR(FRm) );
4.908 + XOP2SSE( OP_STOREL, R_R(Rn), R_FR(FRm) );
4.909 }
4.910 :}
4.911 FMOV @Rm, FRn {:
4.912 CHECKFPUEN();
4.913 if( sh4_xir.double_size ) {
4.914 RALIGN64( R_R(Rm) );
4.915 - XOP2E( OP_LOADQ, R_R(Rm), (FRn&1) ? R_XD(FRn) : R_DR(FRn) );
4.916 + XOP2SSE( OP_LOADQ, R_R(Rm), (FRn&1) ? R_XD(FRn) : R_DR(FRn) );
4.917 } else {
4.918 RALIGN32( R_R(Rm) );
4.919 - XOP2E( OP_LOADL, R_R(Rm), R_FR(FRn) );
4.920 + XOP2SSE( OP_LOADL, R_R(Rm), R_FR(FRn) );
4.921 }
4.922 :}
4.923 FMOV FRm, @-Rn {:
4.924 CHECKFPUEN();
4.925 if( sh4_xir.double_size ) {
4.926 WALIGN64( R_R(Rn) );
4.927 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
4.928 - XOP2I(OP_ADD, -8, REG_TMP0 );
4.929 - XOP2E(OP_STOREQ, REG_TMP0, (FRm&1) ? R_XD(FRm) : R_DR(FRm) );
4.930 - XOP2I(OP_ADD, -8, R_R(Rn) );
4.931 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
4.932 + XOP2IT(OP_ADD, -8, REG_TMP0 );
4.933 + XOP2TSE(OP_STOREQ, REG_TMP0, (FRm&1) ? R_XD(FRm) : R_DR(FRm) );
4.934 + XOP2IS(OP_ADD, -8, R_R(Rn) );
4.935 } else {
4.936 WALIGN32( R_R(Rn) );
4.937 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
4.938 - XOP2I(OP_ADD, -4, REG_TMP0 );
4.939 - XOP2E(OP_STOREL, REG_TMP0, R_FR(FRm) );
4.940 - XOP2I(OP_ADD, -4, R_R(Rn) );
4.941 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
4.942 + XOP2IT(OP_ADD, -4, REG_TMP0 );
4.943 + XOP2TSE(OP_STOREL, REG_TMP0, R_FR(FRm) );
4.944 + XOP2IS(OP_ADD, -4, R_R(Rn) );
4.945 }
4.946 :}
4.947 FMOV @Rm+, FRn {:
4.948 CHECKFPUEN();
4.949 if( sh4_xir.double_size ) {
4.950 RALIGN64( R_R(Rm) );
4.951 - XOP2( OP_LOADQ, R_R(Rm), (FRn&1) ? R_XD(FRn) : R_DR(FRn) );
4.952 - XOP2I( OP_ADD, 8, R_R(Rm) );
4.953 + XOP2SSE( OP_LOADQ, R_R(Rm), (FRn&1) ? R_XD(FRn) : R_DR(FRn) );
4.954 + XOP2IS( OP_ADD, 8, R_R(Rm) );
4.955 } else {
4.956 RALIGN32( R_R(Rm) );
4.957 - XOP2( OP_LOADL, R_R(Rm), R_FR(FRn) );
4.958 - XOP2I( OP_ADD, 4, R_R(Rm) );
4.959 + XOP2SSE( OP_LOADL, R_R(Rm), R_FR(FRn) );
4.960 + XOP2IS( OP_ADD, 4, R_R(Rm) );
4.961 }
4.962 :}
4.963 FMOV FRm, @(R0, Rn) {:
4.964 CHECKFPUEN();
4.965 - XOP2( OP_MOV, R_R0, REG_TMP0 );
4.966 - XOP2( OP_ADD, R_R(Rn), REG_TMP0 );
4.967 + XOP2ST( OP_MOV, R_R0, REG_TMP0 );
4.968 + XOP2ST( OP_ADD, R_R(Rn), REG_TMP0 );
4.969 if( sh4_xir.double_size ) {
4.970 WALIGN64( REG_TMP0 );
4.971 - XOP2E( OP_STOREQ, REG_TMP0, (FRm&1) ? R_XD(FRm) : R_DR(FRm) );
4.972 + XOP2TSE( OP_STOREQ, REG_TMP0, (FRm&1) ? R_XD(FRm) : R_DR(FRm) );
4.973 } else {
4.974 WALIGN32( REG_TMP0 );
4.975 - XOP2E( OP_STOREL, REG_TMP0, R_FR(FRm) );
4.976 + XOP2TSE( OP_STOREL, REG_TMP0, R_FR(FRm) );
4.977 }
4.978 :}
4.979 FMOV @(R0, Rm), FRn {:
4.980 CHECKFPUEN();
4.981 - XOP2( OP_MOV, R_R0, REG_TMP0 );
4.982 - XOP2( OP_ADD, R_R(Rm), REG_TMP0 );
4.983 + XOP2ST( OP_MOV, R_R0, REG_TMP0 );
4.984 + XOP2ST( OP_ADD, R_R(Rm), REG_TMP0 );
4.985 if( sh4_xir.double_size ) {
4.986 RALIGN64( REG_TMP0 );
4.987 - XOP2E( OP_LOADQ, REG_TMP0, (FRn&1) ? R_XD(FRn) : R_DR(FRn) );
4.988 + XOP2TSE( OP_LOADQ, REG_TMP0, (FRn&1) ? R_XD(FRn) : R_DR(FRn) );
4.989 } else {
4.990 RALIGN32( REG_TMP0 );
4.991 - XOP2E( OP_LOADL, REG_TMP0, R_FR(FRn) );
4.992 + XOP2TSE( OP_LOADL, REG_TMP0, R_FR(FRn) );
4.993 }
4.994 :}
4.995 FLDI0 FRn {: /* IFF PR=0 */
4.996 CHECKFPUEN();
4.997 if( sh4_xir.double_prec == 0 ) {
4.998 - XOP2F( OP_MOV, 0.0, R_FR(FRn) );
4.999 + XOP2FS( OP_MOV, 0.0, R_FR(FRn) );
4.1000 }
4.1001 :}
4.1002 FLDI1 FRn {: /* IFF PR=0 */
4.1003 CHECKFPUEN();
4.1004 if( sh4_xir.double_prec == 0 ) {
4.1005 - XOP2F( OP_MOV, 1.0, R_FR(FRn) );
4.1006 + XOP2FS( OP_MOV, 1.0, R_FR(FRn) );
4.1007 }
4.1008 :}
4.1009 FLOAT FPUL, FRn {:
4.1010 CHECKFPUEN();
4.1011 if( sh4_xir.double_prec ) {
4.1012 - XOP2( OP_ITOD, R_FPUL, R_DR(FRn) );
4.1013 + XOP2SS( OP_ITOD, R_FPUL, R_DR(FRn) );
4.1014 } else {
4.1015 - XOP2( OP_ITOF, R_FPUL, R_FR(FRn) );
4.1016 + XOP2SS( OP_ITOF, R_FPUL, R_FR(FRn) );
4.1017 }
4.1018 :}
4.1019 FTRC FRm, FPUL {:
4.1020 CHECKFPUEN();
4.1021 if( sh4_xir.double_prec ) {
4.1022 - XOP2( OP_DTOI, R_DR(FRm), R_FPUL );
4.1023 + XOP2SS( OP_DTOI, R_DR(FRm), R_FPUL );
4.1024 } else {
4.1025 - XOP2( OP_FTOI, R_FR(FRm), R_FPUL );
4.1026 + XOP2SS( OP_FTOI, R_FR(FRm), R_FPUL );
4.1027 }
4.1028 :}
4.1029 FLDS FRm, FPUL {:
4.1030 CHECKFPUEN();
4.1031 - XOP2( OP_MOV, R_FR(FRm), R_FPUL );
4.1032 + XOP2SS( OP_MOV, R_FR(FRm), R_FPUL );
4.1033 :}
4.1034 FSTS FPUL, FRn {:
4.1035 CHECKFPUEN();
4.1036 - XOP2( OP_MOV, R_FPUL, R_FR(FRn) );
4.1037 + XOP2SS( OP_MOV, R_FPUL, R_FR(FRn) );
4.1038 :}
4.1039 FCNVDS FRm, FPUL {:
4.1040 CHECKFPUEN();
4.1041 if( sh4_xir.double_prec && !sh4_xir.double_size ) {
4.1042 - XOP2( OP_DTOF, R_DR(FRm), R_FPUL );
4.1043 + XOP2SS( OP_DTOF, R_DR(FRm), R_FPUL );
4.1044 }
4.1045 :}
4.1046 FCNVSD FPUL, FRn {:
4.1047 CHECKFPUEN();
4.1048 if( sh4_xir.double_prec && !sh4_xir.double_size ) {
4.1049 - XOP2( OP_FTOD, R_FPUL, R_DR(FRn) );
4.1050 + XOP2SS( OP_FTOD, R_FPUL, R_DR(FRn) );
4.1051 }
4.1052 :}
4.1053 FABS FRn {:
4.1054 CHECKFPUEN();
4.1055 if( sh4_xir.double_prec ) {
4.1056 - XOP1( OP_ABSD, R_DR(FRn) );
4.1057 + XOP2SS( OP_ABSD, R_DR(FRn), R_DR(FRn) );
4.1058 } else {
4.1059 - XOP1( OP_ABSF, R_FR(FRn) );
4.1060 + XOP2SS( OP_ABSF, R_FR(FRn), R_FR(FRn) );
4.1061 }
4.1062 :}
4.1063 FADD FRm, FRn {:
4.1064 CHECKFPUEN();
4.1065 if( sh4_xir.double_prec ) {
4.1066 - XOP2( OP_ADDD, R_DR(FRm), R_DR(FRn) );
4.1067 + XOP2SS( OP_ADDD, R_DR(FRm), R_DR(FRn) );
4.1068 } else {
4.1069 - XOP2( OP_ADDF, R_FR(FRm), R_FR(FRn) );
4.1070 + XOP2SS( OP_ADDF, R_FR(FRm), R_FR(FRn) );
4.1071 }
4.1072 :}
4.1073 FDIV FRm, FRn {:
4.1074 CHECKFPUEN();
4.1075 if( sh4_xir.double_prec ) {
4.1076 - XOP2( OP_DIVD, R_DR(FRm), R_DR(FRn) );
4.1077 + XOP2SS( OP_DIVD, R_DR(FRm), R_DR(FRn) );
4.1078 } else {
4.1079 - XOP2( OP_DIVF, R_FR(FRm), R_FR(FRn) );
4.1080 + XOP2SS( OP_DIVF, R_FR(FRm), R_FR(FRn) );
4.1081 }
4.1082 :}
4.1083 FMAC FR0, FRm, FRn {:
4.1084 CHECKFPUEN();
4.1085 if( sh4_xir.double_prec == 0 ) {
4.1086 - XOP2( OP_MOV, R_FR(0), REG_TMP0 );
4.1087 - XOP2( OP_MULF, R_FR(FRm), REG_TMP0 );
4.1088 - XOP2( OP_ADDF, REG_TMP0, R_FR(FRn) );
4.1089 + XOP2ST( OP_MOV, R_FR(0), REG_TMP0 );
4.1090 + XOP2ST( OP_MULF, R_FR(FRm), REG_TMP0 );
4.1091 + XOP2TS( OP_ADDF, REG_TMP0, R_FR(FRn) );
4.1092 }
4.1093 :}
4.1094 FMUL FRm, FRn {:
4.1095 CHECKFPUEN();
4.1096 if( sh4_xir.double_prec ) {
4.1097 - XOP2( OP_MULD, R_DR(FRm), R_DR(FRn) );
4.1098 + XOP2SS( OP_MULD, R_DR(FRm), R_DR(FRn) );
4.1099 } else {
4.1100 - XOP2( OP_MULF, R_FR(FRm), R_FR(FRn) );
4.1101 + XOP2SS( OP_MULF, R_FR(FRm), R_FR(FRn) );
4.1102 }
4.1103 :}
4.1104 FNEG FRn {:
4.1105 CHECKFPUEN();
4.1106 if( sh4_xir.double_prec ) {
4.1107 - XOP1( OP_NEGD, R_DR(FRn) );
4.1108 + XOP2SS( OP_NEGD, R_DR(FRn), R_DR(FRn) );
4.1109 } else {
4.1110 - XOP1( OP_NEGF, R_FR(FRn) );
4.1111 + XOP2SS( OP_NEGF, R_FR(FRn), R_FR(FRn) );
4.1112 }
4.1113 :}
4.1114 FSRRA FRn {:
4.1115 CHECKFPUEN();
4.1116 if( sh4_xir.double_prec == 0 ) {
4.1117 - XOP1( OP_RSQRTF, R_FR(FRn) );
4.1118 + XOP2SS( OP_RSQRTF, R_FR(FRn), R_FR(FRn) );
4.1119 }
4.1120 :}
4.1121 FSQRT FRn {:
4.1122 CHECKFPUEN();
4.1123 if( sh4_xir.double_prec ) {
4.1124 - XOP1( OP_SQRTD, R_DR(FRn) );
4.1125 + XOP2SS( OP_SQRTD, R_DR(FRn), R_DR(FRn) );
4.1126 } else {
4.1127 - XOP1( OP_SQRTF, R_FR(FRn) );
4.1128 + XOP2SS( OP_SQRTF, R_FR(FRn), R_FR(FRn) );
4.1129 }
4.1130 :}
4.1131 FSUB FRm, FRn {:
4.1132 CHECKFPUEN();
4.1133 if( sh4_xir.double_prec ) {
4.1134 - XOP2( OP_SUBD, R_DR(FRm), R_DR(FRn) );
4.1135 + XOP2SS( OP_SUBD, R_DR(FRm), R_DR(FRn) );
4.1136 } else {
4.1137 - XOP2( OP_SUBF, R_FR(FRm), R_FR(FRn) );
4.1138 + XOP2SS( OP_SUBF, R_FR(FRm), R_FR(FRn) );
4.1139 }
4.1140 :}
4.1141 FCMP/EQ FRm, FRn {:
4.1142 CHECKFPUEN();
4.1143 if( sh4_xir.double_prec ) {
4.1144 - XOP2( OP_CMPD, R_DR(FRm), R_DR(FRn) );
4.1145 + XOP2SS( OP_CMPD, R_DR(FRm), R_DR(FRn) );
4.1146 } else {
4.1147 - XOP2( OP_CMPF, R_FR(FRm), R_FR(FRn) );
4.1148 + XOP2SS( OP_CMPF, R_FR(FRm), R_FR(FRn) );
4.1149 }
4.1150 - XOP1CC( OP_ST, CC_EQ, R_T );
4.1151 + XOP1SCC( OP_ST, CC_EQ, R_T );
4.1152 :}
4.1153 FCMP/GT FRm, FRn {:
4.1154 CHECKFPUEN();
4.1155 if( sh4_xir.double_prec ) {
4.1156 - XOP2( OP_CMPD, R_DR(FRm), R_DR(FRn) );
4.1157 + XOP2SS( OP_CMPD, R_DR(FRm), R_DR(FRn) );
4.1158 } else {
4.1159 - XOP2( OP_CMPF, R_FR(FRm), R_FR(FRn) );
4.1160 + XOP2SS( OP_CMPF, R_FR(FRm), R_FR(FRn) );
4.1161 }
4.1162 - XOP1CC( OP_ST, CC_SGT, R_T );
4.1163 + XOP1SCC( OP_ST, CC_SGT, R_T );
4.1164 :}
4.1165 FSCA FPUL, FRn {:
4.1166 CHECKFPUEN();
4.1167 if( sh4_xir.double_prec == 0 ) {
4.1168 - XOP2( OP_SINCOSF, R_FPUL, R_DR(FRn) );
4.1169 + XOP2SS( OP_SINCOSF, R_FPUL, R_DR(FRn) );
4.1170 }
4.1171 :}
4.1172 FIPR FVm, FVn {:
4.1173 CHECKFPUEN();
4.1174 if( sh4_xir.double_prec == 0 ) {
4.1175 - XOP2( OP_DOTPRODV, R_FV(FVm), R_FV(FVn) );
4.1176 + XOP2SS( OP_DOTPRODV, R_FV(FVm), R_FV(FVn) );
4.1177 }
4.1178 :}
4.1179 FTRV XMTRX, FVn {:
4.1180 CHECKFPUEN();
4.1181 if( sh4_xir.double_prec == 0 ) {
4.1182 - XOP2( OP_MATMULV, R_XMTRX, R_FV(FVn) );
4.1183 + XOP2SS( OP_MATMULV, R_XMTRX, R_FV(FVn) );
4.1184 }
4.1185 :}
4.1186 FRCHG {:
4.1187 CHECKFPUEN();
4.1188 - XOP2I( OP_XOR, FPSCR_FR, R_FPSCR );
4.1189 + XOP2IS( OP_XOR, FPSCR_FR, R_FPSCR );
4.1190 XOPCALL0( sh4_switch_fr_banks );
4.1191 :}
4.1192 FSCHG {:
4.1193 CHECKFPUEN();
4.1194 - XOP2I( OP_XOR, FPSCR_SZ, R_FPSCR );
4.1195 - XOP2I( OP_XOR, FPSCR_SZ, R_SH4_MODE );
4.1196 + XOP2IS( OP_XOR, FPSCR_SZ, R_FPSCR );
4.1197 + XOP2IS( OP_XOR, FPSCR_SZ, R_SH4_MODE );
4.1198 sh4_xir.double_size = !sh4_xir.double_size;
4.1199 :}
4.1200 LDC Rm, SR {:
4.1201 @@ -903,20 +941,20 @@
4.1202 SLOTILLEGAL();
4.1203 } else {
4.1204 CHECKPRIV();
4.1205 - XOPCALL1( sh4_write_sr, R_R(Rm) );
4.1206 + XOPCALL1S( sh4_write_sr, R_R(Rm) );
4.1207 }
4.1208 return 2;
4.1209 :}
4.1210 -LDC Rm, GBR {: XOP2( OP_MOV, R_R(Rm), R_GBR ); :}
4.1211 -LDC Rm, VBR {: CHECKPRIV(); XOP2( OP_MOV, R_R(Rm), R_VBR ); :}
4.1212 -LDC Rm, SSR {: CHECKPRIV(); XOP2( OP_MOV, R_R(Rm), R_SSR ); :}
4.1213 -LDC Rm, SGR {: CHECKPRIV(); XOP2( OP_MOV, R_R(Rm), R_SGR ); :}
4.1214 -LDC Rm, SPC {: CHECKPRIV(); XOP2( OP_MOV, R_R(Rm), R_SPC ); :}
4.1215 -LDC Rm, DBR {: CHECKPRIV(); XOP2( OP_MOV, R_R(Rm), R_DBR ); :}
4.1216 -LDC Rm, Rn_BANK {: CHECKPRIV(); XOP2( OP_MOV, R_R(Rm), R_BANK(Rn_BANK) ); :}
4.1217 +LDC Rm, GBR {: XOP2SS( OP_MOV, R_R(Rm), R_GBR ); :}
4.1218 +LDC Rm, VBR {: CHECKPRIV(); XOP2SS( OP_MOV, R_R(Rm), R_VBR ); :}
4.1219 +LDC Rm, SSR {: CHECKPRIV(); XOP2SS( OP_MOV, R_R(Rm), R_SSR ); :}
4.1220 +LDC Rm, SGR {: CHECKPRIV(); XOP2SS( OP_MOV, R_R(Rm), R_SGR ); :}
4.1221 +LDC Rm, SPC {: CHECKPRIV(); XOP2SS( OP_MOV, R_R(Rm), R_SPC ); :}
4.1222 +LDC Rm, DBR {: CHECKPRIV(); XOP2SS( OP_MOV, R_R(Rm), R_DBR ); :}
4.1223 +LDC Rm, Rn_BANK {: CHECKPRIV(); XOP2SS( OP_MOV, R_R(Rm), R_BANK(Rn_BANK) ); :}
4.1224 LDC.L @Rm+, GBR {:
4.1225 - XOP2E( OP_LOADL, R_R(Rm), R_GBR );
4.1226 - XOP2I( OP_ADD, 4, R_R(Rm) );
4.1227 + XOP2SSE( OP_LOADL, R_R(Rm), R_GBR );
4.1228 + XOP2IS( OP_ADD, 4, R_R(Rm) );
4.1229 :}
4.1230 LDC.L @Rm+, SR {:
4.1231 if( in_delay_slot ) {
4.1232 @@ -924,225 +962,225 @@
4.1233 } else {
4.1234 CHECKPRIV();
4.1235 RALIGN32( R_R(Rm) );
4.1236 - XOP2E( OP_LOADL, R_R(Rm), REG_TMP0 );
4.1237 - XOP2I( OP_ADD, 4, R_R(Rm) );
4.1238 - XOPCALL1( sh4_write_sr, REG_TMP0 );
4.1239 + XOP2STE( OP_LOADL, R_R(Rm), REG_TMP0 );
4.1240 + XOP2IS( OP_ADD, 4, R_R(Rm) );
4.1241 + XOPCALL1T( sh4_write_sr, REG_TMP0 );
4.1242 }
4.1243 return 2;
4.1244 :}
4.1245 LDC.L @Rm+, VBR {:
4.1246 CHECKPRIV();
4.1247 RALIGN32( R_R(Rm) );
4.1248 - XOP2E( OP_LOADL, R_R(Rm), R_VBR );
4.1249 - XOP2I( OP_ADD, 4, R_R(Rm) );
4.1250 + XOP2SSE( OP_LOADL, R_R(Rm), R_VBR );
4.1251 + XOP2IS( OP_ADD, 4, R_R(Rm) );
4.1252 :}
4.1253 LDC.L @Rm+, SSR {:
4.1254 CHECKPRIV();
4.1255 RALIGN32( R_R(Rm) );
4.1256 - XOP2E( OP_LOADL, R_R(Rm), R_SSR );
4.1257 - XOP2I( OP_ADD, 4, R_R(Rm) );
4.1258 + XOP2SSE( OP_LOADL, R_R(Rm), R_SSR );
4.1259 + XOP2IS( OP_ADD, 4, R_R(Rm) );
4.1260 :}
4.1261 LDC.L @Rm+, SGR {:
4.1262 CHECKPRIV();
4.1263 RALIGN32( R_R(Rm) );
4.1264 - XOP2E( OP_LOADL, R_R(Rm), R_SGR );
4.1265 - XOP2I( OP_ADD, 4, R_R(Rm) );
4.1266 + XOP2SSE( OP_LOADL, R_R(Rm), R_SGR );
4.1267 + XOP2IS( OP_ADD, 4, R_R(Rm) );
4.1268 :}
4.1269 LDC.L @Rm+, SPC {:
4.1270 CHECKPRIV();
4.1271 RALIGN32( R_R(Rm) );
4.1272 - XOP2E( OP_LOADL, R_R(Rm), R_SPC );
4.1273 - XOP2I( OP_ADD, 4, R_R(Rm) );
4.1274 + XOP2SSE( OP_LOADL, R_R(Rm), R_SPC );
4.1275 + XOP2IS( OP_ADD, 4, R_R(Rm) );
4.1276 :}
4.1277 LDC.L @Rm+, DBR {:
4.1278 CHECKPRIV();
4.1279 RALIGN32( R_R(Rm) );
4.1280 - XOP2E( OP_LOADL, R_R(Rm), R_DBR );
4.1281 - XOP2I( OP_ADD, 4, R_R(Rm) );
4.1282 + XOP2SSE( OP_LOADL, R_R(Rm), R_DBR );
4.1283 + XOP2IS( OP_ADD, 4, R_R(Rm) );
4.1284 :}
4.1285 LDC.L @Rm+, Rn_BANK {:
4.1286 CHECKPRIV();
4.1287 RALIGN32( R_R(Rm) );
4.1288 - XOP2E( OP_LOADL, R_R(Rm), R_BANK(Rn_BANK) );
4.1289 - XOP2I( OP_ADD, 4, R_R(Rm) );
4.1290 + XOP2SSE( OP_LOADL, R_R(Rm), R_BANK(Rn_BANK) );
4.1291 + XOP2IS( OP_ADD, 4, R_R(Rm) );
4.1292 :}
4.1293 LDS Rm, FPSCR {:
4.1294 CHECKFPUEN();
4.1295 - XOPCALL1( sh4_write_fpscr, R_R(Rm) );
4.1296 + XOPCALL1S( sh4_write_fpscr, R_R(Rm) );
4.1297 return 2;
4.1298 :}
4.1299 LDS Rm, FPUL {:
4.1300 CHECKFPUEN();
4.1301 - XOP2( OP_MOV, R_R(Rm), R_FPUL );
4.1302 + XOP2SS( OP_MOV, R_R(Rm), R_FPUL );
4.1303 :}
4.1304 -LDS Rm, MACH {: XOP2( OP_MOV, R_R(Rm), R_MACH ); :}
4.1305 -LDS Rm, MACL {: XOP2( OP_MOV, R_R(Rm), R_MACL ); :}
4.1306 -LDS Rm, PR {: XOP2( OP_MOV, R_R(Rm), R_PR ); :}
4.1307 +LDS Rm, MACH {: XOP2SS( OP_MOV, R_R(Rm), R_MACH ); :}
4.1308 +LDS Rm, MACL {: XOP2SS( OP_MOV, R_R(Rm), R_MACL ); :}
4.1309 +LDS Rm, PR {: XOP2SS( OP_MOV, R_R(Rm), R_PR ); :}
4.1310 LDS.L @Rm+, FPSCR {:
4.1311 CHECKFPUEN();
4.1312 RALIGN32( R_R(Rm) );
4.1313 - XOP2E( OP_LOADL, R_R(Rm), REG_TMP0 );
4.1314 - XOP2I( OP_ADD, 4, R_R(Rm) );
4.1315 - XOPCALL1( sh4_write_fpscr, REG_TMP0 );
4.1316 + XOP2STE( OP_LOADL, R_R(Rm), REG_TMP0 );
4.1317 + XOP2IS( OP_ADD, 4, R_R(Rm) );
4.1318 + XOPCALL1T( sh4_write_fpscr, REG_TMP0 );
4.1319 return 2;
4.1320 :}
4.1321 LDS.L @Rm+, FPUL {:
4.1322 CHECKFPUEN();
4.1323 RALIGN32( R_R(Rm) );
4.1324 - XOP2E( OP_LOADL, R_R(Rm), R_FPUL );
4.1325 - XOP2I( OP_ADD, 4, R_R(Rm) );
4.1326 + XOP2SSE( OP_LOADL, R_R(Rm), R_FPUL );
4.1327 + XOP2IS( OP_ADD, 4, R_R(Rm) );
4.1328 :}
4.1329 LDS.L @Rm+, MACH {:
4.1330 RALIGN32( R_R(Rm) );
4.1331 - XOP2E( OP_LOADL, R_R(Rm), R_MACH );
4.1332 - XOP2I( OP_ADD, 4, R_R(Rm) );
4.1333 + XOP2SSE( OP_LOADL, R_R(Rm), R_MACH );
4.1334 + XOP2IS( OP_ADD, 4, R_R(Rm) );
4.1335 :}
4.1336 LDS.L @Rm+, MACL {:
4.1337 RALIGN32( R_R(Rm) );
4.1338 - XOP2E( OP_LOADL, R_R(Rm), R_MACL );
4.1339 - XOP2I( OP_ADD, 4, R_R(Rm) );
4.1340 + XOP2SSE( OP_LOADL, R_R(Rm), R_MACL );
4.1341 + XOP2IS( OP_ADD, 4, R_R(Rm) );
4.1342 :}
4.1343 LDS.L @Rm+, PR {:
4.1344 RALIGN32( R_R(Rm) );
4.1345 - XOP2E( OP_LOADL, R_R(Rm), R_PR );
4.1346 - XOP2I( OP_ADD, 4, R_R(Rm) );
4.1347 + XOP2SSE( OP_LOADL, R_R(Rm), R_PR );
4.1348 + XOP2IS( OP_ADD, 4, R_R(Rm) );
4.1349 :}
4.1350 STC SR, Rn {:
4.1351 CHECKPRIV();
4.1352 - XOPCALLR( sh4_read_sr, R_R(Rn) );
4.1353 + XOPCALLRS( sh4_read_sr, R_R(Rn) );
4.1354 :}
4.1355 -STC GBR, Rn {: XOP2( OP_MOV, R_GBR, R_R(Rn) ); :}
4.1356 -STC VBR, Rn {: CHECKPRIV(); XOP2( OP_MOV, R_VBR, R_R(Rn) ); :}
4.1357 -STC SSR, Rn {: CHECKPRIV(); XOP2( OP_MOV, R_SSR, R_R(Rn) ); :}
4.1358 -STC SPC, Rn {: CHECKPRIV(); XOP2( OP_MOV, R_SPC, R_R(Rn) ); :}
4.1359 -STC SGR, Rn {: CHECKPRIV(); XOP2( OP_MOV, R_SGR, R_R(Rn) ); :}
4.1360 -STC DBR, Rn {: CHECKPRIV(); XOP2( OP_MOV, R_DBR, R_R(Rn) ); :}
4.1361 -STC Rm_BANK, Rn {: CHECKPRIV(); XOP2( OP_MOV, R_BANK(Rm_BANK), R_R(Rn) ); :}
4.1362 +STC GBR, Rn {: XOP2SS( OP_MOV, R_GBR, R_R(Rn) ); :}
4.1363 +STC VBR, Rn {: CHECKPRIV(); XOP2SS( OP_MOV, R_VBR, R_R(Rn) ); :}
4.1364 +STC SSR, Rn {: CHECKPRIV(); XOP2SS( OP_MOV, R_SSR, R_R(Rn) ); :}
4.1365 +STC SPC, Rn {: CHECKPRIV(); XOP2SS( OP_MOV, R_SPC, R_R(Rn) ); :}
4.1366 +STC SGR, Rn {: CHECKPRIV(); XOP2SS( OP_MOV, R_SGR, R_R(Rn) ); :}
4.1367 +STC DBR, Rn {: CHECKPRIV(); XOP2SS( OP_MOV, R_DBR, R_R(Rn) ); :}
4.1368 +STC Rm_BANK, Rn {: CHECKPRIV(); XOP2SS( OP_MOV, R_BANK(Rm_BANK), R_R(Rn) ); :}
4.1369 STC.L SR, @-Rn {:
4.1370 CHECKPRIV();
4.1371 - XOPCALLR( sh4_read_sr, REG_TMP1 );
4.1372 + XOPCALLRT( sh4_read_sr, REG_TMP1 );
4.1373 WALIGN32( R_R(Rn) );
4.1374 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
4.1375 - XOP2I(OP_ADD, -4, REG_TMP0 );
4.1376 - XOP2E(OP_STOREL, REG_TMP0, REG_TMP1 );
4.1377 - XOP2I(OP_ADD, -4, R_R(Rn) );
4.1378 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
4.1379 + XOP2IT(OP_ADD, -4, REG_TMP0 );
4.1380 + XOP2TTE(OP_STOREL, REG_TMP0, REG_TMP1 );
4.1381 + XOP2IS(OP_ADD, -4, R_R(Rn) );
4.1382 :}
4.1383 STC.L VBR, @-Rn {:
4.1384 CHECKPRIV();
4.1385 WALIGN32( R_R(Rn) );
4.1386 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
4.1387 - XOP2I(OP_ADD, -4, REG_TMP0 );
4.1388 - XOP2E(OP_STOREL, REG_TMP0, R_VBR );
4.1389 - XOP2I(OP_ADD, -4, R_R(Rn) );
4.1390 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
4.1391 + XOP2IT(OP_ADD, -4, REG_TMP0 );
4.1392 + XOP2TSE(OP_STOREL, REG_TMP0, R_VBR );
4.1393 + XOP2IS(OP_ADD, -4, R_R(Rn) );
4.1394 :}
4.1395 STC.L SSR, @-Rn {:
4.1396 CHECKPRIV();
4.1397 WALIGN32( R_R(Rn) );
4.1398 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
4.1399 - XOP2I(OP_ADD, -4, REG_TMP0 );
4.1400 - XOP2E(OP_STOREL, REG_TMP0, R_SSR );
4.1401 - XOP2I(OP_ADD, -4, R_R(Rn) );
4.1402 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
4.1403 + XOP2IT(OP_ADD, -4, REG_TMP0 );
4.1404 + XOP2TSE(OP_STOREL, REG_TMP0, R_SSR );
4.1405 + XOP2IS(OP_ADD, -4, R_R(Rn) );
4.1406 :}
4.1407 STC.L SPC, @-Rn {:
4.1408 CHECKPRIV();
4.1409 WALIGN32( R_R(Rn) );
4.1410 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
4.1411 - XOP2I(OP_ADD, -4, REG_TMP0 );
4.1412 - XOP2E(OP_STOREL, REG_TMP0, R_SPC );
4.1413 - XOP2I(OP_ADD, -4, R_R(Rn) );
4.1414 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
4.1415 + XOP2IT(OP_ADD, -4, REG_TMP0 );
4.1416 + XOP2TSE(OP_STOREL, REG_TMP0, R_SPC );
4.1417 + XOP2IS(OP_ADD, -4, R_R(Rn) );
4.1418 :}
4.1419 STC.L SGR, @-Rn {:
4.1420 CHECKPRIV();
4.1421 WALIGN32( R_R(Rn) );
4.1422 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
4.1423 - XOP2I(OP_ADD, -4, REG_TMP0 );
4.1424 - XOP2E(OP_STOREL, REG_TMP0, R_SGR );
4.1425 - XOP2I(OP_ADD, -4, R_R(Rn) );
4.1426 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
4.1427 + XOP2IT(OP_ADD, -4, REG_TMP0 );
4.1428 + XOP2TSE(OP_STOREL, REG_TMP0, R_SGR );
4.1429 + XOP2IS(OP_ADD, -4, R_R(Rn) );
4.1430 :}
4.1431 STC.L DBR, @-Rn {:
4.1432 CHECKPRIV();
4.1433 WALIGN32( R_R(Rn) );
4.1434 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
4.1435 - XOP2I(OP_ADD, -4, REG_TMP0 );
4.1436 - XOP2E(OP_STOREL, REG_TMP0, R_DBR );
4.1437 - XOP2I(OP_ADD, -4, R_R(Rn) );
4.1438 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
4.1439 + XOP2IT(OP_ADD, -4, REG_TMP0 );
4.1440 + XOP2TSE(OP_STOREL, REG_TMP0, R_DBR );
4.1441 + XOP2IS(OP_ADD, -4, R_R(Rn) );
4.1442 :}
4.1443 STC.L Rm_BANK, @-Rn {:
4.1444 CHECKPRIV();
4.1445 WALIGN32( R_R(Rn) );
4.1446 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
4.1447 - XOP2I(OP_ADD, -4, REG_TMP0 );
4.1448 - XOP2E(OP_STOREL, REG_TMP0, R_BANK(Rm_BANK) );
4.1449 - XOP2I(OP_ADD, -4, R_R(Rn) );
4.1450 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
4.1451 + XOP2IT(OP_ADD, -4, REG_TMP0 );
4.1452 + XOP2TSE(OP_STOREL, REG_TMP0, R_BANK(Rm_BANK) );
4.1453 + XOP2IS(OP_ADD, -4, R_R(Rn) );
4.1454 :}
4.1455 STC.L GBR, @-Rn {:
4.1456 WALIGN32( R_R(Rn) );
4.1457 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
4.1458 - XOP2I(OP_ADD, -4, REG_TMP0 );
4.1459 - XOP2E(OP_STOREL, REG_TMP0, R_GBR );
4.1460 - XOP2I(OP_ADD, -4, R_R(Rn) );
4.1461 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
4.1462 + XOP2IT(OP_ADD, -4, REG_TMP0 );
4.1463 + XOP2TSE(OP_STOREL, REG_TMP0, R_GBR );
4.1464 + XOP2IS(OP_ADD, -4, R_R(Rn) );
4.1465 :}
4.1466 STS FPSCR, Rn {:
4.1467 CHECKFPUEN();
4.1468 - XOP2( OP_MOV, R_FPSCR, R_R(Rn) );
4.1469 + XOP2SS( OP_MOV, R_FPSCR, R_R(Rn) );
4.1470 :}
4.1471 STS FPUL, Rn {:
4.1472 CHECKFPUEN();
4.1473 - XOP2( OP_MOV, R_FPUL, R_R(Rn) );
4.1474 + XOP2SS( OP_MOV, R_FPUL, R_R(Rn) );
4.1475 :}
4.1476 STS MACH, Rn {:
4.1477 - XOP2( OP_MOV, R_MACH, R_R(Rn) );
4.1478 + XOP2SS( OP_MOV, R_MACH, R_R(Rn) );
4.1479 :}
4.1480 STS MACL, Rn {:
4.1481 - XOP2( OP_MOV, R_MACL, R_R(Rn) );
4.1482 + XOP2SS( OP_MOV, R_MACL, R_R(Rn) );
4.1483 :}
4.1484 STS PR, Rn {:
4.1485 - XOP2( OP_MOV, R_PR, R_R(Rn) );
4.1486 + XOP2SS( OP_MOV, R_PR, R_R(Rn) );
4.1487 :}
4.1488 STS.L FPSCR, @-Rn {:
4.1489 CHECKFPUEN();
4.1490 WALIGN32( R_R(Rn) );
4.1491 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
4.1492 - XOP2I(OP_ADD, -4, REG_TMP0 );
4.1493 - XOP2E(OP_STOREL, REG_TMP0, R_FPSCR );
4.1494 - XOP2I(OP_ADD, -4, R_R(Rn) );
4.1495 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
4.1496 + XOP2IT(OP_ADD, -4, REG_TMP0 );
4.1497 + XOP2TSE(OP_STOREL, REG_TMP0, R_FPSCR );
4.1498 + XOP2IS(OP_ADD, -4, R_R(Rn) );
4.1499 :}
4.1500 STS.L FPUL, @-Rn {:
4.1501 CHECKFPUEN();
4.1502 WALIGN32( R_R(Rn) );
4.1503 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
4.1504 - XOP2I(OP_ADD, -4, REG_TMP0 );
4.1505 - XOP2E(OP_STOREL, REG_TMP0, R_FPUL );
4.1506 - XOP2I(OP_ADD, -4, R_R(Rn) );
4.1507 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
4.1508 + XOP2IT(OP_ADD, -4, REG_TMP0 );
4.1509 + XOP2TSE(OP_STOREL, REG_TMP0, R_FPUL );
4.1510 + XOP2IS(OP_ADD, -4, R_R(Rn) );
4.1511 :}
4.1512 STS.L MACH, @-Rn {:
4.1513 WALIGN32( R_R(Rn) );
4.1514 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
4.1515 - XOP2I(OP_ADD, -4, REG_TMP0 );
4.1516 - XOP2E(OP_STOREL, REG_TMP0, R_MACH );
4.1517 - XOP2I(OP_ADD, -4, R_R(Rn) );
4.1518 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
4.1519 + XOP2IT(OP_ADD, -4, REG_TMP0 );
4.1520 + XOP2TSE(OP_STOREL, REG_TMP0, R_MACH );
4.1521 + XOP2IS(OP_ADD, -4, R_R(Rn) );
4.1522 :}
4.1523 STS.L MACL, @-Rn {:
4.1524 WALIGN32( R_R(Rn) );
4.1525 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
4.1526 - XOP2I(OP_ADD, -4, REG_TMP0 );
4.1527 - XOP2E(OP_STOREL, REG_TMP0, R_MACL );
4.1528 - XOP2I(OP_ADD, -4, R_R(Rn) );
4.1529 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
4.1530 + XOP2IT(OP_ADD, -4, REG_TMP0 );
4.1531 + XOP2TSE(OP_STOREL, REG_TMP0, R_MACL );
4.1532 + XOP2IS(OP_ADD, -4, R_R(Rn) );
4.1533 :}
4.1534 STS.L PR, @-Rn {:
4.1535 WALIGN32( R_R(Rn) );
4.1536 - XOP2( OP_MOV, R_R(Rn), REG_TMP0 );
4.1537 - XOP2I(OP_ADD, -4, REG_TMP0 );
4.1538 - XOP2E(OP_STOREL, REG_TMP0, R_PR );
4.1539 - XOP2I(OP_ADD, -4, R_R(Rn) );
4.1540 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP0 );
4.1541 + XOP2IT(OP_ADD, -4, REG_TMP0 );
4.1542 + XOP2TSE(OP_STOREL, REG_TMP0, R_PR );
4.1543 + XOP2IS(OP_ADD, -4, R_R(Rn) );
4.1544 :}
4.1545
4.1546 BF disp {:
4.1547 if( in_delay_slot ) {
4.1548 SLOTILLEGAL();
4.1549 } else {
4.1550 - XOP2I( OP_ADD, (pc+2 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
4.1551 - XOP2I( OP_CMP, 0, R_T );
4.1552 + XOP2IS( OP_ADD, (pc+2 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
4.1553 + XOP2IS( OP_CMP, 0, R_T );
4.1554 XOP2IICC( OP_BRCOND, CC_EQ, disp+pc+4-xbb->pc_begin, pc+2-xbb->pc_begin );
4.1555 }
4.1556 return 2;
4.1557 @@ -1153,16 +1191,16 @@
4.1558 return 2;
4.1559 } else {
4.1560 if( UNTRANSLATABLE(pc+2 ) ) {
4.1561 - XOP2I( OP_CMP, 0, R_T );
4.1562 + XOP2IS( OP_CMP, 0, R_T );
4.1563 XOP2IICC( OP_BRCONDDEL, CC_EQ, disp+pc+4-xbb->pc_begin, pc+4-xbb->pc_begin );
4.1564 EMU_DELAY_SLOT();
4.1565 return 2;
4.1566 } else {
4.1567 - XOP2( OP_MOV, R_T, REG_TMP2 );
4.1568 + XOP2ST( OP_MOV, R_T, REG_TMP2 );
4.1569 sh4_decode_instruction( xbb, pc+2, TRUE );
4.1570 if( !XOP_IS_TERMINATOR( xbb->ir_ptr->prev ) ) {
4.1571 - XOP2I( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
4.1572 - XOP2I( OP_CMP, 0, REG_TMP2 );
4.1573 + XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
4.1574 + XOP2IT( OP_CMP, 0, REG_TMP2 );
4.1575 XOP2IICC( OP_BRCOND, CC_EQ, disp+pc+4-xbb->pc_begin, pc+4-xbb->pc_begin );
4.1576 }
4.1577 return 4;
4.1578 @@ -1173,8 +1211,8 @@
4.1579 if( in_delay_slot ) {
4.1580 SLOTILLEGAL();
4.1581 } else {
4.1582 - XOP2I( OP_ADD, (pc+2 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
4.1583 - XOP2I( OP_CMP, 1, R_T );
4.1584 + XOP2IS( OP_ADD, (pc+2 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
4.1585 + XOP2IS( OP_CMP, 1, R_T );
4.1586 XOP2IICC( OP_BRCOND, CC_EQ, disp+pc+4-xbb->pc_begin, pc+2-xbb->pc_begin );
4.1587 }
4.1588 return 2;
4.1589 @@ -1185,16 +1223,16 @@
4.1590 return 2;
4.1591 } else {
4.1592 if( UNTRANSLATABLE(pc+2 ) ) {
4.1593 - XOP2I( OP_CMP, 1, R_T );
4.1594 + XOP2IS( OP_CMP, 1, R_T );
4.1595 XOP2IICC( OP_BRCONDDEL, CC_EQ, disp+pc+4-xbb->pc_begin, pc+2-xbb->pc_begin );
4.1596 EMU_DELAY_SLOT();
4.1597 return 2;
4.1598 } else {
4.1599 - XOP2( OP_MOV, R_T, REG_TMP2 );
4.1600 + XOP2ST( OP_MOV, R_T, REG_TMP2 );
4.1601 sh4_decode_instruction( xbb, pc+2, TRUE );
4.1602 if( !XOP_IS_TERMINATOR( xbb->ir_ptr->prev ) ) {
4.1603 - XOP2I( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
4.1604 - XOP2I( OP_CMP, 1, REG_TMP2 );
4.1605 + XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
4.1606 + XOP2IT( OP_CMP, 1, REG_TMP2 );
4.1607 XOP2IICC( OP_BRCOND, CC_EQ, disp+pc+4-xbb->pc_begin, pc+4-xbb->pc_begin );
4.1608 }
4.1609 return 4;
4.1610 @@ -1207,14 +1245,14 @@
4.1611 return 2;
4.1612 } else {
4.1613 if( UNTRANSLATABLE(pc+2) ) {
4.1614 - XOP2( OP_MOV, R_PC, R_NEW_PC );
4.1615 - XOP2I( OP_ADD, pc+disp+4-xbb->pc_begin, R_NEW_PC );
4.1616 + XOP2SS( OP_MOV, R_PC, R_NEW_PC );
4.1617 + XOP2IS( OP_ADD, pc+disp+4-xbb->pc_begin, R_NEW_PC );
4.1618 EMU_DELAY_SLOT();
4.1619 return 2;
4.1620 } else {
4.1621 sh4_decode_instruction( xbb, pc+2, TRUE );
4.1622 if( xbb->ir_ptr->prev == NULL || !XOP_IS_TERMINATOR( xbb->ir_ptr->prev ) ) {
4.1623 - XOP2I( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
4.1624 + XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
4.1625 XOP1I( OP_BRREL, pc+disp+4-xbb->pc_begin );
4.1626 }
4.1627 return 4;
4.1628 @@ -1226,18 +1264,18 @@
4.1629 SLOTILLEGAL();
4.1630 return 2;
4.1631 } else {
4.1632 - XOP2( OP_MOV, R_R(Rn), REG_TMP2 );
4.1633 - XOP2( OP_ADD, R_PC, REG_TMP2 );
4.1634 - XOP2I( OP_ADD, pc - xbb->pc_begin + 4, REG_TMP2 );
4.1635 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP2 );
4.1636 + XOP2ST( OP_ADD, R_PC, REG_TMP2 );
4.1637 + XOP2IT( OP_ADD, pc - xbb->pc_begin + 4, REG_TMP2 );
4.1638 if( UNTRANSLATABLE(pc+2) ) {
4.1639 - XOP2( OP_MOV, REG_TMP2, R_NEW_PC );
4.1640 + XOP2TS( OP_MOV, REG_TMP2, R_NEW_PC );
4.1641 EMU_DELAY_SLOT();
4.1642 return 2;
4.1643 } else {
4.1644 sh4_decode_instruction( xbb, pc + 2, TRUE );
4.1645 if( !XOP_IS_TERMINATOR( xbb->ir_ptr->prev ) ) {
4.1646 - XOP2I( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
4.1647 - XOP1( OP_BR, REG_TMP2 );
4.1648 + XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
4.1649 + XOP1T( OP_BR, REG_TMP2 );
4.1650 }
4.1651 return 4;
4.1652 }
4.1653 @@ -1248,17 +1286,17 @@
4.1654 SLOTILLEGAL();
4.1655 return 2;
4.1656 } else {
4.1657 - XOP2( OP_MOV, R_PC, R_PR );
4.1658 - XOP2I( OP_ADD, pc - xbb->pc_begin + 4, R_PR );
4.1659 + XOP2SS( OP_MOV, R_PC, R_PR );
4.1660 + XOP2IS( OP_ADD, pc - xbb->pc_begin + 4, R_PR );
4.1661 if( UNTRANSLATABLE(pc+2) ) {
4.1662 - XOP2( OP_MOV, R_PC, R_NEW_PC );
4.1663 - XOP2I( OP_ADD, pc+disp+4-xbb->pc_begin, R_NEW_PC );
4.1664 + XOP2SS( OP_MOV, R_PC, R_NEW_PC );
4.1665 + XOP2IS( OP_ADD, pc+disp+4-xbb->pc_begin, R_NEW_PC );
4.1666 EMU_DELAY_SLOT();
4.1667 return 2;
4.1668 } else {
4.1669 sh4_decode_instruction( xbb, pc+2, TRUE );
4.1670 if( !XOP_IS_TERMINATOR( xbb->ir_ptr->prev ) ) {
4.1671 - XOP2I( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
4.1672 + XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
4.1673 XOP1I( OP_BRREL, pc+disp+4-xbb->pc_begin );
4.1674 }
4.1675 return 4;
4.1676 @@ -1270,20 +1308,20 @@
4.1677 SLOTILLEGAL();
4.1678 return 2;
4.1679 } else {
4.1680 - XOP2( OP_MOV, R_PC, R_PR );
4.1681 - XOP2I( OP_ADD, pc - xbb->pc_begin + 4, R_PR );
4.1682 - XOP2( OP_MOV, R_R(Rn), REG_TMP2 );
4.1683 - XOP2( OP_ADD, R_PC, REG_TMP2 );
4.1684 - XOP2I( OP_ADD, pc - xbb->pc_begin + 4, REG_TMP2 );
4.1685 + XOP2SS( OP_MOV, R_PC, R_PR );
4.1686 + XOP2IS( OP_ADD, pc - xbb->pc_begin + 4, R_PR );
4.1687 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP2 );
4.1688 + XOP2ST( OP_ADD, R_PC, REG_TMP2 );
4.1689 + XOP2IT( OP_ADD, pc - xbb->pc_begin + 4, REG_TMP2 );
4.1690 if( UNTRANSLATABLE(pc+2) ) {
4.1691 - XOP2( OP_MOV, REG_TMP2, R_NEW_PC );
4.1692 + XOP2TS( OP_MOV, REG_TMP2, R_NEW_PC );
4.1693 EMU_DELAY_SLOT();
4.1694 return 2;
4.1695 } else {
4.1696 sh4_decode_instruction( xbb, pc+2, TRUE );
4.1697 if( !XOP_IS_TERMINATOR( xbb->ir_ptr->prev ) ) {
4.1698 - XOP2I( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
4.1699 - XOP1( OP_BR, REG_TMP2 );
4.1700 + XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
4.1701 + XOP1T( OP_BR, REG_TMP2 );
4.1702 }
4.1703 return 4;
4.1704 }
4.1705 @@ -1295,15 +1333,15 @@
4.1706 return 2;
4.1707 } else {
4.1708 if( UNTRANSLATABLE(pc+2) ) {
4.1709 - XOP2( OP_MOV, R_R(Rn), R_NEW_PC );
4.1710 + XOP2SS( OP_MOV, R_R(Rn), R_NEW_PC );
4.1711 EMU_DELAY_SLOT();
4.1712 return 2;
4.1713 } else {
4.1714 - XOP2( OP_MOV, R_R(Rn), REG_TMP2 );
4.1715 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP2 );
4.1716 sh4_decode_instruction( xbb, pc+2, TRUE );
4.1717 if( !XOP_IS_TERMINATOR( xbb->ir_ptr->prev ) ) {
4.1718 - XOP2I( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
4.1719 - XOP1( OP_BR, REG_TMP2 );
4.1720 + XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
4.1721 + XOP1T( OP_BR, REG_TMP2 );
4.1722 }
4.1723 return 4;
4.1724 }
4.1725 @@ -1314,18 +1352,18 @@
4.1726 SLOTILLEGAL();
4.1727 return 2;
4.1728 } else {
4.1729 - XOP2( OP_MOV, R_PC, R_PR );
4.1730 - XOP2I( OP_ADD, pc - xbb->pc_begin + 4, R_PR );
4.1731 + XOP2SS( OP_MOV, R_PC, R_PR );
4.1732 + XOP2IS( OP_ADD, pc - xbb->pc_begin + 4, R_PR );
4.1733 if( UNTRANSLATABLE(pc+2) ) {
4.1734 - XOP2( OP_MOV, R_R(Rn), R_NEW_PC );
4.1735 + XOP2SS( OP_MOV, R_R(Rn), R_NEW_PC );
4.1736 EMU_DELAY_SLOT();
4.1737 return 2;
4.1738 } else {
4.1739 - XOP2( OP_MOV, R_R(Rn), REG_TMP2 );
4.1740 + XOP2ST( OP_MOV, R_R(Rn), REG_TMP2 );
4.1741 sh4_decode_instruction( xbb, pc+2, TRUE );
4.1742 if( !XOP_IS_TERMINATOR( xbb->ir_ptr->prev ) ) {
4.1743 - XOP2I( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
4.1744 - XOP1( OP_BR, REG_TMP2 );
4.1745 + XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
4.1746 + XOP1T( OP_BR, REG_TMP2 );
4.1747 }
4.1748 return 4;
4.1749 }
4.1750 @@ -1338,16 +1376,16 @@
4.1751 return 2;
4.1752 } else {
4.1753 if( UNTRANSLATABLE(pc+2) ) {
4.1754 - XOP2( OP_MOV, R_SPC, R_NEW_PC );
4.1755 + XOP2SS( OP_MOV, R_SPC, R_NEW_PC );
4.1756 EMU_DELAY_SLOT();
4.1757 return 2;
4.1758 } else {
4.1759 - XOP2( OP_MOV, R_SPC, REG_TMP2 );
4.1760 - XOPCALL1( sh4_write_sr, R_SSR );
4.1761 + XOP2ST( OP_MOV, R_SPC, REG_TMP2 );
4.1762 + XOPCALL1S( sh4_write_sr, R_SSR );
4.1763 sh4_decode_instruction( xbb, pc+2, TRUE );
4.1764 if( !XOP_IS_TERMINATOR( xbb->ir_ptr->prev ) ) {
4.1765 - XOP2I( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
4.1766 - XOP1( OP_BR, REG_TMP2 );
4.1767 + XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
4.1768 + XOP1T( OP_BR, REG_TMP2 );
4.1769 }
4.1770 return 4;
4.1771 }
4.1772 @@ -1359,15 +1397,15 @@
4.1773 return 2;
4.1774 } else {
4.1775 if( UNTRANSLATABLE(pc+2) ) {
4.1776 - XOP2( OP_MOV, R_PR, R_NEW_PC );
4.1777 + XOP2SS( OP_MOV, R_PR, R_NEW_PC );
4.1778 EMU_DELAY_SLOT();
4.1779 return 2;
4.1780 } else {
4.1781 - XOP2( OP_MOV, R_PR, REG_TMP2 );
4.1782 + XOP2ST( OP_MOV, R_PR, REG_TMP2 );
4.1783 sh4_decode_instruction( xbb, pc+2, TRUE );
4.1784 if( !XOP_IS_TERMINATOR( xbb->ir_ptr->prev ) ) {
4.1785 - XOP2I( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
4.1786 - XOP1( OP_BR, REG_TMP2 );
4.1787 + XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
4.1788 + XOP1T( OP_BR, REG_TMP2 );
4.1789 }
4.1790 return 4;
4.1791 }
5.1 --- a/src/test/testsh4xir.c Tue Apr 07 10:55:03 2009 +0000
5.2 +++ b/src/test/testsh4xir.c Sun Apr 12 07:24:45 2009 +0000
5.3 @@ -135,16 +135,19 @@
5.4
5.5 struct xir_basic_block xbb;
5.6 xbb.source = &sh4_source_machine;
5.7 + xbb.target = &x86_target_machine;
5.8 xbb.ir_alloc_begin = &xir[0];
5.9 xbb.ir_alloc_end = &xir[MAX_XIR_OPS];
5.10 xbb.ir_begin = xbb.ir_ptr = xbb.ir_end = xbb.ir_alloc_begin;
5.11 xbb.pc_begin = start_addr;
5.12 xbb.pc_end = start_addr+4096;
5.13 + xir_clear_basic_block(&xbb);
5.14 xbb.source->decode_basic_block( &xbb );
5.15
5.16 - x86_target_machine.lower( &xbb, xbb.ir_begin, xbb.ir_end );
5.17 - xir_set_register_names( sh4_source_machine.reg_names, x86_target_machine.reg_names );
5.18 + //x86_target_machine.lower( &xbb, xbb.ir_begin, xbb.ir_end );
5.19 + xir_promote_source_registers( &xbb, xbb.ir_begin, xbb.ir_end );
5.20 xir_set_symbol_table( debug_symbols );
5.21 - xir_dump_block( &xir[0], NULL );
5.22 + xir_dump_block( &xbb );
5.23 + xir_verify_block( &xbb, xbb.ir_begin, xbb.ir_end );
5.24 return 0;
5.25 }
6.1 --- a/src/test/testxir.c Tue Apr 07 10:55:03 2009 +0000
6.2 +++ b/src/test/testxir.c Sun Apr 12 07:24:45 2009 +0000
6.3 @@ -22,19 +22,23 @@
6.4
6.5 void test_shuffle()
6.6 {
6.7 + int tmp1, tmp2;
6.8 struct xir_op op[64];
6.9 struct xir_basic_block bb;
6.10 xir_basic_block_t xbb = &bb;
6.11 bb.ir_alloc_begin = bb.ir_begin = bb.ir_end = bb.ir_ptr = &op[0];
6.12 bb.ir_alloc_end = &op[64];
6.13 + xir_clear_basic_block( xbb );
6.14 + tmp1 = xir_alloc_temp_reg( xbb, XTY_LONG, -1 );
6.15 + tmp2 = xir_alloc_temp_reg( xbb, XTY_LONG, -1 );
6.16
6.17 - XOP2I( OP_SHUFFLE, 0x1243, REG_TMP1 );
6.18 - XOP2I( OP_SHUFFLE, 0x3412, REG_TMP1 );
6.19 - XOP2I( OP_SHUFFLE, 0x1243, REG_TMP1 );
6.20 - XOP2I( OP_SHUFFLE, 0x3412, REG_TMP1 );
6.21 - XOP2I( OP_SHUFFLE, 0x1234, REG_TMP1 );
6.22 - XOP2I( OP_SHUFFLE, 0x1111, REG_TMP2 );
6.23 - XOP2I( OP_SHUFFLE, 0x0123, REG_TMP1 );
6.24 + XOP2IT( OP_SHUFFLE, 0x1243, REG_TMP1 );
6.25 + XOP2IT( OP_SHUFFLE, 0x3412, REG_TMP1 );
6.26 + XOP2IT( OP_SHUFFLE, 0x1243, REG_TMP1 );
6.27 + XOP2IT( OP_SHUFFLE, 0x3412, REG_TMP1 );
6.28 + XOP2IT( OP_SHUFFLE, 0x1234, REG_TMP1 );
6.29 + XOP2IT( OP_SHUFFLE, 0x1111, REG_TMP2 );
6.30 + XOP2IT( OP_SHUFFLE, 0x0123, REG_TMP1 );
6.31 XOP1I( OP_BR, 0x8C001000 );
6.32 (bb.ir_ptr-1)->next = NULL;
6.33 bb.ir_end = bb.ir_ptr-1;
6.34 @@ -54,13 +58,14 @@
6.35 assert( xir_shuffle_lower_size( &op[4] ) == 0);
6.36 assert( xir_shuffle_lower_size( &op[5] ) == 12);
6.37 assert( xir_shuffle_lower_size( &op[6] ) == 1);
6.38 - xir_shuffle_lower( xbb, &op[0], REG_TMP3, REG_TMP4 );
6.39 - xir_shuffle_lower( xbb, &op[1], REG_TMP3, REG_TMP4 );
6.40 - xir_shuffle_lower( xbb, &op[3], REG_TMP3, REG_TMP4 );
6.41 - xir_shuffle_lower( xbb, &op[4], REG_TMP3, REG_TMP4 );
6.42 - xir_shuffle_lower( xbb, &op[5], REG_TMP3, REG_TMP4 );
6.43 - xir_shuffle_lower( xbb, &op[6], REG_TMP3, REG_TMP4 );
6.44 - xir_dump_block( &op[0], NULL );
6.45 + xir_shuffle_lower( xbb, &op[0], tmp1, tmp2 );
6.46 + xir_shuffle_lower( xbb, &op[1], tmp1, tmp2 );
6.47 + xir_shuffle_lower( xbb, &op[3], tmp1, tmp2 );
6.48 + xir_shuffle_lower( xbb, &op[4], tmp1, tmp2 );
6.49 + xir_shuffle_lower( xbb, &op[5], tmp1, tmp2 );
6.50 + xir_shuffle_lower( xbb, &op[6], tmp1, tmp2 );
6.51 + xir_dump_block( xbb );
6.52 + xir_verify_block( xbb, xbb->ir_begin, xbb->ir_end );
6.53 }
6.54
6.55
7.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
7.2 +++ b/src/xlat/regalloc.c Sun Apr 12 07:24:45 2009 +0000
7.3 @@ -0,0 +1,108 @@
7.4 +/**
7.5 + * $Id: regalloc.h 931 2008-10-31 02:57:59Z nkeynes $
7.6 + *
7.7 + * Register allocation based on simple linear scan
7.8 + *
7.9 + * Copyright (c) 2008 Nathan Keynes.
7.10 + *
7.11 + * This program is free software; you can redistribute it and/or modify
7.12 + * it under the terms of the GNU General Public License as published by
7.13 + * the Free Software Foundation; either version 2 of the License, or
7.14 + * (at your option) any later version.
7.15 + *
7.16 + * This program is distributed in the hope that it will be useful,
7.17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7.18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7.19 + * GNU General Public License for more details.
7.20 + */
7.21 +
7.22 +#include <stdlib.h>
7.23 +#include <string.h>
7.24 +#include "lxdream.h"
7.25 +#include "xir.h"
7.26 +
7.27 +
7.28 +/**
7.29 + * Promote all source registers to temporaries, in preparation for regalloc.
7.30 + * In case of partial aliasing, we flush back to memory before reloading (this
7.31 + * needs to be improved)
7.32 + */
7.33 +void xir_promote_source_registers( xir_basic_block_t xbb, xir_op_t start, xir_op_t end )
7.34 +{
7.35 + struct temp_reg {
7.36 + gboolean is_dirty;
7.37 + xir_op_t last_access;
7.38 + };
7.39 +
7.40 + struct temp_reg all_temp_regs[MAX_TEMP_REGISTER+1];
7.41 +
7.42 +
7.43 + /* -1 if byte is not allocated to a temporary, otherwise temp id */
7.44 + int16_t source_regs[MAX_SOURCE_REGISTER+1];
7.45 +
7.46 + memset( source_regs, -1, sizeof(source_regs) );
7.47 + memset( all_temp_regs, 0, sizeof(all_temp_regs) );
7.48 +
7.49 + for( xir_op_t it = start; it != NULL; it = it->next ) {
7.50 + if( XOP_IS_SRC(it,0) ) {
7.51 + int r = XOP_REG(it,0);
7.52 + int s = XOP_OPSIZE(it,0);
7.53 + int t = source_regs[r];
7.54 + if( t == -1 ) {
7.55 + t = xir_alloc_temp_reg( xbb, XOP_OPTYPE(it,0), r );
7.56 + source_regs[r] = t;
7.57 + if( XOP_READS_OP1(it) ) {
7.58 + xir_insert_op( XOP2ST( OP_MOV, r, t ), it );
7.59 + }
7.60 + }
7.61 + it->operand[0].form = TEMP_OPERAND;
7.62 + it->operand[0].value.i = t;
7.63 + all_temp_regs[t].last_access = it;
7.64 + all_temp_regs[t].is_dirty |= XOP_WRITES_OP1(it);
7.65 + }
7.66 +
7.67 + if( XOP_IS_SRC(it,1) ) {
7.68 + int r = XOP_REG(it,1);
7.69 + int s = XOP_OPSIZE(it,1);
7.70 + int t = source_regs[r];
7.71 + if( t == -1 ) {
7.72 + t = xir_alloc_temp_reg( xbb, XOP_OPTYPE(it,1), r );
7.73 + source_regs[r] = t;
7.74 + if( XOP_READS_OP2(it) ) {
7.75 + xir_insert_op( XOP2ST( OP_MOV, r, t ), it );
7.76 + }
7.77 + }
7.78 + it->operand[1].form = TEMP_OPERAND;
7.79 + it->operand[1].value.i = t;
7.80 + all_temp_regs[t].last_access = it;
7.81 + all_temp_regs[t].is_dirty |= XOP_WRITES_OP2(it);
7.82 + }
7.83 +
7.84 + if( it == end )
7.85 + break;
7.86 + }
7.87 +
7.88 + for( int i=0; i<xbb->next_temp_reg; i++ ) {
7.89 + if( all_temp_regs[i].last_access != NULL && all_temp_regs[i].is_dirty ) {
7.90 + xir_insert_op( XOP2TS( OP_MOV, i, xbb->temp_regs[i].home_register ),
7.91 + all_temp_regs[i].last_access->next );
7.92 + }
7.93 + }
7.94 +}
7.95 +
7.96 +
7.97 +/**
7.98 + * General constraints:
7.99 + * Temporaries can't be spilled, must be held in a target register
7.100 + *
7.101 + * 3 categories of target register:
7.102 + * Argument (ie EAX/EDX for ia32): assign call arguments to appropriate regs
7.103 + * first. Any available lifetime rolls over to the general volatile regs
7.104 + * Volatile (caller-saved): Assign variables with lifetime between calls first
7.105 + * Non-volatile (callee-saved): Everything else with cost-balancing (each
7.106 + * register used costs the equivalent of a spill/unspill pair)
7.107 + *
7.108 + * For x86, argument regs are EAX + EDX, ECX is volatile, and ESI/EDI/EBX are non-volatile.
7.109 + * For x86-64, arguments regs are EDI + ESI, EBX, R8-R11 are volatile, and R12-R15 are non-volatile.
7.110 + * (ESP+EBP are reserved either way)
7.111 + */
7.112 \ No newline at end of file
8.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
8.2 +++ b/src/xlat/regalloc.h Sun Apr 12 07:24:45 2009 +0000
8.3 @@ -0,0 +1,34 @@
8.4 +/**
8.5 + * $Id: regalloc.h 931 2008-10-31 02:57:59Z nkeynes $
8.6 + *
8.7 + * Register allocation based on simple linear scan
8.8 + *
8.9 + * Copyright (c) 2008 Nathan Keynes.
8.10 + *
8.11 + * This program is free software; you can redistribute it and/or modify
8.12 + * it under the terms of the GNU General Public License as published by
8.13 + * the Free Software Foundation; either version 2 of the License, or
8.14 + * (at your option) any later version.
8.15 + *
8.16 + * This program is distributed in the hope that it will be useful,
8.17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8.18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8.19 + * GNU General Public License for more details.
8.20 + */
8.21 +
8.22 +#ifndef lxdream_regalloc_H
8.23 +#define lxdream_regalloc_H 1
8.24 +
8.25 +#include "xlat/xir.h"
8.26 +
8.27 +typedef struct target_machine_reg {
8.28 +
8.29 +} *target_machine_reg_t;
8.30 +
8.31 +/**
8.32 + * Allocate registers from the source machine to the target machine
8.33 + */
8.34 +void xlat_register_alloc( xir_op_t start, xir_op_t end, target_machine_reg_t target_registers );
8.35 +
8.36 +
8.37 +#endif /* !lxdream_regalloc_H */
9.1 --- a/src/xlat/x86/x86gen.c Tue Apr 07 10:55:03 2009 +0000
9.2 +++ b/src/xlat/x86/x86gen.c Sun Apr 12 07:24:45 2009 +0000
9.3 @@ -105,69 +105,81 @@
9.4 #define IS_X86_64() (sizeof(void *)==8)
9.5 #define IS_XMM_REG(op,n) (XOP_REG(op,n) >= MIN_XMM_REGISTER && XOP_REG(op,n) <= MAX_AMD64_XMM_REGISTER)
9.6
9.7 -#define RBP_OFFSET (-128)
9.8 +#define NONE NO_OPERAND
9.9 +#define SRC SOURCE_OPERAND
9.10 +#define DST DEST_OPERAND
9.11 +#define TMP TEMP_OPERAND
9.12 +#define IMM IMMEDIATE_OPERAND
9.13
9.14 -#define NONE NO_OPERAND
9.15 -#define SRC SOURCE_REGISTER_OPERAND
9.16 -#define TGT TARGET_REGISTER_OPERAND
9.17 -#define IMM INT_IMM_OPERAND
9.18 -#define FLT FLOAT_IMM_OPERAND
9.19 -#define DBL DOUBLE_IMM_OPERAND
9.20 +#define MAX_X86_GENERAL_REGISTER 7
9.21 +#define MAX_AMD64_GENERAL_REGISTER 15
9.22 +#define MIN_XMM_REGISTER 16
9.23 +#define MAX_X86_XMM_REGISTER 23
9.24 +#define MAX_AMD64_XMM_REGISTER 31
9.25
9.26 -#define MAX_X86_GENERAL_REGISTER (MIN_TARGET_REGISTER+7)
9.27 -#define MAX_AMD64_GENERAL_REGISTER (MIN_TARGET_REGISTER+15)
9.28 -#define MIN_XMM_REGISTER (MIN_TARGET_REGISTER+16)
9.29 -#define MAX_X86_XMM_REGISTER (MIN_TARGET_REGISTER+23)
9.30 -#define MAX_AMD64_XMM_REGISTER (MIN_TARGET_REGISTER+31)
9.31 +#define SRCADDR(op,n) (XOP_REG(op,n) - 128)
9.32 +#define TMPADDR(op,n) (XOP_REG(op,n)) /* FIXME */
9.33
9.34 -#define ILLOP(op) FATAL("Illegal x86 opcode %s %d %d\n", XIR_OPCODE_TABLE[op->opcode], op->operand[0].type, op->operand[1].type)
9.35 +#define ILLOP(op) FATAL("Illegal x86 opcode %s %d %d\n", XIR_OPCODE_TABLE[op->opcode], op->operand[0].form, op->operand[1].form)
9.36
9.37 // Convenience macros
9.38 #define X86L_IMMS_REG(opname, op) \
9.39 - if( XOP_IS_FORM(op,IMM,TGT) ) { opname##_imms_r32(XOP_INT(op,0),XOP_REG(op,1)); } \
9.40 - else if( XOP_IS_FORM(op,IMM,SRC) ) { opname##_imms_rbpdisp(XOP_INT(op,0),XOP_REG(op,1)+RBP_OFFSET); } \
9.41 + if( XOP_IS_FORM(op,IMM,DST) ) { opname##_imms_r32(XOP_INT(op,0),XOP_REG(op,1)); } \
9.42 + else if( XOP_IS_FORM(op,IMM,SRC) ) { opname##_imms_r32disp(XOP_INT(op,0),REG_RBP,SRCADDR(op,1)); } \
9.43 + else if( XOP_IS_FORM(op,IMM,TMP) ) { opname##_imms_r32disp(XOP_INT(op,0),REG_RSP,TMPADDR(op,1)); } \
9.44 else { ILLOP(op); }
9.45
9.46 -#define X86L_REG_TGT(opname,op) \
9.47 - if( XOP_IS_FORM(op,TGT,TGT) ) { opname##_r32_r32(XOP_REG(op,0),XOP_REG(op,1)); } \
9.48 - else if( XOP_IS_FORM(op,SRC,TGT) ) { opname##_rbpdisp_r32(XOP_REG(op,0)+RBP_OFFSET,XOP_REG(op,1)); } \
9.49 +#define X86L_REG_DST(opname,op) \
9.50 + if( XOP_IS_FORM(op,DST,DST) ) { opname##_r32_r32(XOP_REG(op,0),XOP_REG(op,1)); } \
9.51 + else if( XOP_IS_FORM(op,SRC,DST) ) { opname##_r32disp_r32(REG_RBP, SRCADDR(op,0),XOP_REG(op,1)); } \
9.52 + else if( XOP_IS_FORM(op,TMP,DST) ) { opname##_r32disp_r32(REG_RSP, TMPADDR(op,0),XOP_REG(op,1)); } \
9.53 else { ILLOP(op); }
9.54
9.55 -#define X86F_REG_TGT(opname,op ) \
9.56 - if( XOP_IS_FORM(op,TGT,TGT) ) { opname##_xmm_xmm(XOP_REG(op,0),XOP_REG(op,1)); } \
9.57 - else if( XOP_IS_FORM(op,SRC,TGT) ) { opname##_rbpdisp_xmm(XOP_REG(op,0)+RBP_OFFSET,XOP_REG(op,1)); } \
9.58 +#define X86F_REG_DST(opname,op ) \
9.59 + if( XOP_IS_FORM(op,DST,DST) ) { opname##_xmm_xmm(XOP_REG(op,0),XOP_REG(op,1)); } \
9.60 + else if( XOP_IS_FORM(op,SRC,DST) ) { opname##_r32disp_xmm(REG_RBP, SRCADDR(op,0),XOP_REG(op,1)); } \
9.61 + else if( XOP_IS_FORM(op,TMP,DST) ) { opname##_r32disp_xmm(REG_RSP, TMPADDR(op,0),XOP_REG(op,1)); } \
9.62 else { ILLOP(op); }
9.63
9.64 #define X86L_REG_REG(opname,op) \
9.65 - if( XOP_IS_FORM(op,TGT,TGT) ) { opname##_r32_r32(XOP_REG(op,0),XOP_REG(op,1)); } \
9.66 - else if( XOP_IS_FORM(op,SRC,TGT) ) { opname##_rbpdisp_r32(XOP_REG(op,0)+RBP_OFFSET,XOP_REG(op,1)); } \
9.67 - else if( XOP_IS_FORM(op,TGT,SRC) ) { opname##_r32_rbpdisp(XOP_REG(op,0),XOP_REG(op,1)+RBP_OFFSET); } \
9.68 + if( XOP_IS_FORM(op,DST,DST) ) { opname##_r32_r32(XOP_REG(op,0),XOP_REG(op,1)); } \
9.69 + else if( XOP_IS_FORM(op,SRC,DST) ) { opname##_r32disp_r32(REG_RBP, SRCADDR(op,0),XOP_REG(op,1)); } \
9.70 + else if( XOP_IS_FORM(op,DST,SRC) ) { opname##_r32_r32disp(XOP_REG(op,0),REG_RBP, SRCADDR(op,1)); } \
9.71 + else if( XOP_IS_FORM(op,TMP,DST) ) { opname##_r32disp_r32(REG_RSP, TMPADDR(op,0),XOP_REG(op,1)); } \
9.72 + else if( XOP_IS_FORM(op,DST,TMP) ) { opname##_r32_r32disp(XOP_REG(op,0),REG_RSP, TMPADDR(op,1)); } \
9.73 else { ILLOP(op); }
9.74
9.75 #define X86L_REG(opname,op) \
9.76 - if( XOP_IS_TGTREG(op,0) ) { opname##_r32(XOP_REG(op,0)); } \
9.77 - else if( XOP_IS_SRCREG(op,0) ) { opname##_rbpdisp(XOP_REG(op,0)+RBP_OFFSET); } \
9.78 + if( XOP_IS_DST(op,0) ) { opname##_r32(XOP_REG(op,0)); } \
9.79 + else if( XOP_IS_SRC(op,0) ) { opname##_r32disp(REG_RBP,SRCADDR(op,0)); } \
9.80 + else if( XOP_IS_TMP(op,0) ) { opname##_r32disp(REG_RSP,TMPADDR(op,0)); } \
9.81 else { ILLOP(op); }
9.82
9.83 #define X86L_CL_REG(opname,op) \
9.84 - if( XOP_IS_FORM(op,TGT,TGT) && XOP_REG(op,0) == REG_CL ) { opname##_cl_r32(XOP_REG(op,1)); } \
9.85 - else if( XOP_IS_FORM(op,TGT,SRC) && XOP_REG(op,0) == REG_CL ) { opname##_cl_rbpdisp(XOP_REG(op,1)+RBP_OFFSET); } \
9.86 + if( XOP_IS_FORM(op,DST,DST) && XOP_REG(op,0) == REG_CL ) { opname##_cl_r32(XOP_REG(op,1)); } \
9.87 + else if( XOP_IS_FORM(op,DST,SRC) && XOP_REG(op,0) == REG_CL ) { opname##_cl_r32disp(REG_RBP, SRCADDR(op,1)); } \
9.88 + else if( XOP_IS_FORM(op,DST,TMP) && XOP_REG(op,0) == REG_CL ) { opname##_cl_r32disp(REG_RSP, TMPADDR(op,1)); } \
9.89 else { ILLOP(op); }
9.90
9.91 #define X86L_IMMCL_REG(opname,op) \
9.92 - if( XOP_IS_FORM(op,IMM,TGT) ) { opname##_imm_r32(XOP_INT(op,0),XOP_REG(op,1)); } \
9.93 - else if( XOP_IS_FORM(op,IMM,SRC) ) { opname##_imm_rbpdisp(XOP_INT(op,0),XOP_REG(op,1)+RBP_OFFSET); } \
9.94 - else if( XOP_IS_FORM(op,TGT,TGT) && XOP_REG(op,0) == REG_CL ) { opname##_cl_r32(XOP_REG(op,1)); } \
9.95 - else if( XOP_IS_FORM(op,TGT,SRC) && XOP_REG(op,0) == REG_CL ) { opname##_cl_rbpdisp(XOP_REG(op,1)+RBP_OFFSET); } \
9.96 + if( XOP_IS_FORM(op,IMM,DST) ) { opname##_imm_r32(XOP_INT(op,0),XOP_REG(op,1)); } \
9.97 + else if( XOP_IS_FORM(op,IMM,SRC) ) { opname##_imm_r32disp(XOP_INT(op,0),REG_RBP, SRCADDR(op,1)); } \
9.98 + else if( XOP_IS_FORM(op,IMM,TMP) ) { opname##_imm_r32disp(XOP_INT(op,0),REG_RSP, TMPADDR(op,1)); } \
9.99 + else if( XOP_IS_FORM(op,DST,DST) && XOP_REG(op,0) == REG_CL ) { opname##_cl_r32(XOP_REG(op,1)); } \
9.100 + else if( XOP_IS_FORM(op,DST,SRC) && XOP_REG(op,0) == REG_CL ) { opname##_cl_r32disp(REG_RBP, SRCADDR(op,1)); } \
9.101 + else if( XOP_IS_FORM(op,DST,TMP) && XOP_REG(op,0) == REG_CL ) { opname##_cl_r32disp(REG_RSP, TMPADDR(op,1)); } \
9.102 else { ILLOP(op); }
9.103
9.104 // Standard ALU forms - imms,reg or reg,reg
9.105 #define X86L_ALU_REG(opname,op) \
9.106 - if( XOP_IS_FORM(op,IMM,TGT) ) { opname##_imms_r32(XOP_INT(op,0),XOP_REG(op,1)); } \
9.107 - else if( XOP_IS_FORM(op,IMM,SRC) ) { opname##_imms_rbpdisp(XOP_INT(op,0),XOP_REG(op,1)+RBP_OFFSET); } \
9.108 - else if( XOP_IS_FORM(op,TGT,TGT) ) { opname##_r32_r32(XOP_REG(op,0),XOP_REG(op,1)); } \
9.109 - else if( XOP_IS_FORM(op,SRC,TGT) ) { opname##_rbpdisp_r32(XOP_REG(op,0)+RBP_OFFSET,XOP_REG(op,1)); } \
9.110 - else if( XOP_IS_FORM(op,TGT,SRC) ) { opname##_r32_rbpdisp(XOP_REG(op,0),XOP_REG(op,1)+RBP_OFFSET); } \
9.111 + if( XOP_IS_FORM(op,IMM,DST) ) { opname##_imms_r32(XOP_INT(op,0),XOP_REG(op,1)); } \
9.112 + else if( XOP_IS_FORM(op,IMM,SRC) ) { opname##_imms_r32disp(XOP_INT(op,0),REG_RBP, SRCADDR(op,1)); } \
9.113 + else if( XOP_IS_FORM(op,IMM,TMP) ) { opname##_imms_r32disp(XOP_INT(op,0),REG_RSP, TMPADDR(op,1)); } \
9.114 + else if( XOP_IS_FORM(op,DST,DST) ) { opname##_r32_r32(XOP_REG(op,0),XOP_REG(op,1)); } \
9.115 + else if( XOP_IS_FORM(op,SRC,DST) ) { opname##_r32disp_r32(REG_RBP, SRCADDR(op,0),XOP_REG(op,1)); } \
9.116 + else if( XOP_IS_FORM(op,DST,SRC) ) { opname##_r32_r32disp(XOP_REG(op,0),REG_RBP, SRCADDR(op,1)); } \
9.117 + else if( XOP_IS_FORM(op,TMP,DST) ) { opname##_r32disp_r32(REG_RSP, TMPADDR(op,0),XOP_REG(op,1)); } \
9.118 + else if( XOP_IS_FORM(op,DST,TMP) ) { opname##_r32_r32disp(XOP_REG(op,0),REG_RSP, TMPADDR(op,1)); } \
9.119 else { ILLOP(op); }
9.120
9.121 uint32_t x86_target_get_code_size( xir_op_t begin, xir_op_t end )
9.122 @@ -194,17 +206,19 @@
9.123 /* No code to generate */
9.124 break;
9.125 case OP_MOV:
9.126 - if( XOP_IS_FORM(it, IMM, SRC) ) {
9.127 - MOVL_imm32_rbpdisp( XOP_INT(it,0), XOP_REG2(it)+RBP_OFFSET );
9.128 - } else if( XOP_IS_FORM(it, IMM, TGT) ) {
9.129 + if( XOP_IS_FORM(it, IMM, DST) ) {
9.130 MOVL_imm32_r32( XOP_INT(it,0), XOP_REG2(it) );
9.131 - } else if( XOP_IS_FORM(it, TGT, SRC) ) {
9.132 + } else if( XOP_IS_FORM(it, IMM, SRC) ) {
9.133 + MOVL_imm32_r32disp( XOP_INT(it,0), REG_RBP, SRCADDR(it,1) );
9.134 + } else if( XOP_IS_FORM(it, IMM, TMP) ) {
9.135 + MOVL_imm32_r32disp( XOP_INT(it,0), REG_RSP, TMPADDR(it,1) );
9.136 + } else if( XOP_IS_FORM(it, DST, SRC) ) {
9.137 if( IS_XMM_REG(it,0) ) {
9.138 - MOVSS_xmm_rbpdisp( XOP_REG1(it), XOP_REG2(it)+RBP_OFFSET );
9.139 + MOVSS_xmm_r32disp( XOP_REG1(it), REG_RBP, SRCADDR(it,1) );
9.140 } else {
9.141 - MOVL_r32_rbpdisp( XOP_REG1(it), XOP_REG2(it)+RBP_OFFSET );
9.142 + MOVL_r32_r32disp( XOP_REG1(it), REG_RBP, SRCADDR(it,1) );
9.143 }
9.144 - } else if( XOP_IS_FORM(it, TGT, TGT) ) {
9.145 + } else if( XOP_IS_FORM(it, DST, DST) ) {
9.146 if( IS_XMM_REG(it,0) ) {
9.147 if( IS_XMM_REG(it,1) ) {
9.148 MOVSS_xmm_xmm( XOP_REG1(it), XOP_REG2(it) );
9.149 @@ -216,11 +230,11 @@
9.150 } else {
9.151 MOVL_r32_r32( XOP_REG1(it), XOP_REG2(it) );
9.152 }
9.153 - } else if( XOP_IS_FORM(it, SRC, TGT) ) {
9.154 + } else if( XOP_IS_FORM(it, SRC, DST) ) {
9.155 if( IS_XMM_REG(it,1) ) {
9.156 - MOVSS_rbpdisp_xmm( XOP_REG1(it)+RBP_OFFSET, XOP_REG2(it) );
9.157 + MOVSS_r32disp_xmm( REG_RBP, SRCADDR(it,0), XOP_REG2(it) );
9.158 } else {
9.159 - MOVL_rbpdisp_r32( XOP_REG1(it)+RBP_OFFSET, XOP_REG2(it) );
9.160 + MOVL_r32disp_r32( REG_RBP, SRCADDR(it,0), XOP_REG2(it) );
9.161 }
9.162 } else {
9.163 ILLOP(it);
9.164 @@ -229,7 +243,7 @@
9.165 case OP_MOVQ:
9.166 if( XOP_IS_FORM(it, IMM, SRC) ) {
9.167 ILLOP(it);
9.168 - } else if( XOP_IS_FORM(it, IMM, TGT) ) {
9.169 + } else if( XOP_IS_FORM(it, IMM, DST) ) {
9.170 if( IS_XMM_REG(it,0) ) {
9.171 if( XOP_INT(it,0) == 0 ) {
9.172 XORPD_xmm_xmm( XOP_REG2(it), XOP_REG2(it) );
9.173 @@ -237,13 +251,13 @@
9.174 } else {
9.175 MOVQ_imm64_r64( XOP_INT(it,0), XOP_REG2(it) );
9.176 }
9.177 - } else if( XOP_IS_FORM(it, TGT, SRC) ) {
9.178 + } else if( XOP_IS_FORM(it, DST, SRC) ) {
9.179 if( IS_XMM_REG(it,0) ) {
9.180 - MOVSD_xmm_rbpdisp( XOP_REG1(it), XOP_REG2(it)+RBP_OFFSET );
9.181 + MOVSD_xmm_r32disp( XOP_REG1(it), REG_RBP, SRCADDR(it,1) );
9.182 } else {
9.183 - MOVQ_r64_rbpdisp( XOP_REG1(it), XOP_REG2(it)+RBP_OFFSET );
9.184 + MOVQ_r64_r64disp( XOP_REG1(it), REG_RBP, SRCADDR(it,1) );
9.185 }
9.186 - } else if( XOP_IS_FORM(it, TGT, TGT) ) {
9.187 + } else if( XOP_IS_FORM(it, DST, DST) ) {
9.188 if( IS_XMM_REG(it,0) ) {
9.189 if( IS_XMM_REG(it,1) ) {
9.190 MOVSD_xmm_xmm( XOP_REG1(it), XOP_REG2(it) );
9.191 @@ -255,48 +269,48 @@
9.192 } else {
9.193 MOVQ_r64_r64( XOP_REG1(it), XOP_REG2(it) );
9.194 }
9.195 - } else if( XOP_IS_FORM(it, SRC, TGT) ) {
9.196 + } else if( XOP_IS_FORM(it, SRC, DST) ) {
9.197 if( IS_XMM_REG(it,1) ) {
9.198 - MOVSD_rbpdisp_xmm( XOP_REG1(it)+RBP_OFFSET, XOP_REG2(it) );
9.199 + MOVSD_r32disp_xmm( REG_RBP, SRCADDR(it,0), XOP_REG2(it) );
9.200 } else {
9.201 - MOVQ_rbpdisp_r64( XOP_REG1(it)+RBP_OFFSET, XOP_REG2(it) );
9.202 + MOVQ_r64disp_r64( REG_RBP, SRCADDR(it,0), XOP_REG2(it) );
9.203 }
9.204 } else {
9.205 ILLOP(it);
9.206 }
9.207 break;
9.208 case OP_MOVSX8:
9.209 - if( XOP_IS_FORM(it, TGT, TGT) ) {
9.210 + if( XOP_IS_FORM(it, DST, DST) ) {
9.211 MOVSXL_r8_r32( XOP_REG1(it), XOP_REG2(it) );
9.212 - } else if( XOP_IS_FORM(it, SRC, TGT) ) {
9.213 - MOVSXL_rbpdisp8_r32( XOP_REG1(it)+RBP_OFFSET, XOP_REG2(it) );
9.214 + } else if( XOP_IS_FORM(it, SRC, DST) ) {
9.215 + MOVSXL_r32disp8_r32( REG_RBP, SRCADDR(it,0), XOP_REG2(it) );
9.216 } else {
9.217 ILLOP(it);
9.218 }
9.219 break;
9.220 case OP_MOVSX16:
9.221 - if( XOP_IS_FORM(it, TGT, TGT) ) {
9.222 + if( XOP_IS_FORM(it, DST, DST) ) {
9.223 MOVSXL_r16_r32( XOP_REG1(it), XOP_REG2(it) );
9.224 - } else if( XOP_IS_FORM(it, SRC, TGT) ) {
9.225 - MOVSXL_rbpdisp16_r32( XOP_REG1(it)+RBP_OFFSET, XOP_REG2(it) );
9.226 + } else if( XOP_IS_FORM(it, SRC, DST) ) {
9.227 + MOVSXL_r32disp16_r32( REG_RBP, SRCADDR(it,0), XOP_REG2(it) );
9.228 } else {
9.229 ILLOP(it);
9.230 }
9.231 break;
9.232 case OP_MOVZX8:
9.233 - if( XOP_IS_FORM(it, TGT, TGT) ) {
9.234 + if( XOP_IS_FORM(it, DST, DST) ) {
9.235 MOVZXL_r8_r32( XOP_REG1(it), XOP_REG2(it) );
9.236 - } else if( XOP_IS_FORM(it, SRC, TGT) ) {
9.237 - MOVZXL_rbpdisp8_r32( XOP_REG1(it)+RBP_OFFSET, XOP_REG2(it) );
9.238 + } else if( XOP_IS_FORM(it, SRC, DST) ) {
9.239 + MOVZXL_r32disp8_r32( REG_RBP, SRCADDR(it,0), XOP_REG2(it) );
9.240 } else {
9.241 ILLOP(it);
9.242 }
9.243 break;
9.244 case OP_MOVZX16:
9.245 - if( XOP_IS_FORM(it, TGT, TGT) ) {
9.246 + if( XOP_IS_FORM(it, DST, DST) ) {
9.247 MOVZXL_r16_r32( XOP_REG1(it), XOP_REG2(it) );
9.248 - } else if( XOP_IS_FORM(it, SRC, TGT) ) {
9.249 - MOVZXL_rbpdisp16_r32( XOP_REG1(it)+RBP_OFFSET, XOP_REG2(it) );
9.250 + } else if( XOP_IS_FORM(it, SRC, DST) ) {
9.251 + MOVZXL_r32disp16_r32( REG_RBP, SRCADDR(it,0), XOP_REG2(it) );
9.252 } else {
9.253 ILLOP(it);
9.254 }
9.255 @@ -308,16 +322,16 @@
9.256 case OP_CMP:
9.257 X86L_ALU_REG(CMPL,it); break;
9.258 case OP_DEC:
9.259 - if( XOP_IS_FORM(it,TGT,NONE) ) {
9.260 + if( XOP_IS_FORM(it,DST,NONE) ) {
9.261 DECL_r32(XOP_REG(it,0));
9.262 } else if( XOP_IS_FORM(it,SRC,NONE) ) {
9.263 - DECL_rbpdisp(XOP_REG(it,0)+RBP_OFFSET);
9.264 + DECL_r32disp( REG_RBP, SRCADDR(it,0) );
9.265 } else {
9.266 ILLOP(it);
9.267 }
9.268 break;
9.269 case OP_MUL:
9.270 - X86L_REG_TGT(IMULL,it);
9.271 + X86L_REG_DST(IMULL,it);
9.272 break;
9.273 case OP_NEG: X86L_REG(NEGL,it); break;
9.274 case OP_NOT: X86L_REG(NOTL,it); break;
9.275 @@ -336,7 +350,7 @@
9.276 case OP_SUB:
9.277 case OP_SUBS: X86L_ALU_REG(SUBL,it); break;
9.278 case OP_SHUFFLE:
9.279 - if( XOP_IS_FORM(it,IMM,TGT) ) {
9.280 + if( XOP_IS_FORM(it,IMM,DST) ) {
9.281 if( XOP_INT(it,0) == 0x4321 ) {
9.282 BSWAPL_r32( XOP_REG(it,1) );
9.283 } else if( it->operand[1].value.i == 0x1243 ) {
9.284 @@ -353,63 +367,63 @@
9.285 case OP_ABSD:
9.286 // Why is there no SSE FP ABS instruction?
9.287 break;
9.288 - case OP_ADDF: X86F_REG_TGT(ADDSS,it); break;
9.289 - case OP_ADDD: X86F_REG_TGT(ADDSD,it); break;
9.290 + case OP_ADDF: X86F_REG_DST(ADDSS,it); break;
9.291 + case OP_ADDD: X86F_REG_DST(ADDSD,it); break;
9.292 case OP_CMPF:
9.293 break;
9.294 case OP_CMPD: // UCOMISD
9.295 break;
9.296 - case OP_DIVF: X86F_REG_TGT(DIVSS,it); break;
9.297 - case OP_DIVD: X86F_REG_TGT(DIVSD,it); break;
9.298 - case OP_MULF: X86F_REG_TGT(MULSS,it); break;
9.299 - case OP_MULD: X86F_REG_TGT(MULSD,it); break;
9.300 - case OP_RSQRTF:X86F_REG_TGT(RSQRTSS,it); break;
9.301 - case OP_SQRTF: X86F_REG_TGT(SQRTSS,it); break;
9.302 - case OP_SQRTD: X86F_REG_TGT(SQRTSD,it); break;
9.303 - case OP_SUBF: X86F_REG_TGT(SUBSS,it); break;
9.304 - case OP_SUBD: X86F_REG_TGT(SUBSD,it); break;
9.305 + case OP_DIVF: X86F_REG_DST(DIVSS,it); break;
9.306 + case OP_DIVD: X86F_REG_DST(DIVSD,it); break;
9.307 + case OP_MULF: X86F_REG_DST(MULSS,it); break;
9.308 + case OP_MULD: X86F_REG_DST(MULSD,it); break;
9.309 + case OP_RSQRTF:X86F_REG_DST(RSQRTSS,it); break;
9.310 + case OP_SQRTF: X86F_REG_DST(SQRTSS,it); break;
9.311 + case OP_SQRTD: X86F_REG_DST(SQRTSD,it); break;
9.312 + case OP_SUBF: X86F_REG_DST(SUBSS,it); break;
9.313 + case OP_SUBD: X86F_REG_DST(SUBSD,it); break;
9.314
9.315 case OP_DOTPRODV:
9.316 - MULPS_rbpdisp_xmm( XOP_REG1(it), 4 );
9.317 + MULPS_r32disp_xmm( REG_RBP, SRCADDR(it,0), 4 );
9.318 HADDPS_xmm_xmm( 4, 4 );
9.319 HADDPS_xmm_xmm( 4, 4 );
9.320 - MOVSS_xmm_rbpdisp( 4, XOP_REG1(it) );
9.321 + MOVSS_xmm_r32disp( 4, REG_RBP, SRCADDR(it,0) );
9.322 break;
9.323 case OP_SINCOSF:
9.324 case OP_MATMULV:
9.325 break;
9.326 case OP_FTOD:
9.327 - if( XOP_IS_FORM(it,TGT,TGT) ) {
9.328 + if( XOP_IS_FORM(it,DST,DST) ) {
9.329 CVTSS2SD_xmm_xmm( XOP_REG(it,0), XOP_REG(it,1) );
9.330 - } else if( XOP_IS_FORM(it,SRC,TGT) ) {
9.331 - CVTSS2SD_rbpdisp_xmm( XOP_REG(it,0)+RBP_OFFSET, XOP_REG(it,1) );
9.332 + } else if( XOP_IS_FORM(it,SRC,DST) ) {
9.333 + CVTSS2SD_r32disp_xmm( REG_RBP, SRCADDR(it,0), XOP_REG(it,1) );
9.334 } else {
9.335 ILLOP(it);
9.336 }
9.337 break;
9.338 case OP_DTOF:
9.339 - if( XOP_IS_FORM(it,TGT,TGT) ) {
9.340 + if( XOP_IS_FORM(it,DST,DST) ) {
9.341 CVTSS2SD_xmm_xmm( XOP_REG(it,0), XOP_REG(it,1) );
9.342 - } else if( XOP_IS_FORM(it, SRC,TGT) ) {
9.343 - CVTSS2SD_rbpdisp_xmm( XOP_REG(it,0)+RBP_OFFSET, XOP_REG(it,1) );
9.344 + } else if( XOP_IS_FORM(it, SRC,DST) ) {
9.345 + CVTSS2SD_r32disp_xmm( REG_RBP, SRCADDR(it,0), XOP_REG(it,1) );
9.346 } else {
9.347 ILLOP(it);
9.348 }
9.349 break;
9.350 case OP_ITOD:
9.351 - if( XOP_IS_FORM(it,TGT,TGT) ) {
9.352 + if( XOP_IS_FORM(it,DST,DST) ) {
9.353 CVTSI2SDL_r32_xmm( XOP_REG(it,0), XOP_REG(it,1) );
9.354 - } else if( XOP_IS_FORM(it,SRC,TGT) ) {
9.355 - CVTSI2SDL_rbpdisp_xmm( XOP_REG(it,0)+RBP_OFFSET, XOP_REG(it,1) );
9.356 + } else if( XOP_IS_FORM(it,SRC,DST) ) {
9.357 + CVTSI2SDL_r32disp_xmm( REG_RBP, SRCADDR(it,0), XOP_REG(it,1) );
9.358 } else {
9.359 ILLOP(it);
9.360 }
9.361 break;
9.362 case OP_DTOI:
9.363 - if( XOP_IS_FORM(it,TGT,TGT) ) {
9.364 + if( XOP_IS_FORM(it,DST,DST) ) {
9.365 CVTSD2SIL_xmm_r32( XOP_REG(it,0), XOP_REG(it,1) );
9.366 - } else if( XOP_IS_FORM(it,SRC,TGT) ) {
9.367 - CVTSD2SIL_rbpdisp_r32( XOP_REG(it,0)+RBP_OFFSET, XOP_REG(it,1) );
9.368 + } else if( XOP_IS_FORM(it,SRC,DST) ) {
9.369 + CVTSD2SIL_r32disp_r32( REG_RBP, SRCADDR(it,0), XOP_REG(it,1) );
9.370 } else {
9.371 ILLOP(it);
9.372 }
9.373 @@ -423,9 +437,9 @@
9.374 case OP_BRCONDDEL:
9.375
9.376 case OP_CALL0:
9.377 - if( XOP_IS_INTIMM(it,0) ) {
9.378 + if( XOP_IS_IMM(it,0) ) {
9.379 CALL_imm32( XOP_INT(it,0) );
9.380 - } else if( XOP_IS_SRCREG(it,0) ) {
9.381 + } else if( XOP_IS_SRC(it,0) ) {
9.382 CALL_r32( XOP_INT(it,0) );
9.383 } else {
9.384 ILLOP(it);
9.385 @@ -437,20 +451,20 @@
9.386 } else {
9.387 ss = 2;
9.388 }
9.389 - if( XOP_IS_FORM(it,IMM,TGT) ) {
9.390 + if( XOP_IS_FORM(it,IMM,DST) ) {
9.391 MOVP_sib_rptr(ss, XOP_REG(it,1), -1, XOP_INT(it,0), XOP_REG(it,1));
9.392 - } else if( XOP_IS_FORM(it,TGT,TGT) ) {
9.393 + } else if( XOP_IS_FORM(it,DST,DST) ) {
9.394 MOVP_sib_rptr(ss, XOP_REG(it,1), XOP_REG(it,0), 0, XOP_REG(it,1));
9.395 } else {
9.396 ILLOP(it);
9.397 }
9.398 break;
9.399 case OP_CALLLUT:
9.400 - if( XOP_IS_FORM(it,TGT,IMM) ) {
9.401 + if( XOP_IS_FORM(it,DST,IMM) ) {
9.402 CALL_r32disp(XOP_REG(it,0),XOP_INT(it,1));
9.403 - } else if( XOP_IS_FORM(it,TGT,TGT) ) {
9.404 + } else if( XOP_IS_FORM(it,DST,DST) ) {
9.405 CALL_sib(0,XOP_REG(it,0),XOP_REG(it,1),0);
9.406 - } else if( XOP_IS_FORM(it,IMM,TGT) ) {
9.407 + } else if( XOP_IS_FORM(it,IMM,DST) ) {
9.408 CALL_r32disp(XOP_REG(it,1),XOP_INT(it,0));
9.409 } else {
9.410 ILLOP(it);
9.411 @@ -467,14 +481,14 @@
9.412 case OP_DIV1:
9.413 break;
9.414 case OP_SHAD:
9.415 - assert( it->operand[0].type == TGT && XOP_REG(it,0) == REG_ECX );
9.416 + assert( it->operand[0].form == DST && XOP_REG(it,0) == REG_ECX );
9.417 CMPL_imms_r32(0,REG_ECX);
9.418 JNGE_label(shad_shr);
9.419 X86L_CL_REG(SHLL,it);
9.420 JMP_label(shad_end);
9.421
9.422 JMP_TARGET(shad_shr);
9.423 - if( IS_X86_64() && it->operand[1].type == TGT ) {
9.424 + if( IS_X86_64() && it->operand[1].form == DST ) {
9.425 /* We can do this a little more simply with a 64-bit shift */
9.426 ORL_imms_r32(0xFFFFFFE0,REG_ECX);
9.427 NEGL_r32(REG_ECX);
9.428 @@ -488,10 +502,12 @@
9.429 JMP_label(shad_end2);
9.430
9.431 JMP_TARGET(emptyshr);
9.432 - if( it->operand[1].type == TGT ) {
9.433 + if( it->operand[1].form == DST ) {
9.434 SARL_imm_r32( 31, XOP_REG(it,1) );
9.435 + } else if( it->operand[1].form == SRC ) {
9.436 + SARL_imm_r32disp( 32, REG_RBP, SRCADDR(it,1) );
9.437 } else {
9.438 - SARL_imm_rbpdisp( 32, XOP_REG(it,1)+RBP_OFFSET );
9.439 + SARL_imm_r32disp( 32, REG_RSP, TMPADDR(it,1) );
9.440 }
9.441 JMP_TARGET(shad_end2);
9.442 }
9.443 @@ -499,14 +515,14 @@
9.444 break;
9.445
9.446 case OP_SHLD:
9.447 - assert( it->operand[0].type == TGT && XOP_REG(it,0) == REG_ECX );
9.448 + assert( it->operand[0].form == DST && XOP_REG(it,0) == REG_ECX );
9.449 CMPL_imms_r32(0,REG_ECX);
9.450 JNGE_label(shld_shr);
9.451 X86L_CL_REG(SHLL,it);
9.452 JMP_label(shld_end);
9.453
9.454 JMP_TARGET(shld_shr);
9.455 - if( IS_X86_64() && it->operand[1].type == TGT ) {
9.456 + if( IS_X86_64() && it->operand[1].form == DST ) {
9.457 /* We can do this a little more simply with a 64-bit shift */
9.458 ORL_imms_r32(0xFFFFFFE0,REG_ECX);
9.459 NEGL_r32(REG_ECX);
10.1 --- a/src/xlat/x86/x86op.h Tue Apr 07 10:55:03 2009 +0000
10.2 +++ b/src/xlat/x86/x86op.h Sun Apr 12 07:24:45 2009 +0000
10.3 @@ -317,16 +317,16 @@
10.4 #define x86_encode_r32_mem32(opcode,rr,rb,rx,ss,disp32) x86_encode_modrm(0,opcode,rr,rb,rx,ss,disp32)
10.5 #define x86_encode_r64_mem64(opcode,rr,rb,rx,ss,disp32) x86_encode_modrm(PREF_REXW,opcode,rr,rb,rx,ss,disp32)
10.6 #define x86_encode_rptr_memptr(opcode,rr,rb,rx,ss,disp32) x86_encode_modrm(PREF_PTR,opcode,rr,rb,rx,ss,disp32)
10.7 -#define x86_encode_r32_mem32disp32(opcode,rr,rb,disp32) x86_encode_modrm(0,opcode,rr,rb,-1,0,disp32)
10.8 -#define x86_encode_r64_mem64disp64(opcode,rr,rb,disp32) x86_encode_modrm(PREF_REXW,opcode,rr,rb,-1,0,disp32)
10.9 +#define x86_encode_r32_r32disp32(opcode,rr,rb,disp32) x86_encode_modrm(0,opcode,rr,rb,-1,0,disp32)
10.10 +#define x86_encode_r64_r64disp32(opcode,rr,rb,disp32) x86_encode_modrm(PREF_REXW,opcode,rr,rb,-1,0,disp32)
10.11 #define x86_encode_r32_ripdisp32(opcode,rr,disp32) x86_encode_modrm_rip(0,opcode,rr,disp32)
10.12 #define x86_encode_r64_ripdisp64(opcode,rr,disp32) x86_encode_modrm_rip(PREF_REXW,opcode,rr,disp32)
10.13
10.14 /* Convenience versions for the common rbp/rsp relative displacements */
10.15 #define x86_encode_r32_rbpdisp32(opcode,rr,disp32) x86_encode_modrm(0,opcode,rr,REG_RBP,-1,0,disp32)
10.16 -#define x86_encode_r64_rbpdisp64(opcode,rr,disp32) x86_encode_modrm(PREF_REXW,opcode,rr,REG_RBP,-1,0,disp32)
10.17 +#define x86_encode_r64_rbpdisp32(opcode,rr,disp32) x86_encode_modrm(PREF_REXW,opcode,rr,REG_RBP,-1,0,disp32)
10.18 #define x86_encode_r32_rspdisp32(opcode,rr,disp32) x86_encode_modrm(0,opcode,rr,REG_RSP,-1,0,disp32)
10.19 -#define x86_encode_r64_rspdisp64(opcode,rr,disp32) x86_encode_modrm(PREF_REXW,opcode,rr,REG_RSP,-1,0,disp32)
10.20 +#define x86_encode_r64_rspdisp32(opcode,rr,disp32) x86_encode_modrm(PREF_REXW,opcode,rr,REG_RSP,-1,0,disp32)
10.21
10.22 /* Immediate-selection variants (for instructions with imm8s/imm32 variants) */
10.23 #define x86_encode_imms_rm32(opcode8,opcode32,reg,imm,rb) \
10.24 @@ -342,11 +342,11 @@
10.25 if( IS_INT8(((int32_t)imm)) ) { x86_encode_r32_rbpdisp32(opcode8,reg,disp); OP((int8_t)imm); \
10.26 } else { x86_encode_r32_rbpdisp32(opcode32,reg,disp); OP32(imm); }
10.27 #define x86_encode_imms_r32disp32(opcode8,opcode32,reg,imm,rb,disp) \
10.28 - if( IS_INT8(((int32_t)imm)) ) { x86_encode_r32_mem32disp32(opcode8,reg,rb,disp); OP((int8_t)imm); \
10.29 - } else { x86_encode_r32_mem32disp32(opcode32,reg,rb,disp); OP32(imm); }
10.30 -#define x86_encode_imms_rbpdisp64(opcode8,opcode32,reg,imm,disp) \
10.31 - if( IS_INT8(((int32_t)imm)) ) { x86_encode_r64_rbpdisp64(opcode8,reg,disp); OP((int8_t)imm); \
10.32 - } else { x86_encode_r64_rbpdisp64(opcode32,reg,disp); OP32(imm); }
10.33 + if( IS_INT8(((int32_t)imm)) ) { x86_encode_r32_r32disp32(opcode8,reg,rb,disp); OP((int8_t)imm); \
10.34 + } else { x86_encode_r32_r32disp32(opcode32,reg,rb,disp); OP32(imm); }
10.35 +#define x86_encode_imms_r64disp32(opcode8,opcode32,reg,imm,rb,disp) \
10.36 + if( IS_INT8(((int32_t)imm)) ) { x86_encode_r64_r64disp32(opcode8,reg,rb,disp); OP((int8_t)imm); \
10.37 + } else { x86_encode_r64_r64disp32(opcode32,reg,rb,disp); OP32(imm); }
10.38
10.39 /*************************** Instruction definitions ***********************/
10.40 /* Note this does not try to be an exhaustive definition of the instruction -
10.41 @@ -356,9 +356,12 @@
10.42 #define ADCB_imms_r8(imm,r1) x86_encode_r32_rm32(0x80, 2, r1); OP(imm)
10.43 #define ADCB_r8_r8(r1,r2) x86_encode_r32_rm32(0x10, r1, r2)
10.44 #define ADCL_imms_r32(imm,r1) x86_encode_imms_rm32(0x83, 0x81, 2, imm, r1)
10.45 +#define ADCL_imms_r32disp(imm,rb,d) x86_encode_imms_r32disp32(0x83, 0x81, 2, imm, rb, d)
10.46 #define ADCL_imms_rbpdisp(imm,disp) x86_encode_imms_rbpdisp32(0x83, 0x81, 2, imm, disp)
10.47 #define ADCL_r32_r32(r1,r2) x86_encode_r32_rm32(0x11, r1, r2)
10.48 +#define ADCL_r32_r32disp(r1,rb,d) x86_encode_r32_r32disp32(0x11, r1, rb, d)
10.49 #define ADCL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x11, r1, disp)
10.50 +#define ADCL_r32disp_r32(rb,disp,r1) x86_encode_r32_r32disp32(0x13, r1, rb, disp)
10.51 #define ADCL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x13, r1, disp)
10.52 #define ADCQ_imms_r64(imm,r1) x86_encode_imms_rm64(0x83, 0x81, 2, imm, r1)
10.53 #define ADCQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x11, r1, r2)
10.54 @@ -369,8 +372,9 @@
10.55 #define ADDL_imms_r32disp(imm,rb,d) x86_encode_imms_r32disp32(0x83, 0x81, 0, imm, rb, d)
10.56 #define ADDL_imms_rbpdisp(imm,disp) x86_encode_imms_rbpdisp32(0x83, 0x81, 0, imm, disp)
10.57 #define ADDL_r32_r32(r1,r2) x86_encode_r32_rm32(0x01, r1, r2)
10.58 +#define ADDL_r32_r32disp(r1,r2,dsp) x86_encode_r32_r32disp32(0x01, r1, r2, dsp)
10.59 #define ADDL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x01, r1, disp)
10.60 -#define ADDL_r32_r32disp(r1,r2,dsp) x86_encode_r32_mem32disp32(0x01, r1, r2, dsp)
10.61 +#define ADDL_r32disp_r32(rb,disp,r1) x86_encode_r32_r32disp32(0x03, r1, rb, disp)
10.62 #define ADDL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x03, r1, disp)
10.63 #define ADDQ_imms_r64(imm,r1) x86_encode_imms_rm64(0x83, 0x81, 0, imm, r1)
10.64 #define ADDQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x01, r1, r2)
10.65 @@ -378,9 +382,12 @@
10.66 #define ANDB_imms_r8(imm,r1) x86_encode_r32_rm32(0x80, 4, r1); OP(imm)
10.67 #define ANDB_r8_r8(r1,r2) x86_encode_r32_rm32(0x20, r1, r2)
10.68 #define ANDL_imms_r32(imm,r1) x86_encode_imms_rm32(0x83, 0x81, 4, imm, r1)
10.69 +#define ANDL_imms_r32disp(imm,rb,d) x86_encode_imms_r32disp32(0x83,0x81,4,imm,rb,d)
10.70 #define ANDL_imms_rbpdisp(imm,disp) x86_encode_imms_rbpdisp32(0x83,0x81,4,imm,disp)
10.71 #define ANDL_r32_r32(r1,r2) x86_encode_r32_rm32(0x21, r1, r2)
10.72 +#define ANDL_r32_r32disp(r1,rb,d) x86_encode_r32_r32disp32(0x21, r1, rb, d)
10.73 #define ANDL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x21, r1, disp)
10.74 +#define ANDL_r32disp_r32(rb,d,r1) x86_encode_r32_r32disp32(0x23, r1, rb, d)
10.75 #define ANDL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x23, r1, disp)
10.76 #define ANDQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x21, r1, r2)
10.77 #define ANDQ_imms_r64(imm,r1) x86_encode_imms_rm64(0x83, 0x81, 4, imm, r1)
10.78 @@ -393,16 +400,21 @@
10.79 #define CLD() OP(0xFC)
10.80 #define CMC() OP(0xF5)
10.81
10.82 -#define CMOVCCL_cc_r32_r32(cc,r1,r2) x86_encode_r32_rm32(0x0F40+(cc), r2, r1)
10.83 -#define CMOVCCL_cc_rbpdisp_r32(cc,d,r1) x86_encode_r32_rbpdisp32(0x0F40+(cc), r1, d)
10.84 +#define CMOVCCL_cc_r32_r32(cc,r1,r2) x86_encode_r32_rm32(0x0F40+(cc), r2, r1)
10.85 +#define CMOVCCL_cc_r32disp_r32(cc,rb,d,r1) x86_encode_r32_r32disp32(0x0F40+(cc), r1, rb, d)
10.86 +#define CMOVCCL_cc_rbpdisp_r32(cc,d,r1) x86_encode_r32_rbpdisp32(0x0F40+(cc), r1, d)
10.87
10.88 #define CMPB_imms_r8(imm,r1) x86_encode_r32_rm32(0x80, 7, r1); OP(imm)
10.89 +#define CMPB_imms_r32disp(imm,rb,d) x86_encode_r32_r32disp32(0x80, 7, rb, d); OP(imm)
10.90 #define CMPB_imms_rbpdisp(imm,disp) x86_encode_r32_rbpdisp32(0x80, 7, disp); OP(imm)
10.91 #define CMPB_r8_r8(r1,r2) x86_encode_r32_rm32(0x38, r1, r2)
10.92 #define CMPL_imms_r32(imm,r1) x86_encode_imms_rm32(0x83, 0x81, 7, imm, r1)
10.93 +#define CMPL_imms_r32disp(imm,rb,d) x86_encode_imms_r32disp32(0x83, 0x81, 7, imm, rb, d)
10.94 #define CMPL_imms_rbpdisp(imm,disp) x86_encode_imms_rbpdisp32(0x83, 0x81, 7, imm, disp)
10.95 #define CMPL_r32_r32(r1,r2) x86_encode_r32_rm32(0x39, r1, r2)
10.96 +#define CMPL_r32_r32disp(r1,rb,d) x86_encode_r32_r32disp32(0x39, r1, rb, d)
10.97 #define CMPL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x39, r1, disp)
10.98 +#define CMPL_r32disp_r32(rb,d,r1) x86_encode_r32_r32disp32(0x3B, r1, rb, d)
10.99 #define CMPL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x3B, r1, disp)
10.100 #define CMPQ_imms_r64(imm,r1) x86_encode_imms_rm64(0x83, 0x81, 7, imm, r1)
10.101 #define CMPQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x39, r1, r2)
10.102 @@ -411,60 +423,71 @@
10.103 #define CDOQ() OP(PREF_REXW); OP(0x99)
10.104
10.105 #define DECL_r32(r1) x86_encode_r32_rm32(0xFF,1,r1) /* NB single-op form unavailable in 64-bit mode */
10.106 +#define DECL_r32disp(rb,d) x86_encode_r32_r32disp32(0xFF,1,rb,d)
10.107 #define DECL_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xFF,1,disp)
10.108 #define DECQ_r64(r1) x86_encode_r64_rm64(0xFF,1,r1)
10.109 -#define DECQ_rbpdisp(disp) x86_encode_r64_rbpdisp64(0xFF,1,disp)
10.110 +#define DECQ_r64disp(rb,d) x86_encode_r64_r64disp32(0xFF,1,rb,d)
10.111 +#define DECQ_rbpdisp(disp) x86_encode_r64_rbpdisp32(0xFF,1,disp)
10.112
10.113 #define IDIVL_r32(r1) x86_encode_r32_rm32(0xF7, 7, r1)
10.114 +#define IDIVL_r32disp(rb,d) x86_encode_r32_r32disp32(0xF7, 7, rb, d)
10.115 #define IDIVL_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xF7, 7, disp)
10.116 #define IDIVQ_r64(r1) x86_encode_r64_rm64(0xF7, 7, r1)
10.117
10.118 #define IMULL_imms_r32(imm,r1) x86_encode_imms_rm32(0x6B,0x69, r1, imm, r1)
10.119 #define IMULL_r32(r1) x86_encode_r32_rm32(0xF7, 5, r1)
10.120 #define IMULL_r32_r32(r1,r2) x86_encode_r32_rm32(0x0FAF, r2, r1)
10.121 +#define IMULL_r32disp(rb,d) x86_encode_r32_r32disp32(0xF7, 5, rb, d)
10.122 +#define IMULL_r32disp_r32(rb,d,r1) x86_encode_r32_r32disp32(0x0FAF, r1, rb, d)
10.123 #define IMULL_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xF7, 5, disp)
10.124 #define IMULL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x0FAF, r1, disp)
10.125 #define IMULL_rspdisp(disp) x86_encode_r32_rspdisp32(0xF7, 5, disp)
10.126 #define IMULL_rspdisp_r32(disp,r1) x86_encode_r32_rspdisp32(0x0FAF, r1, disp)
10.127 #define IMULQ_imms_r64(imm,r1) x86_encode_imms_rm64(0x6B,0x69, r1, imm, r1)
10.128 #define IMULQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x0FAF, r2, r1)
10.129 -#define IMULQ_rbpdisp_r64(disp,r1) x86_encode_r64_rbpdisp64(0x0FAF, r1, disp)
10.130 +#define IMULQ_r64disp_r64(rb,d,r1) x86_encode_r64_r64disp32(0x0FAF, r1, rb, d)
10.131 +#define IMULQ_rbpdisp_r64(disp,r1) x86_encode_r64_rbpdisp32(0x0FAF, r1, disp)
10.132
10.133 #define INCL_r32(r1) x86_encode_r32_rm32(0xFF,0,r1) /* NB single-op form unavailable in 64-bit mode */
10.134 +#define INCL_r32disp(rb,d) x86_encode_r32_r32disp32(0xFF,0,rb,d)
10.135 #define INCL_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xFF,0,disp)
10.136 #define INCQ_r64(r1) x86_encode_r64_rm64(0xFF,0,r1)
10.137 -#define INCQ_rbpdisp(disp) x86_encode_r64_rbpdisp64(0xFF,0,disp)
10.138 +#define INCQ_r64disp(rb,d) x86_encode_r64_r64disp32(0xFF,0,rb,d)
10.139 +#define INCQ_rbpdisp(disp) x86_encode_r64_rbpdisp32(0xFF,0,disp)
10.140
10.141 #define LEAL_r32disp_r32(r1,disp,r2) x86_encode_r32_mem32(0x8D, r2, r1, -1, 0, disp)
10.142 #define LEAL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x8D, r1, disp)
10.143 #define LEAL_sib_r32(ss,ii,bb,d,r1) x86_encode_r32_mem32(0x8D, r1, bb, ii, ss, d)
10.144 -#define LEAQ_r64disp_r64(r1,disp,r2) x86_encode_r64_mem64(0x8D, r2, r1, -1, 0, disp)
10.145 -#define LEAQ_rbpdisp_r64(disp,r1) x86_encode_r64_rbpdisp64(0x8D, r1, disp)
10.146 +#define LEAQ_r64disp_r64(r1,disp,r2) x86_encode_r64_r64disp32(0x8D, r2, r1, disp)
10.147 +#define LEAQ_rbpdisp_r64(disp,r1) x86_encode_r64_rbpdisp32(0x8D, r1, disp)
10.148 #define LEAP_rptrdisp_rptr(r1,d,r2) x86_encode_rptr_memptr(0x8D, r2, r1, -1, 0, disp)
10.149 #define LEAP_rbpdisp_rptr(disp,r1) x86_encode_rptr_memptr(0x8D, r1, REG_RBP, -1, 0, disp)
10.150 #define LEAP_sib_rptr(ss,ii,bb,d,r1) x86_encode_rptr_memptr(0x8D, r1, bb, ii, ss, d)
10.151
10.152 #define MOVB_r8_r8(r1,r2) x86_encode_r32_rm32(0x88, r1, r2)
10.153 #define MOVL_imm32_r32(i32,r1) x86_encode_opcode32(0xB8, r1); OP32(i32)
10.154 +#define MOVL_imm32_r32disp(i,rb,d) x86_encode_r32_r32disp32(0xC7,0,rb,d); OP32(i)
10.155 #define MOVL_imm32_rbpdisp(i,disp) x86_encode_r32_rbpdisp32(0xC7,0,disp); OP32(i)
10.156 #define MOVL_imm32_rspdisp(i,disp) x86_encode_r32_rspdisp32(0xC7,0,disp); OP32(i)
10.157 #define MOVL_moffptr_eax(p) OP(0xA1); OPPTR(p)
10.158 #define MOVL_r32_r32(r1,r2) x86_encode_r32_rm32(0x89, r1, r2)
10.159 -#define MOVL_r32_r32disp(r1,r2,dsp) x86_encode_r32_mem32disp32(0x89, r1, r2, dsp)
10.160 +#define MOVL_r32_r32disp(r1,r2,dsp) x86_encode_r32_r32disp32(0x89, r1, r2, dsp)
10.161 #define MOVL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x89, r1, disp)
10.162 #define MOVL_r32_rspdisp(r1,disp) x86_encode_r32_rspdisp32(0x89, r1, disp)
10.163 #define MOVL_r32_sib(r1,ss,ii,bb,d) x86_encode_r32_mem32(0x89, r1, bb, ii, ss, d)
10.164 -#define MOVL_r32disp_r32(r1,dsp,r2) x86_encode_r32_mem32disp32(0x8B, r2, r1, dsp)
10.165 +#define MOVL_r32disp_r32(r1,dsp,r2) x86_encode_r32_r32disp32(0x8B, r2, r1, dsp)
10.166 #define MOVL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x8B, r1, disp)
10.167 #define MOVL_rspdisp_r32(disp,r1) x86_encode_r32_rspdisp32(0x8B, r1, disp)
10.168 #define MOVL_sib_r32(ss,ii,bb,d,r1) x86_encode_r32_mem32(0x8B, r1, bb, ii, ss, d)
10.169 #define MOVQ_imm64_r64(i64,r1) x86_encode_opcode64(0xB8, r1); OP64(i64)
10.170 #define MOVQ_moffptr_rax(p) OP(PREF_REXW); OP(0xA1); OPPTR(p)
10.171 #define MOVQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x89, r1, r2)
10.172 -#define MOVQ_r64_rbpdisp(r1,disp) x86_encode_r64_rbpdisp64(0x89, r1, disp)
10.173 -#define MOVQ_r64_rspdisp(r1,disp) x86_encode_r64_rspdisp64(0x89, r1, disp)
10.174 -#define MOVQ_rbpdisp_r64(disp,r1) x86_encode_r64_rbpdisp64(0x8B, r1, disp)
10.175 -#define MOVQ_rspdisp_r64(disp,r1) x86_encode_r64_rspdisp64(0x8B, r1, disp)
10.176 +#define MOVQ_r64_r64disp(r1,rb,d) x86_encode_r64_r64disp32(0x89, r1, rb, d)
10.177 +#define MOVQ_r64_rbpdisp(r1,disp) x86_encode_r64_rbpdisp32(0x89, r1, disp)
10.178 +#define MOVQ_r64_rspdisp(r1,disp) x86_encode_r64_rspdisp32(0x89, r1, disp)
10.179 +#define MOVQ_r64disp_r64(rb,d,r1) x86_encode_r64_r64disp32(0x8B, r1, rb, d)
10.180 +#define MOVQ_rbpdisp_r64(disp,r1) x86_encode_r64_rbpdisp32(0x8B, r1, disp)
10.181 +#define MOVQ_rspdisp_r64(disp,r1) x86_encode_r64_rspdisp32(0x8B, r1, disp)
10.182 #define MOVP_immptr_rptr(p,r1) x86_encode_opcodereg( PREF_PTR, 0xB8, r1); OPPTR(p)
10.183 #define MOVP_moffptr_rax(p) if( sizeof(void*)==8 ) { OP(PREF_REXW); } OP(0xA1); OPPTR(p)
10.184 #define MOVP_rptr_rptr(r1,r2) x86_encode_reg_rm(PREF_PTR, 0x89, r1, r2)
10.185 @@ -472,39 +495,50 @@
10.186
10.187 #define MOVSXL_r8_r32(r1,r2) x86_encode_r32_rm32(0x0FBE, r2, r1)
10.188 #define MOVSXL_r16_r32(r1,r2) x86_encode_r32_rm32(0x0FBF, r2, r1)
10.189 +#define MOVSXL_r32disp8_r32(r,d,r1) x86_encode_r32_r32disp32(0x0FBE, r1, r, d)
10.190 +#define MOVSXL_r32disp16_r32(r,d,r1) x86_encode_r32_r32disp32(0x0FBF, r1, r, d)
10.191 #define MOVSXL_rbpdisp8_r32(disp,r1) x86_encode_r32_rbpdisp32(0x0FBE, r1, disp)
10.192 #define MOVSXL_rbpdisp16_r32(dsp,r1) x86_encode_r32_rbpdisp32(0x0FBF, r1, dsp)
10.193 #define MOVSXQ_imm32_r64(i32,r1) x86_encode_r64_rm64(0xC7, 0, r1); OP32(i32) /* Technically a MOV */
10.194 #define MOVSXQ_r8_r64(r1,r2) x86_encode_r64_rm64(0x0FBE, r2, r1)
10.195 #define MOVSXQ_r16_r64(r1,r2) x86_encode_r64_rm64(0x0FBF, r2, r1)
10.196 #define MOVSXQ_r32_r64(r1,r2) x86_encode_r64_rm64(0x63, r2, r1)
10.197 -#define MOVSXQ_rbpdisp32_r64(dsp,r1) x86_encode_r64_rbpdisp64(0x63, r1, dsp)
10.198 +#define MOVSXQ_r64disp32_r64(r,d,r1) x86_encode_r64_r64disp32(0x63, r1, r, d)
10.199 +#define MOVSXQ_rbpdisp32_r64(dsp,r1) x86_encode_r64_rbpdisp32(0x63, r1, dsp)
10.200
10.201 #define MOVZXL_r8_r32(r1,r2) x86_encode_r32_rm32(0x0FB6, r2, r1)
10.202 #define MOVZXL_r16_r32(r1,r2) x86_encode_r32_rm32(0x0FB7, r2, r1)
10.203 +#define MOVZXL_r32disp8_r32(r,d,r1) x86_encode_r32_r32disp32(0x0FB6, r1, r, d)
10.204 +#define MOVZXL_r32disp16_r32(r,d,r1) x86_encode_r32_r32disp32(0x0FB7, r1, r, d)
10.205 #define MOVZXL_rbpdisp8_r32(disp,r1) x86_encode_r32_rbpdisp32(0x0FB6, r1, disp)
10.206 #define MOVZXL_rbpdisp16_r32(dsp,r1) x86_encode_r32_rbpdisp32(0x0FB7, r1, dsp)
10.207
10.208 #define MULL_r32(r1) x86_encode_r32_rm32(0xF7, 4, r1)
10.209 +#define MULL_r32disp(rb,d) x86_encode_r32_r32disp32(0xF7,4,rb,d)
10.210 #define MULL_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xF7,4,disp)
10.211 #define MULL_rspdisp(disp) x86_encode_r32_rspdisp32(0xF7,4,disp)
10.212
10.213 #define NEGB_r8(r1) x86_encode_r32_rm32(0xF6, 3, r1)
10.214 #define NEGL_r32(r1) x86_encode_r32_rm32(0xF7, 3, r1)
10.215 +#define NEGL_r32disp(rb,d) x86_encode_r32_r32disp32(0xF7, 3, rb, d)
10.216 #define NEGL_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xF7, 3, disp)
10.217 #define NEGQ_r64(r1) x86_encode_r64_rm64(0xF7, 3, r1)
10.218
10.219 #define NOTB_r8(r1) x86_encode_r32_rm32(0xF6, 2, r1)
10.220 #define NOTL_r32(r1) x86_encode_r32_rm32(0xF7, 2, r1)
10.221 +#define NOTL_r32disp(rb,d) x86_encode_r32_r32disp32(0xF7, 2, rb, d)
10.222 #define NOTL_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xF7, 2, disp)
10.223 #define NOTQ_r64(r1) x86_encode_r64_rm64(0xF7, 2, r1)
10.224
10.225 #define ORB_imms_r8(imm,r1) x86_encode_r32_rm32(0x80, 1, r1); OP(imm)
10.226 #define ORB_r8_r8(r1,r2) x86_encode_r32_rm32(0x08, r1, r2)
10.227 #define ORL_imms_r32(imm,r1) x86_encode_imms_rm32(0x83, 0x81, 1, imm, r1)
10.228 +#define ORL_imms_r32disp(imm,rb,d) x86_encode_imms_r32disp32(0x83,0x81,1,imm,rb,d)
10.229 #define ORL_imms_rbpdisp(imm,disp) x86_encode_imms_rbpdisp32(0x83,0x81,1,imm,disp)
10.230 #define ORL_r32_r32(r1,r2) x86_encode_r32_rm32(0x09, r1, r2)
10.231 +#define ORL_r32_r32disp(r1,rb,d) x86_encode_r32_r32disp32(0x09, r1, rb, d)
10.232 #define ORL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x09, r1, disp)
10.233 +#define ORL_r32disp_r32(rb,d,r1) x86_encode_r32_r32disp32(0x0B, r1, rb, d)
10.234 #define ORL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x0B, r1, disp)
10.235 #define ORQ_imms_r64(imm,r1) x86_encode_imms_rm64(0x83, 0x81, 1, imm, r1)
10.236 #define ORQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x09, r1, r2)
10.237 @@ -515,97 +549,101 @@
10.238 #define PUSH_r32(r1) x86_encode_opcode32(0x50, r1)
10.239
10.240 #define RCLL_cl_r32(r1) x86_encode_r32_rm32(0xD3,2,r1)
10.241 -#define RCLL_cl_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xD3,2,disp)
10.242 +#define RCLL_cl_r32disp(rb,d) x86_encode_r32_r32disp32(0xD3,2,rb,d)
10.243 #define RCLL_imm_r32(imm,r1) if( imm == 1 ) { x86_encode_r32_rm32(0xD1,2,r1); } else { x86_encode_r32_rm32(0xC1,2,r1); OP(imm); }
10.244 -#define RCLL_imm_rbpdisp(imm,disp) if( imm == 1 ) { x86_encode_r32_rbpdisp32(0xD1,2,disp); } else { x86_encode_r32_rbpdisp32(0xC1,2,disp); OP(imm); }
10.245 +#define RCLL_imm_r32disp(imm,rb,d) if( imm == 1 ) { x86_encode_r32_r32disp32(0xD1,2,rb,d); } else { x86_encode_r32_r32disp32(0xC1,2,rb,d); OP(imm); }
10.246 #define RCLQ_cl_r64(r1) x86_encode_r64_rm64(0xD3,2,r1)
10.247 -#define RCLQ_cl_rbpdisp(disp) x86_encode_r64_rbpdisp64(0xD3,2,disp)
10.248 +#define RCLQ_cl_r64disp(rb,d) x86_encode_r64_r64disp32(0xD3,2,rb,d)
10.249 #define RCLQ_imm_r64(imm,r1) if( imm == 1 ) { x86_encode_r64_rm64(0xD1,2,r1); } else { x86_encode_r64_rm64(0xC1,2,r1); OP(imm); }
10.250 -#define RCLQ_imm_rbpdisp(imm,disp) if( imm == 1 ) { x86_encode_r64_rbpdisp64(0xD1,2,disp); } else { x86_encode_r64_rbpdisp64(0xC1,2,disp); OP(imm); }
10.251 +#define RCLQ_imm_r64disp(imm,rb,d) if( imm == 1 ) { x86_encode_r64_r64disp32(0xD1,2,rb,d); } else { x86_encode_r64_r64disp32(0xC1,2,rb,d); OP(imm); }
10.252
10.253 #define RCRL_cl_r32(r1) x86_encode_r32_rm32(0xD3,3,r1)
10.254 -#define RCRL_cl_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xD3,3,disp)
10.255 +#define RCRL_cl_r32disp(rb,d) x86_encode_r32_r32disp32(0xD3,3,rb,d)
10.256 #define RCRL_imm_r32(imm,r1) if( imm == 1 ) { x86_encode_r32_rm32(0xD1,3,r1); } else { x86_encode_r32_rm32(0xC1,3,r1); OP(imm); }
10.257 -#define RCRL_imm_rbpdisp(imm,disp) if( imm == 1 ) { x86_encode_r32_rbpdisp32(0xD1,3,disp); } else { x86_encode_r32_rbpdisp32(0xC1,3,disp); OP(imm); }
10.258 +#define RCRL_imm_r32disp(imm,rb,d) if( imm == 1 ) { x86_encode_r32_r32disp32(0xD1,3,rb,d); } else { x86_encode_r32_r32disp32(0xC1,3,rb,d); OP(imm); }
10.259 #define RCRQ_cl_r64(r1) x86_encode_r64_rm64(0xD3,3,r1)
10.260 -#define RCRQ_cl_rbpdisp(disp) x86_encode_r64_rbpdisp64(0xD3,3,disp)
10.261 +#define RCRQ_cl_r64disp(rb,d) x86_encode_r64_r64disp32(0xD3,3,rb,d)
10.262 #define RCRQ_imm_r64(imm,r1) if( imm == 1 ) { x86_encode_r64_rm64(0xD1,3,r1); } else { x86_encode_r64_rm64(0xC1,3,r1); OP(imm); }
10.263 -#define RCRQ_imm_rbpdisp(imm,disp) if( imm == 1 ) { x86_encode_r64_rbpdisp64(0xD1,3,disp); } else { x86_encode_r64_rbpdisp64(0xC1,3,disp); OP(imm); }
10.264 +#define RCRQ_imm_r64disp(imm,rb,d) if( imm == 1 ) { x86_encode_r64_r64disp32(0xD1,3,rb,d); } else { x86_encode_r64_r64disp32(0xC1,3,rb,d); OP(imm); }
10.265
10.266 #define ROLL_cl_r32(r1) x86_encode_r32_rm32(0xD3,0,r1)
10.267 -#define ROLL_cl_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xD3,0,disp)
10.268 +#define ROLL_cl_r32disp(rb,d) x86_encode_r32_r32disp32(0xD3,0,rb,d)
10.269 #define ROLL_imm_r32(imm,r1) if( imm == 1 ) { x86_encode_r32_rm32(0xD1,0,r1); } else { x86_encode_r32_rm32(0xC1,0,r1); OP(imm); }
10.270 -#define ROLL_imm_rbpdisp(imm,disp) if( imm == 1 ) { x86_encode_r32_rbpdisp32(0xD1,0,disp); } else { x86_encode_r32_rbpdisp32(0xC1,0,disp); OP(imm); }
10.271 +#define ROLL_imm_r32disp(imm,rb,d) if( imm == 1 ) { x86_encode_r32_r32disp32(0xD1,0,rb,d); } else { x86_encode_r32_r32disp32(0xC1,0,rb,d); OP(imm); }
10.272 #define ROLQ_cl_r64(r1) x86_encode_r64_rm64(0xD3,0,r1)
10.273 -#define ROLQ_cl_rbpdisp(disp) x86_encode_r64_rbpdisp64(0xD3,0,disp)
10.274 +#define ROLQ_cl_r64disp(rb,d) x86_encode_r64_r64disp32(0xD3,0,rb,d)
10.275 #define ROLQ_imm_r64(imm,r1) if( imm == 1 ) { x86_encode_r64_rm64(0xD1,0,r1); } else { x86_encode_r64_rm64(0xC1,0,r1); OP(imm); }
10.276 -#define ROLQ_imm_rbpdisp(imm,disp) if( imm == 1 ) { x86_encode_r64_rbpdisp64(0xD1,0,disp); } else { x86_encode_r64_rbpdisp64(0xC1,0,disp); OP(imm); }
10.277 +#define ROLQ_imm_r64disp(imm,rb,d) if( imm == 1 ) { x86_encode_r64_r64disp32(0xD1,0,rb,d); } else { x86_encode_r64_r64disp32(0xC1,0,rb,d); OP(imm); }
10.278
10.279 #define RORL_cl_r32(r1) x86_encode_r32_rm32(0xD3,1,r1)
10.280 -#define RORL_cl_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xD3,1,disp)
10.281 +#define RORL_cl_r32disp(rb,d) x86_encode_r32_r32disp32(0xD3,1,rb,d)
10.282 #define RORL_imm_r32(imm,r1) if( imm == 1 ) { x86_encode_r32_rm32(0xD1,1,r1); } else { x86_encode_r32_rm32(0xC1,1,r1); OP(imm); }
10.283 -#define RORL_imm_rbpdisp(imm,disp) if( imm == 1 ) { x86_encode_r32_rbpdisp32(0xD1,1,disp); } else { x86_encode_r32_rbpdisp32(0xC1,1,disp); OP(imm); }
10.284 +#define RORL_imm_r32disp(imm,rb,d) if( imm == 1 ) { x86_encode_r32_r32disp32(0xD1,1,rb,d); } else { x86_encode_r32_r32disp32(0xC1,1,rb,d); OP(imm); }
10.285 #define RORQ_cl_r64(r1) x86_encode_r64_rm64(0xD3,1,r1)
10.286 -#define RORQ_cl_rbpdisp(disp) x86_encode_r64_rbpdisp64(0xD3,1,disp)
10.287 +#define RORQ_cl_r64disp(rb,d) x86_encode_r64_r64disp32(0xD3,1,rb,d)
10.288 #define RORQ_imm_r64(imm,r1) if( imm == 1 ) { x86_encode_r64_rm64(0xD1,1,r1); } else { x86_encode_r64_rm64(0xC1,1,r1); OP(imm); }
10.289 -#define RORQ_imm_rbpdisp(imm,disp) if( imm == 1 ) { x86_encode_r64_rbpdisp64(0xD1,1,disp); } else { x86_encode_r64_rbpdisp64(0xC1,1,disp); OP(imm); }
10.290 +#define RORQ_imm_r64disp(imm,rb,d) if( imm == 1 ) { x86_encode_r64_r64disp32(0xD1,1,rb,d); } else { x86_encode_r64_r64disp32(0xC1,1,rb,d); OP(imm); }
10.291
10.292 #define SARL_cl_r32(r1) x86_encode_r32_rm32(0xD3,7,r1)
10.293 -#define SARL_cl_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xD3,7,disp)
10.294 +#define SARL_cl_r32disp(rb,d) x86_encode_r32_r32disp32(0xD3,7,rb,d)
10.295 #define SARL_imm_r32(imm,r1) if( imm == 1 ) { x86_encode_r32_rm32(0xD1,7,r1); } else { x86_encode_r32_rm32(0xC1,7,r1); OP(imm); }
10.296 -#define SARL_imm_rbpdisp(imm,disp) if( imm == 1 ) { x86_encode_r32_rbpdisp32(0xD1,7,disp); } else { x86_encode_r32_rbpdisp32(0xC1,7,disp); OP(imm); }
10.297 +#define SARL_imm_r32disp(imm,rb,d) if( imm == 1 ) { x86_encode_r32_r32disp32(0xD1,7,rb,d); } else { x86_encode_r32_r32disp32(0xC1,7,rb,d); OP(imm); }
10.298 #define SARQ_cl_r64(r1) x86_encode_r64_rm64(0xD3,7,r1)
10.299 -#define SARQ_cl_rbpdisp(disp) x86_encode_r64_rbpdisp64(0xD3,7,disp)
10.300 +#define SARQ_cl_r64disp(rb,d) x86_encode_r64_r64disp32(0xD3,7,rb,d)
10.301 #define SARQ_imm_r64(imm,r1) if( imm == 1 ) { x86_encode_r64_rm64(0xD1,7,r1); } else { x86_encode_r64_rm64(0xC1,7,r1); OP(imm); }
10.302 -#define SARQ_imm_rbpdisp(imm,disp) if( imm == 1 ) { x86_encode_r64_rbpdisp64(0xD1,7,disp); } else { x86_encode_r64_rbpdisp64(0xC1,7,disp); OP(imm); }
10.303 +#define SARQ_imm_r64disp(imm,rb,d) if( imm == 1 ) { x86_encode_r64_r64disp32(0xD1,7,rb,d); } else { x86_encode_r64_r64disp32(0xC1,7,rb,d); OP(imm); }
10.304
10.305 #define SHLL_cl_r32(r1) x86_encode_r32_rm32(0xD3,4,r1)
10.306 -#define SHLL_cl_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xD3,4,disp)
10.307 +#define SHLL_cl_r32disp(rb,d) x86_encode_r32_r32disp32(0xD3,4,rb,d)
10.308 #define SHLL_imm_r32(imm,r1) if( imm == 1 ) { x86_encode_r32_rm32(0xD1,4,r1); } else { x86_encode_r32_rm32(0xC1,4,r1); OP(imm); }
10.309 -#define SHLL_imm_rbpdisp(imm,disp) if( imm == 1 ) { x86_encode_r32_rbpdisp32(0xD1,4,disp); } else { x86_encode_r32_rbpdisp32(0xC1,4,disp); OP(imm); }
10.310 +#define SHLL_imm_r32disp(imm,rb,d) if( imm == 1 ) { x86_encode_r32_r32disp32(0xD1,4,rb,d); } else { x86_encode_r32_r32disp32(0xC1,4,rb,d); OP(imm); }
10.311 #define SHLQ_cl_r64(r1) x86_encode_r64_rm64(0xD3,4,r1)
10.312 -#define SHLQ_cl_rbpdisp(disp) x86_encode_r64_rbpdisp64(0xD3,4,disp)
10.313 +#define SHLQ_cl_r64disp(rb,d) x86_encode_r64_r64disp32(0xD3,4,rb,d)
10.314 #define SHLQ_imm_r64(imm,r1) if( imm == 1 ) { x86_encode_r64_rm64(0xD1,4,r1); } else { x86_encode_r64_rm64(0xC1,4,r1); OP(imm); }
10.315 -#define SHLQ_imm_rbpdisp(imm,disp) if( imm == 1 ) { x86_encode_r64_rbpdisp64(0xD1,4,disp); } else { x86_encode_r64_rbpdisp64(0xC1,4,disp); OP(imm); }
10.316 +#define SHLQ_imm_r64disp(imm,rb,d) if( imm == 1 ) { x86_encode_r64_r64disp32(0xD1,4,rb,d); } else { x86_encode_r64_r64disp32(0xC1,4,rb,d); OP(imm); }
10.317
10.318 #define SHLDL_cl_r32_r32(r1,r2) x86_encode_r32_rm32(0x0FA5,r1,r2)
10.319 -#define SHLDL_cl_r32_rbpdisp(r1,d) x86_encode_r32_rbpdisp32(0x0FA5,r1,d)
10.320 +#define SHLDL_cl_r32_r32disp(r1,d) x86_encode_r32_r32disp32(0x0FA5,r1,d)
10.321 #define SHLDL_imm_r32_r32(imm,r1,r2) x86_encode_r32_rm32(0x0FA4,r1,r2); OP(imm)
10.322 -#define SHLDL_imm_r32_rbpdisp(i,r,d) x86_encode_r32_rbpdisp32(0x0FA4,r,d); OP(imm)
10.323 +#define SHLDL_imm_r32_r32disp(i,r,d) x86_encode_r32_r32disp32(0x0FA4,r,d); OP(imm)
10.324 #define SHLDQ_cl_r64_r64(r1,r2) x86_encode_r64_rm64(0x0FA5,r1,r2)
10.325 -#define SHLDQ_cl_r64_rbpdisp(r1,d) x86_encode_r64_rbpdisp64(0x0FA5,r1,d)
10.326 +#define SHLDQ_cl_r64_r64disp(r1,d) x86_encode_r64_r64disp32(0x0FA5,r1,d)
10.327 #define SHLDQ_imm_r64_r64(imm,r1,r2) x86_encode_r64_rm64(0x0FA4,r1,r2); OP(imm)
10.328 -#define SHLDQ_imm_r64_rbpdisp(i,r,d) x86_encode_r64_rbpdisp64(0x0FA4,r,d); OP(imm)
10.329 +#define SHLDQ_imm_r64_r64disp(i,r,d) x86_encode_r64_r64disp32(0x0FA4,r,d); OP(imm)
10.330
10.331 #define SHRL_cl_r32(r1) x86_encode_r32_rm32(0xD3,5,r1)
10.332 -#define SHRL_cl_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xD3,5,disp)
10.333 +#define SHRL_cl_r32disp(rb,d) x86_encode_r32_r32disp32(0xD3,5,rb,d)
10.334 #define SHRL_imm_r32(imm,r1) if( imm == 1 ) { x86_encode_r32_rm32(0xD1,5,r1); } else { x86_encode_r32_rm32(0xC1,5,r1); OP(imm); }
10.335 -#define SHRL_imm_rbpdisp(imm,disp) if( imm == 1 ) { x86_encode_r32_rbpdisp32(0xD1,5,disp); } else { x86_encode_r32_rbpdisp32(0xC1,5,disp); OP(imm); }
10.336 +#define SHRL_imm_r32disp(imm,rb,d) if( imm == 1 ) { x86_encode_r32_r32disp32(0xD1,5,rb,d); } else { x86_encode_r32_r32disp32(0xC1,5,rb,d); OP(imm); }
10.337 #define SHRQ_cl_r64(r1) x86_encode_r64_rm64(0xD3,5,r1)
10.338 -#define SHRQ_cl_rbpdisp(disp) x86_encode_r64_rbpdisp64(0xD3,5,disp)
10.339 +#define SHRQ_cl_r64disp(rb,d) x86_encode_r64_r64disp32(0xD3,5,rb,d)
10.340 #define SHRQ_imm_r64(imm,r1) if( imm == 1 ) { x86_encode_r64_rm64(0xD1,5,r1); } else { x86_encode_r64_rm64(0xC1,5,r1); OP(imm); }
10.341 -#define SHRQ_imm_rbpdisp(imm,disp) if( imm == 1 ) { x86_encode_r64_rbpdisp64(0xD1,5,disp); } else { x86_encode_r64_rbpdisp64(0xC1,5,disp); OP(imm); }
10.342 +#define SHRQ_imm_r64disp(imm,rb,d) if( imm == 1 ) { x86_encode_r64_r64disp32(0xD1,5,rb,d); } else { x86_encode_r64_r64disp32(0xC1,5,rb,d); OP(imm); }
10.343
10.344 -#define SHRDL_cl_r32_r32(r1,r2) x86_encode_r32_rm32(0x0FAD,r1,r2)
10.345 -#define SHRDL_cl_r32_rbpdisp(r1,d) x86_encode_r32_rbpdisp32(0x0FAD,r1,d)
10.346 -#define SHRDL_imm_r32_r32(imm,r1,r2) x86_encode_r32_rm32(0x0FAC,r1,r2); OP(imm)
10.347 -#define SHRDL_imm_r32_rbpdisp(i,r,d) x86_encode_r32_rbpdisp32(0x0FAC,r,d); OP(imm)
10.348 -#define SHRDQ_cl_r64_r64(r1,r2) x86_encode_r64_rm64(0x0FAD,r1,r2)
10.349 -#define SHRDQ_cl_r64_rbpdisp(r1,d) x86_encode_r64_rbpdisp64(0x0FAD,r1,d)
10.350 -#define SHRDQ_imm_r64_r64(imm,r1,r2) x86_encode_r64_rm64(0x0FAC,r1,r2); OP(imm)
10.351 -#define SHRDQ_imm_r64_rbpdisp(i,r,d) x86_encode_r64_rbpdisp64(0x0FAC,r,d); OP(imm)
10.352 +#define SHRDL_cl_r32_r32(r1,r2) x86_encode_r32_rm32(0x0FAD,r1,r2)
10.353 +#define SHRDL_cl_r32_r32disp(r1,rb,d) x86_encode_r32_r32disp32(0x0FAD,r1,rb,d)
10.354 +#define SHRDL_imm_r32_r32(imm,r1,r2) x86_encode_r32_rm32(0x0FAC,r1,r2); OP(imm)
10.355 +#define SHRDL_imm_r32_r32disp(i,r,rb,d) x86_encode_r32_r32disp32(0x0FAC,r,rb,d); OP(imm)
10.356 +#define SHRDQ_cl_r64_r64(r1,r2) x86_encode_r64_rm64(0x0FAD,r1,r2)
10.357 +#define SHRDQ_cl_r64_r64disp(r1,rb,d) x86_encode_r64_r64disp32(0x0FAD,r1,rb,d)
10.358 +#define SHRDQ_imm_r64_r64(imm,r1,r2) x86_encode_r64_rm64(0x0FAC,r1,r2); OP(imm)
10.359 +#define SHRDQ_imm_r64_r64disp(i,r,rb,d) x86_encode_r64_r64disp32(0x0FAC,r,rb,d); OP(imm)
10.360
10.361 #define SBBB_imms_r8(imm,r1) x86_encode_r32_rm32(0x80, 3, r1); OP(imm)
10.362 #define SBBB_r8_r8(r1,r2) x86_encode_r32_rm32(0x18, r1, r2)
10.363 #define SBBL_imms_r32(imm,r1) x86_encode_imms_rm32(0x83, 0x81, 3, imm, r1)
10.364 +#define SBBL_imms_r32disp(imm,rb,d) x86_encode_imms_r32disp32(0x83,0x81,3,imm,rb,d)
10.365 #define SBBL_imms_rbpdisp(imm,disp) x86_encode_imms_rbpdisp32(0x83,0x81,3,imm,disp)
10.366 #define SBBL_r32_r32(r1,r2) x86_encode_r32_rm32(0x19, r1, r2)
10.367 +#define SBBL_r32_r32disp(r1,rb,d) x86_encode_r32_r32disp32(0x19, r1, rb,d)
10.368 #define SBBL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x19, r1, disp)
10.369 +#define SBBL_r32disp_r32(rb,d,r1) x86_encode_r32_r32disp32(0x1B, r1, rb,d)
10.370 #define SBBL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x1B, r1, disp)
10.371 #define SBBQ_imms_r64(imm,r1) x86_encode_imms_rm64(0x83, 0x81, 3, imm, r1)
10.372 #define SBBQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x19, r1, r2)
10.373
10.374 #define SETCCB_cc_r8(cc,r1) x86_encode_r32_rm32(0x0F90+(cc), 0, r1)
10.375 +#define SETCCB_cc_r32disp(cc,rb,d) x86_encode_r32_r32disp32(0x0F90+(cc), 0, rb, d)
10.376 #define SETCCB_cc_rbpdisp(cc,disp) x86_encode_r32_rbpdisp32(0x0F90+(cc), 0, disp)
10.377
10.378 #define STC() OP(0xF9)
10.379 @@ -614,9 +652,12 @@
10.380 #define SUBB_imms_r8(imm,r1) x86_encode_r32_rm32(0x80, 5, r1); OP(imm)
10.381 #define SUBB_r8_r8(r1,r2) x86_encode_r32_rm32(0x28, r1, r2)
10.382 #define SUBL_imms_r32(imm,r1) x86_encode_imms_rm32(0x83, 0x81, 5, imm, r1)
10.383 +#define SUBL_imms_r32disp(imm,rb,d) x86_encode_imms_r32disp32(0x83,0x81,5,imm,rb,d)
10.384 #define SUBL_imms_rbpdisp(imm,disp) x86_encode_imms_rbpdisp32(0x83,0x81,5,imm,disp)
10.385 #define SUBL_r32_r32(r1,r2) x86_encode_r32_rm32(0x29, r1, r2)
10.386 +#define SUBL_r32_r32disp(r1,rb,d) x86_encode_r32_r32disp32(0x29, r1, rb, d)
10.387 #define SUBL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x29, r1, disp)
10.388 +#define SUBL_r32disp_r32(rb,d,r1) x86_encode_r32_r32disp32(0x2B, r1, rb, d)
10.389 #define SUBL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x2B, r1, disp)
10.390 #define SUBQ_imms_r64(imm,r1) x86_encode_imms_rm64(0x83, 0x81, 5, imm, r1)
10.391 #define SUBQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x29, r1, r2)
10.392 @@ -624,9 +665,12 @@
10.393 #define TESTB_imms_r8(imm,r1) x86_encode_r32_rm32(0xF6, 0, r1); OP(imm)
10.394 #define TESTB_r8_r8(r1,r2) x86_encode_r32_rm32(0x84, r1, r2)
10.395 #define TESTL_imms_r32(imm,r1) x86_encode_r32_rm32(0xF7, 0, r1); OP32(imm)
10.396 +#define TESTL_imms_r32disp(imm,r,d) x86_encode_r32_r32disp32(0xF7, 0, r, d); OP32(imm)
10.397 #define TESTL_imms_rbpdisp(imm,dsp) x86_encode_r32_rbpdisp32(0xF7, 0, dsp); OP32(imm)
10.398 #define TESTL_r32_r32(r1,r2) x86_encode_r32_rm32(0x85, r1, r2)
10.399 +#define TESTL_r32_r32disp(r1,rb,d) x86_encode_r32_r32disp32(0x85, r1, rb, d)
10.400 #define TESTL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x85, r1, disp)
10.401 +#define TESTL_r32disp_r32(rb,d,r1) x86_encode_r32_r32disp32(0x85, r1, rb, d) /* Same OP */
10.402 #define TESTL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x85, r1, disp) /* Same OP */
10.403 #define TESTQ_imms_r64(imm,r1) x86_encode_r64_rm64(0xF7, 0, r1); OP32(imm)
10.404 #define TESTQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x85, r1, r2)
10.405 @@ -638,18 +682,21 @@
10.406 #define XORB_imms_r8(imm,r1) x86_encode_r32_rm32(0x80, 6, r1); OP(imm)
10.407 #define XORB_r8_r8(r1,r2) x86_encode_r32_rm32(0x30, r1, r2)
10.408 #define XORL_imms_r32(imm,r1) x86_encode_imms_rm32(0x83, 0x81, 6, imm, r1)
10.409 +#define XORL_imms_r32disp(imm,rb,d) x86_encode_imms_r32disp32(0x83,0x81,6,imm,rb,d)
10.410 #define XORL_imms_rbpdisp(imm,disp) x86_encode_imms_rbpdisp32(0x83,0x81,6,imm,disp)
10.411 #define XORL_r32_r32(r1,r2) x86_encode_r32_rm32(0x31, r1, r2)
10.412 +#define XORL_r32_r32disp(r1,rb,d) x86_encode_r32_r32disp32(0x31, r1, rb, d)
10.413 #define XORL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x31, r1, disp)
10.414 +#define XORL_r32disp_r32(rb,d,r1) x86_encode_r32_r32disp32(0x33, r1, rb, d)
10.415 #define XORL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x33, r1, disp)
10.416 #define XORQ_imms_r64(imm,r1) x86_encode_imms_rm64(0x83, 0x81, 6, imm, r1)
10.417 #define XORQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x31, r1, r2)
10.418
10.419 /* Control flow */
10.420 #define CALL_rel(rel) OP(0xE8); OP32(rel)
10.421 -#define CALL_imm32(ptr) x86_encode_r32_mem32disp32(0xFF, 2, -1, ptr)
10.422 +#define CALL_imm32(ptr) x86_encode_r32_r32disp32(0xFF, 2, -1, ptr)
10.423 #define CALL_r32(r1) x86_encode_r32_rm32(0xFF, 2, r1)
10.424 -#define CALL_r32disp(r1,disp) x86_encode_r32_mem32disp32(0xFF, 2, r1, disp)
10.425 +#define CALL_r32disp(r1,disp) x86_encode_r32_r32disp32(0xFF, 2, r1, disp)
10.426 #define CALL_sib(ss,ii,bb,disp) x86_encode_r32_mem32(0xFF, 2, bb, ii, ss, disp)
10.427
10.428 #define JCC_cc_rel8(cc,rel) OP(0x70+(cc)); OP(rel)
10.429 @@ -661,7 +708,7 @@
10.430 #define JMP_rel(rel) if( IS_INT8(rel) ) { JMP_rel8((int8_t)rel); } else { JMP_rel32(rel); }
10.431 #define JMP_prerel(rel) if( IS_INT8(((int32_t)rel)-2) ) { JMP_rel8(((int8_t)rel)-2); } else { JMP_rel32(((int32_t)rel)-5); }
10.432 #define JMP_r32(r1,disp) x86_encode_r32_rm32(0xFF, 4, r1)
10.433 -#define JMP_r32disp(r1,disp) x86_encode_r32_mem32disp32(0xFF, 4, r1, disp)
10.434 +#define JMP_r32disp(r1,disp) x86_encode_r32_r32disp32(0xFF, 4, r1, disp)
10.435 #define RET() OP(0xC3)
10.436 #define RET_imm(imm) OP(0xC2); OP16(imm)
10.437
10.438 @@ -686,12 +733,12 @@
10.439 #define FCHS_st0() OP(0xD9); OP(0xE0)
10.440 #define FCOMIP_st(st) OP(0xDF); OP(0xF0+(st))
10.441 #define FDIVP_st(st) OP(0xDE); OP(0xF8+(st))
10.442 -#define FILD_r32disp(r32, disp) x86_encode_r32_mem32disp32(0xDB, 0, r32, disp)
10.443 +#define FILD_r32disp(r32, disp) x86_encode_r32_r32disp32(0xDB, 0, r32, disp)
10.444 #define FLD0_st0() OP(0xD9); OP(0xEE);
10.445 #define FLD1_st0() OP(0xD9); OP(0xE8);
10.446 -#define FLDCW_r32disp(r32, disp) x86_encode_r32_mem32disp32(0xD9, 5, r32, disp)
10.447 +#define FLDCW_r32disp(r32, disp) x86_encode_r32_r32disp32(0xD9, 5, r32, disp)
10.448 #define FMULP_st(st) OP(0xDE); OP(0xC8+(st))
10.449 -#define FNSTCW_r32disp(r32, disp) x86_encode_r32_mem32disp32(0xD9, 7, r32, disp)
10.450 +#define FNSTCW_r32disp(r32, disp) x86_encode_r32_r32disp32(0xD9, 7, r32, disp)
10.451 #define FPOP_st() OP(0xDD); OP(0xC0); OP(0xD9); OP(0xF7)
10.452 #define FSUBP_st(st) OP(0xDE); OP(0xE8+(st))
10.453 #define FSQRT_st0() OP(0xD9); OP(0xFA)
10.454 @@ -711,190 +758,190 @@
10.455 #define MOVQ_xmm_r64(r1,r2) OP(0x66); x86_encode_r64_rm64(0x0F7E, r1, r2)
10.456
10.457 /* SSE Packed floating point instructions */
10.458 -#define ADDPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F58, r1, disp)
10.459 +#define ADDPS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0F58, r1, rb,d)
10.460 #define ADDPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F58, r2, r1)
10.461 -#define ANDPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F54, r1, disp)
10.462 +#define ANDPS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0F54, r1, rb,d)
10.463 #define ANDPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F54, r2, r1)
10.464 -#define ANDNPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F55, r1, disp)
10.465 +#define ANDNPS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0F55, r1, rb,d)
10.466 #define ANDNPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F55, r2, r1)
10.467 -#define CMPPS_cc_rbpdisp_xmm(cc,d,r) x86_encode_r32_rbpdisp32(0x0FC2, r, d); OP(cc)
10.468 +#define CMPPS_cc_r32disp_xmm(cc,rb,d,r) x86_encode_r32_r32disp32(0x0FC2, r, rb, d); OP(cc)
10.469 #define CMPPS_cc_xmm_xmm(cc,r1,r2) x86_encode_r32_rm32(0x0FC2, r2, r1); OP(cc)
10.470 -#define DIVPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F5E, r1, disp)
10.471 +#define DIVPS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0F5E, r1, rb,d)
10.472 #define DIVPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F5E, r2, r1)
10.473 -#define MAXPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F5F, r1, disp)
10.474 +#define MAXPS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0F5F, r1, rb,d)
10.475 #define MAXPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F5F, r2, r1)
10.476 -#define MINPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F5D, r1, disp)
10.477 +#define MINPS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0F5D, r1, rb,d)
10.478 #define MINPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F5D, r2, r1)
10.479 #define MOV_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F28, r2, r1)
10.480 -#define MOVAPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F28, r1, disp)
10.481 -#define MOVAPS_xmm_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x0F29, r1, disp)
10.482 +#define MOVAPS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0F28, r1, rb,d)
10.483 +#define MOVAPS_xmm_r32disp(r1,rb,d) x86_encode_r32_r32disp32(0x0F29, r1, rb,d)
10.484 #define MOVHLPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F12, r2, r1)
10.485 -#define MOVHPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F16, r1, disp)
10.486 -#define MOVHPS_xmm_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x0F17, r1, disp)
10.487 +#define MOVHPS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0F16, r1, rb,d)
10.488 +#define MOVHPS_xmm_r32disp(r1,rb,d) x86_encode_r32_r32disp32(0x0F17, r1, rb,d)
10.489 #define MOVLHPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F16, r2, r1)
10.490 -#define MOVLPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F12, r1, disp)
10.491 -#define MOVLPS_xmm_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x0F13, r1, disp)
10.492 -#define MOVUPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F10, r1, disp)
10.493 -#define MOVUPS_xmm_rbpdisp(disp,r1) x86_encode_r32_rbpdisp32(0x0F11, r1, disp)
10.494 +#define MOVLPS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0F12, r1, rb,d)
10.495 +#define MOVLPS_xmm_r32disp(r1,rb,d) x86_encode_r32_r32disp32(0x0F13, r1, rb,d)
10.496 +#define MOVUPS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0F10, r1, rb,d)
10.497 +#define MOVUPS_xmm_r32disp(r1,rb,d) x86_encode_r32_r32disp32(0x0F11, r1, rb,d)
10.498 #define MULPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F59, r2, r1)
10.499 -#define MULPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0xF59, r1, disp)
10.500 -#define ORPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F56, r1, disp)
10.501 +#define MULPS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0xF59, r1, rb,d)
10.502 +#define ORPS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0F56, r1, rb,d)
10.503 #define ORPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F56, r2, r1)
10.504 -#define RCPPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0xF53, r1, disp)
10.505 +#define RCPPS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0xF53, r1, rb,d)
10.506 #define RCPPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F53, r2, r1)
10.507 -#define RSQRTPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F52, r1, disp)
10.508 +#define RSQRTPS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0F52, r1, rb,d)
10.509 #define RSQRTPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F52, r2, r1)
10.510 -#define SHUFPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0FC6, r1, disp)
10.511 +#define SHUFPS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0FC6, r1, rb,d)
10.512 #define SHUFPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0FC6, r2, r1)
10.513 -#define SQRTPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F51, r1, disp)
10.514 +#define SQRTPS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0F51, r1, rb,d)
10.515 #define SQRTPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F51, r2, r1)
10.516 -#define SUBPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F5C, r1, disp)
10.517 +#define SUBPS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0F5C, r1, rb,d)
10.518 #define SUBPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F5C, r2, r1)
10.519 -#define UNPCKHPS_rbpdisp_xmm(dsp,r1) x86_encode_r32_rbpdisp32(0x0F15, r1, disp)
10.520 +#define UNPCKHPS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0F15, r1, rb,d)
10.521 #define UNPCKHPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F15, r2, r1)
10.522 -#define UNPCKLPS_rbpdisp_xmm(dsp,r1) x86_encode_r32_rbpdisp32(0x0F14, r1, disp)
10.523 +#define UNPCKLPS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0F14, r1, rb,d)
10.524 #define UNPCKLPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F14, r2, r1)
10.525 -#define XORPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F57, r1, disp)
10.526 +#define XORPS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0F57, r1, rb,d)
10.527 #define XORPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F57, r2, r1)
10.528
10.529 /* SSE Scalar floating point instructions */
10.530 -#define ADDSS_rbpdisp_xmm(disp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F58, r1, disp)
10.531 +#define ADDSS_r32disp_xmm(rb,d,r1) OP(0xF3); x86_encode_r32_r32disp32(0x0F58, r1, rb,d)
10.532 #define ADDSS_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F58, r2, r1)
10.533 -#define CMPSS_cc_rbpdisp_xmm(cc,d,r) OP(0xF3); x86_encode_r32_rbpdisp32(0x0FC2, r, d); OP(cc)
10.534 +#define CMPSS_cc_r32disp_xmm(cc,rb,d,r) OP(0xF3); x86_encode_r32_r32disp32(0x0FC2, r, rb, d); OP(cc)
10.535 #define CMPSS_cc_xmm_xmm(cc,r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0FC2, r2, r1); OP(cc)
10.536 -#define COMISS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F2F, r1, disp)
10.537 +#define COMISS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0F2F, r1, rb,d)
10.538 #define COMISS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F2F, r2, r1)
10.539 #define CVTSI2SSL_r32_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F2A, r2, r1)
10.540 -#define CVTSI2SSL_rbpdisp_xmm(d,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F2A, r1, d)
10.541 +#define CVTSI2SSL_r32disp_xmm(rb,d,r1) OP(0xF3); x86_encode_r32_r32disp32(0x0F2A, r1, rb,d)
10.542 #define CVTSI2SSQ_r64_xmm(r1,r2) OP(0xF3); x86_encode_r64_rm64(0x0F2A, r2, r1)
10.543 -#define CVTSI2SSQ_rbpdisp_xmm(d,r1) OP(0xF3); x86_encode_r64_rbpdisp64(0x0F2A, r1, d)
10.544 +#define CVTSI2SSQ_r64disp_xmm(rb,d,r1) OP(0xF3); x86_encode_r64_r64disp32(0x0F2A, r1, rb,d)
10.545 #define CVTSS2SIL_xmm_r32(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F2D, r2, r1)
10.546 -#define CVTSS2SIL_rbpdisp_r32(d,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F2D, r1, d)
10.547 +#define CVTSS2SIL_r32disp_r32(rb,d,r1) OP(0xF3); x86_encode_r32_r32disp32(0x0F2D, r1, rb, d)
10.548 #define CVTSS2SIQ_xmm_r64(r1,r2) OP(0xF3); x86_encode_r64_rm64(0x0F2D, r2, r1)
10.549 -#define CVTSS2SIQ_rbpdisp_r64(d,r1) OP(0xF3); x86_encode_r64_rbpdisp64(0x0F2D, r1, d)
10.550 +#define CVTSS2SIQ_r64disp_r64(rb,d,r1) OP(0xF3); x86_encode_r64_r64disp32(0x0F2D, r1, rb, d)
10.551 #define CVTTSS2SIL_xmm_r32(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F2C, r2, r1)
10.552 -#define CVTTSS2SIL_rbpdisp_r32(d,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F2C, r1, d)
10.553 +#define CVTTSS2SIL_r32disp_r32(rb,d,r1) OP(0xF3); x86_encode_r32_r32disp32(0x0F2C, r1, rb, d)
10.554 #define CVTTSS2SIQ_xmm_r64(r1,r2) OP(0xF3); x86_encode_r64_rm64(0x0F2C, r2, r1)
10.555 -#define CVTTSS2SIQ_rbpdisp_r64(d,r1) OP(0xF3); x86_encode_r64_rbpdisp64(0x0F2C, r1, d)
10.556 -#define DIVSS_rbpdisp_xmm(disp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F5E, r1, disp)
10.557 +#define CVTTSS2SIQ_r64disp_r64(rb,d,r1) OP(0xF3); x86_encode_r64_r64disp32(0x0F2C, r1, rb, d)
10.558 +#define DIVSS_r32disp_xmm(rb,d,r1) OP(0xF3); x86_encode_r32_r32disp32(0x0F5E, r1, rb,d)
10.559 #define DIVSS_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F5E, r2, r1)
10.560 -#define MAXSS_rbpdisp_xmm(disp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F5F, r1, disp)
10.561 +#define MAXSS_r32disp_xmm(rb,d,r1) OP(0xF3); x86_encode_r32_r32disp32(0x0F5F, r1, rb,d)
10.562 #define MAXSS_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F5F, r2, r1)
10.563 -#define MINSS_rbpdisp_xmm(disp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F5D, r1, disp)
10.564 +#define MINSS_r32disp_xmm(rb,d,r1) OP(0xF3); x86_encode_r32_r32disp32(0x0F5D, r1, rb,d)
10.565 #define MINSS_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F5D, r2, r1)
10.566 -#define MOVSS_rbpdisp_xmm(disp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F10, r1, disp)
10.567 -#define MOVSS_xmm_rbpdisp(r1,disp) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F11, r1, disp)
10.568 +#define MOVSS_r32disp_xmm(rb,d,r1) OP(0xF3); x86_encode_r32_r32disp32(0x0F10, r1, rb,d)
10.569 +#define MOVSS_xmm_r32disp(r1,rb,d) OP(0xF3); x86_encode_r32_r32disp32(0x0F11, r1, rb,d)
10.570 #define MOVSS_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F10, r2, r1)
10.571 -#define MULSS_rbpdisp_xmm(disp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0xF59, r1, disp)
10.572 +#define MULSS_r32disp_xmm(rb,d,r1) OP(0xF3); x86_encode_r32_r32disp32(0xF59, r1, rb,d)
10.573 #define MULSS_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F59, r2, r1)
10.574 -#define RCPSS_rbpdisp_xmm(disp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0xF53, r1, disp)
10.575 +#define RCPSS_r32disp_xmm(rb,d,r1) OP(0xF3); x86_encode_r32_r32disp32(0xF53, r1, rb,d)
10.576 #define RCPSS_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F53, r2, r1)
10.577 -#define RSQRTSS_rbpdisp_xmm(disp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F52, r1, disp)
10.578 +#define RSQRTSS_r32disp_xmm(rb,d,r1) OP(0xF3); x86_encode_r32_r32disp32(0x0F52, r1, rb,d)
10.579 #define RSQRTSS_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F52, r2, r1)
10.580 -#define SQRTSS_rbpdisp_xmm(disp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F51, r1, disp)
10.581 +#define SQRTSS_r32disp_xmm(rb,d,r1) OP(0xF3); x86_encode_r32_r32disp32(0x0F51, r1, rb,d)
10.582 #define SQRTSS_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F51, r2, r1)
10.583 -#define SUBSS_rbpdisp_xmm(disp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F5C, r1, disp)
10.584 +#define SUBSS_r32disp_xmm(rb,d,r1) OP(0xF3); x86_encode_r32_r32disp32(0x0F5C, r1, rb,d)
10.585 #define SUBSS_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F5C, r2, r1)
10.586 -#define UCOMISS_rbpdisp_xmm(dsp,r1) x86_encode_r32_rbpdisp32(0x0F2E, r1, dsp)
10.587 +#define UCOMISS_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0F2E, r1, rb,d)
10.588 #define UCOMISS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F2E, r2, r1)
10.589
10.590 /* SSE2 Packed floating point instructions */
10.591 -#define ADDPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F58, r1, disp)
10.592 +#define ADDPD_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0x0F58, r1, rb,d)
10.593 #define ADDPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F58, r2, r1)
10.594 -#define ANDPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F54, r1, disp)
10.595 +#define ANDPD_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0x0F54, r1, rb,d)
10.596 #define ANDPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F54, r2, r1)
10.597 -#define ANDNPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F55, r1, disp)
10.598 +#define ANDNPD_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0x0F55, r1, rb,d)
10.599 #define ANDNPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F55, r2, r1)
10.600 -#define CMPPD_cc_rbpdisp_xmm(cc,d,r) OP(0x66); x86_encode_r32_rbpdisp32(0x0FC2, r, d); OP(cc)
10.601 +#define CMPPD_cc_r32disp_xmm(cc,rb,d,r) OP(0x66); x86_encode_r32_r32disp32(0x0FC2, r, rb, d); OP(cc)
10.602 #define CMPPD_cc_xmm_xmm(cc,r1,r2) OP(0x66); x86_encode_r32_rm32(0x0FC2, r2, r1); OP(cc)
10.603 -#define CVTPD2PS_rbpdisp_xmm(dsp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F5A, r1, dsp)
10.604 +#define CVTPD2PS_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0x0F5A, r1, rb,d)
10.605 #define CVTPD2PS_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F5A, r2, r1)
10.606 -#define CVTPS2PD_rbpdisp_xmm(dsp,r1) x86_encode_r32_rbpdisp32(0x0F5A, r1, dsp)
10.607 +#define CVTPS2PD_r32disp_xmm(rb,d,r1) x86_encode_r32_r32disp32(0x0F5A, r1, rb,d)
10.608 #define CVTPS2PD_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F5A, r2, r1)
10.609 -#define DIVPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F5E, r1, disp)
10.610 +#define DIVPD_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0x0F5E, r1, rb,d)
10.611 #define DIVPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F5E, r2, r1)
10.612 -#define MAXPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F5F, r1, disp)
10.613 +#define MAXPD_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0x0F5F, r1, rb,d)
10.614 #define MAXPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F5F, r2, r1)
10.615 -#define MINPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F5D, r1, disp)
10.616 +#define MINPD_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0x0F5D, r1, rb,d)
10.617 #define MINPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F5D, r2, r1)
10.618 -#define MOVHPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F16, r1, disp)
10.619 -#define MOVHPD_xmm_rbpdisp(r1,disp) OP(0x66); x86_encode_r32_rbpdisp32(0x0F17, r1, disp)
10.620 -#define MOVLPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F12, r1, disp)
10.621 -#define MOVLPD_xmm_rbpdisp(r1,disp) OP(0x66); x86_encode_r32_rbpdisp32(0x0F13, r1, disp)
10.622 -#define MULPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0xF59, r1, disp)
10.623 +#define MOVHPD_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0x0F16, r1, rb,d)
10.624 +#define MOVHPD_xmm_r32disp(r1,rb,d) OP(0x66); x86_encode_r32_r32disp32(0x0F17, r1, rb,d)
10.625 +#define MOVLPD_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0x0F12, r1, rb,d)
10.626 +#define MOVLPD_xmm_r32disp(r1,rb,d) OP(0x66); x86_encode_r32_r32disp32(0x0F13, r1, rb,d)
10.627 +#define MULPD_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0xF59, r1, rb,d)
10.628 #define MULPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F59, r2, r1)
10.629 -#define ORPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F56, r1, disp)
10.630 +#define ORPD_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0x0F56, r1, rb,d)
10.631 #define ORPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F56, r2, r1)
10.632 -#define SHUFPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0FC6, r1, disp)
10.633 +#define SHUFPD_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0x0FC6, r1, rb,d)
10.634 #define SHUFPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0FC6, r2, r1)
10.635 -#define SUBPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F5C, r1, disp)
10.636 +#define SUBPD_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0x0F5C, r1, rb,d)
10.637 #define SUBPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F5C, r2, r1)
10.638 -#define UNPCKHPD_rbpdisp_xmm(dsp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F15, r1, disp)
10.639 +#define UNPCKHPD_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0x0F15, r1, disp)
10.640 #define UNPCKHPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F15, r2, r1)
10.641 -#define UNPCKLPD_rbpdisp_xmm(dsp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F14, r1, disp)
10.642 +#define UNPCKLPD_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0x0F14, r1, disp)
10.643 #define UNPCKLPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F14, r2, r1)
10.644 -#define XORPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F57, r1, disp)
10.645 +#define XORPD_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0x0F57, r1, rb,d)
10.646 #define XORPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F57, r2, r1)
10.647
10.648
10.649 /* SSE2 Scalar floating point instructions */
10.650 -#define ADDSD_rbpdisp_xmm(disp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F58, r1, disp)
10.651 +#define ADDSD_r32disp_xmm(rb,d,r1) OP(0xF2); x86_encode_r32_r32disp32(0x0F58, r1, rb,d)
10.652 #define ADDSD_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F58, r2, r1)
10.653 -#define CMPSD_cc_rbpdisp_xmm(cc,d,r) OP(0xF2); x86_encode_r32_rbpdisp32(0x0FC2, r, d); OP(cc)
10.654 +#define CMPSD_cc_r32disp_xmm(cc,rb,d,r) OP(0xF2); x86_encode_r32_r32disp32(0x0FC2, r, rb, d); OP(cc)
10.655 #define CMPSD_cc_xmm_xmm(cc,r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0FC2, r2, r1); OP(cc)
10.656 #define CVTSI2SDL_r32_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F2A, r2, r1)
10.657 -#define CVTSI2SDL_rbpdisp_xmm(d,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F2A, r1, d)
10.658 +#define CVTSI2SDL_r32disp_xmm(rb,d,r1) OP(0xF2); x86_encode_r32_r32disp32(0x0F2A, r1, rb,d)
10.659 #define CVTSI2SDQ_r64_xmm(r1,r2) OP(0xF2); x86_encode_r64_rm64(0x0F2A, r2, r1)
10.660 -#define CVTSI2SDQ_rbpdisp_xmm(d,r1) OP(0xF2); x86_encode_r64_rbpdisp64(0x0F2A, r1, d)
10.661 +#define CVTSI2SDQ_r64disp_xmm(rb,d,r1) OP(0xF2); x86_encode_r64_r64disp32(0x0F2A, r1, rb,d)
10.662 #define CVTSD2SIL_xmm_r32(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F2D, r2, r1)
10.663 -#define CVTSD2SIL_rbpdisp_r32(d,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F2D, r1, d)
10.664 +#define CVTSD2SIL_r32disp_r32(rb, d,r1) OP(0xF2); x86_encode_r32_r32disp32(0x0F2D, r1, rb, d)
10.665 #define CVTSD2SIQ_xmm_r64(r1,r2) OP(0xF2); x86_encode_r64_rm64(0x0F2D, r2, r1)
10.666 -#define CVTSD2SIQ_rbpdisp_r64(d,r1) OP(0xF2); x86_encode_r64_rbpdisp64(0x0F2D, r1, d)
10.667 -#define CVTSD2SS_rbpdisp_xmm(dsp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F5A, r1, dsp)
10.668 +#define CVTSD2SIQ_r64disp_r64(rb,d,r1) OP(0xF2); x86_encode_r64_r64disp32(0x0F2D, r1, rb, d)
10.669 +#define CVTSD2SS_r32disp_xmm(rb,d,r1) OP(0xF2); x86_encode_r32_r32disp32(0x0F5A, r1, rb,d)
10.670 #define CVTSD2SS_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F5A, r2, r1)
10.671 -#define CVTSS2SD_rbpdisp_xmm(dsp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F5A, r1, dsp)
10.672 +#define CVTSS2SD_r32disp_xmm(rb,d,r1) OP(0xF3); x86_encode_r32_r32disp32(0x0F5A, r1, rb,d)
10.673 #define CVTSS2SD_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F5A, r2, r1)
10.674 #define CVTTSD2SIL_xmm_r32(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F2C, r2, r1)
10.675 -#define CVTTSD2SIL_rbpdisp_r32(d,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F2C, r1, d)
10.676 +#define CVTTSD2SIL_r32disp_r32(rb,d,r1) OP(0xF2); x86_encode_r32_r32disp32(0x0F2C, r1, rb, d)
10.677 #define CVTTSD2SIQ_xmm_r64(r1,r2) OP(0xF2); x86_encode_r64_rm64(0x0F2C, r2, r1)
10.678 -#define CVTTSD2SIQ_rbpdisp_r64(d,r1) OP(0xF2); x86_encode_r64_rbpdisp64(0x0F2C, r1, d)
10.679 +#define CVTTSD2SIQ_r64disp_r64(rb,d,r1) OP(0xF2); x86_encode_r64_r64disp32(0x0F2C, r1, rb, d)
10.680
10.681 -#define COMISD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F2F, r1, disp)
10.682 +#define COMISD_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0x0F2F, r1, rb,d)
10.683 #define COMISD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F2F, r2, r1)
10.684 -#define DIVSD_rbpdisp_xmm(disp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F5E, r1, disp)
10.685 +#define DIVSD_r32disp_xmm(rb,d,r1) OP(0xF2); x86_encode_r32_r32disp32(0x0F5E, r1, rb,d)
10.686 #define DIVSD_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F5E, r2, r1)
10.687 -#define MAXSD_rbpdisp_xmm(disp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F5F, r1, disp)
10.688 +#define MAXSD_r32disp_xmm(rb,d,r1) OP(0xF2); x86_encode_r32_r32disp32(0x0F5F, r1, rb,d)
10.689 #define MAXSD_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F5F, r2, r1)
10.690 -#define MINSD_rbpdisp_xmm(disp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F5D, r1, disp)
10.691 +#define MINSD_r32disp_xmm(rb,d,r1) OP(0xF2); x86_encode_r32_r32disp32(0x0F5D, r1, rb,d)
10.692 #define MINSD_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F5D, r2, r1)
10.693 -#define MOVSD_rbpdisp_xmm(disp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F10, r1, disp)
10.694 -#define MOVSD_xmm_rbpdisp(r1,disp) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F11, r1, disp)
10.695 +#define MOVSD_r32disp_xmm(rb,d,r1) OP(0xF2); x86_encode_r32_r32disp32(0x0F10, r1, rb,d)
10.696 +#define MOVSD_xmm_r32disp(r1,rb,d) OP(0xF2); x86_encode_r32_r32disp32(0x0F11, r1, rb,d)
10.697 #define MOVSD_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F10, r2, r1)
10.698 -#define MULSD_rbpdisp_xmm(disp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0xF59, r1, disp)
10.699 +#define MULSD_r32disp_xmm(rb,d,r1) OP(0xF2); x86_encode_r32_r32disp32(0xF59, r1, rb,d)
10.700 #define MULSD_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F59, r2, r1)
10.701 -#define SQRTSD_rbpdisp_xmm(disp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F51, r1, disp)
10.702 +#define SQRTSD_r32disp_xmm(rb,d,r1) OP(0xF2); x86_encode_r32_r32disp32(0x0F51, r1, rb,d)
10.703 #define SQRTSD_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F51, r2, r1)
10.704 -#define SUBSD_rbpdisp_xmm(disp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F5C, r1, disp)
10.705 +#define SUBSD_r32disp_xmm(rb,d,r1) OP(0xF2); x86_encode_r32_r32disp32(0x0F5C, r1, rb,d)
10.706 #define SUBSD_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F5C, r2, r1)
10.707 -#define UCOMISD_rbpdisp_xmm(dsp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F2E, r1, dsp)
10.708 +#define UCOMISD_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0x0F2E, r1, rb,d)
10.709 #define UCOMISD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F2E, r2, r1)
10.710
10.711 /* SSE3 floating point instructions */
10.712 -#define ADDSUBPD_rbpdisp_xmm(dsp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0FD0, r1, dsp)
10.713 +#define ADDSUBPD_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0x0FD0, r1, rb,d)
10.714 #define ADDSUBPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0FD0, r2, r1)
10.715 -#define ADDSUBPS_rbpdisp_xmm(dsp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0FD0, r1, dsp)
10.716 +#define ADDSUBPS_r32disp_xmm(rb,d,r1) OP(0xF2); x86_encode_r32_r32disp32(0x0FD0, r1, rb,d)
10.717 #define ADDSUBPS_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0FD0, r2, r1)
10.718 -#define HADDPD_rbpdisp_xmm(dsp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F7C, r1, dsp)
10.719 +#define HADDPD_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0x0F7C, r1, rb,d)
10.720 #define HADDPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F7C, r2, r1)
10.721 -#define HADDPS_rbpdisp_xmm(dsp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F7C, r1, dsp)
10.722 +#define HADDPS_r32disp_xmm(rb,d,r1) OP(0xF2); x86_encode_r32_r32disp32(0x0F7C, r1, rb,d)
10.723 #define HADDPS_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F7C, r2, r1)
10.724 -#define HSUBPD_rbpdisp_xmm(dsp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F7D, r1, dsp)
10.725 +#define HSUBPD_r32disp_xmm(rb,d,r1) OP(0x66); x86_encode_r32_r32disp32(0x0F7D, r1, rb,d)
10.726 #define HSUBPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F7D, r2, r1)
10.727 -#define HSUBPS_rbpdisp_xmm(dsp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F7D, r1, dsp)
10.728 +#define HSUBPS_r32disp_xmm(rb,d,r1) OP(0xF2); x86_encode_r32_r32disp32(0x0F7D, r1, rb,d)
10.729 #define HSUBPS_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F7D, r2, r1)
10.730 -#define MOVSHDUP_rbpdisp_xmm(dsp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F16, r1, dsp)
10.731 +#define MOVSHDUP_r32disp_xmm(rb,d,r1) OP(0xF3); x86_encode_r32_r32disp32(0x0F16, r1, rb,d)
10.732 #define MOVSHDUP_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F16, r2, r1)
10.733 -#define MOVSLDUP_rbpdisp_xmm(dsp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F12, r1, dsp)
10.734 +#define MOVSLDUP_r32disp_xmm(rb,d,r1) OP(0xF3); x86_encode_r32_r32disp32(0x0F12, r1, rb,d)
10.735 #define MOVSLDUP_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F12, r2, r1)
10.736
10.737 /************************ Import calling conventions *************************/
11.1 --- a/src/xlat/x86/x86target.c Tue Apr 07 10:55:03 2009 +0000
11.2 +++ b/src/xlat/x86/x86target.c Sun Apr 12 07:24:45 2009 +0000
11.3 @@ -21,19 +21,49 @@
11.4 #include "xlat/xlat.h"
11.5 #include "xlat/x86/x86op.h"
11.6
11.7 -static char *x86_reg_names[] = { "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
11.8 - "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
11.9 - "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
11.10 - "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15" };
11.11 +static char *x86_reg_names[] =
11.12 + { "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
11.13 + "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d",
11.14 + "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
11.15 + "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15" };
11.16
11.17 -void x86_target_lower( xir_basic_block_t xbb, xir_op_t begin, xir_op_t end );
11.18 +static char *x86_quad_reg_names[] =
11.19 + { "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
11.20 + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" };
11.21 +
11.22 uint32_t x86_target_get_code_size( xir_op_t begin, xir_op_t end );
11.23 uint32_t x86_target_codegen( target_data_t td, xir_op_t begin, xir_op_t end );
11.24 +static gboolean x86_target_is_legal( xir_opcode_t op, xir_operand_form_t arg0, xir_operand_form_t arg1 );
11.25 +static void x86_target_lower( xir_basic_block_t xbb, xir_op_t begin, xir_op_t end );
11.26
11.27 -struct xlat_target_machine x86_target_machine = { "x86", x86_reg_names,
11.28 - NULL, x86_target_lower, x86_target_get_code_size, x86_target_codegen
11.29 +static const char *x86_get_register_name( uint32_t reg, xir_type_t ty )
11.30 +{
11.31 + if( ty == XTY_QUAD && reg < 16 ) {
11.32 + return x86_quad_reg_names[reg];
11.33 + } else {
11.34 + return x86_reg_names[reg];
11.35 + }
11.36 +}
11.37 +
11.38 +struct xlat_target_machine x86_target_machine = { "x86", x86_get_register_name,
11.39 + x86_target_is_legal, x86_target_lower, x86_target_get_code_size, x86_target_codegen
11.40 };
11.41
11.42 +static gboolean x86_target_is_legal( xir_opcode_t op, xir_operand_form_t arg0, xir_operand_form_t arg1 )
11.43 +{
11.44 + switch( op ) {
11.45 + case OP_DEC: case OP_ST: case OP_LD:
11.46 + case OP_SHUFFLE:
11.47 + return arg0 == IMMEDIATE_OPERAND && arg1 == DEST_OPERAND;
11.48 + }
11.49 + if( arg0 == DEST_OPERAND ) {
11.50 + if( arg1 == DEST_OPERAND ) {
11.51 + return TRUE;
11.52 + } else if( arg1 == SOURCE_OPERAND || arg1 == TEMP_OPERAND ) {
11.53 + }
11.54 + }
11.55 +
11.56 +}
11.57
11.58
11.59 /******************************************************************************
11.60 @@ -51,11 +81,11 @@
11.61 * displacement.
11.62 */
11.63 static inline void xir_append_xlat( xir_basic_block_t xbb, void *address_space,
11.64 - int opertype, int operval )
11.65 + int opertype, int operval, int tmpq )
11.66 {
11.67 if( sizeof(void *) == 8 ) {
11.68 - xir_append_ptr_op2( xbb, OP_MOVQ, address_space, SOURCE_REGISTER_OPERAND, REG_TMP4 );
11.69 - xir_append_op2( xbb, OP_XLAT, SOURCE_REGISTER_OPERAND, REG_TMP4, opertype, operval );
11.70 + xir_append_ptr_op2( xbb, OP_MOVQ, address_space, TEMP_OPERAND, tmpq );
11.71 + xir_append_op2( xbb, OP_XLAT, TEMP_OPERAND, tmpq, opertype, operval );
11.72 } else {
11.73 xir_append_ptr_op2( xbb, OP_XLAT, address_space, opertype, operval );
11.74 }
11.75 @@ -70,94 +100,105 @@
11.76 * call/lut %tmp3, $operation_offset
11.77 * mov %eax, result
11.78 */
11.79 -static void lower_mem_load( xir_basic_block_t xbb, xir_op_t it, void *addr_space, int offset )
11.80 +static void lower_mem_load( xir_basic_block_t xbb, xir_op_t it, void *addr_space, int offset,
11.81 + int tmpl, int tmpq)
11.82 {
11.83 xir_op_t start =
11.84 - xir_append_op2( xbb, OP_MOV, it->operand[0].type, it->operand[0].value.i, TARGET_REGISTER_OPERAND, REG_ARG1 );
11.85 - xir_append_op2( xbb, OP_MOV, it->operand[0].type, it->operand[0].value.i, SOURCE_REGISTER_OPERAND, REG_TMP3 );
11.86 - xir_append_op2( xbb, OP_SLR, INT_IMM_OPERAND, 12, SOURCE_REGISTER_OPERAND, REG_TMP3 );
11.87 - xir_append_xlat( xbb, addr_space, SOURCE_REGISTER_OPERAND, REG_TMP3 );
11.88 + xir_append_op2( xbb, OP_MOV, it->operand[0].form, it->operand[0].value.i, DEST_OPERAND, REG_ARG1 );
11.89 + xir_append_op2( xbb, OP_MOV, it->operand[0].form, it->operand[0].value.i, TEMP_OPERAND, tmpl );
11.90 + xir_append_op2( xbb, OP_SLR, IMMEDIATE_OPERAND, 12, TEMP_OPERAND, tmpl );
11.91 + xir_append_xlat( xbb, addr_space, TEMP_OPERAND, tmpl, tmpq );
11.92 xir_insert_block(start,xbb->ir_ptr-1, it);
11.93 if( XOP_WRITES_OP2(it) ) {
11.94 - xir_insert_op( xir_append_op2( xbb, OP_MOV, TARGET_REGISTER_OPERAND, REG_RESULT1, it->operand[1].type, it->operand[1].value.i ), it->next );
11.95 + xir_insert_op( xir_append_op2( xbb, OP_MOV, DEST_OPERAND, REG_RESULT1, it->operand[1].form, it->operand[1].value.i ), it->next );
11.96 }
11.97 /* Replace original op with CALLLUT */
11.98 it->opcode = OP_CALLLUT;
11.99 - it->operand[0].type = SOURCE_REGISTER_OPERAND;
11.100 - it->operand[0].value.i = REG_TMP3;
11.101 - it->operand[1].type = INT_IMM_OPERAND;
11.102 + it->operand[0].form = TEMP_OPERAND;
11.103 + it->operand[0].value.i = tmpl;
11.104 + it->operand[1].form = IMMEDIATE_OPERAND;
11.105 it->operand[1].value.i = offset;
11.106 }
11.107
11.108 -static void lower_mem_store( xir_basic_block_t xbb, xir_op_t it, void *addr_space, int offset )
11.109 +static void lower_mem_store( xir_basic_block_t xbb, xir_op_t it, void *addr_space, int offset,
11.110 + int tmpl, int tmpq)
11.111 {
11.112 xir_op_t start =
11.113 - xir_append_op2( xbb, OP_MOV, it->operand[0].type, it->operand[0].value.i, TARGET_REGISTER_OPERAND, REG_ARG1 );
11.114 - xir_append_op2( xbb, OP_MOV, it->operand[1].type, it->operand[1].value.i, TARGET_REGISTER_OPERAND, REG_ARG2 );
11.115 - xir_append_op2( xbb, OP_MOV, it->operand[0].type, it->operand[0].value.i, SOURCE_REGISTER_OPERAND, REG_TMP3 );
11.116 - xir_append_op2( xbb, OP_SLR, INT_IMM_OPERAND, 12, SOURCE_REGISTER_OPERAND, REG_TMP3 );
11.117 - xir_append_xlat( xbb, addr_space, SOURCE_REGISTER_OPERAND, REG_TMP3 );
11.118 + xir_append_op2( xbb, OP_MOV, it->operand[0].form, it->operand[0].value.i, DEST_OPERAND, REG_ARG1 );
11.119 + xir_append_op2( xbb, OP_MOV, it->operand[1].form, it->operand[1].value.i, DEST_OPERAND, REG_ARG2 );
11.120 + xir_append_op2( xbb, OP_MOV, it->operand[0].form, it->operand[0].value.i, TEMP_OPERAND, tmpl );
11.121 + xir_append_op2( xbb, OP_SLR, IMMEDIATE_OPERAND, 12, TEMP_OPERAND, tmpl );
11.122 + xir_append_xlat( xbb, addr_space, TEMP_OPERAND, tmpl, tmpq );
11.123 xir_insert_block(start,xbb->ir_ptr-1, it);
11.124 /* Replace original op with CALLLUT */
11.125 it->opcode = OP_CALLLUT;
11.126 - it->operand[0].type = SOURCE_REGISTER_OPERAND;
11.127 - it->operand[0].value.i = REG_TMP3;
11.128 - it->operand[1].type = INT_IMM_OPERAND;
11.129 + it->operand[0].form = TEMP_OPERAND;
11.130 + it->operand[0].value.i = tmpl;
11.131 + it->operand[1].form = IMMEDIATE_OPERAND;
11.132 it->operand[1].value.i = offset;
11.133 }
11.134
11.135 -static void lower_mem_loadq( xir_basic_block_t xbb, xir_op_t it, void *addr_space )
11.136 +static void lower_mem_loadq( xir_basic_block_t xbb, xir_op_t it, void *addr_space,
11.137 + int tmpl, int tmpq )
11.138 {
11.139 - int resulttype = it->operand[1].type;
11.140 + int addrtype = it->operand[0].form;
11.141 + int addrval = it->operand[0].value.i;
11.142 + int resulttype = it->operand[1].form;
11.143 uint32_t resultval = it->operand[1].value.i;
11.144
11.145 /* First block */
11.146 xir_op_t start =
11.147 - xir_append_op2( xbb, OP_MOV, it->operand[0].type, it->operand[0].value.i, TARGET_REGISTER_OPERAND, REG_ARG1 );
11.148 - xir_append_op2( xbb, OP_MOV, it->operand[0].type, it->operand[0].value.i, SOURCE_REGISTER_OPERAND, REG_TMP3 );
11.149 - xir_append_op2( xbb, OP_SLR, INT_IMM_OPERAND, 12, SOURCE_REGISTER_OPERAND, REG_TMP3 );
11.150 - xir_append_xlat( xbb, addr_space, SOURCE_REGISTER_OPERAND, REG_TMP3 );
11.151 + xir_append_op2( xbb, OP_MOV, addrtype, addrval, TEMP_OPERAND, tmpl );
11.152 + xir_append_op2( xbb, OP_SLR, IMMEDIATE_OPERAND, 12, TEMP_OPERAND, tmpl );
11.153 + xir_append_xlat( xbb, addr_space, TEMP_OPERAND, tmpl, tmpq );
11.154 + xir_append_op2( xbb, OP_MOV, it->operand[0].form, it->operand[0].value.i, DEST_OPERAND, REG_ARG1 );
11.155 xir_insert_block(start,xbb->ir_ptr-1, it);
11.156 /* Replace original op with CALLLUT */
11.157 it->opcode = OP_CALLLUT;
11.158 - it->operand[0].type = SOURCE_REGISTER_OPERAND;
11.159 - it->operand[0].value.i = REG_TMP3;
11.160 - it->operand[1].type = INT_IMM_OPERAND;
11.161 + it->operand[0].form = TEMP_OPERAND;
11.162 + it->operand[0].value.i = tmpl;
11.163 + it->operand[1].form = IMMEDIATE_OPERAND;
11.164 it->operand[1].value.i = MEM_FUNC_OFFSET(read_long);
11.165
11.166 /* Second block */
11.167 - start = xir_append_op2( xbb, OP_MOV, TARGET_REGISTER_OPERAND, REG_RESULT1, resulttype, resultval+1 );
11.168 - xir_append_op2( xbb, OP_ADD, INT_IMM_OPERAND, 4, SOURCE_REGISTER_OPERAND, REG_ARG1 );
11.169 - xir_op_t fin = xir_append_op2( xbb, OP_CALLLUT, SOURCE_REGISTER_OPERAND, REG_TMP3, INT_IMM_OPERAND, MEM_FUNC_OFFSET(read_long) );
11.170 - xir_append_op2( xbb, OP_MOV, TARGET_REGISTER_OPERAND, REG_RESULT1, resulttype, resultval );
11.171 + start = xir_append_op2( xbb, OP_MOV, DEST_OPERAND, REG_RESULT1, resulttype, resultval+4 );
11.172 + xir_append_op2( xbb, OP_MOV, addrtype, addrval, DEST_OPERAND, REG_ARG1 );
11.173 + xir_append_op2( xbb, OP_ADD, IMMEDIATE_OPERAND, 4, DEST_OPERAND, REG_ARG1 );
11.174 + xir_op_t fin = xir_append_op2( xbb, OP_CALLLUT, TEMP_OPERAND, tmpl, IMMEDIATE_OPERAND, MEM_FUNC_OFFSET(read_long) );
11.175 + xir_append_op2( xbb, OP_MOV, DEST_OPERAND, REG_RESULT1, resulttype, resultval );
11.176 fin->exc = it->exc;
11.177 xir_insert_block(start, xbb->ir_ptr-1, it->next);
11.178 }
11.179
11.180 -static void lower_mem_storeq( xir_basic_block_t xbb, xir_op_t it, void *addr_space )
11.181 +static void lower_mem_storeq( xir_basic_block_t xbb, xir_op_t it, void *addr_space,
11.182 + int tmpl, int tmpq)
11.183 {
11.184 - int argtype = it->operand[1].type;
11.185 + int addrtype = it->operand[0].form;
11.186 + int addrval = it->operand[0].value.i;
11.187 + int argtype = it->operand[1].form;
11.188 uint32_t argval = it->operand[1].value.i;
11.189
11.190 /* First block */
11.191 xir_op_t start =
11.192 - xir_append_op2( xbb, OP_MOV, it->operand[0].type, it->operand[0].value.i, TARGET_REGISTER_OPERAND, REG_ARG1 );
11.193 - xir_append_op2( xbb, OP_MOV, argtype, argval+1, TARGET_REGISTER_OPERAND, REG_ARG2 );
11.194 - xir_append_op2( xbb, OP_MOV, it->operand[0].type, it->operand[0].value.i, SOURCE_REGISTER_OPERAND, REG_TMP3 );
11.195 - xir_append_op2( xbb, OP_SLR, INT_IMM_OPERAND, 12, SOURCE_REGISTER_OPERAND, REG_TMP3 );
11.196 - xir_append_xlat( xbb, addr_space, SOURCE_REGISTER_OPERAND, REG_TMP3 );
11.197 + xir_append_op2( xbb, OP_MOV, addrtype, addrval, TEMP_OPERAND, tmpl );
11.198 + xir_append_op2( xbb, OP_SLR, IMMEDIATE_OPERAND, 12, TEMP_OPERAND, tmpl );
11.199 + xir_append_xlat( xbb, addr_space, TEMP_OPERAND, tmpl, tmpq );
11.200 + xir_append_op2( xbb, OP_MOV, addrtype, addrval, DEST_OPERAND, REG_ARG1 );
11.201 + xir_append_op2( xbb, OP_MOV, argtype, argval+4, DEST_OPERAND, REG_ARG2 );
11.202 xir_insert_block(start,xbb->ir_ptr-1, it);
11.203 /* Replace original op with CALLLUT */
11.204 it->opcode = OP_CALLLUT;
11.205 - it->operand[0].type = SOURCE_REGISTER_OPERAND;
11.206 - it->operand[0].value.i = REG_TMP3;
11.207 - it->operand[1].type = INT_IMM_OPERAND;
11.208 + it->operand[0].form = TEMP_OPERAND;
11.209 + it->operand[0].value.i = tmpl;
11.210 + it->operand[1].form = IMMEDIATE_OPERAND;
11.211 it->operand[1].value.i = MEM_FUNC_OFFSET(read_long);
11.212
11.213 /* Second block */
11.214 - xir_append_op2( xbb, OP_MOV, argtype, argval, TARGET_REGISTER_OPERAND, REG_ARG2 );
11.215 - xir_append_op2( xbb, OP_ADD, INT_IMM_OPERAND, 4, SOURCE_REGISTER_OPERAND, REG_ARG1 );
11.216 - xir_op_t fin = xir_append_op2( xbb, OP_CALLLUT, SOURCE_REGISTER_OPERAND, REG_TMP3, INT_IMM_OPERAND, MEM_FUNC_OFFSET(read_long) );
11.217 + start =
11.218 + xir_append_op2( xbb, OP_MOV, addrtype, addrval, DEST_OPERAND, REG_ARG1 );
11.219 + xir_append_op2( xbb, OP_ADD, IMMEDIATE_OPERAND, 4, DEST_OPERAND, REG_ARG1 );
11.220 + xir_append_op2( xbb, OP_MOV, argtype, argval, DEST_OPERAND, REG_ARG2 );
11.221 + xir_op_t fin = xir_append_op2( xbb, OP_CALLLUT, TEMP_OPERAND, tmpl, IMMEDIATE_OPERAND, MEM_FUNC_OFFSET(read_long) );
11.222 fin->exc = it->exc;
11.223 xir_insert_block(start, xbb->ir_ptr-1, it->next);
11.224 }
11.225 @@ -172,8 +213,13 @@
11.226 * Run in reverse order so we can track liveness of the flags as we go (for ALU
11.227 * lowering to flags-modifying instructions)
11.228 */
11.229 -void x86_target_lower( xir_basic_block_t xbb, xir_op_t start, xir_op_t end )
11.230 +static void x86_target_lower( xir_basic_block_t xbb, xir_op_t start, xir_op_t end )
11.231 {
11.232 + int tmpl = xir_alloc_temp_reg( xbb, XTY_LONG, -1 );
11.233 + int tmp2 = xir_alloc_temp_reg( xbb, XTY_LONG, -1 );
11.234 + int tmpq = xir_alloc_temp_reg( xbb, XTY_QUAD, -1 );
11.235 + int tmpd = -1, tmpf = -1; /* allocate these when we need them */
11.236 +
11.237 gboolean flags_live = FALSE;
11.238 xir_op_t it;
11.239 for( it=end; it != NULL; it = it->prev ) {
11.240 @@ -188,8 +234,8 @@
11.241 case OP_SUBB: case OP_SDIV:
11.242 it->opcode++;
11.243 if( flags_live ) {
11.244 - xir_insert_op( XOP1( OP_SAVEFLAGS, REG_TMP5 ), it );
11.245 - xir_insert_op( XOP1( OP_RESTFLAGS, REG_TMP5 ), it->next );
11.246 + xir_insert_op( XOP1T( OP_SAVEFLAGS, tmp2 ), it );
11.247 + xir_insert_op( XOP1T( OP_RESTFLAGS, tmp2 ), it->next );
11.248 }
11.249 break;
11.250
11.251 @@ -197,31 +243,31 @@
11.252 /* Promote to *S form since we don't have a non-flag version */
11.253 it->opcode++;
11.254 if( flags_live ) {
11.255 - xir_insert_op( XOP1( OP_SAVEFLAGS, REG_TMP5 ), it );
11.256 - xir_insert_op( XOP1( OP_RESTFLAGS, REG_TMP5 ), it->next );
11.257 + xir_insert_op( XOP1T( OP_SAVEFLAGS, tmp2 ), it );
11.258 + xir_insert_op( XOP1T( OP_RESTFLAGS, tmp2 ), it->next );
11.259 }
11.260 -
11.261 + /* Fallthrough */
11.262 case OP_SARS: case OP_SLLS: case OP_SLRS:
11.263 case OP_RCL: case OP_RCR: case OP_ROLS: case OP_RORS:
11.264 /* Insert mov %reg, %ecx */
11.265 - if( it->operand[0].type == SOURCE_REGISTER_OPERAND ) {
11.266 - xir_insert_op( xir_append_op2( xbb, OP_MOV, SOURCE_REGISTER_OPERAND, it->operand[0].value.i, TARGET_REGISTER_OPERAND, REG_ECX ), it );
11.267 - it->operand[0].type = TARGET_REGISTER_OPERAND;
11.268 + if( XOP_IS_REG(it,0) ) {
11.269 + xir_insert_op( xir_append_op2( xbb, OP_MOV, it->operand[0].form, it->operand[0].value.i, DEST_OPERAND, REG_ECX ), it );
11.270 + it->operand[0].form = DEST_OPERAND;
11.271 it->operand[0].value.i = REG_ECX;
11.272 }
11.273 break;
11.274 case OP_SHLD: case OP_SHAD:
11.275 /* Insert mov %reg, %ecx */
11.276 - if( it->operand[0].type == SOURCE_REGISTER_OPERAND ) {
11.277 - xir_insert_op( xir_append_op2( xbb, OP_MOV, SOURCE_REGISTER_OPERAND, it->operand[0].value.i, TARGET_REGISTER_OPERAND, REG_ECX ), it );
11.278 - it->operand[0].type = TARGET_REGISTER_OPERAND;
11.279 + if( XOP_IS_REG(it,0) ) {
11.280 + xir_insert_op( xir_append_op2( xbb, OP_MOV, it->operand[0].form, it->operand[0].value.i, DEST_OPERAND, REG_ECX ), it );
11.281 + it->operand[0].form = DEST_OPERAND;
11.282 it->operand[0].value.i = REG_ECX;
11.283 - } else if( it->operand[0].type == INT_IMM_OPERAND ) {
11.284 + } else if( it->operand[0].form == IMMEDIATE_OPERAND ) {
11.285 /* Simplify down to SAR/SLL/SLR where we have a constant shift */
11.286 if( it->operand[0].value.i == 0 ) {
11.287 /* No-op */
11.288 it->opcode = OP_NOP;
11.289 - it->operand[1].type = it->operand[0].type = NO_OPERAND;
11.290 + it->operand[1].form = it->operand[0].form = NO_OPERAND;
11.291 } else if( it->operand[0].value.i > 0 ) {
11.292 it->opcode = OP_SLL;
11.293 } else if( (it->operand[0].value.i & 0x1F) == 0 ) {
11.294 @@ -243,87 +289,89 @@
11.295 break;
11.296
11.297 case OP_CALL1: /* Reduce to mov reg, %eax; call0 ptr */
11.298 - xir_insert_op( xir_append_op2( xbb, OP_MOV, it->operand[1].type, it->operand[1].value.i, TARGET_REGISTER_OPERAND, REG_ARG1 ), it );
11.299 + xir_insert_op( xir_append_op2( xbb, OP_MOV, it->operand[1].form, it->operand[1].value.i, DEST_OPERAND, REG_ARG1 ), it );
11.300 it->opcode = OP_CALL0;
11.301 - it->operand[1].type = NO_OPERAND;
11.302 + it->operand[1].form = NO_OPERAND;
11.303 break;
11.304 case OP_CALLR: /* reduce to call0 ptr, mov result, reg */
11.305 - xir_insert_op( xir_append_op2( xbb, OP_MOV, TARGET_REGISTER_OPERAND, REG_RESULT1, it->operand[1].type, it->operand[1].value.i), it->next );
11.306 + xir_insert_op( xir_append_op2( xbb, OP_MOV, DEST_OPERAND, REG_RESULT1, it->operand[1].form, it->operand[1].value.i), it->next );
11.307 it->opcode = OP_CALL0;
11.308 - it->operand[1].type = NO_OPERAND;
11.309 + it->operand[1].form = NO_OPERAND;
11.310 break;
11.311 case OP_LOADB:
11.312 - lower_mem_load( xbb, it, xbb->address_space, MEM_FUNC_OFFSET(read_byte) );
11.313 + lower_mem_load( xbb, it, xbb->address_space, MEM_FUNC_OFFSET(read_byte), tmpl, tmpq );
11.314 break;
11.315 case OP_LOADW:
11.316 - lower_mem_load( xbb, it, xbb->address_space, MEM_FUNC_OFFSET(read_word) );
11.317 + lower_mem_load( xbb, it, xbb->address_space, MEM_FUNC_OFFSET(read_word), tmpl, tmpq );
11.318 break;
11.319 case OP_LOADL:
11.320 - lower_mem_load( xbb, it, xbb->address_space, MEM_FUNC_OFFSET(read_long) );
11.321 + lower_mem_load( xbb, it, xbb->address_space, MEM_FUNC_OFFSET(read_long), tmpl, tmpq );
11.322 break;
11.323 case OP_LOADBFW:
11.324 - lower_mem_load( xbb, it, xbb->address_space, MEM_FUNC_OFFSET(read_byte_for_write) );
11.325 + lower_mem_load( xbb, it, xbb->address_space, MEM_FUNC_OFFSET(read_byte_for_write), tmpl, tmpq );
11.326 break;
11.327 case OP_LOADQ:
11.328 - lower_mem_loadq( xbb, it, xbb->address_space );
11.329 + lower_mem_loadq( xbb, it, xbb->address_space, tmpl, tmpq );
11.330 break;
11.331 case OP_PREF:
11.332 - lower_mem_load( xbb, it, xbb->address_space, MEM_FUNC_OFFSET(prefetch) );
11.333 + lower_mem_load( xbb, it, xbb->address_space, MEM_FUNC_OFFSET(prefetch), tmpl, tmpq );
11.334 break;
11.335 case OP_OCBI:
11.336 case OP_OCBP:
11.337 case OP_OCBWB:
11.338 break;
11.339 case OP_STOREB:
11.340 - lower_mem_store( xbb, it, xbb->address_space, MEM_FUNC_OFFSET(write_byte) );
11.341 + lower_mem_store( xbb, it, xbb->address_space, MEM_FUNC_OFFSET(write_byte), tmpl, tmpq );
11.342 break;
11.343 case OP_STOREW:
11.344 - lower_mem_store( xbb, it, xbb->address_space, MEM_FUNC_OFFSET(write_word) );
11.345 + lower_mem_store( xbb, it, xbb->address_space, MEM_FUNC_OFFSET(write_word), tmpl, tmpq );
11.346 break;
11.347 case OP_STOREL:
11.348 - lower_mem_store( xbb, it, xbb->address_space, MEM_FUNC_OFFSET(write_long) );
11.349 + lower_mem_store( xbb, it, xbb->address_space, MEM_FUNC_OFFSET(write_long), tmpl, tmpq );
11.350 break;
11.351 case OP_STORELCA:
11.352 - lower_mem_store( xbb, it, xbb->address_space, MEM_FUNC_OFFSET(write_long) );
11.353 + lower_mem_store( xbb, it, xbb->address_space, MEM_FUNC_OFFSET(write_long), tmpl, tmpq );
11.354 break;
11.355 case OP_STOREQ:
11.356 - lower_mem_storeq( xbb, it, xbb->address_space );
11.357 + lower_mem_storeq( xbb, it, xbb->address_space, tmpl, tmpq );
11.358 break;
11.359
11.360 case OP_SHUFFLE:
11.361 - assert( it->operand[0].type == INT_IMM_OPERAND );
11.362 + assert( it->operand[0].form == IMMEDIATE_OPERAND );
11.363 if( it->operand[0].value.i = 0x2134 ) { /* Swap low bytes */
11.364 /* This is an xchg al,ah, but we need to force the operand into one of the bottom 4 registers */
11.365 - xir_insert_op( xir_append_op2( xbb, OP_MOV, it->operand[1].type, it->operand[1].value.i, TARGET_REGISTER_OPERAND, REG_EAX ), it);
11.366 - it->operand[1].type = TARGET_REGISTER_OPERAND;
11.367 + xir_insert_op( xir_append_op2( xbb, OP_MOV, it->operand[1].form, it->operand[1].value.i, DEST_OPERAND, REG_EAX ), it);
11.368 + it->operand[1].form = DEST_OPERAND;
11.369 it->operand[1].value.i = REG_EAX;
11.370 } else if( it->operand[0].value.i != 0x4321 ) {
11.371 /* 4321 is a full byteswap (directly supported) - use shift/mask/or
11.372 * sequence for anything else. Although we could use PSHUF...
11.373 */
11.374 - it = xir_shuffle_lower( xbb, it, REG_TMP3, REG_TMP4 );
11.375 + it = xir_shuffle_lower( xbb, it, tmpl, tmp2 );
11.376 }
11.377 break;
11.378 case OP_NEGF:
11.379 - xir_insert_op( xir_append_op2( xbb, OP_MOV, INT_IMM_OPERAND, 0, SOURCE_REGISTER_OPERAND, REG_TMP4 ), it);
11.380 - xir_insert_op( xir_append_op2( xbb, OP_MOV, SOURCE_REGISTER_OPERAND, REG_TMP4,it->operand[0].type, it->operand[0].value.i), it->next );
11.381 + if( tmpf == -1 ) tmpf = xir_alloc_temp_reg( xbb, XTY_FLOAT, -1 );
11.382 + xir_insert_op( xir_append_op2( xbb, OP_MOV, IMMEDIATE_OPERAND, 0, TEMP_OPERAND, tmpf ), it);
11.383 + xir_insert_op( xir_append_op2( xbb, OP_MOV, TEMP_OPERAND, tmpf,it->operand[0].form, it->operand[0].value.i), it->next );
11.384 it->opcode = OP_SUBF;
11.385 - it->operand[1].type = SOURCE_REGISTER_OPERAND;
11.386 - it->operand[1].value.i = REG_TMP4;
11.387 + it->operand[1].form = TEMP_OPERAND;
11.388 + it->operand[1].value.i = tmpf;
11.389 break;
11.390 case OP_NEGD:
11.391 - xir_insert_op( xir_append_op2( xbb, OP_MOVQ, INT_IMM_OPERAND, 0, SOURCE_REGISTER_OPERAND, REG_TMPQ0 ), it);
11.392 - xir_insert_op( xir_append_op2( xbb, OP_MOVQ, SOURCE_REGISTER_OPERAND, REG_TMPQ0,it->operand[0].type, it->operand[0].value.i), it->next );
11.393 + if( tmpd == -1 ) tmpd = xir_alloc_temp_reg( xbb, XTY_DOUBLE, -1 );
11.394 + xir_insert_op( xir_append_op2( xbb, OP_MOVQ, IMMEDIATE_OPERAND, 0, TEMP_OPERAND, REG_TMPQ0 ), it);
11.395 + xir_insert_op( xir_append_op2( xbb, OP_MOVQ, TEMP_OPERAND, tmpd,it->operand[0].form, it->operand[0].value.i), it->next );
11.396 it->opcode = OP_SUBD;
11.397 - it->operand[1].type = SOURCE_REGISTER_OPERAND;
11.398 - it->operand[1].value.i = REG_TMPQ0;
11.399 + it->operand[1].form = TEMP_OPERAND;
11.400 + it->operand[1].value.i = tmpd;
11.401 break;
11.402 case OP_XLAT:
11.403 /* Insert temp register if translating through a 64-bit pointer */
11.404 - if( XOP_IS_PTRIMM(it, 0) && sizeof(void *) == 8 && it->operand[0].value.q >= 0x100000000LL ) {
11.405 - xir_insert_op( XOP2P( OP_MOVQ, it->operand[0].value.p, REG_TMP4 ), it );
11.406 - it->operand[0].type = SOURCE_REGISTER_OPERAND;
11.407 - it->operand[0].value.i = REG_TMP4;
11.408 + if( XOP_IS_IMMP(it, 0) && sizeof(void *) == 8 && it->operand[0].value.q >= 0x100000000LL ) {
11.409 + xir_insert_op( XOP2PT( OP_MOVQ, it->operand[0].value.p, tmpq ), it );
11.410 + it->operand[0].form = TEMP_OPERAND;
11.411 + it->operand[0].value.i = tmpq;
11.412 }
11.413 break;
11.414 }
11.415 @@ -335,7 +383,7 @@
11.416 }
11.417
11.418 /* Lower pointer operands to INT or QUAD according to address and value size. */
11.419 - if( it->operand[0].type == POINTER_OPERAND ) {
11.420 + if( XOP_IS_IMMP(it,0) ) {
11.421 if( sizeof(void *) == 8 && it->operand[0].value.q >= 0x100000000LL ) {
11.422 if( it->opcode == OP_MOV ) {
11.423 // Promote MOV ptr, reg to MOVQ ptr, reg
11.424 @@ -346,17 +394,15 @@
11.425 * (We only check the first operand as there are no instructions that
11.426 * permit the second operand to be an immediate pointer.
11.427 */
11.428 - xir_insert_op( xir_append_op2( xbb, OP_MOVQ, POINTER_OPERAND, it->operand[0].value.q, SOURCE_REGISTER_OPERAND, REG_TMP4 ), it );
11.429 - it->operand[0].type = SOURCE_REGISTER_OPERAND;
11.430 - it->operand[1].value.i = REG_TMP4;
11.431 + xir_insert_op( xir_append_op2( xbb, OP_MOVQ, IMMEDIATE_OPERAND, it->operand[0].value.q, TEMP_OPERAND, tmpq ), it );
11.432 + it->operand[0].form = TEMP_OPERAND;
11.433 + it->operand[1].value.i = tmpq;
11.434 }
11.435 - it->operand[0].type = QUAD_IMM_OPERAND;
11.436 } else {
11.437 if( it->opcode == OP_MOVQ ) {
11.438 /* Lower a MOVQ of a 32-bit quantity to a MOV, and save the 5 bytes */
11.439 it->opcode = OP_MOV;
11.440 }
11.441 - it->operand[0].type = INT_IMM_OPERAND;
11.442 }
11.443 }
11.444
12.1 --- a/src/xlat/xir.c Tue Apr 07 10:55:03 2009 +0000
12.2 +++ b/src/xlat/xir.c Sun Apr 12 07:24:45 2009 +0000
12.3 @@ -20,15 +20,17 @@
12.4 #include <string.h>
12.5 #include <assert.h>
12.6 #include "xlat/xir.h"
12.7 +#include "xlat/xlat.h"
12.8
12.9 -static const char **xir_source_register_names = NULL;
12.10 -static const char **xir_target_register_names = NULL;
12.11 static const struct xir_symbol_entry *xir_symbol_table = NULL;
12.12
12.13 static const char *XIR_CC_NAMES[] = {
12.14 "ov", "no", "uge", "ult", "ule", "ugt", "eq", "ne",
12.15 "neg", "pos", "sge", "slt", "sle", "sgt" };
12.16 -static const int XIR_OPERAND_SIZE[] = { 4, 8, 4, 8, 16, 64, 0, 0 };
12.17 +static const char XIR_TYPE_CODES[] = { 'l', 'q', 'f', 'd', 'v', 'm' };
12.18 +
12.19 +const int XIR_OPERAND_SIZE[] = { 4, 8, 4, 8, 16, 64, (sizeof(void *)), 0 };
12.20 +
12.21
12.22 const struct xir_opcode_entry XIR_OPCODE_TABLE[] = {
12.23 { "NOP", OPM_NO },
12.24 @@ -99,7 +101,6 @@
12.25 { "TST", OPM_R_R_TW },
12.26 { "XOR", OPM_R_RW },
12.27 { "XORS", OPM_R_RW_TW },
12.28 - { "XLAT", OPM_R_RW },
12.29
12.30 { "ABSD", OPM_DR_DW },
12.31 { "ABSF", OPM_FR_FW },
12.32 @@ -163,9 +164,13 @@
12.33 { "RAISE/ME", OPM_R_R | OPM_EXC },
12.34 { "RAISE/MNE", OPM_R_R | OPM_EXC },
12.35
12.36 + /* Native/pointer operations */
12.37 { "CALL/LUT", OPM_R_R | OPM_EXC },
12.38 { "CALL1", OPM_R_R | OPM_CLB },
12.39 { "CALLR", OPM_R_W | OPM_CLB },
12.40 + { "LOADPTRL", OPM_R_W | 0x060 },
12.41 + { "LOADPTRQ", OPM_R_W | 0x160 },
12.42 + { "XLAT", OPM_R_RW | 0x600 }, /* Xlat Rm, Rn - Read native [Rm+Rn] and store in Rn */
12.43
12.44 { "ADDQSAT32", OPM_R_R | OPM_CLBT|OPM_Q_Q },
12.45 { "ADDQSAT48", OPM_R_R | OPM_CLBT|OPM_Q_Q },
12.46 @@ -176,10 +181,23 @@
12.47
12.48 };
12.49
12.50 -void xir_set_register_names( const char **source_regs, const char **target_regs )
12.51 +void xir_clear_basic_block( xir_basic_block_t xbb )
12.52 {
12.53 - xir_source_register_names = source_regs;
12.54 - xir_target_register_names = target_regs;
12.55 + xbb->next_temp_reg = 0;
12.56 + xir_alloc_temp_reg( xbb, XTY_LONG, -1 );
12.57 + xir_alloc_temp_reg( xbb, XTY_LONG, -1 );
12.58 + xir_alloc_temp_reg( xbb, XTY_LONG, -1 );
12.59 + xir_alloc_temp_reg( xbb, XTY_QUAD, -1 );
12.60 + xir_alloc_temp_reg( xbb, XTY_QUAD, -1 );
12.61 +}
12.62 +
12.63 +uint32_t xir_alloc_temp_reg( xir_basic_block_t xbb, xir_type_t type, int home )
12.64 +{
12.65 + assert( xbb->next_temp_reg <= MAX_TEMP_REGISTER );
12.66 + int reg = xbb->next_temp_reg++;
12.67 + xbb->temp_regs[reg].type = type;
12.68 + xbb->temp_regs[reg].home_register = home;
12.69 + return reg;
12.70 }
12.71
12.72 void xir_set_symbol_table( const struct xir_symbol_entry *symtab )
12.73 @@ -200,54 +218,75 @@
12.74 return NULL;
12.75 }
12.76
12.77 -int xir_snprint_operand( char *buf, int buflen, xir_operand_t op )
12.78 +static int xir_snprint_operand( char *buf, int buflen, xir_basic_block_t xbb, xir_operand_t op, xir_type_t ty )
12.79 {
12.80 const char *name;
12.81 - switch( op->type ) {
12.82 - case INT_IMM_OPERAND:
12.83 - return snprintf( buf, buflen, "$0x%x", op->value.i );
12.84 - case FLOAT_IMM_OPERAND:
12.85 - return snprintf( buf, buflen, "%f", op->value.f );
12.86 - case DOUBLE_IMM_OPERAND:
12.87 - return snprintf( buf, buflen, "%f", op->value.f );
12.88 - case POINTER_OPERAND:
12.89 - name = xir_lookup_symbol( op->value.p );
12.90 + xir_temp_register_t tmp;
12.91 +
12.92 + switch( op->form ) {
12.93 + case IMMEDIATE_OPERAND:
12.94 + switch( ty ) {
12.95 + case XTY_LONG:
12.96 + return snprintf( buf, buflen, "$0x%x", op->value.i );
12.97 + case XTY_QUAD:
12.98 + return snprintf( buf, buflen, "$0x%lld", op->value.q );
12.99 + case XTY_FLOAT:
12.100 + return snprintf( buf, buflen, "%f", op->value.f );
12.101 + case XTY_DOUBLE:
12.102 + return snprintf( buf, buflen, "%f", op->value.f );
12.103 + case XTY_PTR:
12.104 + name = xir_lookup_symbol( op->value.p );
12.105 + if( name != NULL ) {
12.106 + return snprintf( buf, buflen, "*%s", name );
12.107 + } else {
12.108 + return snprintf( buf, buflen, "*%p", op->value.p );
12.109 + }
12.110 + default:
12.111 + return snprintf( buf, buflen, "ILLOP" );
12.112 + }
12.113 + break;
12.114 + case SOURCE_OPERAND:
12.115 + name = xbb->source->get_register_name(op->value.i, ty);
12.116 if( name != NULL ) {
12.117 - return snprintf( buf, buflen, "*%s", name );
12.118 + return snprintf( buf, buflen, "%%%s", name );
12.119 } else {
12.120 - return snprintf( buf, buflen, "*%p", op->value.p );
12.121 + return snprintf( buf, buflen, "%%src%d", op->value.i );
12.122 }
12.123 - case SOURCE_REGISTER_OPERAND:
12.124 - if( op->value.i >= MIN_SOURCE_REGISTER && op->value.i <= MAX_SOURCE_REGISTER ) {
12.125 - if( xir_source_register_names ) {
12.126 - return snprintf( buf, buflen, "%%%s", xir_source_register_names[(op->value.i-MIN_SOURCE_REGISTER)>>2] );
12.127 - } else {
12.128 - return snprintf( buf, buflen, "%%src%d", op->value.i-MIN_SOURCE_REGISTER );
12.129 - }
12.130 + break;
12.131 + case TEMP_OPERAND:
12.132 + tmp = &xbb->temp_regs[op->value.i];
12.133 + if( tmp->home_register != -1 &&
12.134 + (name = xbb->source->get_register_name(tmp->home_register,ty)) != NULL ) {
12.135 + return snprintf( buf, buflen, "%%%s.%c%d", name,
12.136 + XIR_TYPE_CODES[tmp->type], op->value.i );
12.137 } else {
12.138 - return snprintf( buf, buflen, "%%tmp%d", op->value.i-MIN_TEMP_REGISTER );
12.139 + return snprintf( buf, buflen, "%%tmp%c%d",
12.140 + XIR_TYPE_CODES[tmp->type], op->value.i );
12.141 }
12.142 - case TARGET_REGISTER_OPERAND:
12.143 - if( xir_target_register_names ) {
12.144 - return snprintf( buf, buflen, "%%%s", xir_target_register_names[op->value.i-MIN_TARGET_REGISTER] );
12.145 + case DEST_OPERAND:
12.146 + name = xbb->target->get_register_name(op->value.i, ty);
12.147 + if( name != NULL ) {
12.148 + return snprintf( buf, buflen, "%%%s", name );
12.149 } else {
12.150 - return snprintf( buf, buflen, "%%dst%d", op->value.i-MIN_TARGET_REGISTER );
12.151 + return snprintf( buf, buflen, "%%dst%d", op->value.i );
12.152 }
12.153 default:
12.154 return snprintf( buf, buflen, "ILLOP" );
12.155 }
12.156 }
12.157
12.158 -void xir_print_instruction( FILE *out, xir_op_t i )
12.159 +static void xir_print_instruction( FILE *out, xir_basic_block_t xbb, xir_op_t i )
12.160 {
12.161 char operands[64] = "";
12.162
12.163 - if( i->operand[0].type != NO_OPERAND ) {
12.164 - int pos = xir_snprint_operand( operands, sizeof(operands), &i->operand[0] );
12.165 - if( i->operand[1].type != NO_OPERAND ) {
12.166 + if( i->operand[0].form != NO_OPERAND ) {
12.167 + int pos = xir_snprint_operand( operands, sizeof(operands), xbb, &i->operand[0],
12.168 + XOP_OPTYPE(i,0));
12.169 + if( i->operand[1].form != NO_OPERAND ) {
12.170 strncat( operands, ", ", sizeof(operands)-pos );
12.171 pos += 2;
12.172 - xir_snprint_operand( operands+pos, sizeof(operands)-pos, &i->operand[1] );
12.173 + xir_snprint_operand( operands+pos, sizeof(operands)-pos, xbb, &i->operand[1],
12.174 + XOP_OPTYPE(i,1) );
12.175 }
12.176 }
12.177 if( i->cond == CC_TRUE ) {
12.178 @@ -263,7 +302,7 @@
12.179 * Sanity check a block of IR to make sure that
12.180 * operands match up with the expected values etc
12.181 */
12.182 -void xir_verify_block( xir_op_t start, xir_op_t end )
12.183 +void xir_verify_block( xir_basic_block_t xbb, xir_op_t start, xir_op_t end )
12.184 {
12.185 xir_op_t it;
12.186 int flags_written = 0;
12.187 @@ -271,30 +310,43 @@
12.188 assert( it != NULL && "Unexpected end of block" );
12.189 assert( it->cond >= CC_TRUE && it->cond <= CC_SGT && "Invalid condition code" );
12.190 if( XOP_HAS_0_OPERANDS(it) ) {
12.191 - assert( it->operand[0].type == NO_OPERAND && it->operand[1].type == NO_OPERAND );
12.192 + assert( it->operand[0].form == NO_OPERAND && it->operand[1].form == NO_OPERAND );
12.193 } else if( XOP_HAS_1_OPERAND(it) ) {
12.194 - assert( it->operand[0].type != NO_OPERAND && it->operand[1].type == NO_OPERAND );
12.195 + assert( it->operand[0].form != NO_OPERAND && it->operand[1].form == NO_OPERAND );
12.196 } else if( XOP_HAS_2_OPERANDS(it) ) {
12.197 - assert( it->operand[0].type != NO_OPERAND && it->operand[1].type != NO_OPERAND );
12.198 + assert( it->operand[0].form != NO_OPERAND && it->operand[1].form != NO_OPERAND );
12.199 }
12.200
12.201 if( it->opcode == OP_ENTER ) {
12.202 assert( it->prev == NULL && "Enter instruction must have no predecessors" );
12.203 assert( it == start && "Enter instruction must occur at the start of the block" );
12.204 - assert( it->operand[0].type == INT_IMM_OPERAND && "Enter instruction must have an immediate operand" );
12.205 + assert( it->operand[0].form == IMMEDIATE_OPERAND && "Enter instruction must have an immediate operand" );
12.206 } else if( it->opcode == OP_ST || it->opcode == OP_LD ) {
12.207 assert( it->cond != CC_TRUE && "Opcode not permitted with True condition code" );
12.208 }
12.209
12.210 if( XOP_WRITES_OP1(it) ) {
12.211 - assert( (it->operand[0].type == SOURCE_REGISTER_OPERAND ||
12.212 - it->operand[0].type == TARGET_REGISTER_OPERAND) && "Writable operand 1 requires a register" );
12.213 + assert( XOP_IS_REG(it,0) && "Writable operand 1 requires a register" );
12.214 }
12.215 if( XOP_WRITES_OP2(it) ) {
12.216 - assert( (it->operand[1].type == SOURCE_REGISTER_OPERAND ||
12.217 - it->operand[1].type == TARGET_REGISTER_OPERAND) && "Writable operand 2 requires a register" );
12.218 + assert( XOP_IS_REG(it,1) && "Writable operand 2 requires a register" );
12.219 }
12.220 -
12.221 +
12.222 + if( XOP_IS_SRC(it,0) ) {
12.223 + assert( XOP_REG(it,0) <= MAX_SOURCE_REGISTER && "Undefined source register" );
12.224 + } else if( XOP_IS_TMP(it,0) ) {
12.225 + assert( XOP_REG(it,0) < xbb->next_temp_reg && "Undefined temporary register" );
12.226 + } else if( XOP_IS_DST(it,0) ) {
12.227 + assert( XOP_REG(it,0) <= MAX_DEST_REGISTER && "Undefined target register" );
12.228 + }
12.229 + if( XOP_IS_SRC(it,1) ) {
12.230 + assert( XOP_REG(it,1) <= MAX_SOURCE_REGISTER && "Undefined source register" );
12.231 + } else if( XOP_IS_TMP(it,1) ) {
12.232 + assert( XOP_REG(it,1) < xbb->next_temp_reg && "Undefined temporary register" );
12.233 + } else if( XOP_IS_DST(it,1) ) {
12.234 + assert( XOP_REG(it,1) <= MAX_DEST_REGISTER && "Undefined target register" );
12.235 + }
12.236 +
12.237 if( XOP_READS_FLAGS(it) ) {
12.238 assert( flags_written && "Flags used without prior definition in block" );
12.239 }
12.240 @@ -305,7 +357,7 @@
12.241 if( XOP_HAS_EXCEPTION(it) ) {
12.242 assert( it->exc != NULL && "Missing exception block" );
12.243 assert( it->exc->prev == it && "Exception back-link broken" );
12.244 - xir_verify_block( it->exc, NULL ); // Verify exception sub-block
12.245 + xir_verify_block( xbb, it->exc, NULL ); // Verify exception sub-block
12.246 } else {
12.247 assert( it->exc == NULL && "Unexpected exception block" );
12.248 }
12.249 @@ -320,13 +372,13 @@
12.250 }
12.251 }
12.252
12.253 -xir_op_t xir_append_op2( xir_basic_block_t xbb, int op, int arg0type, uint32_t arg0, int arg1type, uint32_t arg1 )
12.254 +xir_op_t xir_append_op2( xir_basic_block_t xbb, int op, int arg0form, uint32_t arg0, int arg1form, uint32_t arg1 )
12.255 {
12.256 xbb->ir_ptr->opcode = op;
12.257 xbb->ir_ptr->cond = CC_TRUE;
12.258 - xbb->ir_ptr->operand[0].type = arg0type;
12.259 + xbb->ir_ptr->operand[0].form = arg0form;
12.260 xbb->ir_ptr->operand[0].value.i = arg0;
12.261 - xbb->ir_ptr->operand[1].type = arg1type;
12.262 + xbb->ir_ptr->operand[1].form = arg1form;
12.263 xbb->ir_ptr->operand[1].value.i = arg1;
12.264 xbb->ir_ptr->exc = NULL;
12.265 xbb->ir_ptr->next = xbb->ir_ptr+1;
12.266 @@ -334,13 +386,13 @@
12.267 return xbb->ir_ptr++;
12.268 }
12.269
12.270 -xir_op_t xir_append_op2cc( xir_basic_block_t xbb, int op, xir_cc_t cc, int arg0type, uint32_t arg0, int arg1type, uint32_t arg1 )
12.271 +xir_op_t xir_append_op2cc( xir_basic_block_t xbb, int op, xir_cc_t cc, int arg0form, uint32_t arg0, int arg1form, uint32_t arg1 )
12.272 {
12.273 xbb->ir_ptr->opcode = op;
12.274 xbb->ir_ptr->cond = cc;
12.275 - xbb->ir_ptr->operand[0].type = arg0type;
12.276 + xbb->ir_ptr->operand[0].form = arg0form;
12.277 xbb->ir_ptr->operand[0].value.i = arg0;
12.278 - xbb->ir_ptr->operand[1].type = arg1type;
12.279 + xbb->ir_ptr->operand[1].form = arg1form;
12.280 xbb->ir_ptr->operand[1].value.i = arg1;
12.281 xbb->ir_ptr->exc = NULL;
12.282 xbb->ir_ptr->next = xbb->ir_ptr+1;
12.283 @@ -348,13 +400,13 @@
12.284 return xbb->ir_ptr++;
12.285 }
12.286
12.287 -xir_op_t xir_append_float_op2( xir_basic_block_t xbb, int op, float imm1, int arg1type, uint32_t arg1 )
12.288 +xir_op_t xir_append_float_op2( xir_basic_block_t xbb, int op, float imm1, int arg1form, uint32_t arg1 )
12.289 {
12.290 xbb->ir_ptr->opcode = op;
12.291 xbb->ir_ptr->cond = CC_TRUE;
12.292 - xbb->ir_ptr->operand[0].type = FLOAT_IMM_OPERAND;
12.293 + xbb->ir_ptr->operand[0].form = IMMEDIATE_OPERAND;
12.294 xbb->ir_ptr->operand[0].value.i = imm1;
12.295 - xbb->ir_ptr->operand[1].type = arg1type;
12.296 + xbb->ir_ptr->operand[1].form = arg1form;
12.297 xbb->ir_ptr->operand[1].value.i = arg1;
12.298 xbb->ir_ptr->exc = NULL;
12.299 xbb->ir_ptr->next = xbb->ir_ptr+1;
12.300 @@ -362,13 +414,13 @@
12.301 return xbb->ir_ptr++;
12.302 }
12.303
12.304 -xir_op_t xir_append_ptr_op2( xir_basic_block_t xbb, int op, void *arg0, int arg1type, uint32_t arg1 )
12.305 +xir_op_t xir_append_ptr_op2( xir_basic_block_t xbb, int op, void *arg0, int arg1form, uint32_t arg1 )
12.306 {
12.307 xbb->ir_ptr->opcode = op;
12.308 xbb->ir_ptr->cond = CC_TRUE;
12.309 - xbb->ir_ptr->operand[0].type = POINTER_OPERAND;
12.310 + xbb->ir_ptr->operand[0].form = IMMEDIATE_OPERAND;
12.311 xbb->ir_ptr->operand[0].value.p = arg0;
12.312 - xbb->ir_ptr->operand[1].type = arg1type;
12.313 + xbb->ir_ptr->operand[1].form = arg1form;
12.314 xbb->ir_ptr->operand[1].value.i = arg1;
12.315 xbb->ir_ptr->exc = NULL;
12.316 xbb->ir_ptr->next = xbb->ir_ptr+1;
12.317 @@ -407,19 +459,7 @@
12.318 }
12.319 }
12.320
12.321 -int xir_get_operand_size( xir_op_t op, int operand )
12.322 -{
12.323 - int mode = XIR_OPCODE_TABLE[op->opcode].mode;
12.324 - if( operand == 0 ) {
12.325 - mode >>= 4;
12.326 - } else {
12.327 - mode >>= 8;
12.328 - }
12.329 - mode &= 0x07;
12.330 - return XIR_OPERAND_SIZE[mode];
12.331 -}
12.332 -
12.333 -void xir_print_block( FILE *out, xir_op_t start, xir_op_t end )
12.334 +void xir_print_block( FILE *out, xir_basic_block_t xbb, xir_op_t start, xir_op_t end )
12.335 {
12.336 xir_op_t it = start;
12.337 xir_op_t exc = NULL;
12.338 @@ -428,20 +468,20 @@
12.339 if( it->exc ) {
12.340 while( exc ) {
12.341 fprintf( out, "%40c ", ' ' );
12.342 - xir_print_instruction( out, exc );
12.343 + xir_print_instruction( out, xbb, exc );
12.344 fprintf( out, "\n" );
12.345 exc = exc->next;
12.346 }
12.347 exc = it->exc;
12.348 }
12.349 - xir_print_instruction( out, it );
12.350 + xir_print_instruction( out, xbb, it );
12.351 if( exc ) {
12.352 if( it->exc ) {
12.353 fprintf( out, "=> " );
12.354 } else {
12.355 fprintf( out, " " );
12.356 }
12.357 - xir_print_instruction( out, exc );
12.358 + xir_print_instruction( out, xbb, exc );
12.359 exc = exc->next;
12.360 }
12.361 fprintf( out, "\n" );
12.362 @@ -451,8 +491,7 @@
12.363 }
12.364 }
12.365
12.366 -void xir_dump_block( xir_op_t start, xir_op_t end )
12.367 +void xir_dump_block( xir_basic_block_t xbb )
12.368 {
12.369 - xir_print_block( stdout, start, end );
12.370 - xir_verify_block( start, end );
12.371 + xir_print_block( stdout, xbb, xbb->ir_begin, xbb->ir_end );
12.372 }
13.1 --- a/src/xlat/xir.h Tue Apr 07 10:55:03 2009 +0000
13.2 +++ b/src/xlat/xir.h Sun Apr 12 07:24:45 2009 +0000
13.3 @@ -48,26 +48,17 @@
13.4 * somehow.
13.5 ****************************************************************************/
13.6
13.7 -/* Registers 0..127 belong to the source machine, all higher numbers are temporaries */
13.8 -#define MIN_SOURCE_REGISTER 0
13.9 #define MAX_SOURCE_REGISTER 1023
13.10 -#define MIN_TEMP_REGISTER 1024
13.11 -#define MAX_TEMP_REGISTER 1535
13.12 +#define MAX_TEMP_REGISTER 511
13.13 +#define MAX_DEST_REGISTER 127
13.14
13.15 -/* Target registers have a separate 'address' space. */
13.16 -#define MIN_TARGET_REGISTER 0
13.17 -#define MAX_TARGET_REGISTER 127
13.18 +/* Preallocated temporaries for convenience */
13.19 +#define REG_TMP0 0
13.20 +#define REG_TMP1 1
13.21 +#define REG_TMP2 2
13.22 +#define REG_TMPQ0 3
13.23 +#define REG_TMPQ1 4
13.24
13.25 -/* Convenience defines */
13.26 -#define REG_TMP0 (MIN_TEMP_REGISTER)
13.27 -#define REG_TMP1 (MIN_TEMP_REGISTER+1)
13.28 -#define REG_TMP2 (MIN_TEMP_REGISTER+2)
13.29 -#define REG_TMP3 (MIN_TEMP_REGISTER+3)
13.30 -#define REG_TMP4 (MIN_TEMP_REGISTER+4)
13.31 -#define REG_TMP5 (MIN_TEMP_REGISTER+5)
13.32 -
13.33 -#define REG_TMPQ0 (MIN_TEMP_REGISTER+128)
13.34 -#define REG_TMPQ1 (MIN_TEMP_REGISTER+129)
13.35
13.36 /**
13.37 * Operands are either integer, float, or double, and are either immediate or
13.38 @@ -77,17 +68,14 @@
13.39 */
13.40 typedef enum {
13.41 NO_OPERAND = 0,
13.42 - SOURCE_REGISTER_OPERAND =1, // Source (or temp) register
13.43 - TARGET_REGISTER_OPERAND =2,
13.44 - INT_IMM_OPERAND = 3,
13.45 - QUAD_IMM_OPERAND = 4,
13.46 - FLOAT_IMM_OPERAND = 5,
13.47 - DOUBLE_IMM_OPERAND = 6,
13.48 - POINTER_OPERAND = 7, // Native target pointer, eg direct memory access
13.49 -} xir_operand_type_t;
13.50 + SOURCE_OPERAND =1, // Source (or temp) register
13.51 + DEST_OPERAND =2,
13.52 + TEMP_OPERAND=3,
13.53 + IMMEDIATE_OPERAND=4
13.54 +} xir_operand_form_t;
13.55
13.56 typedef struct xir_operand {
13.57 - xir_operand_type_t type;
13.58 + xir_operand_form_t form;
13.59 union {
13.60 uint32_t i;
13.61 uint64_t q;
13.62 @@ -97,6 +85,16 @@
13.63 } value;
13.64 } *xir_operand_t;
13.65
13.66 +typedef enum {
13.67 + XTY_LONG = 0, /* 32-bit integer */
13.68 + XTY_QUAD = 1, /* 64-bit integer */
13.69 + XTY_FLOAT = 2, /* 32-bit float */
13.70 + XTY_DOUBLE = 3,/* 64-bit float */
13.71 + XTY_VEC4F = 4,/* 4x 32-bit floats (16 bytes) */
13.72 + XTY_MAT16F = 5,/* 4x4x 32-bit floats (64 bytes) */
13.73 + XTY_PTR = 6, /* Native pointer (of appropriate size) */
13.74 +} xir_type_t;
13.75 +
13.76 /* Condition codes */
13.77 typedef enum {
13.78 CC_TRUE = -1, /* Always */
13.79 @@ -193,7 +191,6 @@
13.80 OP_TST,
13.81 OP_XOR,
13.82 OP_XORS,
13.83 - OP_XLAT,
13.84
13.85 /* FPU */
13.86 OP_ABSD,
13.87 @@ -250,10 +247,13 @@
13.88 OP_RAISEMNE, // imm mask in, reg in - branch to exception if (reg & mask) != 0
13.89
13.90
13.91 - // Native calls (not source machine calls)
13.92 + // Native operations
13.93 OP_CALLLUT, // Call indirect through base pointer (reg) + displacement
13.94 OP_CALL1, // Call function with single argument and no return value
13.95 OP_CALLR, // Call function with no arguments and a single return value
13.96 + OP_LOADPTRL,
13.97 + OP_LOADPTRQ,
13.98 + OP_XLAT,
13.99
13.100 /********************** SH4-specific macro operations *************************/
13.101 /* TODO: These need to be broken down into smaller operations eventually,
13.102 @@ -380,6 +380,11 @@
13.103 typedef struct xlat_source_machine *xlat_source_machine_t;
13.104 typedef struct xlat_target_machine *xlat_target_machine_t;
13.105
13.106 +typedef struct xir_temp_register {
13.107 + xir_type_t type;
13.108 + uint32_t home_register; /* corresponding source register, or -1 for none */
13.109 +} *xir_temp_register_t;
13.110 +
13.111 /**
13.112 * Source data structure. This mainly exists to manage memory for XIR operations
13.113 */
13.114 @@ -391,7 +396,10 @@
13.115 xir_op_t ir_alloc_end; /* End of allocation */
13.116 uint32_t pc_begin; /* first instruction */
13.117 uint32_t pc_end; /* next instruction after end */
13.118 + struct xir_temp_register temp_regs[MAX_TEMP_REGISTER+1]; /* temporary register table */
13.119 + uint32_t next_temp_reg;
13.120 xlat_source_machine_t source;
13.121 + xlat_target_machine_t target;
13.122 struct mem_region_fn **address_space; /* source machine memory access table */
13.123 } *xir_basic_block_t;
13.124
13.125 @@ -462,17 +470,8 @@
13.126 void *ptr;
13.127 };
13.128
13.129 -extern const struct xir_opcode_entry XIR_OPCODE_TABLE[];
13.130 -#define XOP_IS_SRCREG(op,n) (op->operand[n].type == SOURCE_REGISTER_OPERAND)
13.131 -#define XOP_IS_TGTREG(op,n) (op->operand[n].type == TARGET_REGISTER_OPERAND)
13.132 -#define XOP_IS_INTIMM(op,n) (op->operand[n].type == INT_IMM_OPERAND)
13.133 -#define XOP_IS_FLOATIMM(op,n) (op->operand[n].type == FLOAT_IMM_OPERAND)
13.134 -#define XOP_IS_DOUBLEIMM(op,n) (op->operand[n].type == DOUBLE_IMM_OPERAND)
13.135 -#define XOP_IS_QUADIMM(op,n) (op->operand[n].type == QUAD_IMM_OPERAND)
13.136 -#define XOP_IS_PTRIMM(op,n) (op->operand[n].type == POINTER_OPERAND)
13.137 -#define XOP_IS_IMM(op,n) (op->operand[n].type > TARGET_REGISTER_OPERAND)
13.138 -#define XOP_IS_REG(op,n) (XOP_IS_SRCREG(op,n)||XOP_IS_TGTREG(op,n)
13.139 -#define XOP_IS_FORM(op,t1,t2) (op->operand[0].type == t1 && op->operand[1].type == t2)
13.140 +extern const struct xir_opcode_entry XIR_OPCODE_TABLE[];
13.141 +extern const int XIR_OPERAND_SIZE[];
13.142
13.143 #define XOP_REG(op,n) (op->operand[n].value.i)
13.144 #define XOP_REG1(op) XOP_REG(op,0)
13.145 @@ -501,33 +500,69 @@
13.146 #define XOP_READS_REG2(op) (XOP_READS_OP2(op) && XOP_IS_REG(op,1))
13.147 #define XOP_WRITES_REG2(op) (XOP_WRITES_OP2(op) && XOP_IS_REG(op,1))
13.148
13.149 -#define XOP_TYPE1(op) (op->operand[0].type)
13.150 -#define XOP_TYPE2(op) (op->operand[1].type)
13.151 +#define XOP_TYPE1(op) ((XIR_OPCODE_TABLE[op->opcode].mode >> 4) & 0x0F)
13.152 +#define XOP_TYPE2(op) ((XIR_OPCODE_TABLE[op->opcode].mode >> 8) & 0x0F)
13.153 +#define XOP_FORM1(op) (op->operand[0].form)
13.154 +#define XOP_FORM2(op) (op->operand[1].form)
13.155 #define XOP_OPERAND(op,i) (&op->operand[i])
13.156 +#define XOP_OPTYPE(op,n) (n == 0 ? XOP_TYPE1(op) : XOP_TYPE2(op))
13.157 +#define XOP_OPSIZE(op,n) (XIR_OPERAND_SIZE[XOP_OPTYPE(op,n)])
13.158
13.159 -/******************************* OP Constructors ******************************/
13.160 +#define XOP_IS_SRC(op,n) (op->operand[n].form == SOURCE_OPERAND)
13.161 +#define XOP_IS_DST(op,n) (op->operand[n].form == DEST_OPERAND)
13.162 +#define XOP_IS_TMP(op,n) (op->operand[n].form == TEMP_OPERAND)
13.163 +#define XOP_IS_IMM(op,n) (op->operand[n].form == IMMEDIATE_OPERAND)
13.164 +#define XOP_IS_IMMF(op,n) (XOP_IS_IMM(op,n) && XOP_OPTYPE(op,n) == XTY_FLOAT)
13.165 +#define XOP_IS_IMMD(op,n) (XOP_IS_IMM(op,n) && XOP_OPTYPE(op,n) == XTY_DOUBLE)
13.166 +#define XOP_IS_IMML(op,n) (XOP_IS_IMM(op,n) && XOP_OPTYPE(op,n) == XTY_LONG)
13.167 +#define XOP_IS_IMMQ(op,n) (XOP_IS_IMM(op,n) && XOP_OPTYPE(op,n) == XTY_QUAD)
13.168 +#define XOP_IS_IMMP(op,n) (XOP_IS_IMM(op,n) && XOP_OPTYPE(op,n) == XTY_PTR)
13.169 +#define XOP_IS_REG(op,n) (op->operand[n].form >= SOURCE_OPERAND && op->operand[n].form <= TEMP_OPERAND)
13.170 +#define XOP_IS_FORM(op,t1,t2) (op->operand[0].form == t1 && op->operand[1].form == t2)
13.171
13.172 -xir_op_t xir_append_op2( xir_basic_block_t xbb, int op, int arg0type, uint32_t arg0, int arg1type, uint32_t arg1 );
13.173 -xir_op_t xir_append_op2cc( xir_basic_block_t xbb, int op, int cc, int arg0type, uint32_t arg0, int arg1type, uint32_t arg1 );
13.174 -xir_op_t xir_append_float_op2( xir_basic_block_t xbb, int op, float imm1, int arg1type, uint32_t arg1 );
13.175 -xir_op_t xir_append_ptr_op2( xir_basic_block_t xbb, int op, void *arg0, int arg1type, uint32_t arg1 );
13.176 +/******************************* IR Construction ******************************/
13.177
13.178 +/**
13.179 + * Clear out a basic block structure, ready for reuse
13.180 + */
13.181 +void xir_clear_basic_block( xir_basic_block_t xbb );
13.182
13.183 -#define XOP1( op, arg0 ) xir_append_op2(xbb, op, SOURCE_REGISTER_OPERAND, arg0, NO_OPERAND, 0)
13.184 -#define XOP1CC( op, cc, arg0 ) xir_append_op2cc(xbb, op, cc, SOURCE_REGISTER_OPERAND, arg0, NO_OPERAND, 0)
13.185 -#define XOP1I( op, arg0 ) xir_append_op2(xbb, op, INT_IMM_OPERAND, arg0, NO_OPERAND, 0)
13.186 -#define XOP2I( op, arg0, arg1 ) xir_append_op2(xbb, op, INT_IMM_OPERAND, arg0, SOURCE_REGISTER_OPERAND, arg1)
13.187 -#define XOP2II( op, arg0, arg1 ) xir_append_op2(xbb, op, INT_IMM_OPERAND, arg0, INT_IMM_OPERAND, arg1)
13.188 -#define XOP2IICC( op, cc, arg0, arg1 ) xir_append_op2cc(xbb, op, cc, INT_IMM_OPERAND, arg0, INT_IMM_OPERAND, arg1)
13.189 -#define XOP2( op, arg0, arg1 ) xir_append_op2(xbb, op, SOURCE_REGISTER_OPERAND, arg0, SOURCE_REGISTER_OPERAND, arg1)
13.190 -#define XOP2CC( op, cc, arg0, arg1 ) xir_append_op2cc(xbb, op, cc, SOURCE_REGISTER_OPERAND, arg0, SOURCE_REGISTER_OPERAND, arg1)
13.191 -#define XOP2F( op, arg0, arg1 ) xir_append_float_op2(xbb, op, arg0, SOURCE_REGISTER_OPERAND, arg1)
13.192 -#define XOP2P( op, arg0, arg1 ) xir_append_ptr_op2(xbb, op, arg0, SOURCE_REGISTER_OPERAND, arg1)
13.193 +/**
13.194 + * Allocate a temporary register of the given type, with given home position
13.195 + * (-1 for a pure temporary)
13.196 + */
13.197 +uint32_t xir_alloc_temp_reg( xir_basic_block_t xbb, xir_type_t type, int home );
13.198 +
13.199 +xir_op_t xir_append_op2( xir_basic_block_t xbb, int op, int arg0form, uint32_t arg0, int arg1form, uint32_t arg1 );
13.200 +xir_op_t xir_append_op2cc( xir_basic_block_t xbb, int op, int cc, int arg0form, uint32_t arg0, int arg1form, uint32_t arg1 );
13.201 +xir_op_t xir_append_float_op2( xir_basic_block_t xbb, int op, float imm1, int arg1form, uint32_t arg1 );
13.202 +xir_op_t xir_append_ptr_op2( xir_basic_block_t xbb, int op, void *arg0, int arg1form, uint32_t arg1 );
13.203 +
13.204 +
13.205 +#define XOP1I( op, arg0 ) xir_append_op2(xbb, op, IMMEDIATE_OPERAND, arg0, NO_OPERAND, 0)
13.206 +#define XOP1S( op, arg0 ) xir_append_op2(xbb, op, SOURCE_OPERAND, arg0, NO_OPERAND, 0)
13.207 +#define XOP1SCC( op, cc, arg0 ) xir_append_op2cc(xbb, op, cc, SOURCE_OPERAND, arg0, NO_OPERAND, 0)
13.208 +#define XOP1T( op, arg0 ) xir_append_op2(xbb, op, TEMP_OPERAND, arg0, NO_OPERAND, 0)
13.209 +#define XOP1TCC( op, cc, arg0 ) xir_append_op2cc(xbb, op, cc, TEMP_OPERAND, arg0, NO_OPERAND, 0)
13.210 +#define XOP2IS( op, arg0, arg1 ) xir_append_op2(xbb, op, IMMEDIATE_OPERAND, arg0, SOURCE_OPERAND, arg1)
13.211 +#define XOP2IT( op, arg0, arg1 ) xir_append_op2(xbb, op, IMMEDIATE_OPERAND, arg0, TEMP_OPERAND, arg1)
13.212 +#define XOP2II( op, arg0, arg1 ) xir_append_op2(xbb, op, IMMEDIATE_OPERAND, arg0, IMMEDIATE_OPERAND, arg1)
13.213 +#define XOP2IICC( op, cc, arg0, arg1 ) xir_append_op2cc(xbb, op, cc, IMMEDIATE_OPERAND, arg0, IMMEDIATE_OPERAND, arg1)
13.214 +#define XOP2SS( op, arg0, arg1 ) xir_append_op2(xbb, op, SOURCE_OPERAND, arg0, SOURCE_OPERAND, arg1)
13.215 +#define XOP2ST( op, arg0, arg1 ) xir_append_op2(xbb, op, SOURCE_OPERAND, arg0, TEMP_OPERAND, arg1)
13.216 +#define XOP2TS( op, arg0, arg1 ) xir_append_op2(xbb, op, TEMP_OPERAND, arg0, SOURCE_OPERAND, arg1)
13.217 +#define XOP2TT( op, arg0, arg1 ) xir_append_op2(xbb, op, TEMP_OPERAND, arg0, TEMP_OPERAND, arg1)
13.218 +#define XOP2CC( op, cc, arg0, arg1 ) xir_append_op2cc(xbb, op, cc, SOURCE_OPERAND, arg0, SOURCE_OPERAND, arg1)
13.219 +#define XOP2FS( op, arg0, arg1 ) xir_append_float_op2(xbb, op, arg0, SOURCE_OPERAND, arg1)
13.220 +#define XOP2PS( op, arg0, arg1 ) xir_append_ptr_op2(xbb, op, arg0, SOURCE_OPERAND, arg1)
13.221 +#define XOP2PT( op, arg0, arg1 ) xir_append_ptr_op2(xbb, op, arg0, TEMP_OPERAND, arg1)
13.222 #define XOP0( op ) xir_append_op2(xbb, op, NO_OPERAND, 0, NO_OPERAND, 0)
13.223 #define XOPCALL0( arg0 ) xir_append_ptr_op2(xbb, OP_CALL0, arg0, NO_OPERAND, 0)
13.224 -#define XOPCALL1( arg0, arg1 ) xir_append_ptr_op2(xbb, OP_CALL1, arg0, SOURCE_REGISTER_OPERAND, arg1)
13.225 -#define XOPCALL1I( arg0, arg1 ) xir_append_ptr_op2(xbb, OP_CALL1, arg0, INT_IMM_OPERAND, arg1)
13.226 -#define XOPCALLR( arg0, arg1 ) xir_append_ptr_op2(xbb, OP_CALLR, arg0, SOURCE_REGISTER_OPERAND, arg1)
13.227 +#define XOPCALL1I( arg0, arg1 ) xir_append_ptr_op2(xbb, OP_CALL1, arg0, IMMEDIATE_OPERAND, arg1)
13.228 +#define XOPCALL1S( arg0, arg1 ) xir_append_ptr_op2(xbb, OP_CALL1, arg0, SOURCE_OPERAND, arg1)
13.229 +#define XOPCALL1T( arg0, arg1 ) xir_append_ptr_op2(xbb, OP_CALL1, arg0, TEMP_OPERAND, arg1)
13.230 +#define XOPCALLRS( arg0, arg1 ) xir_append_ptr_op2(xbb, OP_CALLR, arg0, SOURCE_OPERAND, arg1)
13.231 +#define XOPCALLRT( arg0, arg1 ) xir_append_ptr_op2(xbb, OP_CALLR, arg0, TEMP_OPERAND, arg1)
13.232
13.233 /**************************** IR Modification ******************************/
13.234
13.235 @@ -584,13 +619,7 @@
13.236 * Verify the integrity of an IR block - abort with assertion failure on any
13.237 * errors.
13.238 */
13.239 -void xir_verify_block( xir_op_t start, xir_op_t end );
13.240 -
13.241 -/**
13.242 - * Set the register name mappings for source and target registers - only really
13.243 - * used for debug output
13.244 - */
13.245 -void xir_set_register_names( const char **source_regs, const char **target_regs );
13.246 +void xir_verify_block( xir_basic_block_t xbb, xir_op_t begin, xir_op_t end );
13.247
13.248 /**
13.249 * Set the symbol table mappings for target points - also only really for
13.250 @@ -601,7 +630,7 @@
13.251 /**
13.252 * Dump the specified block of IR to stdout
13.253 */
13.254 -void xir_dump_block( xir_op_t start, xir_op_t end );
13.255 +void xir_dump_block( xir_basic_block_t xbb );
13.256
13.257
13.258 #endif /* !lxdream_xir_H */
14.1 --- a/src/xlat/xirsup.c Tue Apr 07 10:55:03 2009 +0000
14.2 +++ b/src/xlat/xirsup.c Sun Apr 12 07:24:45 2009 +0000
14.3 @@ -127,8 +127,8 @@
14.4
14.5 if( arg == 0x1234 ) { /* Identity - NOP */
14.6 it->opcode = OP_NOP;
14.7 - it->operand[0].type = NO_OPERAND;
14.8 - it->operand[1].type = NO_OPERAND;
14.9 + it->operand[0].form = NO_OPERAND;
14.10 + it->operand[1].form = NO_OPERAND;
14.11 return it;
14.12 }
14.13
14.14 @@ -149,33 +149,33 @@
14.15 arg >>= 4;
14.16 }
14.17
14.18 - int shiftertype = it->operand[1].type, shifterval = it->operand[1].value.i;
14.19 + int shifterform = it->operand[1].form, shifterval = it->operand[1].value.i;
14.20 xir_op_t seq = xbb->ir_ptr;
14.21
14.22 for( i=first; i<=last; i++ ) {
14.23 if( mask_for_shift[i+3] != 0 ) {
14.24 uint32_t maxmask = 0xFFFFFFFF;
14.25 if( first != i ) {
14.26 - shiftertype = SOURCE_REGISTER_OPERAND;
14.27 + shifterform = TEMP_OPERAND;
14.28 if( last == i ) {
14.29 shifterval = tmp1;
14.30 } else {
14.31 shifterval = tmp2;
14.32 - xir_append_op2( xbb, OP_MOV, SOURCE_REGISTER_OPERAND, tmp1, shiftertype, shifterval );
14.33 + xir_append_op2( xbb, OP_MOV, TEMP_OPERAND, tmp1, shifterform, shifterval );
14.34 }
14.35 }
14.36 if( i < 0 ) {
14.37 - xir_append_op2( xbb, OP_SLR, INT_IMM_OPERAND, (-i)<<3, shiftertype, shifterval );
14.38 + xir_append_op2( xbb, OP_SLR, IMMEDIATE_OPERAND, (-i)<<3, shifterform, shifterval );
14.39 maxmask >>= ((-i)<<3);
14.40 } else if( i > 0 ) {
14.41 - xir_append_op2( xbb, OP_SLL, INT_IMM_OPERAND, i<<3, shiftertype, shifterval );
14.42 + xir_append_op2( xbb, OP_SLL, IMMEDIATE_OPERAND, i<<3, shifterform, shifterval );
14.43 maxmask <<= (i<<3);
14.44 }
14.45 if( mask_for_shift[i+3] != maxmask ) {
14.46 - xir_append_op2( xbb, OP_AND, INT_IMM_OPERAND, mask_for_shift[i+3], shiftertype, shifterval );
14.47 + xir_append_op2( xbb, OP_AND, IMMEDIATE_OPERAND, mask_for_shift[i+3], shifterform, shifterval );
14.48 }
14.49 if( first != i ) {
14.50 - xir_append_op2( xbb, OP_OR, shiftertype, shifterval, it->operand[1].type, it->operand[1].value.i );
14.51 + xir_append_op2( xbb, OP_OR, shifterform, shifterval, it->operand[1].form, it->operand[1].value.i );
14.52 }
14.53 }
14.54 }
14.55 @@ -183,14 +183,14 @@
14.56 /* Replace original shuffle with either a temp move or a nop */
14.57 if( first != last ) {
14.58 it->opcode = OP_MOV;
14.59 - it->operand[0].type = it->operand[1].type;
14.60 + it->operand[0].form = it->operand[1].form;
14.61 it->operand[0].value.i = it->operand[1].value.i;
14.62 - it->operand[1].type = SOURCE_REGISTER_OPERAND;
14.63 + it->operand[1].form = TEMP_OPERAND;
14.64 it->operand[1].value.i = tmp1;
14.65 } else {
14.66 it->opcode = OP_NOP;
14.67 - it->operand[0].type = NO_OPERAND;
14.68 - it->operand[1].type = NO_OPERAND;
14.69 + it->operand[0].form = NO_OPERAND;
14.70 + it->operand[1].form = NO_OPERAND;
14.71 }
14.72
14.73 /* Finally insert the new sequence after the original op */
15.1 --- a/src/xlat/xlat.h Tue Apr 07 10:55:03 2009 +0000
15.2 +++ b/src/xlat/xlat.h Sun Apr 12 07:24:45 2009 +0000
15.3 @@ -30,7 +30,6 @@
15.4 struct xlat_source_machine {
15.5 const char *name;
15.6 void *state_data; /* Pointer to source machine state structure */
15.7 - const char **reg_names; /* Register names, indexed by offset/4 */
15.8 uint32_t pc_offset; /* Offset of source PC, relative to state_data */
15.9 uint32_t delayed_pc_offset; /* Offset of source delayed PC offset, relative to state_data */
15.10 uint32_t t_offset; /* Offset of source T reg, relative to state_data */
15.11 @@ -39,6 +38,12 @@
15.12 uint32_t s_offset;
15.13
15.14 /**
15.15 + * Return the name of the register with the given type,
15.16 + * or NULL if no such register exists
15.17 + */
15.18 + const char * (*get_register_name)( uint32_t reg, xir_type_t type );
15.19 +
15.20 + /**
15.21 * Decode a basic block of instructions from start, stopping after a
15.22 * control transfer or before the given end instruction.
15.23 * @param sd source data. This method should set the address_space field.
15.24 @@ -51,17 +56,21 @@
15.25 /* Target machine description (no these are not meant to be symmetrical) */
15.26 struct xlat_target_machine {
15.27 const char *name;
15.28 - /* Register information */
15.29 - const char **reg_names;
15.30
15.31 /* Required functions */
15.32
15.33 /**
15.34 + * Return the name of the register with the given type,
15.35 + * or NULL if no such register exists
15.36 + */
15.37 + const char * (*get_register_name)( uint32_t reg, xir_type_t type );
15.38 +
15.39 + /**
15.40 * Test if the given operands are legal for the opcode. Note that it is assumed that
15.41 * target register operands are always legal. This is used by the register allocator
15.42 * to determine when it can fuse load/stores with another operation.
15.43 */
15.44 - gboolean (*is_legal)( xir_opcode_t op, xir_operand_type_t arg0, xir_operand_type_t arg1 );
15.45 + gboolean (*is_legal)( xir_opcode_t op, xir_operand_form_t arg0, xir_operand_form_t arg1 );
15.46
15.47 /**
15.48 * Lower IR closer to the machine, handling machine-specific issues that can't
.