October 5th, 2007 by nkeynes
More speed, less bugs
Posted in Development

Fixed some minor bugs and improved the speed a little more – overall core speed is now roughly double that of M3 – not bad for a couple of weeks work. For certain use cases the system now runs at nearly 100% speed (under the unlikely assumption of 100,000,000 instructions/second[0]). Unfortunately I think I’ve just about tapped out the low-hanging fruit – further performance gains are likely to be obtained inch by painful inch.

My plan for the moment is to get a decent user UI up and running, fix some of the nastier audio + video bugs, and shoot for an interim release later this month. It’d be particularly nice if the bootup sound was approximately correct (now that things are fast enough that you can actually tell that its b0rked).

Changes

  • Fix more translation cache bugs
  • Fix controller triggers (sense was inverted)
  • Remove MMU AT checks from sh4mem.c (needs to be in core anyway for exception correctness). Also #define out the trace checks by default – slight performance gain.
  • Add explicit branches in sh4mem.c for main memory access – it’s actually faster this way, if less flexible.
  • Fix save state loader bug (SH4).
  • Add command-line opt to change the SH4 speed scaling
  • Remove instruction counter in ESI (change to constant loads where needed)
  • Suppress redundant flag loads

[0] Bloody complicated superscalar pipeline design… real code could run at anywhere between 10 MIPS and 400 MIPS for a 200Mhz clock. Getting even approximate cycle accuracy would be nice, just as soon as I have an efficient way to implement it.

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