I’ve been taking some time to tidy up a few lingering issues with the emulation, mostly small fixes but it does tend to take some time to find the bugs. As part of this, I’ve also started putting together a test harness for the ARM processor, but it’s not quite working on the actual hardware yet (In other news, the G2 bus hates me with a rather astounding passion).

I’ll probably keep going through these for another couple of weeks at this stage – it would be nice to get through the remaining known black-screen/hang type of bugs before I get back to mangling the renderer.
Changes

• SH4: Fix 64-bit bugs that broke the OS X 64-bit builds
• SH4: Fix ASID usage in ITLB lookups
• SH4: Fix core-exit on a translation-cache flush when it occurs in a branch delay slot
• SH4: Add the 1Cxx..1Fxx mapping for the P4 region when accessed through the TLB
• SH4: Add version register 0xFF000030 (read-only).
• SH4: Add undocumented performance counters (just stubbed for now) . Removes the 0xFF100008 warnings, but breaks save-state compatibility.
• ARM: Fix STM {R15} offset (should be +12, was +8)
• ARM: Add missing half-word load/store instructions
• ARM: Add test harness work-in-progress
• Other: Cleanup all the -Wall compile-time warnings

This entry was posted on Wednesday, August 20th, 2008 at 9:40 am and is filed under Development. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.