Memory Map

SH4 Address Space
The SH4 provides a 32-bit address space which is broken down as follows:

The external memory space of the SH4 is 29-bits wide, which is accessible through all defined regions except P4 (which is used for the MMU and control of other on-board peripherals).

In general, all IO access should be performed through the P2 region (to avoid caching), while user programs are generally assumed to execute from the P0/P1 and U0 regions (for privileged and user-mode code respectively).

SH4 External Address Space
Note: This needs to be updated to include repeating areas (the address decoding is generally fairly loose).

Areas marked "burst" should normally only be accessed by DMA or store queue.