lxdream.org :: Memory Map
lxdream 0.9.1
released Jun 29
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    SH4 Address Space

    The SH4 provides a 32-bit address space which is broken down as follows:

    Start End Privileged Mode User mode Description
    0x00000000 0x7FFFFFFF P0 U0 Cached, address translation ok (if enabled)
    0x80000000 0x9FFFFFFF P1 Forbidden Cacheable, no address translation.
    0xA0000000 0xBFFFFFFF P2 Forbidden Not cached, no address translation.
    0xC0000000 0xDFFFFFFF P3 Forbidden Cacheable, address translation ok (if enabled)
    0xE0000000 0xFFFFFFFF P4 Forbidden except for store queue, depending on MMU settings Store queue and internal SH4 peripheral access

    The external memory space of the SH4 is 29-bits wide, which is accessible through all defined regions except P4 (which is used for the MMU and control of other on-board peripherals).

    In general, all IO access should be performed through the P2 region (to avoid caching), while user programs are generally assumed to execute from the P0/P1 and U0 regions (for privileged and user-mode code respectively).

    SH4 External Address Space

    Note: This needs to be updated to include repeating areas (the address decoding is generally fairly loose).

    Start End Size Description
    0x00000000 0x001FFFFF 2M BIOS Boot ROM. Reset entry point is at 0x00000000.
    0x00200000 0x0021FFFF 128K Flash ROM
    0x005F6000 0x005F7FFF N/A ASIC registers (including GD-Rom and Maple control registers)
    0x005F8000 0x005F8FFF N/A PVR2 registers
    0x005F9000 0x005F9FFF 4K PVR2 Palette
    0x00700000 0x00710FFF N/A AICA control registers
    0x00800000 0x009FFFFF 2M Audio RAM access (via G2 FIFO)
    0x04000000 0x047FFFFF 8M 64-bit VRAM access
    0x05000000 0x057FFFFF 8M 32-bit VRAM access
    0x0C000000 0x0CFFFFFF 16M Main RAM
    0x10000000 0x107FFFFF N/A Tile Accelerator FIFO (burst)
    0x10800000 0x10FFFFFF N/A YUV Decoder FIFO (burst)
    0x11000000 0x11FFFFFF N/A VRAM access 1 FIFO (burst)
    0x12000000 0x127FFFFF N/A Tile Accelerator FIFO (burst) repeat
    0x12800000 0x12FFFFFF N/A YUV Decoder FIFO (burst) repeat
    0x13000000 0x13FFFFFF N/A VRAM access 2 FIFO (burst)
    0x1C000000 0x1FFFFFFF N/A Access to CPU control registers in P4 region or when mapped via TLB. Reserved area in all other regions.

    Areas marked "burst" should normally only be accessed by DMA or store queue.