nkeynes@20 | 1 | /**
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nkeynes@428 | 2 | * $Id: scif.c,v 1.9 2007-10-07 06:27:12 nkeynes Exp $
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nkeynes@20 | 3 | * SCIF (Serial Communication Interface with FIFO) implementation - part of the
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nkeynes@20 | 4 | * SH4 standard on-chip peripheral set. The SCIF is hooked up to the DCs
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nkeynes@20 | 5 | * external serial port
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nkeynes@20 | 6 | *
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nkeynes@20 | 7 | * Copyright (c) 2005 Nathan Keynes.
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nkeynes@20 | 8 | *
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nkeynes@20 | 9 | * This program is free software; you can redistribute it and/or modify
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nkeynes@20 | 10 | * it under the terms of the GNU General Public License as published by
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nkeynes@20 | 11 | * the Free Software Foundation; either version 2 of the License, or
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nkeynes@20 | 12 | * (at your option) any later version.
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nkeynes@20 | 13 | *
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nkeynes@20 | 14 | * This program is distributed in the hope that it will be useful,
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nkeynes@20 | 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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nkeynes@20 | 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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nkeynes@20 | 17 | * GNU General Public License for more details.
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nkeynes@20 | 18 | */
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nkeynes@20 | 19 |
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nkeynes@20 | 20 | #include <glib.h>
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nkeynes@20 | 21 | #include "dream.h"
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nkeynes@20 | 22 | #include "mem.h"
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nkeynes@54 | 23 | #include "sh4/sh4core.h"
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nkeynes@54 | 24 | #include "sh4/sh4mmio.h"
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nkeynes@54 | 25 | #include "sh4/intc.h"
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nkeynes@54 | 26 | #include "sh4/dmac.h"
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nkeynes@20 | 27 | #include "clock.h"
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nkeynes@20 | 28 | #include "serial.h"
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nkeynes@20 | 29 |
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nkeynes@20 | 30 | void SCIF_set_break(void);
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nkeynes@20 | 31 |
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nkeynes@20 | 32 | /************************* External serial interface ************************/
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nkeynes@20 | 33 |
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nkeynes@20 | 34 | /**
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nkeynes@20 | 35 | * Note: serial_* operations are called from outside the SH4, and as such are
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nkeynes@20 | 36 | * named relative to the external serial device. SCIF_* operations are only
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nkeynes@20 | 37 | * called internally to the SH4 and so are named relative to the CPU.
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nkeynes@20 | 38 | */
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nkeynes@20 | 39 |
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nkeynes@20 | 40 | /**
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nkeynes@20 | 41 | * Storage space for inbound/outbound data blocks. It's a little more
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nkeynes@20 | 42 | * convenient for serial consumers to be able to deal with block-sized pieces
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nkeynes@20 | 43 | * rather than a byte at a time, even if it makes all this look rather
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nkeynes@20 | 44 | * complicated.
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nkeynes@20 | 45 | *
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nkeynes@20 | 46 | * Currently there's no limit on the number of blocks that can be queued up.
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nkeynes@20 | 47 | */
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nkeynes@20 | 48 | typedef struct serial_data_block {
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nkeynes@20 | 49 | uint32_t length;
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nkeynes@20 | 50 | uint32_t offset;
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nkeynes@20 | 51 | struct serial_data_block *next;
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nkeynes@20 | 52 | char data[];
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nkeynes@20 | 53 | } *serial_data_block_t;
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nkeynes@20 | 54 |
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nkeynes@20 | 55 | serial_data_block_t serial_recvq_head = NULL, serial_recvq_tail = NULL;
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nkeynes@20 | 56 | serial_device_t serial_device = NULL;
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nkeynes@20 | 57 |
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nkeynes@20 | 58 | void serial_attach_device( serial_device_t dev )
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nkeynes@20 | 59 | {
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nkeynes@20 | 60 | if( serial_device != NULL )
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nkeynes@20 | 61 | serial_detach_device();
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nkeynes@20 | 62 | serial_device = dev;
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nkeynes@20 | 63 | }
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nkeynes@20 | 64 |
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nkeynes@20 | 65 |
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nkeynes@20 | 66 | void serial_detach_device( void )
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nkeynes@20 | 67 | {
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nkeynes@20 | 68 | serial_device = NULL;
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nkeynes@20 | 69 | }
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nkeynes@20 | 70 |
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nkeynes@20 | 71 | /**
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nkeynes@20 | 72 | * Add a block of data to the serial receive queue. The data will be received
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nkeynes@20 | 73 | * by the CPU at the appropriate baud rate.
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nkeynes@20 | 74 | */
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nkeynes@20 | 75 | void serial_transmit_data( char *data, int length ) {
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nkeynes@20 | 76 | if( length == 0 )
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nkeynes@20 | 77 | return;
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nkeynes@20 | 78 | serial_data_block_t block =
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nkeynes@20 | 79 | g_malloc( sizeof( struct serial_data_block ) + length );
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nkeynes@20 | 80 | block->length = length;
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nkeynes@20 | 81 | block->offset = 0;
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nkeynes@20 | 82 | block->next = NULL;
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nkeynes@20 | 83 | memcpy( block->data, data, length );
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nkeynes@20 | 84 |
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nkeynes@20 | 85 | if( serial_recvq_head == NULL ) {
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nkeynes@20 | 86 | serial_recvq_head = serial_recvq_tail = block;
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nkeynes@20 | 87 | } else {
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nkeynes@20 | 88 | serial_recvq_tail->next = block;
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nkeynes@20 | 89 | serial_recvq_tail = block;
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nkeynes@20 | 90 | }
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nkeynes@20 | 91 | }
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nkeynes@20 | 92 |
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nkeynes@20 | 93 | /**
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nkeynes@20 | 94 | * Dequeue a byte from the serial input queue
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nkeynes@20 | 95 | */
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nkeynes@20 | 96 | static int serial_transmit_dequeue( ) {
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nkeynes@20 | 97 | if( serial_recvq_head != NULL ) {
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nkeynes@20 | 98 | uint8_t val = serial_recvq_head->data[serial_recvq_head->offset++];
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nkeynes@20 | 99 | if( serial_recvq_head->offset >= serial_recvq_head->length ) {
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nkeynes@20 | 100 | serial_data_block_t next = serial_recvq_head->next;
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nkeynes@20 | 101 | g_free( serial_recvq_head );
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nkeynes@20 | 102 | serial_recvq_head = next;
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nkeynes@20 | 103 | if( next == NULL )
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nkeynes@20 | 104 | serial_recvq_tail = NULL;
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nkeynes@20 | 105 | }
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nkeynes@20 | 106 | return (int)(unsigned int)val;
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nkeynes@20 | 107 | }
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nkeynes@20 | 108 | return -1;
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nkeynes@20 | 109 |
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nkeynes@20 | 110 | }
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nkeynes@20 | 111 |
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nkeynes@20 | 112 | void serial_transmit_break() {
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nkeynes@20 | 113 | SCIF_set_break();
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nkeynes@20 | 114 | }
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nkeynes@20 | 115 |
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nkeynes@20 | 116 | /********************************* SCIF *************************************/
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nkeynes@20 | 117 |
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nkeynes@20 | 118 | #define FIFO_LENGTH 16
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nkeynes@20 | 119 | #define FIFO_ARR_LENGTH (FIFO_LENGTH+1)
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nkeynes@20 | 120 |
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nkeynes@20 | 121 | /* Serial control register flags */
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nkeynes@20 | 122 | #define SCSCR2_TIE 0x80
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nkeynes@20 | 123 | #define SCSCR2_RIE 0x40
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nkeynes@20 | 124 | #define SCSCR2_TE 0x20
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nkeynes@20 | 125 | #define SCSCR2_RE 0x10
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nkeynes@20 | 126 | #define SCSCR2_REIE 0x08
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nkeynes@20 | 127 | #define SCSCR2_CKE 0x02
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nkeynes@20 | 128 |
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nkeynes@20 | 129 | #define IS_TRANSMIT_IRQ_ENABLED() (MMIO_READ(SCIF,SCSCR2) & SCSCR2_TIE)
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nkeynes@20 | 130 | #define IS_RECEIVE_IRQ_ENABLED() (MMIO_READ(SCIF,SCSCR2) & SCSCR2_RIE)
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nkeynes@20 | 131 | #define IS_RECEIVE_ERROR_IRQ_ENABLED() (MMIO_READ(SCIF,SCSCR2) & (SCSCR2_RIE|SCSCR2_REIE))
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nkeynes@20 | 132 | /* Receive is enabled if the RE bit is set in SCSCR2, and the ORER bit is cleared in SCLSR2 */
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nkeynes@428 | 133 | #define IS_RECEIVE_ENABLED() ( (MMIO_READ(SCIF,SCSCR2) & SCSCR2_RE) && ((MMIO_READ(SCIF,SCLSR2) & SCLSR2_ORER) == 0) )
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nkeynes@20 | 134 | /* Transmit is enabled if the TE bit is set in SCSCR2 */
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nkeynes@20 | 135 | #define IS_TRANSMIT_ENABLED() (MMIO_READ(SCIF,SCSCR2) & SCSCR2_TE)
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nkeynes@20 | 136 | #define IS_LOOPBACK_ENABLED() (MMIO_READ(SCIF,SCFCR2) & SCFCR2_LOOP)
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nkeynes@20 | 137 |
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nkeynes@20 | 138 | /* Serial status register flags */
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nkeynes@20 | 139 | #define SCFSR2_ER 0x80
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nkeynes@20 | 140 | #define SCFSR2_TEND 0x40
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nkeynes@20 | 141 | #define SCFSR2_TDFE 0x20
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nkeynes@20 | 142 | #define SCFSR2_BRK 0x10
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nkeynes@20 | 143 | #define SCFSR2_RDF 0x02
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nkeynes@20 | 144 | #define SCFSR2_DR 0x01
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nkeynes@20 | 145 |
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nkeynes@20 | 146 | /* FIFO control register flags */
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nkeynes@20 | 147 | #define SCFCR2_MCE 0x08
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nkeynes@20 | 148 | #define SCFCR2_TFRST 0x04
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nkeynes@20 | 149 | #define SCFCR2_RFRST 0x02
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nkeynes@20 | 150 | #define SCFCR2_LOOP 0x01
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nkeynes@20 | 151 |
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nkeynes@20 | 152 | /* Line Status Register */
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nkeynes@20 | 153 | #define SCLSR2_ORER 0x01
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nkeynes@20 | 154 |
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nkeynes@20 | 155 | struct SCIF_fifo {
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nkeynes@20 | 156 | int head;
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nkeynes@20 | 157 | int tail;
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nkeynes@20 | 158 | int trigger;
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nkeynes@20 | 159 | uint8_t data[FIFO_ARR_LENGTH];
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nkeynes@20 | 160 | };
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nkeynes@20 | 161 |
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nkeynes@22 | 162 | int SCIF_recvq_triggers[4] = {1, 4, 8, 14};
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nkeynes@22 | 163 | struct SCIF_fifo SCIF_recvq = {0,0,1};
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nkeynes@22 | 164 |
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nkeynes@22 | 165 | int SCIF_sendq_triggers[4] = {8, 4, 2, 1};
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nkeynes@22 | 166 | struct SCIF_fifo SCIF_sendq = {0,0,8};
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nkeynes@22 | 167 |
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nkeynes@22 | 168 | /**
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nkeynes@22 | 169 | * Flag to indicate if data was received (ie added to the receive queue)
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nkeynes@22 | 170 | * during the last SCIF clock tick. Used to determine when to set the DR
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nkeynes@22 | 171 | * flag.
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nkeynes@22 | 172 | */
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nkeynes@22 | 173 | gboolean SCIF_rcvd_last_tick = FALSE;
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nkeynes@22 | 174 |
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nkeynes@30 | 175 | uint32_t SCIF_tick_period = 0;
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nkeynes@30 | 176 | uint32_t SCIF_tick_remainder = 0;
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nkeynes@30 | 177 |
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nkeynes@20 | 178 | void SCIF_save_state( FILE *f )
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nkeynes@20 | 179 | {
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nkeynes@22 | 180 | fwrite( &SCIF_recvq, sizeof(SCIF_recvq), 1, f );
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nkeynes@22 | 181 | fwrite( &SCIF_sendq, sizeof(SCIF_sendq), 1, f );
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nkeynes@22 | 182 | fwrite( &SCIF_rcvd_last_tick, sizeof(gboolean), 1, f );
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nkeynes@20 | 183 |
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nkeynes@20 | 184 | }
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nkeynes@20 | 185 |
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nkeynes@20 | 186 | int SCIF_load_state( FILE *f )
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nkeynes@20 | 187 | {
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nkeynes@22 | 188 | fread( &SCIF_recvq, sizeof(SCIF_recvq), 1, f );
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nkeynes@22 | 189 | fread( &SCIF_sendq, sizeof(SCIF_sendq), 1, f );
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nkeynes@22 | 190 | fread( &SCIF_rcvd_last_tick, sizeof(gboolean), 1, f );
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nkeynes@20 | 191 | return 0;
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nkeynes@20 | 192 | }
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nkeynes@20 | 193 |
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nkeynes@20 | 194 | static inline uint8_t SCIF_recvq_size( )
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nkeynes@20 | 195 | {
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nkeynes@20 | 196 | int val = SCIF_recvq.tail - SCIF_recvq.head;
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nkeynes@20 | 197 | if( val < 0 ) {
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nkeynes@20 | 198 | val = FIFO_ARR_LENGTH - SCIF_recvq.head + SCIF_recvq.tail;
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nkeynes@20 | 199 | }
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nkeynes@20 | 200 | return val;
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nkeynes@20 | 201 | }
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nkeynes@20 | 202 |
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nkeynes@20 | 203 | int SCIF_recvq_dequeue( gboolean clearFlags )
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nkeynes@20 | 204 | {
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nkeynes@20 | 205 | uint8_t result;
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nkeynes@20 | 206 | uint32_t tmp, length;
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nkeynes@20 | 207 | if( SCIF_recvq.head == SCIF_recvq.tail )
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nkeynes@20 | 208 | return -1; /* No data */
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nkeynes@20 | 209 | result = SCIF_recvq.data[SCIF_recvq.head++];
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nkeynes@20 | 210 | if( SCIF_recvq.head > FIFO_LENGTH )
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nkeynes@20 | 211 | SCIF_recvq.head = 0;
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nkeynes@20 | 212 |
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nkeynes@20 | 213 | /* Update data count register */
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nkeynes@20 | 214 | tmp = MMIO_READ( SCIF, SCFDR2 ) & 0xF0;
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nkeynes@20 | 215 | length = SCIF_recvq_size();
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nkeynes@20 | 216 | MMIO_WRITE( SCIF, SCFDR2, tmp | length );
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nkeynes@20 | 217 |
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nkeynes@20 | 218 | /* Clear flags (if requested ) */
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nkeynes@20 | 219 | if( clearFlags && length < SCIF_recvq.trigger ) {
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nkeynes@20 | 220 | tmp = SCFSR2_RDF;
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nkeynes@20 | 221 | if( length == 0 )
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nkeynes@20 | 222 | tmp |= SCFSR2_DR;
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nkeynes@20 | 223 | tmp = MMIO_READ( SCIF, SCFSR2 ) & (~tmp);
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nkeynes@20 | 224 | MMIO_WRITE( SCIF, SCFSR2, tmp );
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nkeynes@20 | 225 | /* If both flags are cleared, clear the interrupt as well */
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nkeynes@21 | 226 | if( (tmp & (SCFSR2_DR|SCFSR2_RDF)) == 0 && IS_RECEIVE_IRQ_ENABLED() )
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nkeynes@20 | 227 | intc_clear_interrupt( INT_SCIF_RXI );
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nkeynes@20 | 228 | }
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nkeynes@20 | 229 |
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nkeynes@20 | 230 | return (int)(unsigned int)result;
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nkeynes@20 | 231 | }
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nkeynes@20 | 232 |
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nkeynes@20 | 233 | gboolean SCIF_recvq_enqueue( uint8_t value )
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nkeynes@20 | 234 | {
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nkeynes@20 | 235 | uint32_t tmp, length;
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nkeynes@20 | 236 | int newpos = SCIF_recvq.tail + 1;
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nkeynes@20 | 237 | if( newpos > FIFO_LENGTH )
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nkeynes@20 | 238 | newpos = 0;
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nkeynes@20 | 239 | if( newpos == SCIF_recvq.head ) {
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nkeynes@20 | 240 | /* FIFO full - set ORER and discard the value */
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nkeynes@20 | 241 | MMIO_WRITE( SCIF, SCLSR2, SCLSR2_ORER );
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nkeynes@20 | 242 | if( IS_RECEIVE_ERROR_IRQ_ENABLED() )
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nkeynes@20 | 243 | intc_raise_interrupt( INT_SCIF_ERI );
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nkeynes@20 | 244 | return FALSE;
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nkeynes@20 | 245 | }
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nkeynes@20 | 246 | SCIF_recvq.data[SCIF_recvq.tail] = value;
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nkeynes@20 | 247 |
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nkeynes@20 | 248 | /* Update data count register */
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nkeynes@20 | 249 | tmp = MMIO_READ( SCIF, SCFDR2 ) & 0xF0;
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nkeynes@20 | 250 | length = SCIF_recvq_size();
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nkeynes@20 | 251 | MMIO_WRITE( SCIF, SCFDR2, tmp | length );
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nkeynes@20 | 252 |
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nkeynes@20 | 253 | /* Update status register */
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nkeynes@20 | 254 | tmp = MMIO_READ( SCIF, SCFSR2 );
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nkeynes@20 | 255 | if( length >= SCIF_recvq.trigger ) {
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nkeynes@20 | 256 | tmp |= SCFSR2_RDF;
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nkeynes@20 | 257 | if( IS_RECEIVE_IRQ_ENABLED() )
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nkeynes@20 | 258 | intc_raise_interrupt( INT_SCIF_RXI );
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nkeynes@54 | 259 | DMAC_trigger( DMAC_SCIF_RDF );
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nkeynes@20 | 260 | }
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nkeynes@20 | 261 | MMIO_WRITE( SCIF, SCFSR2, tmp );
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nkeynes@20 | 262 | return TRUE;
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nkeynes@20 | 263 | }
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nkeynes@20 | 264 |
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nkeynes@20 | 265 |
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nkeynes@20 | 266 | /**
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nkeynes@20 | 267 | * Reset the receive FIFO to its initial state. Manual is unclear as to
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nkeynes@20 | 268 | * whether this also clears flags/interrupts, but we're assuming here that
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nkeynes@20 | 269 | * it does until proven otherwise.
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nkeynes@20 | 270 | */
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nkeynes@20 | 271 | void SCIF_recvq_clear( void )
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nkeynes@20 | 272 | {
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nkeynes@20 | 273 | SCIF_recvq.head = SCIF_recvq.tail = 0;
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nkeynes@20 | 274 | MMIO_WRITE( SCIF, SCFDR2, MMIO_READ( SCIF, SCFDR2 ) & 0xF0 );
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nkeynes@20 | 275 | MMIO_WRITE( SCIF, SCFSR2, MMIO_READ( SCIF, SCFSR2 ) & ~(SCFSR2_DR|SCFSR2_RDF) );
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nkeynes@21 | 276 | if( IS_RECEIVE_IRQ_ENABLED() )
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nkeynes@21 | 277 | intc_clear_interrupt( INT_SCIF_RXI );
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nkeynes@20 | 278 | }
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nkeynes@20 | 279 |
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nkeynes@20 | 280 | static inline uint8_t SCIF_sendq_size( )
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nkeynes@20 | 281 | {
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nkeynes@20 | 282 | int val = SCIF_sendq.tail - SCIF_sendq.head;
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nkeynes@20 | 283 | if( val < 0 ) {
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nkeynes@20 | 284 | val = FIFO_ARR_LENGTH - SCIF_sendq.head + SCIF_sendq.tail;
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nkeynes@20 | 285 | }
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nkeynes@20 | 286 | return val;
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nkeynes@20 | 287 | }
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nkeynes@20 | 288 |
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nkeynes@20 | 289 | /**
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nkeynes@20 | 290 | * Dequeue one byte from the SCIF transmit queue (ie transmit the byte),
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nkeynes@20 | 291 | * updating all status flags as required.
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nkeynes@20 | 292 | * @return The byte dequeued, or -1 if the queue is empty.
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nkeynes@20 | 293 | */
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nkeynes@20 | 294 | int SCIF_sendq_dequeue( )
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nkeynes@20 | 295 | {
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nkeynes@20 | 296 | uint8_t result;
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nkeynes@20 | 297 | uint32_t tmp, length;
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nkeynes@20 | 298 | if( SCIF_sendq.head == SCIF_sendq.tail )
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nkeynes@20 | 299 | return -1; /* No data */
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nkeynes@20 | 300 |
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nkeynes@20 | 301 | /* Update queue head pointer */
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nkeynes@20 | 302 | result = SCIF_sendq.data[SCIF_sendq.head++];
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nkeynes@20 | 303 | if( SCIF_sendq.head > FIFO_LENGTH )
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nkeynes@20 | 304 | SCIF_sendq.head = 0;
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nkeynes@20 | 305 |
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nkeynes@20 | 306 | /* Update data count register */
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nkeynes@20 | 307 | tmp = MMIO_READ( SCIF, SCFDR2 ) & 0x0F;
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nkeynes@20 | 308 | length = SCIF_sendq_size();
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nkeynes@20 | 309 | MMIO_WRITE( SCIF, SCFDR2, tmp | (length << 8) );
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nkeynes@20 | 310 |
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nkeynes@20 | 311 | /* Update status register */
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nkeynes@20 | 312 | if( length <= SCIF_sendq.trigger ) {
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nkeynes@20 | 313 | tmp = MMIO_READ( SCIF, SCFSR2 ) | SCFSR2_TDFE;
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nkeynes@20 | 314 | if( length == 0 )
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nkeynes@20 | 315 | tmp |= SCFSR2_TEND; /* Transmission ended - no data waiting */
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nkeynes@20 | 316 | if( IS_TRANSMIT_IRQ_ENABLED() )
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nkeynes@20 | 317 | intc_raise_interrupt( INT_SCIF_TXI );
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nkeynes@54 | 318 | DMAC_trigger( DMAC_SCIF_TDE );
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nkeynes@20 | 319 | MMIO_WRITE( SCIF, SCFSR2, tmp );
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nkeynes@20 | 320 | }
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nkeynes@20 | 321 | return (int)(unsigned int)result;
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nkeynes@20 | 322 | }
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nkeynes@20 | 323 |
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nkeynes@20 | 324 | /**
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nkeynes@20 | 325 | * Enqueue a single byte in the SCIF transmit queue. If the queue is full,
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nkeynes@20 | 326 | * the value will be discarded.
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nkeynes@20 | 327 | * @param value to be queued.
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nkeynes@20 | 328 | * @param clearFlags TRUE if the TEND/TDFE flags should be cleared
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nkeynes@20 | 329 | * if the queue exceeds the trigger level. (According to the manual,
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nkeynes@20 | 330 | * DMAC writes will clear the flag, whereas regular SH4 writes do NOT
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nkeynes@20 | 331 | * automatically clear it. Go figure).
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nkeynes@20 | 332 | * @return gboolean TRUE if the value was queued, FALSE if the queue was
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nkeynes@20 | 333 | * full.
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nkeynes@20 | 334 | */
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nkeynes@20 | 335 | gboolean SCIF_sendq_enqueue( uint8_t value, gboolean clearFlags )
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nkeynes@20 | 336 | {
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nkeynes@20 | 337 | uint32_t tmp, length;
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nkeynes@20 | 338 | int newpos = SCIF_sendq.tail + 1;
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nkeynes@20 | 339 | if( newpos > FIFO_LENGTH )
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nkeynes@20 | 340 | newpos = 0;
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nkeynes@20 | 341 | if( newpos == SCIF_sendq.head ) {
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nkeynes@20 | 342 | /* FIFO full - discard */
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nkeynes@20 | 343 | return FALSE;
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nkeynes@20 | 344 | }
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nkeynes@20 | 345 | SCIF_sendq.data[SCIF_sendq.tail] = value;
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nkeynes@20 | 346 | SCIF_sendq.tail = newpos;
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nkeynes@20 | 347 |
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nkeynes@20 | 348 | /* Update data count register */
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nkeynes@20 | 349 | tmp = MMIO_READ( SCIF, SCFDR2 ) & 0x0F;
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nkeynes@20 | 350 | length = SCIF_sendq_size();
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nkeynes@20 | 351 | MMIO_WRITE( SCIF, SCFDR2, tmp | (length << 8) );
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nkeynes@20 | 352 |
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nkeynes@20 | 353 | /* Update flags if requested */
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nkeynes@20 | 354 | if( clearFlags ) {
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nkeynes@20 | 355 | tmp = SCFSR2_TEND;
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nkeynes@20 | 356 | if( length > SCIF_sendq.trigger ) {
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nkeynes@20 | 357 | tmp |= SCFSR2_TDFE;
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nkeynes@21 | 358 | if( IS_TRANSMIT_IRQ_ENABLED() )
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nkeynes@21 | 359 | intc_clear_interrupt( INT_SCIF_TXI );
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nkeynes@20 | 360 | }
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nkeynes@20 | 361 | tmp = MMIO_READ( SCIF, SCFSR2 ) & (~tmp);
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nkeynes@20 | 362 | MMIO_WRITE( SCIF, SCFSR2, tmp );
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nkeynes@20 | 363 | }
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nkeynes@20 | 364 | return TRUE;
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nkeynes@20 | 365 | }
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nkeynes@20 | 366 |
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nkeynes@20 | 367 | void SCIF_sendq_clear( void )
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nkeynes@20 | 368 | {
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nkeynes@20 | 369 | SCIF_sendq.head = SCIF_sendq.tail = 0;
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nkeynes@20 | 370 | MMIO_WRITE( SCIF, SCFDR2, MMIO_READ( SCIF, SCFDR2 ) & 0x0F );
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nkeynes@20 | 371 | MMIO_WRITE( SCIF, SCFSR2, MMIO_READ( SCIF, SCFSR2 ) | SCFSR2_TEND | SCFSR2_TDFE );
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nkeynes@20 | 372 | if( IS_TRANSMIT_IRQ_ENABLED() ) {
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nkeynes@20 | 373 | intc_raise_interrupt( INT_SCIF_TXI );
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nkeynes@54 | 374 | DMAC_trigger( DMAC_SCIF_TDE );
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nkeynes@20 | 375 | }
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nkeynes@20 | 376 | }
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nkeynes@20 | 377 |
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nkeynes@21 | 378 | /**
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nkeynes@21 | 379 | * Update the SCFSR2 status register with the given mask (ie clear any values
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nkeynes@21 | 380 | * that are set to 0 in the mask. According to a strict reading of the doco
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nkeynes@21 | 381 | * though, the bits will only actually clear if the flag state is no longer
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nkeynes@21 | 382 | * true, so we need to recheck everything...
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nkeynes@21 | 383 | */
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nkeynes@21 | 384 | void SCIF_update_status( uint32_t mask )
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nkeynes@21 | 385 | {
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nkeynes@21 | 386 | uint32_t value = MMIO_READ( SCIF, SCFSR2 );
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nkeynes@21 | 387 | uint32_t result = value & mask;
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nkeynes@21 | 388 | uint32_t sendq_size = SCIF_sendq_size();
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nkeynes@21 | 389 | uint32_t recvq_size = SCIF_recvq_size();
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nkeynes@21 | 390 |
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nkeynes@21 | 391 | if( sendq_size != 0 )
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nkeynes@21 | 392 | result |= SCFSR2_TEND;
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nkeynes@21 | 393 |
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nkeynes@21 | 394 | if( sendq_size <= SCIF_sendq.trigger )
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nkeynes@21 | 395 | result |= SCFSR2_TDFE;
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nkeynes@428 | 396 | else if( (result & SCFSR2_TDFE) == 0 && IS_TRANSMIT_IRQ_ENABLED() )
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nkeynes@21 | 397 | intc_clear_interrupt( INT_SCIF_TXI );
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nkeynes@21 | 398 |
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nkeynes@21 | 399 | if( recvq_size >= SCIF_recvq.trigger )
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nkeynes@21 | 400 | result |= SCFSR2_RDF;
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nkeynes@21 | 401 | if( (value & SCFSR2_DR) != 0 && (result & SCFSR2_DR) == 0 &&
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nkeynes@21 | 402 | recvq_size != 0 )
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nkeynes@21 | 403 | result |= SCFSR2_DR;
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nkeynes@21 | 404 | if( (result & (SCFSR2_DR|SCFSR2_RDF)) == 0 && IS_RECEIVE_IRQ_ENABLED() )
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nkeynes@21 | 405 | intc_clear_interrupt( INT_SCIF_RXI );
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nkeynes@21 | 406 |
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nkeynes@21 | 407 | if( IS_RECEIVE_ERROR_IRQ_ENABLED() ) {
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nkeynes@21 | 408 | if( (result & SCFSR2_BRK) == 0 )
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nkeynes@21 | 409 | intc_clear_interrupt( INT_SCIF_BRI );
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nkeynes@21 | 410 | if( (result & SCFSR2_ER) == 0 &&
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nkeynes@21 | 411 | (MMIO_READ( SCIF, SCLSR2 ) & SCLSR2_ORER) == 0 )
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nkeynes@21 | 412 | intc_clear_interrupt( INT_SCIF_ERI );
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nkeynes@21 | 413 | }
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nkeynes@21 | 414 | }
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nkeynes@20 | 415 |
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nkeynes@20 | 416 | /**
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nkeynes@20 | 417 | * Set the break detected flag
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nkeynes@20 | 418 | */
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nkeynes@20 | 419 | void SCIF_set_break( void )
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nkeynes@20 | 420 | {
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nkeynes@20 | 421 | MMIO_WRITE( SCIF, SCFSR2, MMIO_READ( SCIF, SCFSR2 ) | SCFSR2_BRK );
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nkeynes@20 | 422 | if( IS_RECEIVE_ERROR_IRQ_ENABLED() )
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nkeynes@20 | 423 | intc_raise_interrupt( INT_SCIF_BRI );
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nkeynes@20 | 424 | }
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nkeynes@20 | 425 |
|
nkeynes@20 | 426 | const static int SCIF_CLOCK_MULTIPLIER[4] = {1, 4, 16, 64};
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nkeynes@20 | 427 |
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nkeynes@20 | 428 | /**
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nkeynes@20 | 429 | * Calculate the current line speed.
|
nkeynes@20 | 430 | */
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nkeynes@20 | 431 | void SCIF_update_line_speed( void )
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nkeynes@20 | 432 | {
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nkeynes@20 | 433 | /* If CKE1 is set, use the external clock as a base */
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nkeynes@20 | 434 | if( MMIO_READ( SCIF, SCSCR2 ) & SCSCR2_CKE ) {
|
nkeynes@20 | 435 |
|
nkeynes@20 | 436 |
|
nkeynes@20 | 437 | } else {
|
nkeynes@20 | 438 |
|
nkeynes@20 | 439 | /* Otherwise, SH4 peripheral clock divided by n */
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nkeynes@20 | 440 | int mult = SCIF_CLOCK_MULTIPLIER[MMIO_READ( SCIF, SCSMR2 ) & 0x03];
|
nkeynes@20 | 441 |
|
nkeynes@20 | 442 | /* Then process the bitrate register */
|
nkeynes@20 | 443 | int bbr = MMIO_READ( SCIF, SCBRR2 ) & 0xFF;
|
nkeynes@20 | 444 |
|
nkeynes@20 | 445 | int baudrate = sh4_peripheral_freq / (32 * mult * (bbr+1) );
|
nkeynes@20 | 446 |
|
nkeynes@20 | 447 | if( serial_device != NULL && serial_device->set_line_speed != NULL )
|
nkeynes@20 | 448 | serial_device->set_line_speed( baudrate );
|
nkeynes@30 | 449 |
|
nkeynes@30 | 450 | SCIF_tick_period = sh4_peripheral_period * (32 * mult * (bbr+1));
|
nkeynes@30 | 451 |
|
nkeynes@20 | 452 | /*
|
nkeynes@20 | 453 | clock_set_tick_rate( CLOCK_SCIF, baudrate / 10 );
|
nkeynes@20 | 454 | */
|
nkeynes@20 | 455 | }
|
nkeynes@20 | 456 | }
|
nkeynes@20 | 457 |
|
nkeynes@20 | 458 | int32_t mmio_region_SCIF_read( uint32_t reg )
|
nkeynes@20 | 459 | {
|
nkeynes@20 | 460 | switch( reg ) {
|
nkeynes@20 | 461 | case SCFRDR2: /* Receive data */
|
nkeynes@20 | 462 | return SCIF_recvq_dequeue(FALSE);
|
nkeynes@20 | 463 | default:
|
nkeynes@20 | 464 | return MMIO_READ( SCIF, reg );
|
nkeynes@20 | 465 | }
|
nkeynes@20 | 466 | }
|
nkeynes@20 | 467 |
|
nkeynes@20 | 468 | void mmio_region_SCIF_write( uint32_t reg, uint32_t val )
|
nkeynes@20 | 469 | {
|
nkeynes@20 | 470 | uint32_t tmp;
|
nkeynes@20 | 471 | switch( reg ) {
|
nkeynes@20 | 472 | case SCSMR2: /* Serial mode register */
|
nkeynes@20 | 473 | /* Bit 6 => 0 = 8-bit, 1 = 7-bit
|
nkeynes@20 | 474 | * Bit 5 => 0 = Parity disabled, 1 = parity enabled
|
nkeynes@20 | 475 | * Bit 4 => 0 = Even parity, 1 = Odd parity
|
nkeynes@20 | 476 | * Bit 3 => 0 = 1 stop bit, 1 = 2 stop bits
|
nkeynes@20 | 477 | * Bits 0-1 => Clock select 00 = P, 01 = P/4, 10 = P/16, 11 = P/64
|
nkeynes@20 | 478 | */
|
nkeynes@20 | 479 | val &= 0x007B;
|
nkeynes@20 | 480 | if( serial_device != NULL ) {
|
nkeynes@20 | 481 | serial_device->set_line_params( val );
|
nkeynes@20 | 482 | }
|
nkeynes@20 | 483 | tmp = MMIO_READ( SCIF, SCSMR2 );
|
nkeynes@428 | 484 | if( (tmp & 0x03) != (val & 0x03) ) {
|
nkeynes@20 | 485 | /* Clock change */
|
nkeynes@20 | 486 | SCIF_update_line_speed( );
|
nkeynes@20 | 487 | }
|
nkeynes@20 | 488 | /* Save for later read-back */
|
nkeynes@20 | 489 | MMIO_WRITE( SCIF, SCSMR2, val );
|
nkeynes@20 | 490 | break;
|
nkeynes@20 | 491 | case SCBRR2: /* Bit rate register */
|
nkeynes@20 | 492 | MMIO_WRITE( SCIF, SCBRR2, val );
|
nkeynes@20 | 493 | SCIF_update_line_speed( );
|
nkeynes@20 | 494 | break;
|
nkeynes@20 | 495 | case SCSCR2: /* Serial control register */
|
nkeynes@20 | 496 | /* Bit 7 => Transmit-FIFO-data-empty interrupt enabled
|
nkeynes@20 | 497 | * Bit 6 => Receive-data-full interrupt enabled
|
nkeynes@20 | 498 | * Bit 5 => Transmit enable
|
nkeynes@20 | 499 | * Bit 4 => Receive enable
|
nkeynes@20 | 500 | * Bit 3 => Receive-error/break interrupt enabled
|
nkeynes@20 | 501 | * Bit 1 => Clock enable
|
nkeynes@20 | 502 | */
|
nkeynes@20 | 503 | val &= 0x00FA;
|
nkeynes@20 | 504 | /* Clear any interrupts that just became disabled */
|
nkeynes@428 | 505 | if( (val & SCSCR2_TIE) == 0 )
|
nkeynes@20 | 506 | intc_clear_interrupt( INT_SCIF_TXI );
|
nkeynes@428 | 507 | if( (val & SCSCR2_RIE) == 0 )
|
nkeynes@20 | 508 | intc_clear_interrupt( INT_SCIF_RXI );
|
nkeynes@428 | 509 | if( (val & (SCSCR2_RIE|SCSCR2_REIE)) == 0 ) {
|
nkeynes@20 | 510 | intc_clear_interrupt( INT_SCIF_ERI );
|
nkeynes@20 | 511 | intc_clear_interrupt( INT_SCIF_BRI );
|
nkeynes@20 | 512 | }
|
nkeynes@20 | 513 |
|
nkeynes@20 | 514 | MMIO_WRITE( SCIF, reg, val );
|
nkeynes@20 | 515 | break;
|
nkeynes@20 | 516 | case SCFTDR2: /* Transmit FIFO data register */
|
nkeynes@20 | 517 | SCIF_sendq_enqueue( val, FALSE );
|
nkeynes@20 | 518 | break;
|
nkeynes@20 | 519 | case SCFSR2: /* Serial status register */
|
nkeynes@20 | 520 | /* Bits 12-15 Parity error count
|
nkeynes@20 | 521 | * Bits 8-11 Framing erro count
|
nkeynes@20 | 522 | * Bit 7 - Receive error
|
nkeynes@20 | 523 | * Bit 6 - Transmit end
|
nkeynes@20 | 524 | * Bit 5 - Transmit FIFO data empty
|
nkeynes@20 | 525 | * Bit 4 - Break detect
|
nkeynes@20 | 526 | * Bit 3 - Framing error
|
nkeynes@20 | 527 | * Bit 2 - Parity error
|
nkeynes@20 | 528 | * Bit 1 - Receive FIFO data full
|
nkeynes@20 | 529 | * Bit 0 - Receive data ready
|
nkeynes@20 | 530 | */
|
nkeynes@20 | 531 | /* Clear off any flags/interrupts that are being set to 0 */
|
nkeynes@21 | 532 | SCIF_update_status( val );
|
nkeynes@20 | 533 | break;
|
nkeynes@20 | 534 | case SCFCR2: /* FIFO control register */
|
nkeynes@20 | 535 | val &= 0x0F;
|
nkeynes@20 | 536 | SCIF_recvq.trigger = SCIF_recvq_triggers[val >> 6];
|
nkeynes@20 | 537 | SCIF_sendq.trigger = SCIF_sendq_triggers[(val >> 4) & 0x03];
|
nkeynes@20 | 538 | if( val & SCFCR2_TFRST ) {
|
nkeynes@20 | 539 | SCIF_sendq_clear();
|
nkeynes@20 | 540 | }
|
nkeynes@20 | 541 | if( val & SCFCR2_RFRST ) {
|
nkeynes@20 | 542 | SCIF_recvq_clear();
|
nkeynes@20 | 543 | }
|
nkeynes@20 | 544 |
|
nkeynes@20 | 545 | MMIO_WRITE( SCIF, reg, val );
|
nkeynes@20 | 546 | break;
|
nkeynes@20 | 547 | case SCSPTR2: /* Serial Port Register */
|
nkeynes@20 | 548 | MMIO_WRITE( SCIF, reg, val );
|
nkeynes@20 | 549 | /* NOT IMPLEMENTED */
|
nkeynes@21 | 550 | WARN( "SCSPTR2 not implemented: Write %08X", val );
|
nkeynes@20 | 551 | break;
|
nkeynes@20 | 552 | case SCLSR2:
|
nkeynes@20 | 553 | val = val & SCLSR2_ORER;
|
nkeynes@20 | 554 | if( val == 0 ) {
|
nkeynes@20 | 555 | MMIO_WRITE( SCIF, SCLSR2, val );
|
nkeynes@21 | 556 | if( (MMIO_READ( SCIF, SCFSR2 ) & SCFSR2_ER) == 0 &&
|
nkeynes@21 | 557 | IS_RECEIVE_ERROR_IRQ_ENABLED() )
|
nkeynes@20 | 558 | intc_clear_interrupt( INT_SCIF_ERI );
|
nkeynes@20 | 559 | }
|
nkeynes@20 | 560 |
|
nkeynes@20 | 561 | break;
|
nkeynes@20 | 562 | }
|
nkeynes@20 | 563 | }
|
nkeynes@20 | 564 |
|
nkeynes@20 | 565 | /**
|
nkeynes@20 | 566 | * Actions for a single tick of the serial clock, defined as the transmission
|
nkeynes@20 | 567 | * time of a single frame.
|
nkeynes@20 | 568 | *
|
nkeynes@20 | 569 | * If transmit queue is non-empty:
|
nkeynes@20 | 570 | * Transmit one byte and remove from queue
|
nkeynes@20 | 571 | * If input receive source is non-empty:
|
nkeynes@20 | 572 | * Transfer one byte to the receive queue (if queue is full, byte is lost)
|
nkeynes@20 | 573 | * If recvq is non-empty, less than the trigger level, and no data has been
|
nkeynes@20 | 574 | * received in the last 2 ticks (including this one), set the DR flag and
|
nkeynes@20 | 575 | * IRQ if appropriate.
|
nkeynes@20 | 576 | */
|
nkeynes@20 | 577 | void SCIF_clock_tick( void )
|
nkeynes@20 | 578 | {
|
nkeynes@20 | 579 | gboolean rcvd = FALSE;
|
nkeynes@20 | 580 |
|
nkeynes@20 | 581 | if( IS_LOOPBACK_ENABLED() ) {
|
nkeynes@20 | 582 | if( IS_TRANSMIT_ENABLED() ) {
|
nkeynes@20 | 583 | int val = SCIF_sendq_dequeue();
|
nkeynes@20 | 584 | if( val != -1 && IS_RECEIVE_ENABLED() ) {
|
nkeynes@20 | 585 | SCIF_recvq_enqueue( val );
|
nkeynes@20 | 586 | rcvd = TRUE;
|
nkeynes@20 | 587 | }
|
nkeynes@20 | 588 | }
|
nkeynes@20 | 589 | } else {
|
nkeynes@20 | 590 | if( IS_TRANSMIT_ENABLED() ) {
|
nkeynes@20 | 591 | int val = SCIF_sendq_dequeue();
|
nkeynes@20 | 592 | if( val != -1 && serial_device != NULL &&
|
nkeynes@20 | 593 | serial_device->receive_data != NULL ) {
|
nkeynes@20 | 594 | serial_device->receive_data( val );
|
nkeynes@20 | 595 | }
|
nkeynes@20 | 596 | }
|
nkeynes@20 | 597 |
|
nkeynes@20 | 598 | if( IS_RECEIVE_ENABLED() ) {
|
nkeynes@20 | 599 | int val = serial_transmit_dequeue();
|
nkeynes@20 | 600 | if( val != -1 ) {
|
nkeynes@20 | 601 | SCIF_recvq_enqueue( val );
|
nkeynes@20 | 602 | rcvd = TRUE;
|
nkeynes@20 | 603 | }
|
nkeynes@20 | 604 | }
|
nkeynes@20 | 605 | }
|
nkeynes@20 | 606 |
|
nkeynes@20 | 607 | /* Check if we need to set the DR flag */
|
nkeynes@20 | 608 | if( !rcvd && !SCIF_rcvd_last_tick &&
|
nkeynes@20 | 609 | SCIF_recvq.head != SCIF_recvq.tail &&
|
nkeynes@20 | 610 | SCIF_recvq_size() < SCIF_recvq.trigger ) {
|
nkeynes@20 | 611 | uint32_t tmp = MMIO_READ( SCIF, SCFSR2 );
|
nkeynes@428 | 612 | if( (tmp & SCFSR2_DR) == 0 ) {
|
nkeynes@20 | 613 | MMIO_WRITE( SCIF, SCFSR2, tmp | SCFSR2_DR );
|
nkeynes@20 | 614 | if( IS_RECEIVE_IRQ_ENABLED() )
|
nkeynes@20 | 615 | intc_raise_interrupt( INT_SCIF_RXI );
|
nkeynes@54 | 616 | DMAC_trigger( DMAC_SCIF_RDF );
|
nkeynes@20 | 617 | }
|
nkeynes@20 | 618 | }
|
nkeynes@20 | 619 | SCIF_rcvd_last_tick = rcvd;
|
nkeynes@20 | 620 | }
|
nkeynes@23 | 621 |
|
nkeynes@30 | 622 | void SCIF_reset( void )
|
nkeynes@23 | 623 | {
|
nkeynes@32 | 624 | SCIF_recvq_clear();
|
nkeynes@32 | 625 | SCIF_sendq_clear();
|
nkeynes@32 | 626 | SCIF_update_line_speed();
|
nkeynes@23 | 627 | }
|
nkeynes@30 | 628 |
|
nkeynes@30 | 629 | void SCIF_run_slice( uint32_t nanosecs )
|
nkeynes@30 | 630 | {
|
nkeynes@30 | 631 | SCIF_tick_remainder += nanosecs;
|
nkeynes@30 | 632 | while( SCIF_tick_remainder >= SCIF_tick_period ) {
|
nkeynes@30 | 633 | SCIF_tick_remainder -= SCIF_tick_period;
|
nkeynes@30 | 634 | SCIF_clock_tick();
|
nkeynes@30 | 635 | }
|
nkeynes@30 | 636 | }
|