nkeynes@31 | 1 | /**
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nkeynes@421 | 2 | * $Id: intc.c,v 1.8 2007-10-06 08:52:08 nkeynes Exp $
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nkeynes@31 | 3 | *
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nkeynes@31 | 4 | * SH4 onboard interrupt controller (INTC) implementation
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nkeynes@31 | 5 | *
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nkeynes@31 | 6 | * Copyright (c) 2005 Nathan Keynes.
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nkeynes@31 | 7 | *
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nkeynes@31 | 8 | * This program is free software; you can redistribute it and/or modify
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nkeynes@31 | 9 | * it under the terms of the GNU General Public License as published by
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nkeynes@31 | 10 | * the Free Software Foundation; either version 2 of the License, or
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nkeynes@31 | 11 | * (at your option) any later version.
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nkeynes@31 | 12 | *
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nkeynes@31 | 13 | * This program is distributed in the hope that it will be useful,
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nkeynes@31 | 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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nkeynes@31 | 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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nkeynes@31 | 16 | * GNU General Public License for more details.
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nkeynes@31 | 17 | */
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nkeynes@31 | 18 |
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nkeynes@1 | 19 | #include <assert.h>
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nkeynes@1 | 20 | #include "sh4mmio.h"
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nkeynes@1 | 21 | #include "sh4core.h"
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nkeynes@1 | 22 | #include "intc.h"
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nkeynes@265 | 23 | #include "eventq.h"
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nkeynes@1 | 24 |
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nkeynes@1 | 25 | struct intc_sources_t {
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nkeynes@1 | 26 | char *name;
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nkeynes@1 | 27 | uint32_t code;
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nkeynes@157 | 28 | } intc_sources[INT_NUM_SOURCES] = {
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nkeynes@157 | 29 | { "IRQ0", 0x200 }, { "IRQ1", 0x220 }, { "IRQ2", 0x240 },
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nkeynes@157 | 30 | { "IRQ3", 0x260 }, { "IRQ4", 0x280 }, { "IRQ5", 0x2A0 },
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nkeynes@157 | 31 | { "IRQ6", 0x2C0 }, { "IRQ7", 0x2E0 }, { "IRQ8", 0x300 },
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nkeynes@157 | 32 | { "IRQ9", 0x320 }, { "IRQ10",0x340 }, { "IRQ11",0x360 },
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nkeynes@157 | 33 | { "IRQ12",0x380 }, { "IRQ13",0x3A0 }, { "IRQ14",0x3C0 },
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nkeynes@157 | 34 | { "NMI", 0x1C0 }, { "H-UDI",0x600 }, { "GPIOI",0x620 },
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nkeynes@157 | 35 | { "DMTE0",0x640 }, { "DMTE1",0x660 }, { "DMTE2",0x680 },
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nkeynes@157 | 36 | { "DMTE3",0x6A0 }, { "DMTAE",0x6C0 }, { "TUNI0",0x400 },
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nkeynes@157 | 37 | { "TUNI1",0x420 }, { "TUNI2",0x440 }, { "TICPI2",0x460 },
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nkeynes@157 | 38 | { "RTC_ATI",0x480 },{ "RTC_PRI",0x4A0 },{ "RTC_CUI",0x4C0 },
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nkeynes@157 | 39 | { "SCI_ERI",0x4E0 },{ "SCI_RXI",0x500 },{ "SCI_TXI",0x520 },
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nkeynes@157 | 40 | { "SCI_TEI",0x540 },
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nkeynes@421 | 41 | { "SCIF_ERI",0x700 },{ "SCIF_RXI",0x720 },{ "SCIF_BRI",0x740 },
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nkeynes@157 | 42 | { "SCIF_TXI",0x760 },
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nkeynes@157 | 43 | { "WDT_ITI",0x560 },{ "RCMI",0x580 }, { "ROVI",0x5A0 } };
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nkeynes@1 | 44 |
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nkeynes@157 | 45 | static int intc_default_priority[INT_NUM_SOURCES] = { 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 16 };
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nkeynes@157 | 46 |
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nkeynes@157 | 47 | #define PRIORITY(which) intc_state.priority[which]
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nkeynes@1 | 48 | #define INTCODE(which) intc_sources[which].code
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nkeynes@1 | 49 |
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nkeynes@157 | 50 | static struct intc_state {
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nkeynes@157 | 51 | int num_pending;
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nkeynes@157 | 52 | int pending[INT_NUM_SOURCES];
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nkeynes@157 | 53 | int priority[INT_NUM_SOURCES];
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nkeynes@157 | 54 | } intc_state;
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nkeynes@1 | 55 |
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nkeynes@1 | 56 | void mmio_region_INTC_write( uint32_t reg, uint32_t val )
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nkeynes@1 | 57 | {
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nkeynes@1 | 58 | /* Well it saves having to use an intermediate table... */
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nkeynes@1 | 59 | switch( reg ) {
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nkeynes@1 | 60 | case ICR: /* care about this later */
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nkeynes@1 | 61 | break;
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nkeynes@1 | 62 | case IPRA:
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nkeynes@1 | 63 | PRIORITY(INT_TMU_TUNI0) = (val>>12)&0x000F;
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nkeynes@1 | 64 | PRIORITY(INT_TMU_TUNI1) = (val>>8)&0x000F;
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nkeynes@1 | 65 | PRIORITY(INT_TMU_TUNI2) =
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nkeynes@1 | 66 | PRIORITY(INT_TMU_TICPI2) = (val>>4)&0x000F;
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nkeynes@1 | 67 | PRIORITY(INT_RTC_ATI) =
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nkeynes@1 | 68 | PRIORITY(INT_RTC_PRI) =
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nkeynes@1 | 69 | PRIORITY(INT_RTC_CUI) = val&0x000F;
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nkeynes@1 | 70 | break;
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nkeynes@1 | 71 | case IPRB:
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nkeynes@1 | 72 | PRIORITY(INT_WDT_ITI) = (val>>12)&0x000F;
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nkeynes@1 | 73 | PRIORITY(INT_REF_RCMI) =
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nkeynes@1 | 74 | PRIORITY(INT_REF_ROVI) = (val>>8)&0x000F;
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nkeynes@1 | 75 | PRIORITY(INT_SCI_ERI) =
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nkeynes@1 | 76 | PRIORITY(INT_SCI_RXI) =
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nkeynes@1 | 77 | PRIORITY(INT_SCI_TXI) =
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nkeynes@1 | 78 | PRIORITY(INT_SCI_TEI) = (val>>4)&0x000F;
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nkeynes@1 | 79 | /* Bits 0-3 reserved */
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nkeynes@1 | 80 | break;
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nkeynes@1 | 81 | case IPRC:
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nkeynes@1 | 82 | PRIORITY(INT_GPIO) = (val>>12)&0x000F;
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nkeynes@1 | 83 | PRIORITY(INT_DMA_DMTE0) =
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nkeynes@1 | 84 | PRIORITY(INT_DMA_DMTE1) =
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nkeynes@1 | 85 | PRIORITY(INT_DMA_DMTE2) =
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nkeynes@1 | 86 | PRIORITY(INT_DMA_DMTE3) =
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nkeynes@1 | 87 | PRIORITY(INT_DMA_DMAE) = (val>>8)&0x000F;
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nkeynes@1 | 88 | PRIORITY(INT_SCIF_ERI) =
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nkeynes@1 | 89 | PRIORITY(INT_SCIF_RXI) =
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nkeynes@1 | 90 | PRIORITY(INT_SCIF_BRI) =
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nkeynes@1 | 91 | PRIORITY(INT_SCIF_TXI) = (val>>4)&0x000F;
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nkeynes@1 | 92 | PRIORITY(INT_HUDI) = val&0x000F;
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nkeynes@1 | 93 | break;
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nkeynes@1 | 94 | }
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nkeynes@1 | 95 | MMIO_WRITE( INTC, reg, val );
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nkeynes@1 | 96 | }
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nkeynes@1 | 97 |
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nkeynes@1 | 98 | int32_t mmio_region_INTC_read( uint32_t reg )
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nkeynes@1 | 99 | {
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nkeynes@1 | 100 | return MMIO_READ( INTC, reg );
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nkeynes@1 | 101 | }
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nkeynes@157 | 102 |
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nkeynes@157 | 103 | void INTC_reset()
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nkeynes@157 | 104 | {
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nkeynes@157 | 105 | int i;
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nkeynes@157 | 106 |
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nkeynes@157 | 107 | intc_state.num_pending = 0;
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nkeynes@157 | 108 | for( i=0; i<INT_NUM_SOURCES; i++ )
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nkeynes@157 | 109 | intc_state.priority[i] = intc_default_priority[i];
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nkeynes@265 | 110 | sh4r.event_pending = event_get_next_time();
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nkeynes@265 | 111 | sh4r.event_types &= (~PENDING_IRQ);
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nkeynes@157 | 112 | }
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nkeynes@157 | 113 |
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nkeynes@157 | 114 |
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nkeynes@157 | 115 | void INTC_save_state( FILE *f )
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nkeynes@157 | 116 | {
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nkeynes@157 | 117 | fwrite( &intc_state, sizeof(intc_state), 1, f );
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nkeynes@157 | 118 | }
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nkeynes@157 | 119 |
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nkeynes@157 | 120 | int INTC_load_state( FILE *f )
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nkeynes@157 | 121 | {
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nkeynes@157 | 122 | if( fread(&intc_state, sizeof(intc_state), 1, f) != 1 )
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nkeynes@157 | 123 | return -1;
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nkeynes@157 | 124 | return 0;
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nkeynes@157 | 125 | }
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nkeynes@157 | 126 |
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nkeynes@1 | 127 | /* We basically maintain a priority queue here, raise_interrupt adds an entry,
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nkeynes@265 | 128 | * accept_interrupt takes it off. At the moment this is done as a simple
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nkeynes@1 | 129 | * ordered array, on the basis that in practice there's unlikely to be more
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nkeynes@1 | 130 | * than one at a time. There are lots of ways to optimize this if it turns out
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nkeynes@1 | 131 | * to be necessary, but I'd doubt it will be...
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nkeynes@1 | 132 | */
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nkeynes@1 | 133 |
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nkeynes@1 | 134 | void intc_raise_interrupt( int which )
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nkeynes@1 | 135 | {
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nkeynes@1 | 136 | int i, j, pri;
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nkeynes@1 | 137 |
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nkeynes@1 | 138 | pri = PRIORITY(which);
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nkeynes@1 | 139 | if( pri == 0 ) return; /* masked off */
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nkeynes@1 | 140 |
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nkeynes@157 | 141 | for( i=0; i<intc_state.num_pending; i++ ) {
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nkeynes@157 | 142 | if( intc_state.pending[i] == which ) return; /* Don't queue more than once */
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nkeynes@157 | 143 | if( PRIORITY(intc_state.pending[i]) > pri ||
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nkeynes@157 | 144 | (PRIORITY(intc_state.pending[i]) == pri &&
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nkeynes@157 | 145 | intc_state.pending[i] < which))
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nkeynes@1 | 146 | break;
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nkeynes@1 | 147 | }
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nkeynes@1 | 148 | /* i == insertion point */
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nkeynes@157 | 149 | for( j=intc_state.num_pending; j > i; j-- )
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nkeynes@157 | 150 | intc_state.pending[j] = intc_state.pending[j-1];
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nkeynes@157 | 151 | intc_state.pending[i] = which;
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nkeynes@1 | 152 |
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nkeynes@265 | 153 | if( i == intc_state.num_pending && (sh4r.sr&SR_BL)==0 && SH4_INTMASK() < pri ) {
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nkeynes@265 | 154 | sh4r.event_pending = 0;
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nkeynes@265 | 155 | sh4r.event_types |= PENDING_IRQ;
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nkeynes@265 | 156 | }
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nkeynes@1 | 157 |
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nkeynes@157 | 158 | intc_state.num_pending++;
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nkeynes@1 | 159 | }
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nkeynes@1 | 160 |
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nkeynes@19 | 161 | void intc_clear_interrupt( int which )
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nkeynes@19 | 162 | {
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nkeynes@20 | 163 | int i;
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nkeynes@157 | 164 | for( i=intc_state.num_pending-1; i>=0; i-- ) {
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nkeynes@157 | 165 | if( intc_state.pending[i] == which ) {
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nkeynes@20 | 166 | /* Shift array contents down */
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nkeynes@157 | 167 | while( i < intc_state.num_pending-1 ) {
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nkeynes@421 | 168 | intc_state.pending[i] = intc_state.pending[i+1];
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nkeynes@421 | 169 | i++;
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nkeynes@20 | 170 | }
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nkeynes@157 | 171 | intc_state.num_pending--;
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nkeynes@114 | 172 | intc_mask_changed();
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nkeynes@20 | 173 | break;
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nkeynes@20 | 174 | }
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nkeynes@20 | 175 | }
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nkeynes@20 | 176 |
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nkeynes@19 | 177 | }
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nkeynes@19 | 178 |
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nkeynes@1 | 179 | uint32_t intc_accept_interrupt( void )
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nkeynes@1 | 180 | {
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nkeynes@157 | 181 | assert(intc_state.num_pending > 0);
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nkeynes@157 | 182 | return INTCODE(intc_state.pending[intc_state.num_pending-1]);
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nkeynes@1 | 183 | }
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nkeynes@1 | 184 |
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nkeynes@1 | 185 | void intc_mask_changed( void )
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nkeynes@1 | 186 | {
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nkeynes@157 | 187 | if( intc_state.num_pending > 0 && (sh4r.sr&SR_BL)==0 &&
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nkeynes@265 | 188 | SH4_INTMASK() < PRIORITY(intc_state.pending[intc_state.num_pending-1]) ) {
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nkeynes@265 | 189 | sh4r.event_pending = 0;
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nkeynes@265 | 190 | sh4r.event_types |= PENDING_IRQ ;
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nkeynes@265 | 191 | }
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nkeynes@265 | 192 | else {
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nkeynes@265 | 193 | sh4r.event_pending = event_get_next_time();
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nkeynes@265 | 194 | sh4r.event_types &= (~PENDING_IRQ);
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nkeynes@265 | 195 | }
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nkeynes@1 | 196 | }
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nkeynes@1 | 197 |
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nkeynes@1 | 198 |
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nkeynes@1 | 199 | char *intc_get_interrupt_name( int code )
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nkeynes@1 | 200 | {
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nkeynes@1 | 201 | return intc_sources[code].name;
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nkeynes@1 | 202 | }
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