1.1 --- a/src/asic.c	Wed Feb 15 13:11:50 2006 +0000
     1.2 +++ b/src/asic.c	Thu Mar 30 11:26:45 2006 +0000
     1.3 @@ -1,5 +1,5 @@
     1.4  /**
     1.5 - * $Id: asic.c,v 1.12 2006-02-15 13:11:42 nkeynes Exp $
     1.6 + * $Id: asic.c,v 1.13 2006-03-22 14:29:00 nkeynes Exp $
     1.7   *
     1.8   * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
     1.9   * and DMA). 
    1.10 @@ -50,14 +50,15 @@
    1.11      register_io_region( &mmio_region_ASIC );
    1.12      register_io_region( &mmio_region_EXTDMA );
    1.13      mmio_region_ASIC.trace_flag = 0; /* Because this is called so often */
    1.14 -    asic_event( EVENT_GDROM_CMD );
    1.15  }
    1.16  
    1.17  void mmio_region_ASIC_write( uint32_t reg, uint32_t val )
    1.18  {
    1.19      switch( reg ) {
    1.20 +    case PIRQ1:
    1.21 +	val = val & 0xFFFFFFFE; /* Prevent the IDE event from clearing */
    1.22 +	/* fallthrough */
    1.23      case PIRQ0:
    1.24 -    case PIRQ1:
    1.25      case PIRQ2:
    1.26  	/* Clear any interrupts */
    1.27  	MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
    1.28 @@ -143,6 +144,14 @@
    1.29          intc_raise_interrupt( INT_IRQ9 );
    1.30  }
    1.31  
    1.32 +void asic_clear_event( int event ) {
    1.33 +    int offset = ((event&0x60)>>3);
    1.34 +    uint32_t result = MMIO_READ(ASIC, PIRQ0 + offset)  & (~(1<<(event&0x1F)));
    1.35 +    MMIO_WRITE( ASIC, PIRQ0 + offset, result );
    1.36 +
    1.37 +    asic_check_cleared_events();
    1.38 +}
    1.39 +
    1.40  void asic_check_cleared_events( )
    1.41  {
    1.42      int i, setA = 0, setB = 0, setC = 0;
    1.43 @@ -164,46 +173,55 @@
    1.44  
    1.45  MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
    1.46  {
    1.47 +    WARN( "EXTDMA write %08X <= %08X", reg, val );
    1.48 +
    1.49      switch( reg ) {
    1.50 -        case IDEALTSTATUS: /* Device control */
    1.51 -            ide_write_control( val );
    1.52 -            break;
    1.53 -        case IDEDATA:
    1.54 -            ide_write_data_pio( val );
    1.55 -            break;
    1.56 -        case IDEFEAT:
    1.57 -            if( ide_can_write_regs() )
    1.58 -                idereg.feature = (uint8_t)val;
    1.59 -            break;
    1.60 -        case IDECOUNT:
    1.61 -            if( ide_can_write_regs() )
    1.62 -                idereg.count = (uint8_t)val;
    1.63 -            break;
    1.64 -        case IDELBA0:
    1.65 -            if( ide_can_write_regs() )
    1.66 -                idereg.lba0 = (uint8_t)val;
    1.67 -            break;
    1.68 -        case IDELBA1:
    1.69 -            if( ide_can_write_regs() )
    1.70 -                idereg.lba1 = (uint8_t)val;
    1.71 -            break;
    1.72 -        case IDELBA2:
    1.73 -            if( ide_can_write_regs() )
    1.74 -                idereg.lba2 = (uint8_t)val;
    1.75 -            break;
    1.76 -        case IDEDEV:
    1.77 -            if( ide_can_write_regs() )
    1.78 -                idereg.device = (uint8_t)val;
    1.79 -            break;
    1.80 -        case IDECMD:
    1.81 -            if( ide_can_write_regs() ) {
    1.82 -                ide_clear_interrupt();
    1.83 -                ide_write_command( (uint8_t)val );
    1.84 -            }
    1.85 -            break;
    1.86 -        default:
    1.87 -	    WARN( "EXTDMA write %08X <= %08X", reg, val );
    1.88 -
    1.89 +    case IDEALTSTATUS: /* Device control */
    1.90 +	ide_write_control( val );
    1.91 +	break;
    1.92 +    case IDEDATA:
    1.93 +	ide_write_data_pio( val );
    1.94 +	break;
    1.95 +    case IDEFEAT:
    1.96 +	if( ide_can_write_regs() )
    1.97 +	    idereg.feature = (uint8_t)val;
    1.98 +	break;
    1.99 +    case IDECOUNT:
   1.100 +	if( ide_can_write_regs() )
   1.101 +	    idereg.count = (uint8_t)val;
   1.102 +	break;
   1.103 +    case IDELBA0:
   1.104 +	if( ide_can_write_regs() )
   1.105 +	    idereg.lba0 = (uint8_t)val;
   1.106 +	break;
   1.107 +    case IDELBA1:
   1.108 +	if( ide_can_write_regs() )
   1.109 +	    idereg.lba1 = (uint8_t)val;
   1.110 +	break;
   1.111 +    case IDELBA2:
   1.112 +	if( ide_can_write_regs() )
   1.113 +	    idereg.lba2 = (uint8_t)val;
   1.114 +	break;
   1.115 +    case IDEDEV:
   1.116 +	if( ide_can_write_regs() )
   1.117 +	    idereg.device = (uint8_t)val;
   1.118 +	break;
   1.119 +    case IDECMD:
   1.120 +	if( ide_can_write_regs() ) {
   1.121 +	    ide_write_command( (uint8_t)val );
   1.122 +	}
   1.123 +	break;
   1.124 +    case IDEDMACTL1:
   1.125 +    case IDEDMACTL2:
   1.126 +	MMIO_WRITE( EXTDMA, reg, val );
   1.127 +	if( MMIO_READ( EXTDMA, IDEDMACTL1 ) == 1 &&
   1.128 +	    MMIO_READ( EXTDMA, IDEDMACTL2 ) == 1 ) {
   1.129 +	    uint32_t target_addr = MMIO_READ( EXTDMA, IDEDMASH4 );
   1.130 +	    uint32_t length = MMIO_READ( EXTDMA, IDEDMASIZ );
   1.131 +	    int dir = MMIO_READ( EXTDMA, IDEDMADIR );
   1.132 +	}
   1.133 +	break;
   1.134 +    default:
   1.135              MMIO_WRITE( EXTDMA, reg, val );
   1.136      }
   1.137  }
   1.138 @@ -221,8 +239,7 @@
   1.139          case IDELBA2: return idereg.lba2;
   1.140          case IDEDEV: return idereg.device;
   1.141          case IDECMD:
   1.142 -            ide_clear_interrupt();
   1.143 -            return idereg.status;
   1.144 +	    return ide_read_status();
   1.145          default:
   1.146  	    val = MMIO_READ( EXTDMA, reg );
   1.147  	    //DEBUG( "EXTDMA read %08X => %08X", reg, val );