1.1 --- a/src/sh4/sh4x86.in Tue Jan 22 11:30:37 2008 +0000
1.2 +++ b/src/sh4/sh4x86.in Fri Feb 08 11:30:04 2008 +0000
1.3 @@ -2487,13 +2487,15 @@
1.4 store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
1.5 sh4_x86.tstate = TSTATE_NONE;
1.10 load_reg( R_EAX, Rm );
1.11 store_spreg( R_EAX, R_FPSCR );
1.12 update_fr_bank( R_EAX );
1.13 sh4_x86.tstate = TSTATE_NONE;
1.15 LDS.L @Rm+, FPSCR {:
1.17 load_reg( R_EAX, Rm );
1.18 check_ralign32( R_EAX );
1.19 MMU_TRANSLATE_READ( R_EAX );
1.20 @@ -2504,10 +2506,12 @@
1.21 sh4_x86.tstate = TSTATE_NONE;
1.25 load_reg( R_EAX, Rm );
1.26 store_spreg( R_EAX, R_FPUL );
1.30 load_reg( R_EAX, Rm );
1.31 check_ralign32( R_EAX );
1.32 MMU_TRANSLATE_READ( R_EAX );
1.33 @@ -2716,10 +2720,12 @@
1.34 sh4_x86.tstate = TSTATE_NONE;
1.38 load_spreg( R_EAX, R_FPSCR );
1.39 store_reg( R_EAX, Rn );
1.41 STS.L FPSCR, @-Rn {:
1.43 load_reg( R_EAX, Rn );
1.44 check_walign32( R_EAX );
1.45 ADD_imm8s_r32( -4, R_EAX );
1.46 @@ -2730,10 +2736,12 @@
1.47 sh4_x86.tstate = TSTATE_NONE;
1.51 load_spreg( R_EAX, R_FPUL );
1.52 store_reg( R_EAX, Rn );
1.56 load_reg( R_EAX, Rn );
1.57 check_walign32( R_EAX );
1.58 ADD_imm8s_r32( -4, R_EAX );