1.1 --- a/src/sh4/sh4dasm.c	Thu Aug 23 12:33:27 2007 +0000
     1.2 +++ b/src/sh4/sh4dasm.c	Wed Nov 07 11:45:53 2007 +0000
     1.3 @@ -1,5 +1,5 @@
     1.4  /**
     1.5 - * $Id: sh4dasm.c,v 1.11 2007-08-23 12:33:27 nkeynes Exp $
     1.6 + * $Id: sh4dasm.c,v 1.12 2007-10-08 12:06:01 nkeynes Exp $
     1.7   * 
     1.8   * SH4 CPU definition and disassembly functions
     1.9   *
    1.10 @@ -1146,7 +1146,7 @@
    1.11                      case 0x1:
    1.12                          { /* MOV.W R0, @(disp, Rn) */
    1.13                          uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
    1.14 -                        snprintf( buf, len, "MOV.W   R0, @(%d, Rn)", disp, Rn );
    1.15 +                        snprintf( buf, len, "MOV.W   R0, @(%d, R%d)", disp, Rn );
    1.16                          }
    1.17                          break;
    1.18                      case 0x4:
    1.19 @@ -1337,13 +1337,13 @@
    1.20                      case 0x1:
    1.21                          { /* FSUB FRm, FRn */
    1.22                          uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
    1.23 -                        snprintf( buf, len, "FSUB    FRm, FR%d", FRm, FRn );
    1.24 +                        snprintf( buf, len, "FSUB    FR%d, FR%d", FRm, FRn );
    1.25                          }
    1.26                          break;
    1.27                      case 0x2:
    1.28                          { /* FMUL FRm, FRn */
    1.29                          uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
    1.30 -                        snprintf( buf, len, "FMUL    FRm, FR%d", FRm, FRn );
    1.31 +                        snprintf( buf, len, "FMUL    FR%d, FR%d", FRm, FRn );
    1.32                          }
    1.33                          break;
    1.34                      case 0x3: