1.1 --- a/src/asic.c Tue Jan 15 20:50:23 2008 +0000
1.2 +++ b/src/asic.c Tue Jan 22 09:45:21 2008 +0000
1.5 int i, setA = 0, setB = 0, setC = 0;
1.7 - for( i=0; i<3; i++ ) {
1.8 + for( i=0; i<12; i+=4 ) {
1.9 bits = MMIO_READ( ASIC, PIRQ0 + i );
1.10 setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));
1.11 setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));
1.12 @@ -261,6 +261,30 @@
1.13 intc_clear_interrupt( INT_IRQ9 );
1.16 +void asic_event_mask_changed( )
1.18 + int i, setA = 0, setB = 0, setC = 0;
1.20 + for( i=0; i<12; i+=4 ) {
1.21 + bits = MMIO_READ( ASIC, PIRQ0 + i );
1.22 + setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));
1.23 + setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));
1.24 + setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));
1.27 + intc_clear_interrupt( INT_IRQ13 );
1.29 + intc_raise_interrupt( INT_IRQ13 );
1.31 + intc_clear_interrupt( INT_IRQ11 );
1.33 + intc_raise_interrupt( INT_IRQ11 );
1.35 + intc_clear_interrupt( INT_IRQ9 );
1.37 + intc_raise_interrupt( INT_IRQ9 );
1.40 void g2_dma_transfer( int channel )
1.42 uint32_t offset = channel << 5;
1.43 @@ -345,6 +369,18 @@
1.45 asic_check_cleared_events();
1.56 + MMIO_WRITE( ASIC, reg, val );
1.57 + asic_event_mask_changed();
1.60 if( val == 0x7611 ) {