filename | test/interrupt.s |
changeset | 233:f8333b94f503 |
prev | 228:70adc8ffa8d1 |
next | 815:866c103d72cd |
author | nkeynes |
date | Sat Jun 14 11:57:11 2008 +0000 (15 years ago) |
permissions | -rw-r--r-- |
last change | And the updated configure from the previous commit |
file | annotate | diff | log | raw |
1.1 --- a/test/interrupt.s Mon Sep 25 11:13:56 2006 +00001.2 +++ b/test/interrupt.s Sat Jun 14 11:57:11 2008 +00001.3 @@ -177,6 +177,26 @@1.4 nop1.6 ex_dontcare: ! Not the event we were waiting for.1.7 +! Check if its a trapa #42 ("Switch to system mode")1.8 + mov.l trapa_exc_k, r01.9 + cmp/eq r0,r11.10 + bf ex_chain1.11 + mov.l trapa_k, r01.12 + mov.l @r0, r01.13 + shlr2 r01.14 + cmp/eq #42, r01.15 + bf ex_chain1.16 +! Yes, yes it is - update SSR and return without chaining1.17 + stc ssr, r01.18 + mov #0x40, r11.19 + mov #24, r21.20 + shld r2, r11.21 + or r0, r11.22 + ldc r1, ssr1.23 + bra ex_nochain1.24 + nop1.25 +1.26 +ex_chain:1.27 mov.l old_vbr_k, r21.28 mov.l @r2, r21.29 xor r0, r01.30 @@ -213,9 +233,9 @@1.31 mov.l @r15+, r21.32 mov.l @r15+, r11.33 mov.l @r15+, r01.34 + stc sgr, r151.35 rte1.36 - stc sgr, r151.37 -1.38 + nop1.39 .align 41.40 expected_intevt_k:1.41 .long expected_intevt
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