filename | src/aica/armcore.c |
changeset | 86:f151e63f9754 |
prev | 81:1c1d53584da4 |
next | 431:248dd77a9e44 |
author | nkeynes |
date | Wed Jan 03 09:00:17 2007 +0000 (17 years ago) |
permissions | -rw-r--r-- |
last change | Adjust timers when they're read rather than waiting until the next time slice. Also temporarily cut the CPU time by 4. Initialize the FRQCR register to 0x0E0A for convenience |
file | annotate | diff | log | raw |
1.1 --- a/src/aica/armcore.c Tue Jan 17 12:53:39 2006 +00001.2 +++ b/src/aica/armcore.c Wed Jan 03 09:00:17 2007 +00001.3 @@ -1,5 +1,5 @@1.4 /**1.5 - * $Id: armcore.c,v 1.19 2006-01-17 12:53:39 nkeynes Exp $1.6 + * $Id: armcore.c,v 1.20 2006-01-22 22:40:05 nkeynes Exp $1.7 *1.8 * ARM7TDMI CPU emulation core.1.9 *1.10 @@ -90,6 +90,10 @@1.11 uint32_t arm_run_slice( uint32_t num_samples )1.12 {1.13 int i,j,k;1.14 +1.15 + if( !armr.running )1.16 + return num_samples;1.17 +1.18 for( i=0; i<num_samples; i++ ) {1.19 for( j=0; j < CYCLES_PER_SAMPLE; j++ ) {1.20 armr.icount++;1.21 @@ -143,6 +147,7 @@1.23 armr.cpsr = MODE_SVC | CPSR_I | CPSR_F;1.24 armr.r[15] = 0x00000000;1.25 + armr.running = TRUE;1.26 }1.28 #define SET_CPSR_CONTROL 0x000100001.29 @@ -757,8 +762,7 @@1.30 cond = 0;1.31 UNDEF(ir);1.32 }1.33 - if( !cond )1.34 - return TRUE;1.35 + if( cond ) {1.37 /**1.38 * Condition passed, now for the actual instructions...1.39 @@ -1369,9 +1373,12 @@1.40 }1.41 break;1.42 }1.43 - if( armr.r[15] > 0x00200000 ) {1.44 - dreamcast_stop();1.45 - ERROR( "BRANCH to fishkill at %08X", pc );1.46 +1.47 + }1.48 +1.49 + if( armr.r[15] >= 0x00200000 ) {1.50 + armr.running = FALSE;1.51 + ERROR( "ARM Halted: BRANCH to invalid address %08X at %08X", armr.r[15], pc );1.52 return FALSE;1.53 }1.54 return TRUE;
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