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tree revision 936:f394309c399a lxdream-mem
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filename test/testta4.data
changeset 211:4c7ec3e3eb8a
prev193:31151fcc3cb7
author nkeynes
date Sat Dec 27 02:59:35 2008 +0000 (15 years ago)
branchlxdream-mem
permissions -rw-r--r--
last change Replace fpscr_mask/fpscr flags in xlat_cache_block with a single xlat_sh4_mode,
which tracks the field of the same name in sh4r - actually a little faster this way.
Now depends on SR.MD, FPSCR.PR and FPSCR.SZ (although it doesn't benefit from the SR
flag yet).

Also fixed the failure to check the flags in the common case (code address returned
by previous block) which took away the performance benefits, but oh well.
file annotate diff log raw 
     1.1 --- a/test/testta4.data	Fri Aug 04 01:38:30 2006 +0000

     1.2 +++ b/test/testta4.data	Sat Dec 27 02:59:35 2008 +0000

     1.3 @@ -2309,3 +2309,78 @@

     1.4  0.5      31.6     0.7      F8878787

     1.5  31.5     31.6     0.7      F0565656

     1.6  tile 3 =

     1.7 +[4.17 Test high memory (polygon buf)]

     1.8 +config = 00100001 000E0013 007F0000 00000000 00070000 00060000 00070000

     1.9 +input =

    1.10 +80800002 E0000000 2083242D 00000000 00000000 00000000 00000000 00000000

    1.11 +E0000000 0.0      0.1      0.2      00000000 00000000 FF00FF00 FE010203

    1.12 +E0000000 31.2     0.3      0.4      00000000 00000000 FF0000FF FD040506

    1.13 +F0000000 31.8     31.9     0.9      00000000 00000000 FFFFFFFF FB0A0B0C

    1.14 +00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000

    1.15 +output =

    1.16 +E0A00000 2083242D 00000000

    1.17 +0.0      0.1      0.2      FF00FF00

    1.18 +31.2     0.3      0.4      FF0000FF

    1.19 +31.8     31.9     0.9      FFFFFFFF

    1.20 +tile 1 =

    1.21 +8023C000

    1.22 +[4.18 Test MB boundary spill]

    1.23 +config = 00100001 000E0013 006FFFFC 00000000 00070000 00060000 00070000

    1.24 +input =

    1.25 +80800002 E0000000 2083242D 00000000 00000000 00000000 00000000 00000000

    1.26 +E0000000 0.0      0.1      0.2      00000000 00000000 FF00FF00 FE010203

    1.27 +E0000000 31.2     0.3      0.4      00000000 00000000 FF0000FF FD040506

    1.28 +F0000000 31.8     31.9     0.9      00000000 00000000 FFFFFFFF FB0A0B0C

    1.29 +80840002 E0000000 2083242D 00000000 00000000 00000000 00000000 00000000

    1.30 +E0000000 0.0      0.1      0.2      00000000 00000000 FF00FF00 FE010203

    1.31 +E0000000 31.2     0.3      0.4      00000000 00000000 FF0000FF FD040506

    1.32 +E0000000 15.2     15.3     0.4      00000000 00000000 FF0000FF FD040506

    1.33 +F0000000 31.8     31.9     0.9      00000000 00000000 FFFFFFFF FB0A0B0C

    1.34 +00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000

    1.35 +output =

    1.36 +E0A00000 2083242D 00000000

    1.37 +0.0      0.1      0.2      FF00FF00

    1.38 +31.2     0.3      0.4      FF0000FF

    1.39 +31.8     31.9     0.9      FFFFFFFF

    1.40 +E0A00000 2083242D 00000000

    1.41 +0.0      0.1      0.2      FF00FF00

    1.42 +31.2     0.3      0.4      FF0000FF

    1.43 +15.2     15.3     0.4      FF0000FF

    1.44 +31.8     31.9     0.9      FFFFFFFF

    1.45 +tile 1 =

    1.46 +8023FFFF 6024000E

    1.47 +[4.19 Test Wrap-around boundary spill]

    1.48 +config = 00100001 000E0013 007FFFF8 00100000 00070000 00060000 00070000

    1.49 +input =

    1.50 +80800002 E0000000 2083242D 00000000 00000000 00000000 00000000 00000000

    1.51 +E0000000 0.0      0.1      0.2      00000000 00000000 FF00FF00 FE010203

    1.52 +E0000000 31.2     0.3      0.4      00000000 00000000 FF0000FF FD040506

    1.53 +F0000000 31.8     31.9     0.9      00000000 00000000 FFFFFFFF FB0A0B0C

    1.54 +80840002 E0000000 2083242D 00000000 00000000 00000000 00000000 00000000

    1.55 +E0000000 0.0      0.1      0.2      00000000 00000000 FF00FF00 FE010203

    1.56 +E0000000 31.2     0.3      0.4      00000000 00000000 FF0000FF FD040506

    1.57 +E0000000 15.2     15.3     0.4      00000000 00000000 FF0000FF FD040506

    1.58 +F0000000 31.8     31.9     0.9      00000000 00000000 FFFFFFFF FB0A0B0C

    1.59 +80840002 E0000000 2083242D 00000000 00000000 00000000 00000000 00000000

    1.60 +E0000000 0.0      0.1      0.2      00000000 00000000 FF00FF00 FE010203

    1.61 +E0000000 31.2     0.3      0.4      00000000 00000000 FF0000FF FD040506

    1.62 +E0000000 15.2     15.3     0.4      00000000 00000000 FF0000FF FD040506

    1.63 +F0000000 31.8     31.9     0.9      00000000 00000000 FFFFFFFF FB0A0B0C

    1.64 +00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000

    1.65 +output =

    1.66 +E0A00000 2083242D FEFEFEFE

    1.67 +FEFEFEFE FEFEFEFE FEFEFEFE FEFEFEFE

    1.68 +FEFEFEFE FEFEFEFE FEFEFEFE FEFEFEFE

    1.69 +FEFEFEFE FEFEFEFE FEFEFEFE FEFEFEFE

    1.70 +FEFEFEFE FEFEFEFE FEFEFEFE FEFEFEFE

    1.71 +FEFEFEFE FEFEFEFE FEFEFEFE FEFEFEFE

    1.72 +FEFEFEFE FEFEFEFE FEFEFEFE FEFEFEFE

    1.73 +FEFEFEFE FEFEFEFE FEFEFEFE FEFEFEFE

    1.74 +FEFEFEFE FEFEFEFE FEFEFEFE FEFEFEFE

    1.75 +FEFEFEFE FEFEFEFE FEFEFEFE FEFEFEFE

    1.76 +FEFEFEFE FEFEFEFE FEFEFEFE FEFEFEFE

    1.77 +FEFEFEFE FEFEFEFE FEFEFEFE FEFEFEFE

    1.78 +FEFEFEFE FEFEFEFE FEFEFEFE FEFEFEFE

    1.79 +FEFEFEFE FEFEFEFE 

    1.80 +tile 1 =

    1.81 +8023FFFE 6024000D 60240020
.