lxdream 0.9.1| filename | src/pvr2/pvr2.c |
| changeset | 1076:18c164e8aec4 |
| prev | 1067:d3c00ffccfcd |
| next | 1080:5b17c9900d9e |
| author | nkeynes |
| date | Mon Aug 03 08:41:11 2009 +1000 (14 years ago) |
| permissions | -rw-r--r-- |
| last change | Rearrange frame output slightly. pvr2_display_frame renamed to pvr2_next_frame and changed to update the frame data without displaying it. pvr2_redraw_display renamed to pvr2_draw_frame, called internally after pvr2_next_frame Add swap_buffers() method to the display driver Remove explicit glDrawBuffer() calls where they're referencing the window. pvr2_draw_frame now gets to decide where to draw. Add force_vsync flag to force double-buffering (not configurable yet) |
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1 /**
2 * $Id$
3 *
4 * PVR2 (Video) Core module implementation and MMIO registers.
5 *
6 * Copyright (c) 2005 Nathan Keynes.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18 #define MODULE pvr2_module
20 #include <assert.h>
21 #include "dream.h"
22 #include "eventq.h"
23 #include "display.h"
24 #include "mem.h"
25 #include "asic.h"
26 #include "clock.h"
27 #include "pvr2/pvr2.h"
28 #include "pvr2/pvr2mmio.h"
29 #include "pvr2/scene.h"
30 #include "sh4/sh4.h"
31 #define MMIO_IMPL
32 #include "pvr2/pvr2mmio.h"
34 #define MAX_RENDER_BUFFERS 4
36 #define HPOS_PER_FRAME 0
37 #define HPOS_PER_LINECOUNT 1
39 static void pvr2_init( void );
40 static void pvr2_reset( void );
41 static uint32_t pvr2_run_slice( uint32_t );
42 static void pvr2_save_state( FILE *f );
43 static int pvr2_load_state( FILE *f );
44 static void pvr2_update_raster_posn( uint32_t nanosecs );
45 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int line_time_ns );
46 static render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame );
47 static render_buffer_t pvr2_next_render_buffer( );
48 static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame );
49 uint32_t pvr2_get_sync_status();
50 static gboolean force_vsync = FALSE;
51 static int output_colour_formats[] = { COLFMT_BGRA1555, COLFMT_RGB565, COLFMT_BGR888, COLFMT_BGRA8888 };
52 static int render_colour_formats[8] = {
53 COLFMT_BGRA1555, COLFMT_RGB565, COLFMT_BGRA4444, COLFMT_BGRA1555,
54 COLFMT_BGR888, COLFMT_BGRA8888, COLFMT_BGRA8888, COLFMT_BGRA4444 };
57 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL,
58 pvr2_run_slice, NULL,
59 pvr2_save_state, pvr2_load_state };
62 display_driver_t display_driver = NULL;
64 struct pvr2_state {
65 uint32_t frame_count;
66 uint32_t line_count;
67 uint32_t line_remainder;
68 uint32_t cycles_run; /* Cycles already executed prior to main time slice */
69 uint32_t irq_hpos_line;
70 uint32_t irq_hpos_line_count;
71 uint32_t irq_hpos_mode;
72 uint32_t irq_hpos_time_ns; /* Time within the line */
73 uint32_t irq_vpos1;
74 uint32_t irq_vpos2;
75 uint32_t odd_even_field; /* 1 = odd, 0 = even */
76 int32_t palette_changed; /* TRUE if palette has changed since last render */
77 /* timing */
78 uint32_t dot_clock;
79 uint32_t total_lines;
80 uint32_t line_size;
81 uint32_t line_time_ns;
82 uint32_t vsync_lines;
83 uint32_t hsync_width_ns;
84 uint32_t front_porch_ns;
85 uint32_t back_porch_ns;
86 uint32_t retrace_start_line;
87 uint32_t retrace_end_line;
88 int32_t interlaced;
89 } pvr2_state;
91 static gchar *save_next_render_filename;
92 static render_buffer_t render_buffers[MAX_RENDER_BUFFERS];
93 static uint32_t render_buffer_count = 0;
94 static render_buffer_t displayed_render_buffer = NULL;
95 static uint32_t displayed_border_colour = 0;
97 /**
98 * Event handler for the hpos callback
99 */
100 static void pvr2_hpos_callback( int eventid ) {
101 asic_event( eventid );
102 pvr2_update_raster_posn(sh4r.slice_cycle);
103 if( pvr2_state.irq_hpos_mode == HPOS_PER_LINECOUNT ) {
104 pvr2_state.irq_hpos_line += pvr2_state.irq_hpos_line_count;
105 while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
106 pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
107 }
108 }
109 pvr2_schedule_scanline_event( eventid, pvr2_state.irq_hpos_line, 1,
110 pvr2_state.irq_hpos_time_ns );
111 }
113 /**
114 * Event handler for the scanline callbacks. Fires the corresponding
115 * ASIC event, and resets the timer for the next field.
116 */
117 static void pvr2_scanline_callback( int eventid )
118 {
119 asic_event( eventid );
120 pvr2_update_raster_posn(sh4r.slice_cycle);
121 if( eventid == EVENT_SCANLINE1 ) {
122 pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos1, 1, 0 );
123 } else {
124 pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos2, 1, 0 );
125 }
126 }
128 static void pvr2_gunpos_callback( int eventid )
129 {
130 pvr2_update_raster_posn(sh4r.slice_cycle);
131 int hpos = pvr2_state.line_remainder * pvr2_state.dot_clock / 1000000;
132 MMIO_WRITE( PVR2, GUNPOS, ((pvr2_state.line_count<<16)|(hpos&0x3FF)) );
133 asic_event( EVENT_MAPLE_DMA );
134 }
136 static void pvr2_init( void )
137 {
138 int i;
139 register_io_region( &mmio_region_PVR2 );
140 register_io_region( &mmio_region_PVR2PAL );
141 register_event_callback( EVENT_HPOS, pvr2_hpos_callback );
142 register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback );
143 register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback );
144 register_event_callback( EVENT_GUNPOS, pvr2_gunpos_callback );
145 texcache_init();
146 pvr2_reset();
147 pvr2_ta_reset();
148 save_next_render_filename = NULL;
149 for( i=0; i<MAX_RENDER_BUFFERS; i++ ) {
150 render_buffers[i] = NULL;
151 }
152 render_buffer_count = 0;
153 displayed_render_buffer = NULL;
154 displayed_border_colour = 0;
155 }
157 static void pvr2_reset( void )
158 {
159 int i;
160 pvr2_state.line_count = 0;
161 pvr2_state.line_remainder = 0;
162 pvr2_state.cycles_run = 0;
163 pvr2_state.irq_vpos1 = 0;
164 pvr2_state.irq_vpos2 = 0;
165 pvr2_state.dot_clock = PVR2_DOT_CLOCK;
166 pvr2_state.back_porch_ns = 4000;
167 pvr2_state.palette_changed = FALSE;
168 mmio_region_PVR2_write( DISP_TOTAL, 0x0270035F );
169 mmio_region_PVR2_write( DISP_SYNCTIME, 0x07D6A53F );
170 mmio_region_PVR2_write( YUV_ADDR, 0 );
171 mmio_region_PVR2_write( YUV_CFG, 0 );
173 pvr2_ta_init();
174 texcache_flush();
175 if( display_driver ) {
176 display_driver->display_blank(0);
177 for( i=0; i<render_buffer_count; i++ ) {
178 display_driver->destroy_render_buffer(render_buffers[i]);
179 render_buffers[i] = NULL;
180 }
181 render_buffer_count = 0;
182 }
183 }
185 void pvr2_save_render_buffer( FILE *f, render_buffer_t buffer )
186 {
187 struct frame_buffer fbuf;
189 fbuf.width = buffer->width;
190 fbuf.height = buffer->height;
191 fbuf.rowstride = fbuf.width*3;
192 fbuf.colour_format = COLFMT_BGR888;
193 fbuf.inverted = buffer->inverted;
194 fbuf.data = g_malloc0( buffer->width * buffer->height * 3 );
196 display_driver->read_render_buffer( fbuf.data, buffer, fbuf.rowstride, COLFMT_BGR888 );
197 write_png_to_stream( f, &fbuf );
198 g_free( fbuf.data );
200 fwrite( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );
201 fwrite( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );
202 fwrite( &buffer->address, sizeof(buffer->address), 1, f );
203 fwrite( &buffer->scale, sizeof(buffer->scale), 1, f );
204 int32_t flushed = (int32_t)buffer->flushed; // Force to 32-bits for save-file consistency
205 fwrite( &flushed, sizeof(flushed), 1, f );
207 }
209 render_buffer_t pvr2_load_render_buffer( FILE *f, gboolean *status )
210 {
211 frame_buffer_t frame = read_png_from_stream( f );
212 if( frame == NULL ) {
213 *status = FALSE;
214 return NULL;
215 }
216 *status = TRUE;
218 render_buffer_t buffer = pvr2_frame_buffer_to_render_buffer(frame);
219 if( buffer != NULL ) {
220 int32_t flushed;
221 fread( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );
222 fread( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );
223 fread( &buffer->address, sizeof(buffer->address), 1, f );
224 fread( &buffer->scale, sizeof(buffer->scale), 1, f );
225 fread( &flushed, sizeof(flushed), 1, f );
226 buffer->flushed = (gboolean)flushed;
227 } else {
228 fseek( f, sizeof(buffer->rowstride)+sizeof(buffer->colour_format)+
229 sizeof(buffer->address)+sizeof(buffer->scale)+
230 sizeof(int32_t), SEEK_CUR );
231 }
232 return buffer;
233 }
238 void pvr2_save_render_buffers( FILE *f )
239 {
240 int i;
241 uint32_t has_frontbuffer;
242 fwrite( &render_buffer_count, sizeof(render_buffer_count), 1, f );
243 if( displayed_render_buffer != NULL ) {
244 has_frontbuffer = 1;
245 fwrite( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
246 pvr2_save_render_buffer( f, displayed_render_buffer );
247 } else {
248 has_frontbuffer = 0;
249 fwrite( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
250 }
252 for( i=0; i<render_buffer_count; i++ ) {
253 if( render_buffers[i] != displayed_render_buffer && render_buffers[i] != NULL ) {
254 pvr2_save_render_buffer( f, render_buffers[i] );
255 }
256 }
257 }
259 gboolean pvr2_load_render_buffers( FILE *f )
260 {
261 uint32_t count, has_frontbuffer;
262 gboolean loadok;
263 int i;
265 fread( &count, sizeof(count), 1, f );
266 if( count > MAX_RENDER_BUFFERS ) {
267 return FALSE;
268 }
269 fread( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
270 for( i=0; i<render_buffer_count; i++ ) {
271 display_driver->destroy_render_buffer(render_buffers[i]);
272 render_buffers[i] = NULL;
273 }
274 render_buffer_count = 0;
276 if( has_frontbuffer ) {
277 displayed_render_buffer = pvr2_load_render_buffer(f, &loadok);
278 if( displayed_render_buffer != NULL )
279 display_driver->display_render_buffer( displayed_render_buffer );
280 else if( !loadok )
281 return FALSE;
282 count--;
283 }
285 for( i=0; i<count; i++ ) {
286 pvr2_load_render_buffer( f, &loadok );
287 if( !loadok )
288 return FALSE;
289 }
290 return TRUE;
291 }
294 static void pvr2_save_state( FILE *f )
295 {
296 pvr2_save_render_buffers( f );
297 fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
298 pvr2_ta_save_state( f );
299 pvr2_yuv_save_state( f );
300 }
302 static int pvr2_load_state( FILE *f )
303 {
304 if( !pvr2_load_render_buffers(f) )
305 return 1;
306 if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
307 return 1;
308 if( pvr2_ta_load_state(f) ) {
309 return 1;
310 }
311 return pvr2_yuv_load_state(f);
312 }
314 /**
315 * Update the current raster position to the given number of nanoseconds,
316 * relative to the last time slice. (ie the raster will be adjusted forward
317 * by nanosecs - nanosecs_already_run_this_timeslice)
318 */
319 static void pvr2_update_raster_posn( uint32_t nanosecs )
320 {
321 uint32_t old_line_count = pvr2_state.line_count;
322 if( pvr2_state.line_time_ns == 0 ) {
323 return; /* do nothing */
324 }
325 pvr2_state.line_remainder += (nanosecs - pvr2_state.cycles_run);
326 pvr2_state.cycles_run = nanosecs;
327 while( pvr2_state.line_remainder >= pvr2_state.line_time_ns ) {
328 pvr2_state.line_count ++;
329 pvr2_state.line_remainder -= pvr2_state.line_time_ns;
330 }
332 if( pvr2_state.line_count >= pvr2_state.total_lines ) {
333 pvr2_state.line_count -= pvr2_state.total_lines;
334 if( pvr2_state.interlaced ) {
335 pvr2_state.odd_even_field = !pvr2_state.odd_even_field;
336 }
337 }
338 if( pvr2_state.line_count >= pvr2_state.retrace_end_line &&
339 (old_line_count < pvr2_state.retrace_end_line ||
340 old_line_count > pvr2_state.line_count) ) {
341 pvr2_state.frame_count++;
342 pvr2_next_frame();
343 pvr2_draw_frame();
344 }
345 }
347 static uint32_t pvr2_run_slice( uint32_t nanosecs )
348 {
349 pvr2_update_raster_posn( nanosecs );
350 pvr2_state.cycles_run = 0;
351 return nanosecs;
352 }
354 int pvr2_get_frame_count()
355 {
356 return pvr2_state.frame_count;
357 }
359 /**
360 * Draw the base (emulated) frame only.
361 */
362 static void pvr2_draw_base_frame()
363 {
364 if( displayed_render_buffer == NULL ) {
365 display_driver->display_blank(displayed_border_colour);
366 } else {
367 display_driver->display_render_buffer(displayed_render_buffer);
368 }
369 }
371 void pvr2_draw_frame()
372 {
373 if( display_driver != NULL ) {
374 if( force_vsync ) {
375 glDrawBuffer( GL_BACK );
376 pvr2_draw_base_frame();
377 display_driver->swap_buffers();
378 } else {
379 glDrawBuffer( GL_FRONT );
380 pvr2_draw_base_frame();
381 }
382 }
383 }
385 gboolean pvr2_save_next_scene( const gchar *filename )
386 {
387 if( save_next_render_filename != NULL ) {
388 g_free( save_next_render_filename );
389 }
390 save_next_render_filename = g_strdup(filename);
391 return TRUE;
392 }
396 /**
397 * Advance to the next frame, copying the current contents of video ram to
398 * the window. If the video configuration has changed, first recompute the
399 * new frame size/depth.
400 */
401 void pvr2_next_frame( void )
402 {
403 int dispmode = MMIO_READ( PVR2, DISP_MODE );
404 int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG );
405 gboolean bEnabled = (dispmode & DISPMODE_ENABLE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
407 if( !bEnabled ) {
408 /* Output disabled == black */
409 displayed_render_buffer = NULL;
410 displayed_border_colour = 0;
411 } else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) {
412 /* Enabled but blanked - border colour */
413 displayed_border_colour = MMIO_READ( PVR2, DISP_BORDER );
414 displayed_render_buffer = NULL;
415 } else {
416 /* Real output - determine dimensions etc */
417 struct frame_buffer fbuf;
418 uint32_t dispsize = MMIO_READ( PVR2, DISP_SIZE );
419 int vid_stride = (((dispsize & DISPSIZE_MODULO) >> 20) - 1);
420 int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
422 fbuf.colour_format = output_colour_formats[(dispmode & DISPMODE_COLFMT) >> 2];
423 fbuf.width = (vid_ppl << 2) / colour_formats[fbuf.colour_format].bpp;
424 fbuf.height = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
425 fbuf.size = (vid_ppl << 2) * fbuf.height;
426 fbuf.rowstride = (vid_ppl + vid_stride) << 2;
428 /* Determine the field to display, and deinterlace if possible */
429 if( pvr2_state.interlaced ) {
430 if( vid_ppl == vid_stride ) { /* Magic deinterlace */
431 fbuf.height = fbuf.height << 1;
432 fbuf.rowstride = vid_ppl << 2;
433 fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
434 } else {
435 /* Just display the field as is, folks. This is slightly tricky -
436 * we pick the field based on which frame is about to come through,
437 * which may not be the same as the odd_even_field.
438 */
439 gboolean oddfield = pvr2_state.odd_even_field;
440 if( pvr2_state.line_count >= pvr2_state.retrace_start_line ) {
441 oddfield = !oddfield;
442 }
443 if( oddfield ) {
444 fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
445 } else {
446 fbuf.address = MMIO_READ( PVR2, DISP_ADDR2 );
447 }
448 }
449 } else {
450 fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
451 }
452 fbuf.address = (fbuf.address & 0x00FFFFFF) + PVR2_RAM_BASE;
453 fbuf.inverted = FALSE;
454 fbuf.data = pvr2_main_ram + (fbuf.address&0x00FFFFFF);
456 render_buffer_t rbuf = pvr2_get_render_buffer( &fbuf );
457 if( rbuf == NULL ) {
458 rbuf = pvr2_frame_buffer_to_render_buffer( &fbuf );
459 }
460 displayed_render_buffer = rbuf;
461 }
462 }
464 /**
465 * This has to handle every single register individually as they all get masked
466 * off differently (and its easier to do it at write time)
467 */
468 MMIO_REGION_WRITE_FN( PVR2, reg, val )
469 {
470 reg &= 0xFFF;
471 if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
472 MMIO_WRITE( PVR2, reg, val );
473 return;
474 }
476 switch(reg) {
477 case PVRID:
478 case PVRVER:
479 case GUNPOS: /* Read only registers */
480 break;
481 case PVRRESET:
482 val &= 0x00000007; /* Do stuff? */
483 MMIO_WRITE( PVR2, reg, val );
484 break;
485 case RENDER_START: /* Don't really care what value */
486 if( save_next_render_filename != NULL ) {
487 if( pvr2_render_save_scene(save_next_render_filename) == 0 ) {
488 INFO( "Saved scene to %s", save_next_render_filename);
489 }
490 g_free( save_next_render_filename );
491 save_next_render_filename = NULL;
492 }
493 pvr2_scene_read();
494 render_buffer_t buffer = pvr2_next_render_buffer();
495 if( buffer != NULL ) {
496 pvr2_scene_render( buffer );
497 if( buffer->address < PVR2_RAM_BASE ) {
498 // Flush immediately - optimize this later. Otherwise this gets
499 // complicated very quickly trying to second-guess how it's
500 // going to be used as a texture.
501 pvr2_finish_render_buffer( buffer );
502 pvr2_render_buffer_copy_to_sh4( buffer );
503 }
504 }
505 asic_event( EVENT_PVR_RENDER_DONE );
506 break;
507 case RENDER_POLYBASE:
508 MMIO_WRITE( PVR2, reg, val&0x00F00000 );
509 break;
510 case RENDER_TSPCFG:
511 MMIO_WRITE( PVR2, reg, val&0x00010101 );
512 break;
513 case DISP_BORDER:
514 MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
515 break;
516 case DISP_MODE:
517 MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
518 break;
519 case RENDER_MODE:
520 MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
521 break;
522 case RENDER_SIZE:
523 MMIO_WRITE( PVR2, reg, val&0x000001FF );
524 break;
525 case DISP_ADDR1:
526 val &= 0x00FFFFFC;
527 MMIO_WRITE( PVR2, reg, val );
528 pvr2_update_raster_posn(sh4r.slice_cycle);
529 break;
530 case DISP_ADDR2:
531 MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
532 pvr2_update_raster_posn(sh4r.slice_cycle);
533 break;
534 case DISP_SIZE:
535 MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
536 break;
537 case RENDER_ADDR1:
538 case RENDER_ADDR2:
539 MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
540 break;
541 case RENDER_HCLIP:
542 MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
543 break;
544 case RENDER_VCLIP:
545 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
546 break;
547 case DISP_HPOSIRQ:
548 MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
549 pvr2_state.irq_hpos_line = val & 0x03FF;
550 pvr2_state.irq_hpos_time_ns = 2000000*((val>>16)&0x03FF)/pvr2_state.dot_clock;
551 pvr2_state.irq_hpos_mode = (val >> 12) & 0x03;
552 switch( pvr2_state.irq_hpos_mode ) {
553 case 3: /* Reserved - treat as 0 */
554 case 0: /* Once per frame at specified line */
555 pvr2_state.irq_hpos_mode = HPOS_PER_FRAME;
556 break;
557 case 2: /* Once per line - as per-line-count */
558 pvr2_state.irq_hpos_line = 1;
559 pvr2_state.irq_hpos_mode = 1;
560 case 1: /* Once per N lines */
561 pvr2_state.irq_hpos_line_count = pvr2_state.irq_hpos_line;
562 pvr2_state.irq_hpos_line = (pvr2_state.line_count >> 1) +
563 pvr2_state.irq_hpos_line_count;
564 while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
565 pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
566 }
567 pvr2_state.irq_hpos_mode = HPOS_PER_LINECOUNT;
568 }
569 pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,
570 pvr2_state.irq_hpos_time_ns );
571 break;
572 case DISP_VPOSIRQ:
573 val = val & 0x03FF03FF;
574 pvr2_state.irq_vpos1 = (val >> 16);
575 pvr2_state.irq_vpos2 = val & 0x03FF;
576 pvr2_update_raster_posn(sh4r.slice_cycle);
577 pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
578 pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
579 MMIO_WRITE( PVR2, reg, val );
580 break;
581 case RENDER_NEARCLIP:
582 MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );
583 break;
584 case RENDER_SHADOW:
585 MMIO_WRITE( PVR2, reg, val&0x000001FF );
586 break;
587 case RENDER_OBJCFG:
588 MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
589 break;
590 case RENDER_TSPCLIP:
591 MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
592 break;
593 case RENDER_FARCLIP:
594 MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );
595 break;
596 case RENDER_BGPLANE:
597 MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
598 break;
599 case RENDER_ISPCFG:
600 MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
601 break;
602 case VRAM_CFG1:
603 MMIO_WRITE( PVR2, reg, val&0x000000FF );
604 break;
605 case VRAM_CFG2:
606 MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
607 break;
608 case VRAM_CFG3:
609 MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
610 break;
611 case RENDER_FOGTBLCOL:
612 case RENDER_FOGVRTCOL:
613 MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );
614 break;
615 case RENDER_FOGCOEFF:
616 MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
617 break;
618 case RENDER_CLAMPHI:
619 case RENDER_CLAMPLO:
620 MMIO_WRITE( PVR2, reg, val );
621 break;
622 case RENDER_TEXSIZE:
623 MMIO_WRITE( PVR2, reg, val&0x00031F1F );
624 break;
625 case RENDER_PALETTE:
626 MMIO_WRITE( PVR2, reg, val&0x00000003 );
627 break;
628 case RENDER_ALPHA_REF:
629 MMIO_WRITE( PVR2, reg, val&0x000000FF );
630 break;
631 /********** CRTC registers *************/
632 case DISP_HBORDER:
633 case DISP_VBORDER:
634 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
635 break;
636 case DISP_TOTAL:
637 val = val & 0x03FF03FF;
638 MMIO_WRITE( PVR2, reg, val );
639 pvr2_update_raster_posn(sh4r.slice_cycle);
640 pvr2_state.total_lines = (val >> 16) + 1;
641 pvr2_state.line_size = (val & 0x03FF) + 1;
642 pvr2_state.line_time_ns = 1000000 * pvr2_state.line_size / pvr2_state.dot_clock;
643 pvr2_state.retrace_end_line = 0x2A;
644 pvr2_state.retrace_start_line = pvr2_state.total_lines - 6;
645 pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
646 pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
647 pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,
648 pvr2_state.irq_hpos_time_ns );
649 break;
650 case DISP_SYNCCFG:
651 MMIO_WRITE( PVR2, reg, val&0x000003FF );
652 pvr2_state.interlaced = (val & 0x0010) ? TRUE : FALSE;
653 break;
654 case DISP_SYNCTIME:
655 pvr2_state.vsync_lines = (val >> 8) & 0x0F;
656 pvr2_state.hsync_width_ns = ((val & 0x7F) + 1) * 2000000 / pvr2_state.dot_clock;
657 MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );
658 break;
659 case DISP_CFG2:
660 MMIO_WRITE( PVR2, reg, val&0x003F01FF );
661 break;
662 case DISP_HPOS:
663 val = val & 0x03FF;
664 pvr2_state.front_porch_ns = (val + 1) * 1000000 / pvr2_state.dot_clock;
665 MMIO_WRITE( PVR2, reg, val );
666 break;
667 case DISP_VPOS:
668 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
669 break;
671 /*********** Tile accelerator registers ***********/
672 case TA_POLYPOS:
673 case TA_LISTPOS:
674 /* Readonly registers */
675 break;
676 case TA_TILEBASE:
677 case TA_LISTEND:
678 case TA_LISTBASE:
679 MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
680 break;
681 case RENDER_TILEBASE:
682 case TA_POLYBASE:
683 case TA_POLYEND:
684 MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
685 break;
686 case TA_TILESIZE:
687 MMIO_WRITE( PVR2, reg, val&0x000F003F );
688 break;
689 case TA_TILECFG:
690 MMIO_WRITE( PVR2, reg, val&0x00133333 );
691 break;
692 case TA_INIT:
693 if( val & 0x80000000 )
694 pvr2_ta_init();
695 break;
696 case TA_REINIT:
697 break;
698 /**************** Scaler registers? ****************/
699 case RENDER_SCALER:
700 MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
701 break;
703 case YUV_ADDR:
704 val = val & 0x00FFFFF8;
705 MMIO_WRITE( PVR2, reg, val );
706 pvr2_yuv_init( val );
707 break;
708 case YUV_CFG:
709 MMIO_WRITE( PVR2, reg, val&0x01013F3F );
710 pvr2_yuv_set_config(val);
711 break;
713 /**************** Unknowns ***************/
714 case PVRUNK1:
715 MMIO_WRITE( PVR2, reg, val&0x000007FF );
716 break;
717 case PVRUNK2:
718 MMIO_WRITE( PVR2, reg, val&0x00000007 );
719 break;
720 case PVRUNK3:
721 MMIO_WRITE( PVR2, reg, val&0x000FFF3F );
722 break;
723 case PVRUNK5:
724 MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
725 break;
726 case PVRUNK7:
727 MMIO_WRITE( PVR2, reg, val&0x00000001 );
728 break;
729 case PVRUNK8:
730 MMIO_WRITE( PVR2, reg, val&0x0300FFFF );
731 break;
732 }
733 }
735 /**
736 * Calculate the current read value of the syncstat register, using
737 * the current SH4 clock time as an offset from the last timeslice.
738 * The register reads (LSB to MSB) as:
739 * 0..9 Current scan line
740 * 10 Odd/even field (1 = odd, 0 = even)
741 * 11 Display active (including border and overscan)
742 * 12 Horizontal sync off
743 * 13 Vertical sync off
744 * Note this method is probably incorrect for anything other than straight
745 * interlaced PAL/NTSC, and needs further testing.
746 */
747 uint32_t pvr2_get_sync_status()
748 {
749 pvr2_update_raster_posn(sh4r.slice_cycle);
750 uint32_t result = pvr2_state.line_count;
752 if( pvr2_state.odd_even_field ) {
753 result |= 0x0400;
754 }
755 if( (pvr2_state.line_count & 0x01) == pvr2_state.odd_even_field ) {
756 if( pvr2_state.line_remainder > pvr2_state.hsync_width_ns ) {
757 result |= 0x1000; /* !HSYNC */
758 }
759 if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
760 if( pvr2_state.line_remainder > pvr2_state.front_porch_ns ) {
761 result |= 0x2800; /* Display active */
762 } else {
763 result |= 0x2000; /* Front porch */
764 }
765 }
766 } else {
767 if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
768 if( pvr2_state.line_remainder < (pvr2_state.line_time_ns - pvr2_state.back_porch_ns)) {
769 result |= 0x3800; /* Display active */
770 } else {
771 result |= 0x3000;
772 }
773 } else {
774 result |= 0x1000; /* Back porch */
775 }
776 }
777 return result;
778 }
780 /**
781 * Schedule a "scanline" event. This actually goes off at
782 * 2 * line in even fields and 2 * line + 1 in odd fields.
783 * Otherwise this behaves as per pvr2_schedule_line_event().
784 * The raster position should be updated before calling this
785 * method.
786 * @param eventid Event to fire at the specified time
787 * @param line Line on which to fire the event (this is 2n/2n+1 for interlaced
788 * displays).
789 * @param hpos_ns Nanoseconds into the line at which to fire.
790 */
791 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int hpos_ns )
792 {
793 uint32_t field = pvr2_state.odd_even_field;
794 if( line <= pvr2_state.line_count && pvr2_state.interlaced ) {
795 field = !field;
796 }
797 if( hpos_ns > pvr2_state.line_time_ns ) {
798 hpos_ns = pvr2_state.line_time_ns;
799 }
801 line <<= 1;
802 if( field ) {
803 line += 1;
804 }
806 if( line < pvr2_state.total_lines ) {
807 uint32_t lines;
808 uint32_t time;
809 if( line <= pvr2_state.line_count ) {
810 lines = (pvr2_state.total_lines - pvr2_state.line_count + line);
811 } else {
812 lines = (line - pvr2_state.line_count);
813 }
814 if( lines <= minimum_lines ) {
815 lines += pvr2_state.total_lines;
816 }
817 time = (lines * pvr2_state.line_time_ns) - pvr2_state.line_remainder + hpos_ns;
818 event_schedule( eventid, time );
819 } else {
820 event_cancel( eventid );
821 }
822 }
824 void pvr2_queue_gun_event( int xpos, int ypos )
825 {
826 pvr2_update_raster_posn(sh4r.slice_cycle);
827 pvr2_schedule_scanline_event( EVENT_GUNPOS, (ypos >> 1) + pvr2_state.vsync_lines, 0,
828 (1000000 * xpos / pvr2_state.dot_clock) + pvr2_state.hsync_width_ns );
829 }
831 MMIO_REGION_READ_FN( PVR2, reg )
832 {
833 reg &= 0xFFF;
834 switch( reg ) {
835 case DISP_SYNCSTAT:
836 return pvr2_get_sync_status();
837 default:
838 return MMIO_READ( PVR2, reg );
839 }
840 }
841 MMIO_REGION_READ_DEFSUBFNS(PVR2)
842 MMIO_REGION_READ_DEFSUBFNS(PVR2PAL)
844 MMIO_REGION_WRITE_FN( PVR2PAL, reg, val )
845 {
846 reg &= 0xFFF;
847 MMIO_WRITE( PVR2PAL, reg, val );
848 pvr2_state.palette_changed = TRUE;
849 }
851 void pvr2_check_palette_changed()
852 {
853 if( pvr2_state.palette_changed ) {
854 texcache_invalidate_palette();
855 pvr2_state.palette_changed = FALSE;
856 }
857 }
859 MMIO_REGION_READ_DEFFN( PVR2PAL );
861 void pvr2_set_base_address( uint32_t base )
862 {
863 mmio_region_PVR2_write( DISP_ADDR1, base );
864 }
866 render_buffer_t pvr2_create_render_buffer( sh4addr_t addr, int width, int height, GLuint tex_id )
867 {
868 if( display_driver != NULL && display_driver->create_render_buffer != NULL ) {
869 render_buffer_t buffer = display_driver->create_render_buffer(width,height,tex_id);
870 buffer->address = addr;
871 return buffer;
872 }
873 return NULL;
874 }
876 void pvr2_destroy_render_buffer( render_buffer_t buffer )
877 {
878 if( !buffer->flushed )
879 pvr2_render_buffer_copy_to_sh4( buffer );
880 display_driver->destroy_render_buffer( buffer );
881 }
883 void pvr2_finish_render_buffer( render_buffer_t buffer )
884 {
885 display_driver->finish_render( buffer );
886 }
888 /**
889 * Find the render buffer corresponding to the requested output frame
890 * (does not consider texture renders).
891 * @return the render_buffer if found, or null if no such buffer.
892 *
893 * Note: Currently does not consider "partial matches", ie partial
894 * frame overlap - it probably needs to do this.
895 */
896 render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame )
897 {
898 int i;
899 for( i=0; i<render_buffer_count; i++ ) {
900 if( render_buffers[i] != NULL && render_buffers[i]->address == frame->address ) {
901 return render_buffers[i];
902 }
903 }
904 return NULL;
905 }
907 /**
908 * Allocate a render buffer with the requested parameters.
909 * The order of preference is:
910 * 1. An existing buffer with the same address. (not flushed unless the new
911 * size is smaller than the old one).
912 * 2. An existing buffer with the same size chosen by LRU order. Old buffer
913 * is flushed to vram.
914 * 3. A new buffer if one can be created.
915 * 4. The current display buff
916 * Note: The current display field(s) will never be overwritten except as a last
917 * resort.
918 */
919 render_buffer_t pvr2_alloc_render_buffer( sh4addr_t render_addr, int width, int height )
920 {
921 int i;
922 render_buffer_t result = NULL;
924 /* Check existing buffers for an available buffer */
925 for( i=0; i<render_buffer_count; i++ ) {
926 if( render_buffers[i]->width == width && render_buffers[i]->height == height ) {
927 /* needs to be the right dimensions */
928 if( render_buffers[i]->address == render_addr ) {
929 if( displayed_render_buffer == render_buffers[i] ) {
930 /* Same address, but we can't use it because the
931 * display has it. Mark it as unaddressed for later.
932 */
933 render_buffers[i]->address = -1;
934 } else {
935 /* perfect */
936 result = render_buffers[i];
937 break;
938 }
939 } else if( render_buffers[i]->address == -1 && result == NULL &&
940 displayed_render_buffer != render_buffers[i] ) {
941 result = render_buffers[i];
942 }
944 } else if( render_buffers[i]->address == render_addr ) {
945 /* right address, wrong size - if it's larger, flush it, otherwise
946 * nuke it quietly */
947 if( render_buffers[i]->width * render_buffers[i]->height >
948 width*height ) {
949 pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
950 }
951 render_buffers[i]->address = -1;
952 }
953 }
955 /* Nothing available - make one */
956 if( result == NULL ) {
957 if( render_buffer_count == MAX_RENDER_BUFFERS ) {
958 /* maximum buffers reached - need to throw one away */
959 uint32_t field1_addr = MMIO_READ( PVR2, DISP_ADDR1 );
960 uint32_t field2_addr = MMIO_READ( PVR2, DISP_ADDR2 );
961 for( i=0; i<render_buffer_count; i++ ) {
962 if( render_buffers[i]->address != field1_addr &&
963 render_buffers[i]->address != field2_addr &&
964 render_buffers[i] != displayed_render_buffer ) {
965 /* Never throw away the current "front buffer(s)" */
966 result = render_buffers[i];
967 if( !result->flushed && result->address != -1 ) {
968 pvr2_render_buffer_copy_to_sh4( result );
969 }
970 if( result->width != width || result->height != height ) {
971 display_driver->destroy_render_buffer(render_buffers[i]);
972 result = display_driver->create_render_buffer(width,height,0);
973 render_buffers[i] = result;
974 }
975 break;
976 }
977 }
978 } else {
979 result = display_driver->create_render_buffer(width,height,0);
980 if( result != NULL ) {
981 render_buffers[render_buffer_count++] = result;
982 }
983 }
984 }
986 if( result != NULL ) {
987 result->address = render_addr;
988 }
989 return result;
990 }
992 /**
993 * Allocate a render buffer based on the current rendering settings
994 */
995 render_buffer_t pvr2_next_render_buffer()
996 {
997 render_buffer_t result = NULL;
998 uint32_t render_addr = MMIO_READ( PVR2, RENDER_ADDR1 );
999 uint32_t render_mode = MMIO_READ( PVR2, RENDER_MODE );
1000 uint32_t render_scale = MMIO_READ( PVR2, RENDER_SCALER );
1001 uint32_t render_stride = MMIO_READ( PVR2, RENDER_SIZE ) << 3;
1003 int width = pvr2_scene_buffer_width();
1004 int height = pvr2_scene_buffer_height();
1005 int colour_format = render_colour_formats[render_mode&0x07];
1007 if( render_addr & 0x01000000 ) { /* vram64 */
1008 render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE_INT;
1009 } else { /* vram32 */
1010 render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE;
1011 }
1012 result = pvr2_alloc_render_buffer( render_addr, width, height );
1014 /* Setup the buffer */
1015 if( result != NULL ) {
1016 result->rowstride = render_stride;
1017 result->colour_format = colour_format;
1018 result->scale = render_scale;
1019 result->size = width * height * colour_formats[colour_format].bpp;
1020 result->flushed = FALSE;
1021 result->inverted = TRUE; // render buffers are inverted normally
1022 }
1023 return result;
1024 }
1026 static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame )
1027 {
1028 render_buffer_t result = pvr2_alloc_render_buffer( frame->address, frame->width, frame->height );
1029 if( result != NULL ) {
1030 int bpp = colour_formats[frame->colour_format].bpp;
1031 result->rowstride = frame->rowstride;
1032 result->colour_format = frame->colour_format;
1033 result->scale = 0x400;
1034 result->size = frame->width * frame->height * bpp;
1035 result->flushed = TRUE;
1036 result->inverted = frame->inverted;
1037 display_driver->load_frame_buffer( frame, result );
1038 }
1039 return result;
1040 }
1043 /**
1044 * Invalidate any caching on the supplied address. Specifically, if it falls
1045 * within any of the render buffers, flush the buffer back to PVR2 ram.
1046 */
1047 gboolean pvr2_render_buffer_invalidate( sh4addr_t address, gboolean isWrite )
1048 {
1049 int i;
1050 address = address & 0x1FFFFFFF;
1051 for( i=0; i<render_buffer_count; i++ ) {
1052 uint32_t bufaddr = render_buffers[i]->address;
1053 if( bufaddr != -1 && bufaddr <= address &&
1054 (bufaddr + render_buffers[i]->size) > address ) {
1055 if( !render_buffers[i]->flushed ) {
1056 pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
1057 }
1058 if( isWrite ) {
1059 render_buffers[i]->address = -1; /* Invalid */
1060 }
1061 return TRUE; /* should never have overlapping buffers */
1062 }
1063 }
1064 return FALSE;
1065 }
.