2 * $Id: sh4core.c,v 1.49 2007-10-08 12:06:01 nkeynes Exp $
4 * SH4 emulation core, and parent module for all the SH4 peripheral
7 * Copyright (c) 2005 Nathan Keynes.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #define MODULE sh4_module
23 #include "dreamcast.h"
28 #include "sh4/sh4core.h"
29 #include "sh4/sh4mmio.h"
32 #define SH4_CALLTRACE 1
34 #define MAX_INT 0x7FFFFFFF
35 #define MIN_INT 0x80000000
36 #define MAX_INTF 2147483647.0
37 #define MIN_INTF -2147483648.0
39 /********************** SH4 Module Definition ****************************/
41 uint16_t *sh4_icache = NULL;
42 uint32_t sh4_icache_addr = 0;
44 uint32_t sh4_run_slice( uint32_t nanosecs )
49 if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
50 if( sh4r.event_pending < nanosecs ) {
51 sh4r.sh4_state = SH4_STATE_RUNNING;
52 sh4r.slice_cycle = sh4r.event_pending;
56 if( sh4_breakpoint_count == 0 ) {
57 for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
58 if( SH4_EVENT_PENDING() ) {
59 if( sh4r.event_types & PENDING_EVENT ) {
62 /* Eventq execute may (quite likely) deliver an immediate IRQ */
63 if( sh4r.event_types & PENDING_IRQ ) {
64 sh4_accept_interrupt();
67 if( !sh4_execute_instruction() ) {
72 for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
73 if( SH4_EVENT_PENDING() ) {
74 if( sh4r.event_types & PENDING_EVENT ) {
77 /* Eventq execute may (quite likely) deliver an immediate IRQ */
78 if( sh4r.event_types & PENDING_IRQ ) {
79 sh4_accept_interrupt();
83 if( !sh4_execute_instruction() )
85 #ifdef ENABLE_DEBUG_MODE
86 for( i=0; i<sh4_breakpoint_count; i++ ) {
87 if( sh4_breakpoints[i].address == sh4r.pc ) {
91 if( i != sh4_breakpoint_count ) {
93 if( sh4_breakpoints[i].type == BREAK_ONESHOT )
94 sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
101 /* If we aborted early, but the cpu is still technically running,
102 * we're doing a hard abort - cut the timeslice back to what we
105 if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
106 nanosecs = sh4r.slice_cycle;
108 if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
109 TMU_run_slice( nanosecs );
110 SCIF_run_slice( nanosecs );
115 /********************** SH4 emulation core ****************************/
117 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
118 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
120 #if(SH4_CALLTRACE == 1)
121 #define MAX_CALLSTACK 32
122 static struct call_stack {
124 sh4addr_t target_addr;
125 sh4addr_t stack_pointer;
126 } call_stack[MAX_CALLSTACK];
128 static int call_stack_depth = 0;
129 int sh4_call_trace_on = 0;
131 static inline void trace_call( sh4addr_t source, sh4addr_t dest )
133 if( call_stack_depth < MAX_CALLSTACK ) {
134 call_stack[call_stack_depth].call_addr = source;
135 call_stack[call_stack_depth].target_addr = dest;
136 call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
141 static inline void trace_return( sh4addr_t source, sh4addr_t dest )
143 if( call_stack_depth > 0 ) {
148 void fprint_stack_trace( FILE *f )
150 int i = call_stack_depth -1;
151 if( i >= MAX_CALLSTACK )
152 i = MAX_CALLSTACK - 1;
153 for( ; i >= 0; i-- ) {
154 fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n",
155 (call_stack_depth - i), call_stack[i].call_addr,
156 call_stack[i].target_addr, call_stack[i].stack_pointer );
160 #define TRACE_CALL( source, dest ) trace_call(source, dest)
161 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
163 #define TRACE_CALL( dest, rts )
164 #define TRACE_RETURN( source, dest )
167 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
168 #define MEM_READ_WORD( addr ) sh4_read_word(addr)
169 #define MEM_READ_LONG( addr ) sh4_read_long(addr)
170 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
171 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
172 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
174 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
176 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
177 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
179 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )
180 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
181 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
182 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
183 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
185 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }
186 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
187 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)
189 static void sh4_write_float( uint32_t addr, int reg )
191 if( IS_FPU_DOUBLESIZE() ) {
193 sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
194 sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
196 sh4_write_long( addr, *((uint32_t *)&FR(reg)) );
197 sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
200 sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
204 static void sh4_read_float( uint32_t addr, int reg )
206 if( IS_FPU_DOUBLESIZE() ) {
208 *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
209 *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
211 *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
212 *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
215 *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
219 gboolean sh4_execute_instruction( void )
229 if( pc > 0xFFFFFF00 ) {
231 syscall_invoke( pc );
232 sh4r.in_delay_slot = 0;
233 pc = sh4r.pc = sh4r.pr;
234 sh4r.new_pc = sh4r.pc + 2;
238 /* Read instruction */
239 uint32_t pageaddr = pc >> 12;
240 if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
241 ir = sh4_icache[(pc&0xFFF)>>1];
243 sh4_icache = (uint16_t *)mem_get_page(pc);
244 if( ((uint32_t)sh4_icache) < MAX_IO_REGIONS ) {
245 /* If someone's actually been so daft as to try to execute out of an IO
246 * region, fallback on the full-blown memory read
249 ir = MEM_READ_WORD(pc);
251 sh4_icache_addr = pageaddr;
252 ir = sh4_icache[(pc&0xFFF)>>1];
255 switch( (ir&0xF000) >> 12 ) {
259 switch( (ir&0x80) >> 7 ) {
261 switch( (ir&0x70) >> 4 ) {
264 uint32_t Rn = ((ir>>8)&0xF);
266 sh4r.r[Rn] = sh4_read_sr();
271 uint32_t Rn = ((ir>>8)&0xF);
273 sh4r.r[Rn] = sh4r.gbr;
278 uint32_t Rn = ((ir>>8)&0xF);
280 sh4r.r[Rn] = sh4r.vbr;
285 uint32_t Rn = ((ir>>8)&0xF);
287 sh4r.r[Rn] = sh4r.ssr;
292 uint32_t Rn = ((ir>>8)&0xF);
294 sh4r.r[Rn] = sh4r.spc;
303 { /* STC Rm_BANK, Rn */
304 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);
306 sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];
312 switch( (ir&0xF0) >> 4 ) {
315 uint32_t Rn = ((ir>>8)&0xF);
317 CHECKDEST( pc + 4 + sh4r.r[Rn] );
318 sh4r.in_delay_slot = 1;
319 sh4r.pr = sh4r.pc + 4;
320 sh4r.pc = sh4r.new_pc;
321 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
322 TRACE_CALL( pc, sh4r.new_pc );
328 uint32_t Rn = ((ir>>8)&0xF);
330 CHECKDEST( pc + 4 + sh4r.r[Rn] );
331 sh4r.in_delay_slot = 1;
332 sh4r.pc = sh4r.new_pc;
333 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
339 uint32_t Rn = ((ir>>8)&0xF);
341 if( (tmp & 0xFC000000) == 0xE0000000 ) {
342 sh4_flush_store_queue(tmp);
348 uint32_t Rn = ((ir>>8)&0xF);
353 uint32_t Rn = ((ir>>8)&0xF);
358 uint32_t Rn = ((ir>>8)&0xF);
362 { /* MOVCA.L R0, @Rn */
363 uint32_t Rn = ((ir>>8)&0xF);
366 MEM_WRITE_LONG( tmp, R0 );
375 { /* MOV.B Rm, @(R0, Rn) */
376 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
377 MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] );
381 { /* MOV.W Rm, @(R0, Rn) */
382 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
383 CHECKWALIGN16( R0 + sh4r.r[Rn] );
384 MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );
388 { /* MOV.L Rm, @(R0, Rn) */
389 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
390 CHECKWALIGN32( R0 + sh4r.r[Rn] );
391 MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );
396 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
397 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
398 (sh4r.r[Rm] * sh4r.r[Rn]);
402 switch( (ir&0xFF0) >> 4 ) {
439 switch( (ir&0xF0) >> 4 ) {
447 sh4r.m = sh4r.q = sh4r.t = 0;
452 uint32_t Rn = ((ir>>8)&0xF);
462 switch( (ir&0xF0) >> 4 ) {
465 uint32_t Rn = ((ir>>8)&0xF);
466 sh4r.r[Rn] = (sh4r.mac>>32);
471 uint32_t Rn = ((ir>>8)&0xF);
472 sh4r.r[Rn] = (uint32_t)sh4r.mac;
477 uint32_t Rn = ((ir>>8)&0xF);
478 sh4r.r[Rn] = sh4r.pr;
483 uint32_t Rn = ((ir>>8)&0xF);
485 sh4r.r[Rn] = sh4r.sgr;
490 uint32_t Rn = ((ir>>8)&0xF);
491 sh4r.r[Rn] = sh4r.fpul;
495 { /* STS FPSCR, Rn */
496 uint32_t Rn = ((ir>>8)&0xF);
497 sh4r.r[Rn] = sh4r.fpscr;
502 uint32_t Rn = ((ir>>8)&0xF);
503 CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr;
512 switch( (ir&0xFF0) >> 4 ) {
516 CHECKDEST( sh4r.pr );
517 sh4r.in_delay_slot = 1;
518 sh4r.pc = sh4r.new_pc;
519 sh4r.new_pc = sh4r.pr;
520 TRACE_RETURN( pc, sh4r.new_pc );
526 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
527 sh4r.sh4_state = SH4_STATE_STANDBY;
529 sh4r.sh4_state = SH4_STATE_SLEEP;
531 return FALSE; /* Halt CPU */
537 CHECKDEST( sh4r.spc );
539 sh4r.in_delay_slot = 1;
540 sh4r.pc = sh4r.new_pc;
541 sh4r.new_pc = sh4r.spc;
542 sh4_write_sr( sh4r.ssr );
552 { /* MOV.B @(R0, Rm), Rn */
553 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
554 sh4r.r[Rn] = MEM_READ_BYTE( R0 + sh4r.r[Rm] );
558 { /* MOV.W @(R0, Rm), Rn */
559 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
560 CHECKRALIGN16( R0 + sh4r.r[Rm] );
561 sh4r.r[Rn] = MEM_READ_WORD( R0 + sh4r.r[Rm] );
565 { /* MOV.L @(R0, Rm), Rn */
566 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
567 CHECKRALIGN32( R0 + sh4r.r[Rm] );
568 sh4r.r[Rn] = MEM_READ_LONG( R0 + sh4r.r[Rm] );
572 { /* MAC.L @Rm+, @Rn+ */
573 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
574 CHECKRALIGN32( sh4r.r[Rm] );
575 CHECKRALIGN32( sh4r.r[Rn] );
576 int64_t tmpl = SIGNEXT32(MEM_READ_LONG(sh4r.r[Rn]));
578 tmpl = tmpl * SIGNEXT32(MEM_READ_LONG(sh4r.r[Rm])) + sh4r.mac;
581 /* 48-bit Saturation. Yuch */
582 if( tmpl < (int64_t)0xFFFF800000000000LL )
583 tmpl = 0xFFFF800000000000LL;
584 else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )
585 tmpl = 0x00007FFFFFFFFFFFLL;
596 { /* MOV.L Rm, @(disp, Rn) */
597 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;
598 tmp = sh4r.r[Rn] + disp;
599 CHECKWALIGN32( tmp );
600 MEM_WRITE_LONG( tmp, sh4r.r[Rm] );
606 { /* MOV.B Rm, @Rn */
607 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
608 MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] );
612 { /* MOV.W Rm, @Rn */
613 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
614 CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] );
618 { /* MOV.L Rm, @Rn */
619 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
620 CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] );
624 { /* MOV.B Rm, @-Rn */
625 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
626 sh4r.r[Rn] --; MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] );
630 { /* MOV.W Rm, @-Rn */
631 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
632 sh4r.r[Rn] -= 2; CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] );
636 { /* MOV.L Rm, @-Rn */
637 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
638 sh4r.r[Rn] -= 4; CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] );
643 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
644 sh4r.q = sh4r.r[Rn]>>31;
645 sh4r.m = sh4r.r[Rm]>>31;
646 sh4r.t = sh4r.q ^ sh4r.m;
651 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
652 sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1);
657 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
658 sh4r.r[Rn] &= sh4r.r[Rm];
663 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
664 sh4r.r[Rn] ^= sh4r.r[Rm];
669 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
670 sh4r.r[Rn] |= sh4r.r[Rm];
674 { /* CMP/STR Rm, Rn */
675 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
676 /* set T = 1 if any byte in RM & RN is the same */
677 tmp = sh4r.r[Rm] ^ sh4r.r[Rn];
678 sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
679 (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
684 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
685 sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16);
689 { /* MULU.W Rm, Rn */
690 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
691 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
692 (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));
696 { /* MULS.W Rm, Rn */
697 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
698 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
699 (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));
710 { /* CMP/EQ Rm, Rn */
711 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
712 sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 );
716 { /* CMP/HS Rm, Rn */
717 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
718 sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 );
722 { /* CMP/GE Rm, Rn */
723 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
724 sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 );
729 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
730 /* This is derived from the sh4 manual with some simplifications */
731 uint32_t tmp0, tmp1, tmp2, dir;
733 dir = sh4r.q ^ sh4r.m;
734 sh4r.q = (sh4r.r[Rn] >> 31);
736 sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;
740 tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );
743 tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );
745 sh4r.q ^= sh4r.m ^ tmp1;
746 sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
750 { /* DMULU.L Rm, Rn */
751 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
752 sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]);
756 { /* CMP/HI Rm, Rn */
757 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
758 sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 );
762 { /* CMP/GT Rm, Rn */
763 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
764 sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 );
769 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
770 sh4r.r[Rn] -= sh4r.r[Rm];
775 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
777 sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;
778 sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));
782 UNIMP(ir); /* SUBV Rm, Rn */
786 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
787 sh4r.r[Rn] += sh4r.r[Rm];
791 { /* DMULS.L Rm, Rn */
792 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
793 sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]);
798 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
800 sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;
801 sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );
806 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
807 tmp = sh4r.r[Rn] + sh4r.r[Rm];
808 sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );
820 switch( (ir&0xF0) >> 4 ) {
823 uint32_t Rn = ((ir>>8)&0xF);
824 sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1;
829 uint32_t Rn = ((ir>>8)&0xF);
831 sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );
836 uint32_t Rn = ((ir>>8)&0xF);
837 sh4r.t = sh4r.r[Rn] >> 31;
847 switch( (ir&0xF0) >> 4 ) {
850 uint32_t Rn = ((ir>>8)&0xF);
851 sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1;
856 uint32_t Rn = ((ir>>8)&0xF);
857 sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 );
862 uint32_t Rn = ((ir>>8)&0xF);
863 sh4r.t = sh4r.r[Rn] & 0x00000001;
864 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;
873 switch( (ir&0xF0) >> 4 ) {
875 { /* STS.L MACH, @-Rn */
876 uint32_t Rn = ((ir>>8)&0xF);
878 CHECKWALIGN32( sh4r.r[Rn] );
879 MEM_WRITE_LONG( sh4r.r[Rn], (sh4r.mac>>32) );
883 { /* STS.L MACL, @-Rn */
884 uint32_t Rn = ((ir>>8)&0xF);
886 CHECKWALIGN32( sh4r.r[Rn] );
887 MEM_WRITE_LONG( sh4r.r[Rn], (uint32_t)sh4r.mac );
891 { /* STS.L PR, @-Rn */
892 uint32_t Rn = ((ir>>8)&0xF);
894 CHECKWALIGN32( sh4r.r[Rn] );
895 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.pr );
899 { /* STC.L SGR, @-Rn */
900 uint32_t Rn = ((ir>>8)&0xF);
903 CHECKWALIGN32( sh4r.r[Rn] );
904 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.sgr );
908 { /* STS.L FPUL, @-Rn */
909 uint32_t Rn = ((ir>>8)&0xF);
911 CHECKWALIGN32( sh4r.r[Rn] );
912 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpul );
916 { /* STS.L FPSCR, @-Rn */
917 uint32_t Rn = ((ir>>8)&0xF);
919 CHECKWALIGN32( sh4r.r[Rn] );
920 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpscr );
924 { /* STC.L DBR, @-Rn */
925 uint32_t Rn = ((ir>>8)&0xF);
928 CHECKWALIGN32( sh4r.r[Rn] );
929 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.dbr );
938 switch( (ir&0x80) >> 7 ) {
940 switch( (ir&0x70) >> 4 ) {
942 { /* STC.L SR, @-Rn */
943 uint32_t Rn = ((ir>>8)&0xF);
946 CHECKWALIGN32( sh4r.r[Rn] );
947 MEM_WRITE_LONG( sh4r.r[Rn], sh4_read_sr() );
951 { /* STC.L GBR, @-Rn */
952 uint32_t Rn = ((ir>>8)&0xF);
954 CHECKWALIGN32( sh4r.r[Rn] );
955 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.gbr );
959 { /* STC.L VBR, @-Rn */
960 uint32_t Rn = ((ir>>8)&0xF);
963 CHECKWALIGN32( sh4r.r[Rn] );
964 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.vbr );
968 { /* STC.L SSR, @-Rn */
969 uint32_t Rn = ((ir>>8)&0xF);
972 CHECKWALIGN32( sh4r.r[Rn] );
973 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.ssr );
977 { /* STC.L SPC, @-Rn */
978 uint32_t Rn = ((ir>>8)&0xF);
981 CHECKWALIGN32( sh4r.r[Rn] );
982 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.spc );
991 { /* STC.L Rm_BANK, @-Rn */
992 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);
995 CHECKWALIGN32( sh4r.r[Rn] );
996 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r_bank[Rm_BANK] );
1002 switch( (ir&0xF0) >> 4 ) {
1005 uint32_t Rn = ((ir>>8)&0xF);
1006 sh4r.t = sh4r.r[Rn] >> 31;
1008 sh4r.r[Rn] |= sh4r.t;
1013 uint32_t Rn = ((ir>>8)&0xF);
1014 tmp = sh4r.r[Rn] >> 31;
1016 sh4r.r[Rn] |= sh4r.t;
1026 switch( (ir&0xF0) >> 4 ) {
1029 uint32_t Rn = ((ir>>8)&0xF);
1030 sh4r.t = sh4r.r[Rn] & 0x00000001;
1032 sh4r.r[Rn] |= (sh4r.t << 31);
1037 uint32_t Rn = ((ir>>8)&0xF);
1038 sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 );
1043 uint32_t Rn = ((ir>>8)&0xF);
1044 tmp = sh4r.r[Rn] & 0x00000001;
1046 sh4r.r[Rn] |= (sh4r.t << 31 );
1056 switch( (ir&0xF0) >> 4 ) {
1058 { /* LDS.L @Rm+, MACH */
1059 uint32_t Rm = ((ir>>8)&0xF);
1060 CHECKRALIGN32( sh4r.r[Rm] );
1061 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
1062 (((uint64_t)MEM_READ_LONG(sh4r.r[Rm]))<<32);
1067 { /* LDS.L @Rm+, MACL */
1068 uint32_t Rm = ((ir>>8)&0xF);
1069 CHECKRALIGN32( sh4r.r[Rm] );
1070 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
1071 (uint64_t)((uint32_t)MEM_READ_LONG(sh4r.r[Rm]));
1076 { /* LDS.L @Rm+, PR */
1077 uint32_t Rm = ((ir>>8)&0xF);
1078 CHECKRALIGN32( sh4r.r[Rm] );
1079 sh4r.pr = MEM_READ_LONG( sh4r.r[Rm] );
1084 { /* LDC.L @Rm+, SGR */
1085 uint32_t Rm = ((ir>>8)&0xF);
1087 CHECKRALIGN32( sh4r.r[Rm] );
1088 sh4r.sgr = MEM_READ_LONG(sh4r.r[Rm]);
1093 { /* LDS.L @Rm+, FPUL */
1094 uint32_t Rm = ((ir>>8)&0xF);
1095 CHECKRALIGN32( sh4r.r[Rm] );
1096 sh4r.fpul = MEM_READ_LONG(sh4r.r[Rm]);
1101 { /* LDS.L @Rm+, FPSCR */
1102 uint32_t Rm = ((ir>>8)&0xF);
1103 CHECKRALIGN32( sh4r.r[Rm] );
1104 sh4r.fpscr = MEM_READ_LONG(sh4r.r[Rm]);
1106 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
1110 { /* LDC.L @Rm+, DBR */
1111 uint32_t Rm = ((ir>>8)&0xF);
1113 CHECKRALIGN32( sh4r.r[Rm] );
1114 sh4r.dbr = MEM_READ_LONG(sh4r.r[Rm]);
1124 switch( (ir&0x80) >> 7 ) {
1126 switch( (ir&0x70) >> 4 ) {
1128 { /* LDC.L @Rm+, SR */
1129 uint32_t Rm = ((ir>>8)&0xF);
1132 CHECKWALIGN32( sh4r.r[Rm] );
1133 sh4_write_sr( MEM_READ_LONG(sh4r.r[Rm]) );
1138 { /* LDC.L @Rm+, GBR */
1139 uint32_t Rm = ((ir>>8)&0xF);
1140 CHECKRALIGN32( sh4r.r[Rm] );
1141 sh4r.gbr = MEM_READ_LONG(sh4r.r[Rm]);
1146 { /* LDC.L @Rm+, VBR */
1147 uint32_t Rm = ((ir>>8)&0xF);
1149 CHECKRALIGN32( sh4r.r[Rm] );
1150 sh4r.vbr = MEM_READ_LONG(sh4r.r[Rm]);
1155 { /* LDC.L @Rm+, SSR */
1156 uint32_t Rm = ((ir>>8)&0xF);
1158 CHECKRALIGN32( sh4r.r[Rm] );
1159 sh4r.ssr = MEM_READ_LONG(sh4r.r[Rm]);
1164 { /* LDC.L @Rm+, SPC */
1165 uint32_t Rm = ((ir>>8)&0xF);
1167 CHECKRALIGN32( sh4r.r[Rm] );
1168 sh4r.spc = MEM_READ_LONG(sh4r.r[Rm]);
1178 { /* LDC.L @Rm+, Rn_BANK */
1179 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);
1181 CHECKRALIGN32( sh4r.r[Rm] );
1182 sh4r.r_bank[Rn_BANK] = MEM_READ_LONG( sh4r.r[Rm] );
1189 switch( (ir&0xF0) >> 4 ) {
1192 uint32_t Rn = ((ir>>8)&0xF);
1198 uint32_t Rn = ((ir>>8)&0xF);
1204 uint32_t Rn = ((ir>>8)&0xF);
1214 switch( (ir&0xF0) >> 4 ) {
1217 uint32_t Rn = ((ir>>8)&0xF);
1223 uint32_t Rn = ((ir>>8)&0xF);
1229 uint32_t Rn = ((ir>>8)&0xF);
1239 switch( (ir&0xF0) >> 4 ) {
1241 { /* LDS Rm, MACH */
1242 uint32_t Rm = ((ir>>8)&0xF);
1243 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
1244 (((uint64_t)sh4r.r[Rm])<<32);
1248 { /* LDS Rm, MACL */
1249 uint32_t Rm = ((ir>>8)&0xF);
1250 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
1251 (uint64_t)((uint32_t)(sh4r.r[Rm]));
1256 uint32_t Rm = ((ir>>8)&0xF);
1257 sh4r.pr = sh4r.r[Rm];
1262 uint32_t Rm = ((ir>>8)&0xF);
1264 sh4r.sgr = sh4r.r[Rm];
1268 { /* LDS Rm, FPUL */
1269 uint32_t Rm = ((ir>>8)&0xF);
1270 sh4r.fpul = sh4r.r[Rm];
1274 { /* LDS Rm, FPSCR */
1275 uint32_t Rm = ((ir>>8)&0xF);
1276 sh4r.fpscr = sh4r.r[Rm];
1277 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
1282 uint32_t Rm = ((ir>>8)&0xF);
1284 sh4r.dbr = sh4r.r[Rm];
1293 switch( (ir&0xF0) >> 4 ) {
1296 uint32_t Rn = ((ir>>8)&0xF);
1297 CHECKDEST( sh4r.r[Rn] );
1299 sh4r.in_delay_slot = 1;
1300 sh4r.pc = sh4r.new_pc;
1301 sh4r.new_pc = sh4r.r[Rn];
1303 TRACE_CALL( pc, sh4r.new_pc );
1309 uint32_t Rn = ((ir>>8)&0xF);
1310 tmp = MEM_READ_BYTE( sh4r.r[Rn] );
1311 sh4r.t = ( tmp == 0 ? 1 : 0 );
1312 MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );
1317 uint32_t Rn = ((ir>>8)&0xF);
1318 CHECKDEST( sh4r.r[Rn] );
1320 sh4r.in_delay_slot = 1;
1321 sh4r.pc = sh4r.new_pc;
1322 sh4r.new_pc = sh4r.r[Rn];
1333 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1335 if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
1336 else if( (tmp & 0x1F) == 0 )
1337 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;
1339 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);
1344 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1346 if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
1347 else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;
1348 else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);
1352 switch( (ir&0x80) >> 7 ) {
1354 switch( (ir&0x70) >> 4 ) {
1357 uint32_t Rm = ((ir>>8)&0xF);
1360 sh4_write_sr( sh4r.r[Rm] );
1365 uint32_t Rm = ((ir>>8)&0xF);
1366 sh4r.gbr = sh4r.r[Rm];
1371 uint32_t Rm = ((ir>>8)&0xF);
1373 sh4r.vbr = sh4r.r[Rm];
1378 uint32_t Rm = ((ir>>8)&0xF);
1380 sh4r.ssr = sh4r.r[Rm];
1385 uint32_t Rm = ((ir>>8)&0xF);
1387 sh4r.spc = sh4r.r[Rm];
1396 { /* LDC Rm, Rn_BANK */
1397 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);
1399 sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];
1405 { /* MAC.W @Rm+, @Rn+ */
1406 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1407 CHECKRALIGN16( sh4r.r[Rn] );
1408 CHECKRALIGN16( sh4r.r[Rm] );
1409 int32_t stmp = SIGNEXT16(MEM_READ_WORD(sh4r.r[Rn]));
1411 stmp = stmp * SIGNEXT16(MEM_READ_WORD(sh4r.r[Rm]));
1414 int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;
1415 if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {
1416 sh4r.mac = 0x000000017FFFFFFFLL;
1417 } else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {
1418 sh4r.mac = 0x0000000180000000LL;
1420 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
1421 ((uint32_t)(sh4r.mac + stmp));
1424 sh4r.mac += SIGNEXT32(stmp);
1431 { /* MOV.L @(disp, Rm), Rn */
1432 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;
1433 tmp = sh4r.r[Rm] + disp;
1434 CHECKRALIGN32( tmp );
1435 sh4r.r[Rn] = MEM_READ_LONG( tmp );
1441 { /* MOV.B @Rm, Rn */
1442 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1443 sh4r.r[Rn] = MEM_READ_BYTE( sh4r.r[Rm] );
1447 { /* MOV.W @Rm, Rn */
1448 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1449 CHECKRALIGN16( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_WORD( sh4r.r[Rm] );
1453 { /* MOV.L @Rm, Rn */
1454 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1455 CHECKRALIGN32( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_LONG( sh4r.r[Rm] );
1460 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1461 sh4r.r[Rn] = sh4r.r[Rm];
1465 { /* MOV.B @Rm+, Rn */
1466 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1467 sh4r.r[Rn] = MEM_READ_BYTE( sh4r.r[Rm] ); sh4r.r[Rm] ++;
1471 { /* MOV.W @Rm+, Rn */
1472 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1473 CHECKRALIGN16( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_WORD( sh4r.r[Rm] ); sh4r.r[Rm] += 2;
1477 { /* MOV.L @Rm+, Rn */
1478 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1479 CHECKRALIGN32( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_LONG( sh4r.r[Rm] ); sh4r.r[Rm] += 4;
1484 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1485 sh4r.r[Rn] = ~sh4r.r[Rm];
1489 { /* SWAP.B Rm, Rn */
1490 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1491 sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8);
1495 { /* SWAP.W Rm, Rn */
1496 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1497 sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16);
1502 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1503 tmp = 0 - sh4r.r[Rm];
1504 sh4r.r[Rn] = tmp - sh4r.t;
1505 sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );
1510 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1511 sh4r.r[Rn] = 0 - sh4r.r[Rm];
1515 { /* EXTU.B Rm, Rn */
1516 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1517 sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF;
1521 { /* EXTU.W Rm, Rn */
1522 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1523 sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF;
1527 { /* EXTS.B Rm, Rn */
1528 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1529 sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF );
1533 { /* EXTS.W Rm, Rn */
1534 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1535 sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF );
1541 { /* ADD #imm, Rn */
1542 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);
1547 switch( (ir&0xF00) >> 8 ) {
1549 { /* MOV.B R0, @(disp, Rn) */
1550 uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);
1551 MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 );
1555 { /* MOV.W R0, @(disp, Rn) */
1556 uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;
1557 tmp = sh4r.r[Rn] + disp;
1558 CHECKWALIGN16( tmp );
1559 MEM_WRITE_WORD( tmp, R0 );
1563 { /* MOV.B @(disp, Rm), R0 */
1564 uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);
1565 R0 = MEM_READ_BYTE( sh4r.r[Rm] + disp );
1569 { /* MOV.W @(disp, Rm), R0 */
1570 uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;
1571 tmp = sh4r.r[Rm] + disp;
1572 CHECKRALIGN16( tmp );
1573 R0 = MEM_READ_WORD( tmp );
1577 { /* CMP/EQ #imm, R0 */
1578 int32_t imm = SIGNEXT8(ir&0xFF);
1579 sh4r.t = ( R0 == imm ? 1 : 0 );
1584 int32_t disp = SIGNEXT8(ir&0xFF)<<1;
1587 CHECKDEST( sh4r.pc + disp + 4 )
1588 sh4r.pc += disp + 4;
1589 sh4r.new_pc = sh4r.pc + 2;
1596 int32_t disp = SIGNEXT8(ir&0xFF)<<1;
1599 CHECKDEST( sh4r.pc + disp + 4 )
1600 sh4r.pc += disp + 4;
1601 sh4r.new_pc = sh4r.pc + 2;
1608 int32_t disp = SIGNEXT8(ir&0xFF)<<1;
1611 CHECKDEST( sh4r.pc + disp + 4 )
1612 sh4r.in_delay_slot = 1;
1613 sh4r.pc = sh4r.new_pc;
1614 sh4r.new_pc = pc + disp + 4;
1615 sh4r.in_delay_slot = 1;
1622 int32_t disp = SIGNEXT8(ir&0xFF)<<1;
1625 CHECKDEST( sh4r.pc + disp + 4 )
1626 sh4r.in_delay_slot = 1;
1627 sh4r.pc = sh4r.new_pc;
1628 sh4r.new_pc = pc + disp + 4;
1639 { /* MOV.W @(disp, PC), Rn */
1640 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1;
1642 tmp = pc + 4 + disp;
1643 sh4r.r[Rn] = MEM_READ_WORD( tmp );
1648 int32_t disp = SIGNEXT12(ir&0xFFF)<<1;
1650 CHECKDEST( sh4r.pc + disp + 4 );
1651 sh4r.in_delay_slot = 1;
1652 sh4r.pc = sh4r.new_pc;
1653 sh4r.new_pc = pc + 4 + disp;
1659 int32_t disp = SIGNEXT12(ir&0xFFF)<<1;
1660 CHECKDEST( sh4r.pc + disp + 4 );
1662 sh4r.in_delay_slot = 1;
1664 sh4r.pc = sh4r.new_pc;
1665 sh4r.new_pc = pc + 4 + disp;
1666 TRACE_CALL( pc, sh4r.new_pc );
1671 switch( (ir&0xF00) >> 8 ) {
1673 { /* MOV.B R0, @(disp, GBR) */
1674 uint32_t disp = (ir&0xFF);
1675 MEM_WRITE_BYTE( sh4r.gbr + disp, R0 );
1679 { /* MOV.W R0, @(disp, GBR) */
1680 uint32_t disp = (ir&0xFF)<<1;
1681 tmp = sh4r.gbr + disp;
1682 CHECKWALIGN16( tmp );
1683 MEM_WRITE_WORD( tmp, R0 );
1687 { /* MOV.L R0, @(disp, GBR) */
1688 uint32_t disp = (ir&0xFF)<<2;
1689 tmp = sh4r.gbr + disp;
1690 CHECKWALIGN32( tmp );
1691 MEM_WRITE_LONG( tmp, R0 );
1696 uint32_t imm = (ir&0xFF);
1698 MMIO_WRITE( MMU, TRA, imm<<2 );
1700 sh4_raise_exception( EXC_TRAP );
1704 { /* MOV.B @(disp, GBR), R0 */
1705 uint32_t disp = (ir&0xFF);
1706 R0 = MEM_READ_BYTE( sh4r.gbr + disp );
1710 { /* MOV.W @(disp, GBR), R0 */
1711 uint32_t disp = (ir&0xFF)<<1;
1712 tmp = sh4r.gbr + disp;
1713 CHECKRALIGN16( tmp );
1714 R0 = MEM_READ_WORD( tmp );
1718 { /* MOV.L @(disp, GBR), R0 */
1719 uint32_t disp = (ir&0xFF)<<2;
1720 tmp = sh4r.gbr + disp;
1721 CHECKRALIGN32( tmp );
1722 R0 = MEM_READ_LONG( tmp );
1726 { /* MOVA @(disp, PC), R0 */
1727 uint32_t disp = (ir&0xFF)<<2;
1729 R0 = (pc&0xFFFFFFFC) + disp + 4;
1733 { /* TST #imm, R0 */
1734 uint32_t imm = (ir&0xFF);
1735 sh4r.t = (R0 & imm ? 0 : 1);
1739 { /* AND #imm, R0 */
1740 uint32_t imm = (ir&0xFF);
1745 { /* XOR #imm, R0 */
1746 uint32_t imm = (ir&0xFF);
1752 uint32_t imm = (ir&0xFF);
1757 { /* TST.B #imm, @(R0, GBR) */
1758 uint32_t imm = (ir&0xFF);
1759 sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & imm ? 0 : 1 );
1763 { /* AND.B #imm, @(R0, GBR) */
1764 uint32_t imm = (ir&0xFF);
1765 MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & MEM_READ_BYTE(R0 + sh4r.gbr) );
1769 { /* XOR.B #imm, @(R0, GBR) */
1770 uint32_t imm = (ir&0xFF);
1771 MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ MEM_READ_BYTE(R0 + sh4r.gbr) );
1775 { /* OR.B #imm, @(R0, GBR) */
1776 uint32_t imm = (ir&0xFF);
1777 MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | MEM_READ_BYTE(R0 + sh4r.gbr) );
1783 { /* MOV.L @(disp, PC), Rn */
1784 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2;
1786 tmp = (pc&0xFFFFFFFC) + disp + 4;
1787 sh4r.r[Rn] = MEM_READ_LONG( tmp );
1791 { /* MOV #imm, Rn */
1792 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);
1799 { /* FADD FRm, FRn */
1800 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1802 if( IS_FPU_DOUBLEPREC() ) {
1810 { /* FSUB FRm, FRn */
1811 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1813 if( IS_FPU_DOUBLEPREC() ) {
1821 { /* FMUL FRm, FRn */
1822 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1824 if( IS_FPU_DOUBLEPREC() ) {
1832 { /* FDIV FRm, FRn */
1833 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1835 if( IS_FPU_DOUBLEPREC() ) {
1843 { /* FCMP/EQ FRm, FRn */
1844 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1846 if( IS_FPU_DOUBLEPREC() ) {
1847 sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );
1849 sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );
1854 { /* FCMP/GT FRm, FRn */
1855 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1857 if( IS_FPU_DOUBLEPREC() ) {
1858 sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );
1860 sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );
1865 { /* FMOV @(R0, Rm), FRn */
1866 uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1867 MEM_FP_READ( sh4r.r[Rm] + R0, FRn );
1871 { /* FMOV FRm, @(R0, Rn) */
1872 uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1873 MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm );
1877 { /* FMOV @Rm, FRn */
1878 uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1879 MEM_FP_READ( sh4r.r[Rm], FRn );
1883 { /* FMOV @Rm+, FRn */
1884 uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1885 MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH;
1889 { /* FMOV FRm, @Rn */
1890 uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1891 MEM_FP_WRITE( sh4r.r[Rn], FRm );
1895 { /* FMOV FRm, @-Rn */
1896 uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1897 sh4r.r[Rn] -= FP_WIDTH; MEM_FP_WRITE( sh4r.r[Rn], FRm );
1901 { /* FMOV FRm, FRn */
1902 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1903 if( IS_FPU_DOUBLESIZE() )
1910 switch( (ir&0xF0) >> 4 ) {
1912 { /* FSTS FPUL, FRn */
1913 uint32_t FRn = ((ir>>8)&0xF);
1914 CHECKFPUEN(); FR(FRn) = FPULf;
1918 { /* FLDS FRm, FPUL */
1919 uint32_t FRm = ((ir>>8)&0xF);
1920 CHECKFPUEN(); FPULf = FR(FRm);
1924 { /* FLOAT FPUL, FRn */
1925 uint32_t FRn = ((ir>>8)&0xF);
1927 if( IS_FPU_DOUBLEPREC() ) {
1928 if( FRn&1 ) { // No, really...
1929 dtmp = (double)FPULi;
1930 FR(FRn) = *(((float *)&dtmp)+1);
1932 DRF(FRn>>1) = (double)FPULi;
1935 FR(FRn) = (float)FPULi;
1940 { /* FTRC FRm, FPUL */
1941 uint32_t FRm = ((ir>>8)&0xF);
1943 if( IS_FPU_DOUBLEPREC() ) {
1946 *(((float *)&dtmp)+1) = FR(FRm);
1950 if( dtmp >= MAX_INTF )
1952 else if( dtmp <= MIN_INTF )
1955 FPULi = (int32_t)dtmp;
1958 if( ftmp >= MAX_INTF )
1960 else if( ftmp <= MIN_INTF )
1963 FPULi = (int32_t)ftmp;
1969 uint32_t FRn = ((ir>>8)&0xF);
1971 if( IS_FPU_DOUBLEPREC() ) {
1980 uint32_t FRn = ((ir>>8)&0xF);
1982 if( IS_FPU_DOUBLEPREC() ) {
1983 DR(FRn) = fabs(DR(FRn));
1985 FR(FRn) = fabsf(FR(FRn));
1991 uint32_t FRn = ((ir>>8)&0xF);
1993 if( IS_FPU_DOUBLEPREC() ) {
1994 DR(FRn) = sqrt(DR(FRn));
1996 FR(FRn) = sqrtf(FR(FRn));
2002 uint32_t FRn = ((ir>>8)&0xF);
2004 if( !IS_FPU_DOUBLEPREC() ) {
2005 FR(FRn) = 1.0/sqrtf(FR(FRn));
2011 uint32_t FRn = ((ir>>8)&0xF);
2013 if( IS_FPU_DOUBLEPREC() ) {
2022 uint32_t FRn = ((ir>>8)&0xF);
2024 if( IS_FPU_DOUBLEPREC() ) {
2032 { /* FCNVSD FPUL, FRn */
2033 uint32_t FRn = ((ir>>8)&0xF);
2035 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
2036 DR(FRn) = (double)FPULf;
2041 { /* FCNVDS FRm, FPUL */
2042 uint32_t FRm = ((ir>>8)&0xF);
2044 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
2045 FPULf = (float)DR(FRm);
2050 { /* FIPR FVm, FVn */
2051 uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3);
2053 if( !IS_FPU_DOUBLEPREC() ) {
2056 FR(tmp2+3) = FR(tmp)*FR(tmp2) +
2057 FR(tmp+1)*FR(tmp2+1) +
2058 FR(tmp+2)*FR(tmp2+2) +
2059 FR(tmp+3)*FR(tmp2+3);
2064 switch( (ir&0x100) >> 8 ) {
2066 { /* FSCA FPUL, FRn */
2067 uint32_t FRn = ((ir>>9)&0x7)<<1;
2069 if( !IS_FPU_DOUBLEPREC() ) {
2070 sh4_fsca( FPULi, &(DRF(FRn>>1)) );
2072 float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;
2073 FR(FRn) = sinf(angle);
2074 FR((FRn)+1) = cosf(angle);
2080 switch( (ir&0x200) >> 9 ) {
2082 { /* FTRV XMTRX, FVn */
2083 uint32_t FVn = ((ir>>10)&0x3);
2085 if( !IS_FPU_DOUBLEPREC() ) {
2086 sh4_ftrv(&(DRF(FVn<<1)), &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0]);
2089 float *xf = &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0];
2090 float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
2091 FR(tmp) = xf[1] * fv[0] + xf[5]*fv[1] +
2092 xf[9]*fv[2] + xf[13]*fv[3];
2093 FR(tmp+1) = xf[0] * fv[0] + xf[4]*fv[1] +
2094 xf[8]*fv[2] + xf[12]*fv[3];
2095 FR(tmp+2) = xf[3] * fv[0] + xf[7]*fv[1] +
2096 xf[11]*fv[2] + xf[15]*fv[3];
2097 FR(tmp+3) = xf[2] * fv[0] + xf[6]*fv[1] +
2098 xf[10]*fv[2] + xf[14]*fv[3];
2104 switch( (ir&0xC00) >> 10 ) {
2107 CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ;
2113 sh4r.fpscr ^= FPSCR_FR;
2114 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
2137 { /* FMAC FR0, FRm, FRn */
2138 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
2140 if( IS_FPU_DOUBLEPREC() ) {
2141 DR(FRn) += DR(FRm)*DR(0);
2143 FR(FRn) += FR(FRm)*FR(0);
2154 sh4r.pc = sh4r.new_pc;
2156 sh4r.in_delay_slot = 0;
.